1 /* 2 * include/asm-arm/arch-sa1100/flexanet.h 3 * 4 * Created 2001/05/04 by Jordi Colomer <jco@ict.es> 5 * 6 * This file contains the hardware specific definitions for FlexaNet 7 * 8 */ 9 10 #ifndef __ASM_ARCH_HARDWARE_H 11 #error "include <asm/hardware.h> instead" 12 #endif 13 14 /* Board Control Register (virtual address) */ 15 #define FHH_BCR_PHYS 0x10000000 16 #define FHH_BCR_VIRT 0xf0000000 17 #define FHH_BCR (*(volatile unsigned int *)(FHH_BCR_VIRT)) 18 19 /* Power-up value */ 20 #define FHH_BCR_POWERUP 0x00000000 21 22 /* Mandatory bits */ 23 #define FHH_BCR_LED_GREEN (1<<0) /* General-purpose green LED (1 = on) */ 24 #define FHH_BCR_SPARE_1 (1<<1) /* Not defined */ 25 #define FHH_BCR_CF1_RST (1<<2) /* Compact Flash Slot #1 Reset (1 = reset) */ 26 #define FHH_BCR_CF2_RST (1<<3) /* Compact Flash Slot #2 Reset (1 = reset) */ 27 #define FHH_BCR_GUI_NRST (1<<4) /* GUI board reset (0 = reset) */ 28 #define FHH_BCR_RTS1 (1<<5) /* RS232 RTS for UART-1 */ 29 #define FHH_BCR_RTS3 (1<<6) /* RS232 RTS for UART-3 */ 30 #define FHH_BCR_XCDBG0 (1<<7) /* Not defined. Wired to XPLA3 for debug */ 31 32 /* BCR extension, only required by L3-bus in some audio codecs */ 33 #define FHH_BCR_L3MOD (1<<8) /* L3-bus MODE signal */ 34 #define FHH_BCR_L3DAT (1<<9) /* L3-bus DATA signal */ 35 #define FHH_BCR_L3CLK (1<<10) /* L3-bus CLK signal */ 36 #define FHH_BCR_SPARE_11 (1<<11) /* Not defined */ 37 #define FHH_BCR_SPARE_12 (1<<12) /* Not defined */ 38 #define FHH_BCR_SPARE_13 (1<<13) /* Not defined */ 39 #define FHH_BCR_SPARE_14 (1<<14) /* Not defined */ 40 #define FHH_BCR_SPARE_15 (1<<15) /* Not defined */ 41 42 /* Board Status Register (virtual address) */ 43 #define FHH_BSR_BASE FHH_BCR_VIRT 44 #define FHH_BSR (*(volatile unsigned int *)(FHH_BSR_BASE)) 45 46 #define FHH_BSR_CTS1 (1<<0) /* RS232 CTS for UART-1 */ 47 #define FHH_BSR_CTS3 (1<<1) /* RS232 CTS for UART-3 */ 48 #define FHH_BSR_DSR1 (1<<2) /* RS232 DSR for UART-1 */ 49 #define FHH_BSR_DSR3 (1<<3) /* RS232 DSR for UART-3 */ 50 #define FHH_BSR_ID0 (1<<4) /* Board identification */ 51 #define FHH_BSR_ID1 (1<<5) 52 #define FHH_BSR_CFG0 (1<<6) /* Board configuration options */ 53 #define FHH_BSR_CFG1 (1<<7) 54 55 #ifndef __ASSEMBLY__ 56 extern unsigned long flexanet_BCR; /* Image of the BCR */ 57 #define FLEXANET_BCR_set( x ) FHH_BCR = (flexanet_BCR |= (x)) 58 #define FLEXANET_BCR_clear( x ) FHH_BCR = (flexanet_BCR &= ~(x)) 59 #endif 60 61 /* GPIOs for which the generic definition doesn't say much */ 62 #define GPIO_CF1_NCD GPIO_GPIO (14) /* Card Detect from CF slot #1 */ 63 #define GPIO_CF2_NCD GPIO_GPIO (15) /* Card Detect from CF slot #2 */ 64 #define GPIO_CF1_IRQ GPIO_GPIO (16) /* IRQ from CF slot #1 */ 65 #define GPIO_CF2_IRQ GPIO_GPIO (17) /* IRQ from CF slot #2 */ 66 #define GPIO_APP_IRQ GPIO_GPIO (18) /* Extra IRQ from application bus */ 67 #define GPIO_RADIO_REF GPIO_GPIO (20) /* Ref. clock for UART3 (Radio) */ 68 #define GPIO_CF1_BVD1 GPIO_GPIO (21) /* BVD1 from CF slot #1 */ 69 #define GPIO_CF2_BVD1 GPIO_GPIO (22) /* BVD1 from CF slot #2 */ 70 #define GPIO_GUI_IRQ GPIO_GPIO (23) /* IRQ from GUI board (i.e., UCB1300) */ 71 #define GPIO_ETH_IRQ GPIO_GPIO (24) /* IRQ from Ethernet controller */ 72 #define GPIO_INTIP_IRQ GPIO_GPIO (25) /* Measurement IRQ (INTIP) */ 73 #define GPIO_LED_RED GPIO_GPIO (26) /* General-purpose red LED */ 74 75 /* IRQ sources from GPIOs */ 76 #define IRQ_GPIO_CF1_CD IRQ_GPIO14 77 #define IRQ_GPIO_CF2_CD IRQ_GPIO15 78 #define IRQ_GPIO_CF1_IRQ IRQ_GPIO16 79 #define IRQ_GPIO_CF2_IRQ IRQ_GPIO17 80 #define IRQ_GPIO_APP IRQ_GPIO18 81 #define IRQ_GPIO_CF1_BVD1 IRQ_GPIO21 82 #define IRQ_GPIO_CF2_BVD1 IRQ_GPIO22 83 #define IRQ_GPIO_GUI IRQ_GPIO23 84 #define IRQ_GPIO_ETH IRQ_GPIO24 85 #define IRQ_GPIO_INTIP IRQ_GPIO25 86 87 88 /* On-Board Ethernet */ 89 #define _FHH_ETH_IOBASE 0x18000000 /* I/O base (physical addr) */ 90 #define _FHH_ETH_MMBASE 0x18800000 /* Attribute-memory base */ 91 #define FHH_ETH_SIZE 0x01000000 /* total size */ 92 #define FHH_ETH_VIRT 0xF1000000 /* Ethernet virtual address */ 93 94 #define FHH_ETH_p2v( x ) ((x) - _FHH_ETH_IOBASE + FHH_ETH_VIRT) 95 #define FHH_ETH_v2p( x ) ((x) - FHH_ETH_VIRT + _FHH_ETH_IOBASE) 96 97 #define FHH_ETH_IOBASE FHH_ETH_p2v(_FHH_ETH_IOBASE) /* Virtual base addr */ 98 #define FHH_ETH_MMBASE FHH_ETH_p2v(_FHH_ETH_MMBASE) 99 100 101