1 #ifndef _IOP13XX_HW_H_
2 #define _IOP13XX_HW_H_
3
4 #ifndef __ASSEMBLY__
5 /* The ATU offsets can change based on the strapping */
6 extern u32 iop13xx_atux_pmmr_offset;
7 extern u32 iop13xx_atue_pmmr_offset;
8 void iop13xx_init_irq(void);
9 void iop13xx_map_io(void);
10 void iop13xx_platform_init(void);
11 void iop13xx_add_tpmi_devices(void);
12 void iop13xx_init_irq(void);
13
14 /* CPUID CP6 R0 Page 0 */
iop13xx_cpu_id(void)15 static inline int iop13xx_cpu_id(void)
16 {
17 int id;
18 asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
19 return id;
20 }
21
22 /* WDTCR CP6 R7 Page 9 */
read_wdtcr(void)23 static inline u32 read_wdtcr(void)
24 {
25 u32 val;
26 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
27 return val;
28 }
write_wdtcr(u32 val)29 static inline void write_wdtcr(u32 val)
30 {
31 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
32 }
33
34 /* WDTSR CP6 R8 Page 9 */
read_wdtsr(void)35 static inline u32 read_wdtsr(void)
36 {
37 u32 val;
38 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
39 return val;
40 }
write_wdtsr(u32 val)41 static inline void write_wdtsr(u32 val)
42 {
43 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
44 }
45
46 /* RCSR - Reset Cause Status Register */
read_rcsr(void)47 static inline u32 read_rcsr(void)
48 {
49 u32 val;
50 asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
51 return val;
52 }
53
54 extern unsigned long get_iop_tick_rate(void);
55 #endif
56
57 /*
58 * IOP13XX I/O and Mem space regions for PCI autoconfiguration
59 */
60 #define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
61 #define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
62
63 /* PCI MAP
64 * bus range cpu phys cpu virt note
65 * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM
66 * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window
67 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
68 *
69 * IO MAP
70 * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window
71 * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window
72 */
73 #define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
74 #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
75 #define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
76 #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
77 #define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
78 #define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
79 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
80 #define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
81 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
82 #define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
83 (IOP13XX_PCIX_LOWER_IO_PA\
84 - IOP13XX_PCIX_LOWER_IO_VA))
85
86 #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
87 #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
88 #define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
89 #define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
90 IOP13XX_PCIX_LOWER_MEM_BA)
91 #define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
92 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
93 #define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
94 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
95
96 #define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
97 #define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
98 #define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
99 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
100 #define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
101 IOP13XX_PCIX_LOWER_MEM_BA)
102
103 /* PCI-E ranges */
104 #define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
105 #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
106 #define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
107 #define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
108 #define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
109 #define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
110 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
111 #define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
112 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
113 #define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
114 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
115 #define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
116 (IOP13XX_PCIE_LOWER_IO_PA\
117 - IOP13XX_PCIE_LOWER_IO_VA))
118
119 #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
120 #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
121 #define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
122 #define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
123 IOP13XX_PCIE_LOWER_MEM_BA)
124 #define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
125 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
126 #define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
127 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
128
129 /* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
130 #define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
131 #define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
132 #define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
133 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
134 #define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
135 IOP13XX_PCIE_LOWER_MEM_BA)
136
137 /* PBI Ranges */
138 #define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
139 #define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
140 #define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
141 #define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
142 #define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
143 IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
144
145 /*
146 * IOP13XX chipset registers
147 */
148 #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
149 #define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */
150 #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
151 #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
152 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
153 #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
154 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
155 #define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\
156 (IOP13XX_PMMR_PHYS_MEM_BASE\
157 - IOP13XX_PMMR_VIRT_MEM_BASE))
158 #define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
159 (IOP13XX_PMMR_PHYS_MEM_BASE\
160 - IOP13XX_PMMR_VIRT_MEM_BASE))
161 #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
162 #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
163 #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
164 #define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
165 #define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
166 #define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
167 #define IOP13XX_PMMR_SIZE 0x00080000
168
169 /*=================== Defines for Platform Devices =====================*/
170 #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
171 #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
172 #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
173 #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
174
175 #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
176 #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
177 #define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
178 #define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
179 #define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
180 #define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
181
182 /* ATU selection flags */
183 /* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
184 #define IOP13XX_INIT_ATU_DEFAULT (0)
185 #define IOP13XX_INIT_ATU_ATUX (1 << 0)
186 #define IOP13XX_INIT_ATU_ATUE (1 << 1)
187 #define IOP13XX_INIT_ATU_NONE (1 << 2)
188
189 /* UART selection flags */
190 /* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
191 #define IOP13XX_INIT_UART_DEFAULT (0)
192 #define IOP13XX_INIT_UART_0 (1 << 0)
193 #define IOP13XX_INIT_UART_1 (1 << 1)
194
195 /* I2C selection flags */
196 /* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
197 #define IOP13XX_INIT_I2C_DEFAULT (0)
198 #define IOP13XX_INIT_I2C_0 (1 << 0)
199 #define IOP13XX_INIT_I2C_1 (1 << 1)
200 #define IOP13XX_INIT_I2C_2 (1 << 2)
201
202 /* ADMA selection flags */
203 /* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */
204 #define IOP13XX_INIT_ADMA_DEFAULT (0)
205 #define IOP13XX_INIT_ADMA_0 (1 << 0)
206 #define IOP13XX_INIT_ADMA_1 (1 << 1)
207 #define IOP13XX_INIT_ADMA_2 (1 << 2)
208
209 /* Platform devices */
210 #define IQ81340_NUM_UART 2
211 #define IQ81340_NUM_I2C 3
212 #define IQ81340_NUM_PHYS_MAP_FLASH 1
213 #define IQ81340_NUM_ADMA 3
214 #define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \
215 IQ81340_NUM_I2C + \
216 IQ81340_NUM_PHYS_MAP_FLASH + \
217 IQ81340_NUM_ADMA)
218
219 /*========================== PMMR offsets for key registers ============*/
220 #define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
221 #define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
222 #define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
223 #define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
224 #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
225 #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
226 #define IOP13XX_PBI_PMMR_OFFSET 0x00001580
227 #define IOP13XX_MU_PMMR_OFFSET 0x00004000
228 #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
229 #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
230
231 #define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
232 #define IOP13XX_CONTROLLER_ONLY (1 << 14)
233 #define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
234
235 #define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
236 #define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
237 IOP13XX_PMON_PMMR_OFFSET)
238 #define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
239 IOP13XX_PMON_PMMR_OFFSET)
240
241 #define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
242 #define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
243 #define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
244 #define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
245
246 #define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
247 #define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
248 #define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
249 #define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
250
251 #define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
252 #define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
253 #define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
254 #define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
255
256 #define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
257 #define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
258
259 /*================================ATU===================================*/
260 #define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
261 iop13xx_atux_pmmr_offset + (ofs))
262
263 #define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
264 iop13xx_atux_pmmr_offset + 0x2)
265
266 #define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
267 iop13xx_atux_pmmr_offset + 0x4)
268 #define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
269 iop13xx_atux_pmmr_offset + 0x6)
270
271 #define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
272 #define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
273 #define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
274 #define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
275 #define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
276 #define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
277 #define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
278 #define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
279 #define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
280 #define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
281 #define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
282 #define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
283 #define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
284 #define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
285 #define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
286 #define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
287 #define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
288 #define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
289 #define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
290 #define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
291 #define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
292 #define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
293 #define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
294 #define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
295
296 #define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
297 #define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
298 #define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
299 #define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
300 #define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
301 #define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
302 #define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
303 #define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
304 #define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
305 #define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
306 #define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
307 #define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
308 #define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
309 #define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
310
311 #define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
312 #define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
313 #define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
314 #define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
315 #define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
316 #define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
317
318 #define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
319 #define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
320 #define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
321 #define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
322 #define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
323 #define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
324 #define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
325 #define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
326 #define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
327 #define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
328 #define IOP13XX_ATUX_STAT_BIST (1 << 8 )
329 #define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
330 #define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
331 #define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
332 #define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
333 #define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
334 #define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
335
336 #define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
337 #define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
338 #define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
339
340 #define IOP13XX_ATUX_IALR_DISABLE 0x00000001
341 #define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
342
343 #define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
344 iop13xx_atue_pmmr_offset + (ofs))
345
346 #define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
347 iop13xx_atue_pmmr_offset + 0x2)
348 #define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
349 iop13xx_atue_pmmr_offset + 0x4)
350 #define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
351 iop13xx_atue_pmmr_offset + 0x6)
352
353 #define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
354 #define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
355 #define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
356 #define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
357 #define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
358 #define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
359 #define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
360 #define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
361 #define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
362 #define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
363 #define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
364 #define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
365 #define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
366 #define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
367 #define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
368 #define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
369 iop13xx_atue_pmmr_offset + 0xe2)
370 #define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
371 #define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
372 #define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
373 #define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
374 #define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
375 #define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
376 #define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
377 #define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
378 #define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
379
380 #define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
381 #define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
382 #define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
383 #define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
384 #define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
385 #define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
386
387 #define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
388 #define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
389
390 #define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
391 #define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
392 #define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
393 #define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
394 #define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
395 #define IOP13XX_ATUE_OCCAR_EXT_REG (8)
396 #define IOP13XX_ATUE_OCCAR_REG (2)
397
398 #define IOP13XX_ATUE_PCSR_BUS_NUM (24)
399 #define IOP13XX_ATUE_PCSR_DEV_NUM (19)
400 #define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
401 #define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
402 #define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
403 #define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
404 #define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
405
406 #define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
407 #define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
408 #define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
409
410 #define IOP13XX_ATUE_PCSR_CORE_RESET (8)
411 #define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
412
413 #define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
414 #define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
415 #define IOP13XX_ATUE_STAT_PME (1 << 27)
416 #define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
417 #define IOP13XX_ATUE_STAT_IVM (1 << 25)
418 #define IOP13XX_ATUE_STAT_BIST (1 << 24)
419 #define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
420 #define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
421 #define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
422 #define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
423 #define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
424 #define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
425 #define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
426 #define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
427 #define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
428 #define IOP13XX_ATUE_STAT_CRS (1 << 7 )
429 #define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
430 #define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
431 #define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
432 #define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
433 #define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
434 #define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
435 #define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
436
437 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
438 #define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
439 #define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
440 #define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
441 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
442 #define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
443 #define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
444 #define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
445 #define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
446 #define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
447 #define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
448 #define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
449 #define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
450 #define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
451 #define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
452
453 #define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
454 #define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
455 #define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
456 #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
457 /*=======================================================================*/
458
459 /*============================MESSAGING UNIT=============================*/
460 #define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\
461 (ofs))
462
463 #define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10)
464 #define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14)
465 #define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18)
466 #define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C)
467 #define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20)
468 #define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24)
469 #define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28)
470 #define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C)
471 #define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30)
472 #define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34)
473 #define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38)
474 #define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C)
475 #define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48)
476 #define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50)
477 #define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54)
478 #define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84)
479
480 #define IOP13XX_MU_WINDOW_SIZE (8 * 1024)
481 #define IOP13XX_MU_BASE_PHYS (0xff000000)
482 #define IOP13XX_MU_BASE_PCI (0xff000000)
483 #define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48)
484 #define IOP13XX_MU_MIMR_CORE_SELECT (15)
485 /*=======================================================================*/
486
487 /*==============================ADMA UNITS===============================*/
488 #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
489 #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
490
491 /*==============================XSI BRIDGE===============================*/
492 #define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
493 #define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
494 #define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
495 #define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
496 IOP13XX_PMMR_VIRT_TO_PHYS(\
497 IOP13XX_ATUE_OCCDR))\
498 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
499 #define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
500 IOP13XX_PMMR_VIRT_TO_PHYS(\
501 IOP13XX_ATUX_OCCDR))\
502 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
503 /*=======================================================================*/
504
505 #define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
506 (ofs))
507
508 #define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
509 #define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
510 #define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
511 #define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
512 #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
513 #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
514
515 #define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
516
517 /* Watchdog timer definitions */
518 #define IOP_WDTCR_EN_ARM 0x1e1e1e1e
519 #define IOP_WDTCR_EN 0xe1e1e1e1
520 #define IOP_WDTCR_DIS_ARM 0x1f1f1f1f
521 #define IOP_WDTCR_DIS 0xf1f1f1f1
522 #define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */
523 #define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */
524 #define IOP13XX_WDTCR_IB_RESET (1 << 0)
525
526 #endif /* _IOP13XX_HW_H_ */
527