1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  *  arch/arm/include/asm/hardware/iomd.h
4  *
5  *  Copyright (C) 1999 Russell King
6  *
7  *  This file contains information out the IOMD ASIC used in the
8  *  Acorn RiscPC and subsequently integrated into the CLPS7500 chips.
9  */
10 #ifndef __ASMARM_HARDWARE_IOMD_H
11 #define __ASMARM_HARDWARE_IOMD_H
12 
13 
14 #ifndef __ASSEMBLY__
15 
16 /*
17  * We use __raw_base variants here so that we give the compiler the
18  * chance to keep IOC_BASE in a register.
19  */
20 #define iomd_readb(off)		__raw_readb(IOMD_BASE + (off))
21 #define iomd_readl(off)		__raw_readl(IOMD_BASE + (off))
22 #define iomd_writeb(val,off)	__raw_writeb(val, IOMD_BASE + (off))
23 #define iomd_writel(val,off)	__raw_writel(val, IOMD_BASE + (off))
24 
25 #endif
26 
27 #define IOMD_CONTROL	(0x000)
28 #define IOMD_KARTTX	(0x004)
29 #define IOMD_KARTRX	(0x004)
30 #define IOMD_KCTRL	(0x008)
31 
32 #define IOMD_IRQSTATA	(0x010)
33 #define IOMD_IRQREQA	(0x014)
34 #define IOMD_IRQCLRA	(0x014)
35 #define IOMD_IRQMASKA	(0x018)
36 
37 #define IOMD_IRQSTATB	(0x020)
38 #define IOMD_IRQREQB	(0x024)
39 #define IOMD_IRQMASKB	(0x028)
40 
41 #define IOMD_FIQSTAT	(0x030)
42 #define IOMD_FIQREQ	(0x034)
43 #define IOMD_FIQMASK	(0x038)
44 
45 #define IOMD_T0CNTL	(0x040)
46 #define IOMD_T0LTCHL	(0x040)
47 #define IOMD_T0CNTH	(0x044)
48 #define IOMD_T0LTCHH	(0x044)
49 #define IOMD_T0GO	(0x048)
50 #define IOMD_T0LATCH	(0x04c)
51 
52 #define IOMD_T1CNTL	(0x050)
53 #define IOMD_T1LTCHL	(0x050)
54 #define IOMD_T1CNTH	(0x054)
55 #define IOMD_T1LTCHH	(0x054)
56 #define IOMD_T1GO	(0x058)
57 #define IOMD_T1LATCH	(0x05c)
58 
59 #define IOMD_ROMCR0	(0x080)
60 #define IOMD_ROMCR1	(0x084)
61 #ifdef CONFIG_ARCH_RPC
62 #define IOMD_DRAMCR	(0x088)
63 #endif
64 #define IOMD_REFCR	(0x08C)
65 
66 #define IOMD_FSIZE	(0x090)
67 #define IOMD_ID0	(0x094)
68 #define IOMD_ID1	(0x098)
69 #define IOMD_VERSION	(0x09C)
70 
71 #ifdef CONFIG_ARCH_RPC
72 #define IOMD_MOUSEX	(0x0A0)
73 #define IOMD_MOUSEY	(0x0A4)
74 #endif
75 
76 #ifdef CONFIG_ARCH_RPC
77 #define IOMD_DMATCR	(0x0C0)
78 #endif
79 #define IOMD_IOTCR	(0x0C4)
80 #define IOMD_ECTCR	(0x0C8)
81 #ifdef CONFIG_ARCH_RPC
82 #define IOMD_DMAEXT	(0x0CC)
83 #endif
84 
85 #ifdef CONFIG_ARCH_RPC
86 #define DMA_EXT_IO0	1
87 #define DMA_EXT_IO1	2
88 #define DMA_EXT_IO2	4
89 #define DMA_EXT_IO3	8
90 
91 #define IOMD_IO0CURA	(0x100)
92 #define IOMD_IO0ENDA	(0x104)
93 #define IOMD_IO0CURB	(0x108)
94 #define IOMD_IO0ENDB	(0x10C)
95 #define IOMD_IO0CR	(0x110)
96 #define IOMD_IO0ST	(0x114)
97 
98 #define IOMD_IO1CURA	(0x120)
99 #define IOMD_IO1ENDA	(0x124)
100 #define IOMD_IO1CURB	(0x128)
101 #define IOMD_IO1ENDB	(0x12C)
102 #define IOMD_IO1CR	(0x130)
103 #define IOMD_IO1ST	(0x134)
104 
105 #define IOMD_IO2CURA	(0x140)
106 #define IOMD_IO2ENDA	(0x144)
107 #define IOMD_IO2CURB	(0x148)
108 #define IOMD_IO2ENDB	(0x14C)
109 #define IOMD_IO2CR	(0x150)
110 #define IOMD_IO2ST	(0x154)
111 
112 #define IOMD_IO3CURA	(0x160)
113 #define IOMD_IO3ENDA	(0x164)
114 #define IOMD_IO3CURB	(0x168)
115 #define IOMD_IO3ENDB	(0x16C)
116 #define IOMD_IO3CR	(0x170)
117 #define IOMD_IO3ST	(0x174)
118 #endif
119 
120 #define IOMD_SD0CURA	(0x180)
121 #define IOMD_SD0ENDA	(0x184)
122 #define IOMD_SD0CURB	(0x188)
123 #define IOMD_SD0ENDB	(0x18C)
124 #define IOMD_SD0CR	(0x190)
125 #define IOMD_SD0ST	(0x194)
126 
127 #ifdef CONFIG_ARCH_RPC
128 #define IOMD_SD1CURA	(0x1A0)
129 #define IOMD_SD1ENDA	(0x1A4)
130 #define IOMD_SD1CURB	(0x1A8)
131 #define IOMD_SD1ENDB	(0x1AC)
132 #define IOMD_SD1CR	(0x1B0)
133 #define IOMD_SD1ST	(0x1B4)
134 #endif
135 
136 #define IOMD_CURSCUR	(0x1C0)
137 #define IOMD_CURSINIT	(0x1C4)
138 
139 #define IOMD_VIDCUR	(0x1D0)
140 #define IOMD_VIDEND	(0x1D4)
141 #define IOMD_VIDSTART	(0x1D8)
142 #define IOMD_VIDINIT	(0x1DC)
143 #define IOMD_VIDCR	(0x1E0)
144 
145 #define IOMD_DMASTAT	(0x1F0)
146 #define IOMD_DMAREQ	(0x1F4)
147 #define IOMD_DMAMASK	(0x1F8)
148 
149 #define DMA_END_S	(1 << 31)
150 #define DMA_END_L	(1 << 30)
151 
152 #define DMA_CR_C	0x80
153 #define DMA_CR_D	0x40
154 #define DMA_CR_E	0x20
155 
156 #define DMA_ST_OFL	4
157 #define DMA_ST_INT	2
158 #define DMA_ST_AB	1
159 
160 /*
161  * DMA (MEMC) compatibility
162  */
163 #define HALF_SAM	vram_half_sam
164 #define VDMA_ALIGNMENT	(HALF_SAM * 2)
165 #define VDMA_XFERSIZE	(HALF_SAM)
166 #define VDMA_INIT	IOMD_VIDINIT
167 #define VDMA_START	IOMD_VIDSTART
168 #define VDMA_END	IOMD_VIDEND
169 
170 #ifndef __ASSEMBLY__
171 extern unsigned int vram_half_sam;
172 #define video_set_dma(start,end,offset)				\
173 do {								\
174 	outl (SCREEN_START + start, VDMA_START);		\
175 	outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END);	\
176 	if (offset >= end - VDMA_XFERSIZE)			\
177 		offset |= 0x40000000;				\
178 	outl (SCREEN_START + offset, VDMA_INIT);		\
179 } while (0)
180 #endif
181 
182 #endif
183