1 /* 2 * arch/arm/include/asm/hardware/iomd.h 3 * 4 * Copyright (C) 1999 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This file contains information out the IOMD ASIC used in the 11 * Acorn RiscPC and subsequently integrated into the CLPS7500 chips. 12 */ 13 #ifndef __ASMARM_HARDWARE_IOMD_H 14 #define __ASMARM_HARDWARE_IOMD_H 15 16 17 #ifndef __ASSEMBLY__ 18 19 /* 20 * We use __raw_base variants here so that we give the compiler the 21 * chance to keep IOC_BASE in a register. 22 */ 23 #define iomd_readb(off) __raw_readb(IOMD_BASE + (off)) 24 #define iomd_readl(off) __raw_readl(IOMD_BASE + (off)) 25 #define iomd_writeb(val,off) __raw_writeb(val, IOMD_BASE + (off)) 26 #define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off)) 27 28 #endif 29 30 #define IOMD_CONTROL (0x000) 31 #define IOMD_KARTTX (0x004) 32 #define IOMD_KARTRX (0x004) 33 #define IOMD_KCTRL (0x008) 34 35 #define IOMD_IRQSTATA (0x010) 36 #define IOMD_IRQREQA (0x014) 37 #define IOMD_IRQCLRA (0x014) 38 #define IOMD_IRQMASKA (0x018) 39 40 #define IOMD_IRQSTATB (0x020) 41 #define IOMD_IRQREQB (0x024) 42 #define IOMD_IRQMASKB (0x028) 43 44 #define IOMD_FIQSTAT (0x030) 45 #define IOMD_FIQREQ (0x034) 46 #define IOMD_FIQMASK (0x038) 47 48 #define IOMD_T0CNTL (0x040) 49 #define IOMD_T0LTCHL (0x040) 50 #define IOMD_T0CNTH (0x044) 51 #define IOMD_T0LTCHH (0x044) 52 #define IOMD_T0GO (0x048) 53 #define IOMD_T0LATCH (0x04c) 54 55 #define IOMD_T1CNTL (0x050) 56 #define IOMD_T1LTCHL (0x050) 57 #define IOMD_T1CNTH (0x054) 58 #define IOMD_T1LTCHH (0x054) 59 #define IOMD_T1GO (0x058) 60 #define IOMD_T1LATCH (0x05c) 61 62 #define IOMD_ROMCR0 (0x080) 63 #define IOMD_ROMCR1 (0x084) 64 #ifdef CONFIG_ARCH_RPC 65 #define IOMD_DRAMCR (0x088) 66 #endif 67 #define IOMD_REFCR (0x08C) 68 69 #define IOMD_FSIZE (0x090) 70 #define IOMD_ID0 (0x094) 71 #define IOMD_ID1 (0x098) 72 #define IOMD_VERSION (0x09C) 73 74 #ifdef CONFIG_ARCH_RPC 75 #define IOMD_MOUSEX (0x0A0) 76 #define IOMD_MOUSEY (0x0A4) 77 #endif 78 79 #ifdef CONFIG_ARCH_RPC 80 #define IOMD_DMATCR (0x0C0) 81 #endif 82 #define IOMD_IOTCR (0x0C4) 83 #define IOMD_ECTCR (0x0C8) 84 #ifdef CONFIG_ARCH_RPC 85 #define IOMD_DMAEXT (0x0CC) 86 #endif 87 88 #ifdef CONFIG_ARCH_RPC 89 #define DMA_EXT_IO0 1 90 #define DMA_EXT_IO1 2 91 #define DMA_EXT_IO2 4 92 #define DMA_EXT_IO3 8 93 94 #define IOMD_IO0CURA (0x100) 95 #define IOMD_IO0ENDA (0x104) 96 #define IOMD_IO0CURB (0x108) 97 #define IOMD_IO0ENDB (0x10C) 98 #define IOMD_IO0CR (0x110) 99 #define IOMD_IO0ST (0x114) 100 101 #define IOMD_IO1CURA (0x120) 102 #define IOMD_IO1ENDA (0x124) 103 #define IOMD_IO1CURB (0x128) 104 #define IOMD_IO1ENDB (0x12C) 105 #define IOMD_IO1CR (0x130) 106 #define IOMD_IO1ST (0x134) 107 108 #define IOMD_IO2CURA (0x140) 109 #define IOMD_IO2ENDA (0x144) 110 #define IOMD_IO2CURB (0x148) 111 #define IOMD_IO2ENDB (0x14C) 112 #define IOMD_IO2CR (0x150) 113 #define IOMD_IO2ST (0x154) 114 115 #define IOMD_IO3CURA (0x160) 116 #define IOMD_IO3ENDA (0x164) 117 #define IOMD_IO3CURB (0x168) 118 #define IOMD_IO3ENDB (0x16C) 119 #define IOMD_IO3CR (0x170) 120 #define IOMD_IO3ST (0x174) 121 #endif 122 123 #define IOMD_SD0CURA (0x180) 124 #define IOMD_SD0ENDA (0x184) 125 #define IOMD_SD0CURB (0x188) 126 #define IOMD_SD0ENDB (0x18C) 127 #define IOMD_SD0CR (0x190) 128 #define IOMD_SD0ST (0x194) 129 130 #ifdef CONFIG_ARCH_RPC 131 #define IOMD_SD1CURA (0x1A0) 132 #define IOMD_SD1ENDA (0x1A4) 133 #define IOMD_SD1CURB (0x1A8) 134 #define IOMD_SD1ENDB (0x1AC) 135 #define IOMD_SD1CR (0x1B0) 136 #define IOMD_SD1ST (0x1B4) 137 #endif 138 139 #define IOMD_CURSCUR (0x1C0) 140 #define IOMD_CURSINIT (0x1C4) 141 142 #define IOMD_VIDCUR (0x1D0) 143 #define IOMD_VIDEND (0x1D4) 144 #define IOMD_VIDSTART (0x1D8) 145 #define IOMD_VIDINIT (0x1DC) 146 #define IOMD_VIDCR (0x1E0) 147 148 #define IOMD_DMASTAT (0x1F0) 149 #define IOMD_DMAREQ (0x1F4) 150 #define IOMD_DMAMASK (0x1F8) 151 152 #define DMA_END_S (1 << 31) 153 #define DMA_END_L (1 << 30) 154 155 #define DMA_CR_C 0x80 156 #define DMA_CR_D 0x40 157 #define DMA_CR_E 0x20 158 159 #define DMA_ST_OFL 4 160 #define DMA_ST_INT 2 161 #define DMA_ST_AB 1 162 163 /* 164 * DMA (MEMC) compatibility 165 */ 166 #define HALF_SAM vram_half_sam 167 #define VDMA_ALIGNMENT (HALF_SAM * 2) 168 #define VDMA_XFERSIZE (HALF_SAM) 169 #define VDMA_INIT IOMD_VIDINIT 170 #define VDMA_START IOMD_VIDSTART 171 #define VDMA_END IOMD_VIDEND 172 173 #ifndef __ASSEMBLY__ 174 extern unsigned int vram_half_sam; 175 #define video_set_dma(start,end,offset) \ 176 do { \ 177 outl (SCREEN_START + start, VDMA_START); \ 178 outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \ 179 if (offset >= end - VDMA_XFERSIZE) \ 180 offset |= 0x40000000; \ 181 outl (SCREEN_START + offset, VDMA_INIT); \ 182 } while (0) 183 #endif 184 185 #endif 186