1 /*
2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
3  *
4  *   This program is free software; you can redistribute it and/or
5  *   modify it under the terms of the GNU General Public License
6  *   as published by the Free Software Foundation, version 2.
7  *
8  *   This program is distributed in the hope that it will be useful, but
9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11  *   NON INFRINGEMENT.  See the GNU General Public License for
12  *   more details.
13  */
14 
15 #ifndef __ARCH_INTERRUPTS_H__
16 #define __ARCH_INTERRUPTS_H__
17 
18 /** Mask for an interrupt. */
19 /* Note: must handle breaking interrupts into high and low words manually. */
20 #define INT_MASK_LO(intno) (1 << (intno))
21 #define INT_MASK_HI(intno) (1 << ((intno) - 32))
22 
23 #ifndef __ASSEMBLER__
24 #define INT_MASK(intno) (1ULL << (intno))
25 #endif
26 
27 
28 /** Where a given interrupt executes */
29 #define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
30 
31 /** Where to store a vector for a given interrupt. */
32 #define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
33 
34 /** The base address of user-level interrupts. */
35 #define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
36 
37 
38 /** Additional synthetic interrupt. */
39 #define INT_BREAKPOINT (63)
40 
41 #define INT_ITLB_MISS    0
42 #define INT_MEM_ERROR    1
43 #define INT_ILL    2
44 #define INT_GPV    3
45 #define INT_SN_ACCESS    4
46 #define INT_IDN_ACCESS    5
47 #define INT_UDN_ACCESS    6
48 #define INT_IDN_REFILL    7
49 #define INT_UDN_REFILL    8
50 #define INT_IDN_COMPLETE    9
51 #define INT_UDN_COMPLETE   10
52 #define INT_SWINT_3   11
53 #define INT_SWINT_2   12
54 #define INT_SWINT_1   13
55 #define INT_SWINT_0   14
56 #define INT_UNALIGN_DATA   15
57 #define INT_DTLB_MISS   16
58 #define INT_DTLB_ACCESS   17
59 #define INT_DMATLB_MISS   18
60 #define INT_DMATLB_ACCESS   19
61 #define INT_SNITLB_MISS   20
62 #define INT_SN_NOTIFY   21
63 #define INT_SN_FIREWALL   22
64 #define INT_IDN_FIREWALL   23
65 #define INT_UDN_FIREWALL   24
66 #define INT_TILE_TIMER   25
67 #define INT_IDN_TIMER   26
68 #define INT_UDN_TIMER   27
69 #define INT_DMA_NOTIFY   28
70 #define INT_IDN_CA   29
71 #define INT_UDN_CA   30
72 #define INT_IDN_AVAIL   31
73 #define INT_UDN_AVAIL   32
74 #define INT_PERF_COUNT   33
75 #define INT_INTCTRL_3   34
76 #define INT_INTCTRL_2   35
77 #define INT_INTCTRL_1   36
78 #define INT_INTCTRL_0   37
79 #define INT_BOOT_ACCESS   38
80 #define INT_WORLD_ACCESS   39
81 #define INT_I_ASID   40
82 #define INT_D_ASID   41
83 #define INT_DMA_ASID   42
84 #define INT_SNI_ASID   43
85 #define INT_DMA_CPL   44
86 #define INT_SN_CPL   45
87 #define INT_DOUBLE_FAULT   46
88 #define INT_SN_STATIC_ACCESS   47
89 #define INT_AUX_PERF_COUNT   48
90 
91 #define NUM_INTERRUPTS 49
92 
93 #ifndef __ASSEMBLER__
94 #define QUEUED_INTERRUPTS ( \
95     INT_MASK(INT_MEM_ERROR) | \
96     INT_MASK(INT_DMATLB_MISS) | \
97     INT_MASK(INT_DMATLB_ACCESS) | \
98     INT_MASK(INT_SNITLB_MISS) | \
99     INT_MASK(INT_SN_NOTIFY) | \
100     INT_MASK(INT_SN_FIREWALL) | \
101     INT_MASK(INT_IDN_FIREWALL) | \
102     INT_MASK(INT_UDN_FIREWALL) | \
103     INT_MASK(INT_TILE_TIMER) | \
104     INT_MASK(INT_IDN_TIMER) | \
105     INT_MASK(INT_UDN_TIMER) | \
106     INT_MASK(INT_DMA_NOTIFY) | \
107     INT_MASK(INT_IDN_CA) | \
108     INT_MASK(INT_UDN_CA) | \
109     INT_MASK(INT_IDN_AVAIL) | \
110     INT_MASK(INT_UDN_AVAIL) | \
111     INT_MASK(INT_PERF_COUNT) | \
112     INT_MASK(INT_INTCTRL_3) | \
113     INT_MASK(INT_INTCTRL_2) | \
114     INT_MASK(INT_INTCTRL_1) | \
115     INT_MASK(INT_INTCTRL_0) | \
116     INT_MASK(INT_BOOT_ACCESS) | \
117     INT_MASK(INT_WORLD_ACCESS) | \
118     INT_MASK(INT_I_ASID) | \
119     INT_MASK(INT_D_ASID) | \
120     INT_MASK(INT_DMA_ASID) | \
121     INT_MASK(INT_SNI_ASID) | \
122     INT_MASK(INT_DMA_CPL) | \
123     INT_MASK(INT_SN_CPL) | \
124     INT_MASK(INT_DOUBLE_FAULT) | \
125     INT_MASK(INT_AUX_PERF_COUNT) | \
126     0)
127 #define NONQUEUED_INTERRUPTS ( \
128     INT_MASK(INT_ITLB_MISS) | \
129     INT_MASK(INT_ILL) | \
130     INT_MASK(INT_GPV) | \
131     INT_MASK(INT_SN_ACCESS) | \
132     INT_MASK(INT_IDN_ACCESS) | \
133     INT_MASK(INT_UDN_ACCESS) | \
134     INT_MASK(INT_IDN_REFILL) | \
135     INT_MASK(INT_UDN_REFILL) | \
136     INT_MASK(INT_IDN_COMPLETE) | \
137     INT_MASK(INT_UDN_COMPLETE) | \
138     INT_MASK(INT_SWINT_3) | \
139     INT_MASK(INT_SWINT_2) | \
140     INT_MASK(INT_SWINT_1) | \
141     INT_MASK(INT_SWINT_0) | \
142     INT_MASK(INT_UNALIGN_DATA) | \
143     INT_MASK(INT_DTLB_MISS) | \
144     INT_MASK(INT_DTLB_ACCESS) | \
145     INT_MASK(INT_SN_STATIC_ACCESS) | \
146     0)
147 #define CRITICAL_MASKED_INTERRUPTS ( \
148     INT_MASK(INT_MEM_ERROR) | \
149     INT_MASK(INT_DMATLB_MISS) | \
150     INT_MASK(INT_DMATLB_ACCESS) | \
151     INT_MASK(INT_SNITLB_MISS) | \
152     INT_MASK(INT_SN_NOTIFY) | \
153     INT_MASK(INT_SN_FIREWALL) | \
154     INT_MASK(INT_IDN_FIREWALL) | \
155     INT_MASK(INT_UDN_FIREWALL) | \
156     INT_MASK(INT_TILE_TIMER) | \
157     INT_MASK(INT_IDN_TIMER) | \
158     INT_MASK(INT_UDN_TIMER) | \
159     INT_MASK(INT_DMA_NOTIFY) | \
160     INT_MASK(INT_IDN_CA) | \
161     INT_MASK(INT_UDN_CA) | \
162     INT_MASK(INT_IDN_AVAIL) | \
163     INT_MASK(INT_UDN_AVAIL) | \
164     INT_MASK(INT_PERF_COUNT) | \
165     INT_MASK(INT_INTCTRL_3) | \
166     INT_MASK(INT_INTCTRL_2) | \
167     INT_MASK(INT_INTCTRL_1) | \
168     INT_MASK(INT_INTCTRL_0) | \
169     INT_MASK(INT_AUX_PERF_COUNT) | \
170     0)
171 #define CRITICAL_UNMASKED_INTERRUPTS ( \
172     INT_MASK(INT_ITLB_MISS) | \
173     INT_MASK(INT_ILL) | \
174     INT_MASK(INT_GPV) | \
175     INT_MASK(INT_SN_ACCESS) | \
176     INT_MASK(INT_IDN_ACCESS) | \
177     INT_MASK(INT_UDN_ACCESS) | \
178     INT_MASK(INT_IDN_REFILL) | \
179     INT_MASK(INT_UDN_REFILL) | \
180     INT_MASK(INT_IDN_COMPLETE) | \
181     INT_MASK(INT_UDN_COMPLETE) | \
182     INT_MASK(INT_SWINT_3) | \
183     INT_MASK(INT_SWINT_2) | \
184     INT_MASK(INT_SWINT_1) | \
185     INT_MASK(INT_SWINT_0) | \
186     INT_MASK(INT_UNALIGN_DATA) | \
187     INT_MASK(INT_DTLB_MISS) | \
188     INT_MASK(INT_DTLB_ACCESS) | \
189     INT_MASK(INT_BOOT_ACCESS) | \
190     INT_MASK(INT_WORLD_ACCESS) | \
191     INT_MASK(INT_I_ASID) | \
192     INT_MASK(INT_D_ASID) | \
193     INT_MASK(INT_DMA_ASID) | \
194     INT_MASK(INT_SNI_ASID) | \
195     INT_MASK(INT_DMA_CPL) | \
196     INT_MASK(INT_SN_CPL) | \
197     INT_MASK(INT_DOUBLE_FAULT) | \
198     INT_MASK(INT_SN_STATIC_ACCESS) | \
199     0)
200 #define MASKABLE_INTERRUPTS ( \
201     INT_MASK(INT_MEM_ERROR) | \
202     INT_MASK(INT_IDN_REFILL) | \
203     INT_MASK(INT_UDN_REFILL) | \
204     INT_MASK(INT_IDN_COMPLETE) | \
205     INT_MASK(INT_UDN_COMPLETE) | \
206     INT_MASK(INT_DMATLB_MISS) | \
207     INT_MASK(INT_DMATLB_ACCESS) | \
208     INT_MASK(INT_SNITLB_MISS) | \
209     INT_MASK(INT_SN_NOTIFY) | \
210     INT_MASK(INT_SN_FIREWALL) | \
211     INT_MASK(INT_IDN_FIREWALL) | \
212     INT_MASK(INT_UDN_FIREWALL) | \
213     INT_MASK(INT_TILE_TIMER) | \
214     INT_MASK(INT_IDN_TIMER) | \
215     INT_MASK(INT_UDN_TIMER) | \
216     INT_MASK(INT_DMA_NOTIFY) | \
217     INT_MASK(INT_IDN_CA) | \
218     INT_MASK(INT_UDN_CA) | \
219     INT_MASK(INT_IDN_AVAIL) | \
220     INT_MASK(INT_UDN_AVAIL) | \
221     INT_MASK(INT_PERF_COUNT) | \
222     INT_MASK(INT_INTCTRL_3) | \
223     INT_MASK(INT_INTCTRL_2) | \
224     INT_MASK(INT_INTCTRL_1) | \
225     INT_MASK(INT_INTCTRL_0) | \
226     INT_MASK(INT_AUX_PERF_COUNT) | \
227     0)
228 #define UNMASKABLE_INTERRUPTS ( \
229     INT_MASK(INT_ITLB_MISS) | \
230     INT_MASK(INT_ILL) | \
231     INT_MASK(INT_GPV) | \
232     INT_MASK(INT_SN_ACCESS) | \
233     INT_MASK(INT_IDN_ACCESS) | \
234     INT_MASK(INT_UDN_ACCESS) | \
235     INT_MASK(INT_SWINT_3) | \
236     INT_MASK(INT_SWINT_2) | \
237     INT_MASK(INT_SWINT_1) | \
238     INT_MASK(INT_SWINT_0) | \
239     INT_MASK(INT_UNALIGN_DATA) | \
240     INT_MASK(INT_DTLB_MISS) | \
241     INT_MASK(INT_DTLB_ACCESS) | \
242     INT_MASK(INT_BOOT_ACCESS) | \
243     INT_MASK(INT_WORLD_ACCESS) | \
244     INT_MASK(INT_I_ASID) | \
245     INT_MASK(INT_D_ASID) | \
246     INT_MASK(INT_DMA_ASID) | \
247     INT_MASK(INT_SNI_ASID) | \
248     INT_MASK(INT_DMA_CPL) | \
249     INT_MASK(INT_SN_CPL) | \
250     INT_MASK(INT_DOUBLE_FAULT) | \
251     INT_MASK(INT_SN_STATIC_ACCESS) | \
252     0)
253 #define SYNC_INTERRUPTS ( \
254     INT_MASK(INT_ITLB_MISS) | \
255     INT_MASK(INT_ILL) | \
256     INT_MASK(INT_GPV) | \
257     INT_MASK(INT_SN_ACCESS) | \
258     INT_MASK(INT_IDN_ACCESS) | \
259     INT_MASK(INT_UDN_ACCESS) | \
260     INT_MASK(INT_IDN_REFILL) | \
261     INT_MASK(INT_UDN_REFILL) | \
262     INT_MASK(INT_IDN_COMPLETE) | \
263     INT_MASK(INT_UDN_COMPLETE) | \
264     INT_MASK(INT_SWINT_3) | \
265     INT_MASK(INT_SWINT_2) | \
266     INT_MASK(INT_SWINT_1) | \
267     INT_MASK(INT_SWINT_0) | \
268     INT_MASK(INT_UNALIGN_DATA) | \
269     INT_MASK(INT_DTLB_MISS) | \
270     INT_MASK(INT_DTLB_ACCESS) | \
271     INT_MASK(INT_SN_STATIC_ACCESS) | \
272     0)
273 #define NON_SYNC_INTERRUPTS ( \
274     INT_MASK(INT_MEM_ERROR) | \
275     INT_MASK(INT_DMATLB_MISS) | \
276     INT_MASK(INT_DMATLB_ACCESS) | \
277     INT_MASK(INT_SNITLB_MISS) | \
278     INT_MASK(INT_SN_NOTIFY) | \
279     INT_MASK(INT_SN_FIREWALL) | \
280     INT_MASK(INT_IDN_FIREWALL) | \
281     INT_MASK(INT_UDN_FIREWALL) | \
282     INT_MASK(INT_TILE_TIMER) | \
283     INT_MASK(INT_IDN_TIMER) | \
284     INT_MASK(INT_UDN_TIMER) | \
285     INT_MASK(INT_DMA_NOTIFY) | \
286     INT_MASK(INT_IDN_CA) | \
287     INT_MASK(INT_UDN_CA) | \
288     INT_MASK(INT_IDN_AVAIL) | \
289     INT_MASK(INT_UDN_AVAIL) | \
290     INT_MASK(INT_PERF_COUNT) | \
291     INT_MASK(INT_INTCTRL_3) | \
292     INT_MASK(INT_INTCTRL_2) | \
293     INT_MASK(INT_INTCTRL_1) | \
294     INT_MASK(INT_INTCTRL_0) | \
295     INT_MASK(INT_BOOT_ACCESS) | \
296     INT_MASK(INT_WORLD_ACCESS) | \
297     INT_MASK(INT_I_ASID) | \
298     INT_MASK(INT_D_ASID) | \
299     INT_MASK(INT_DMA_ASID) | \
300     INT_MASK(INT_SNI_ASID) | \
301     INT_MASK(INT_DMA_CPL) | \
302     INT_MASK(INT_SN_CPL) | \
303     INT_MASK(INT_DOUBLE_FAULT) | \
304     INT_MASK(INT_AUX_PERF_COUNT) | \
305     0)
306 #endif /* !__ASSEMBLER__ */
307 #endif /* !__ARCH_INTERRUPTS_H__ */
308