1 /* bnx2x.h: QLogic Everest network driver.
2  *
3  * Copyright (c) 2007-2013 Broadcom Corporation
4  * Copyright (c) 2014 QLogic Corporation
5  * All rights reserved
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation.
10  *
11  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12  * Written by: Eliezer Tamir
13  * Based on code from Michael Chan's bnx2 driver
14  */
15 
16 #ifndef BNX2X_H
17 #define BNX2X_H
18 
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/types.h>
23 #include <linux/pci_regs.h>
24 
25 #include <linux/ptp_clock_kernel.h>
26 #include <linux/net_tstamp.h>
27 #include <linux/timecounter.h>
28 
29 /* compilation time flags */
30 
31 /* define this to make the driver freeze on error to allow getting debug info
32  * (you will need to reboot afterwards) */
33 /* #define BNX2X_STOP_ON_ERROR */
34 
35 /* FIXME: Delete the DRV_MODULE_VERSION below, but please be warned
36  * that it is not an easy task because such change has all chances
37  * to break this driver due to amount of abuse of in-kernel interfaces
38  * between modules and FW.
39  *
40  * DO NOT UPDATE DRV_MODULE_VERSION below.
41  */
42 #define DRV_MODULE_VERSION      "1.713.36-0"
43 #define BNX2X_BC_VER            0x040200
44 
45 #if defined(CONFIG_DCB)
46 #define BCM_DCBNL
47 #endif
48 
49 #include "bnx2x_hsi.h"
50 
51 #include "../cnic_if.h"
52 
53 #define BNX2X_MIN_MSIX_VEC_CNT(bp)		((bp)->min_msix_vec_cnt)
54 
55 #include <linux/mdio.h>
56 
57 #include "bnx2x_reg.h"
58 #include "bnx2x_fw_defs.h"
59 #include "bnx2x_mfw_req.h"
60 #include "bnx2x_link.h"
61 #include "bnx2x_sp.h"
62 #include "bnx2x_dcb.h"
63 #include "bnx2x_stats.h"
64 #include "bnx2x_vfpf.h"
65 
66 enum bnx2x_int_mode {
67 	BNX2X_INT_MODE_MSIX,
68 	BNX2X_INT_MODE_INTX,
69 	BNX2X_INT_MODE_MSI
70 };
71 
72 /* error/debug prints */
73 
74 #define DRV_MODULE_NAME		"bnx2x"
75 
76 /* for messages that are currently off */
77 #define BNX2X_MSG_OFF			0x0
78 #define BNX2X_MSG_MCP			0x0010000 /* was: NETIF_MSG_HW */
79 #define BNX2X_MSG_STATS			0x0020000 /* was: NETIF_MSG_TIMER */
80 #define BNX2X_MSG_NVM			0x0040000 /* was: NETIF_MSG_HW */
81 #define BNX2X_MSG_DMAE			0x0080000 /* was: NETIF_MSG_HW */
82 #define BNX2X_MSG_SP			0x0100000 /* was: NETIF_MSG_INTR */
83 #define BNX2X_MSG_FP			0x0200000 /* was: NETIF_MSG_INTR */
84 #define BNX2X_MSG_IOV			0x0800000
85 #define BNX2X_MSG_PTP			0x1000000
86 #define BNX2X_MSG_IDLE			0x2000000 /* used for idle check*/
87 #define BNX2X_MSG_ETHTOOL		0x4000000
88 #define BNX2X_MSG_DCB			0x8000000
89 
90 /* regular debug print */
91 #define DP_INNER(fmt, ...)					\
92 	pr_notice("[%s:%d(%s)]" fmt,				\
93 		  __func__, __LINE__,				\
94 		  bp->dev ? (bp->dev->name) : "?",		\
95 		  ##__VA_ARGS__);
96 
97 #define DP(__mask, fmt, ...)					\
98 do {								\
99 	if (unlikely(bp->msg_enable & (__mask)))		\
100 		DP_INNER(fmt, ##__VA_ARGS__);			\
101 } while (0)
102 
103 #define DP_AND(__mask, fmt, ...)				\
104 do {								\
105 	if (unlikely((bp->msg_enable & (__mask)) == __mask))	\
106 		DP_INNER(fmt, ##__VA_ARGS__);			\
107 } while (0)
108 
109 #define DP_CONT(__mask, fmt, ...)				\
110 do {								\
111 	if (unlikely(bp->msg_enable & (__mask)))		\
112 		pr_cont(fmt, ##__VA_ARGS__);			\
113 } while (0)
114 
115 /* errors debug print */
116 #define BNX2X_DBG_ERR(fmt, ...)					\
117 do {								\
118 	if (unlikely(netif_msg_probe(bp)))			\
119 		pr_err("[%s:%d(%s)]" fmt,			\
120 		       __func__, __LINE__,			\
121 		       bp->dev ? (bp->dev->name) : "?",		\
122 		       ##__VA_ARGS__);				\
123 } while (0)
124 
125 /* for errors (never masked) */
126 #define BNX2X_ERR(fmt, ...)					\
127 do {								\
128 	pr_err("[%s:%d(%s)]" fmt,				\
129 	       __func__, __LINE__,				\
130 	       bp->dev ? (bp->dev->name) : "?",			\
131 	       ##__VA_ARGS__);					\
132 } while (0)
133 
134 #define BNX2X_ERROR(fmt, ...)					\
135 	pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
136 
137 /* before we have a dev->name use dev_info() */
138 #define BNX2X_DEV_INFO(fmt, ...)				 \
139 do {								 \
140 	if (unlikely(netif_msg_probe(bp)))			 \
141 		dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__);	 \
142 } while (0)
143 
144 /* Error handling */
145 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
146 #ifdef BNX2X_STOP_ON_ERROR
147 #define bnx2x_panic()				\
148 do {						\
149 	bp->panic = 1;				\
150 	BNX2X_ERR("driver assert\n");		\
151 	bnx2x_panic_dump(bp, true);		\
152 } while (0)
153 #else
154 #define bnx2x_panic()				\
155 do {						\
156 	bp->panic = 1;				\
157 	BNX2X_ERR("driver assert\n");		\
158 	bnx2x_panic_dump(bp, false);		\
159 } while (0)
160 #endif
161 
162 #define bnx2x_mc_addr(ha)      ((ha)->addr)
163 #define bnx2x_uc_addr(ha)      ((ha)->addr)
164 
165 #define U64_LO(x)			((u32)(((u64)(x)) & 0xffffffff))
166 #define U64_HI(x)			((u32)(((u64)(x)) >> 32))
167 #define HILO_U64(hi, lo)		((((u64)(hi)) << 32) + (lo))
168 
169 #define REG_ADDR(bp, offset)		((bp->regview) + (offset))
170 
171 #define REG_RD(bp, offset)		readl(REG_ADDR(bp, offset))
172 #define REG_RD8(bp, offset)		readb(REG_ADDR(bp, offset))
173 #define REG_RD16(bp, offset)		readw(REG_ADDR(bp, offset))
174 
175 #define REG_WR_RELAXED(bp, offset, val)	\
176 	writel_relaxed((u32)val, REG_ADDR(bp, offset))
177 
178 #define REG_WR16_RELAXED(bp, offset, val) \
179 	writew_relaxed((u16)val, REG_ADDR(bp, offset))
180 
181 #define REG_WR(bp, offset, val)		writel((u32)val, REG_ADDR(bp, offset))
182 #define REG_WR8(bp, offset, val)	writeb((u8)val, REG_ADDR(bp, offset))
183 #define REG_WR16(bp, offset, val)	writew((u16)val, REG_ADDR(bp, offset))
184 
185 #define REG_RD_IND(bp, offset)		bnx2x_reg_rd_ind(bp, offset)
186 #define REG_WR_IND(bp, offset, val)	bnx2x_reg_wr_ind(bp, offset, val)
187 
188 #define REG_RD_DMAE(bp, offset, valp, len32) \
189 	do { \
190 		bnx2x_read_dmae(bp, offset, len32);\
191 		memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
192 	} while (0)
193 
194 #define REG_WR_DMAE(bp, offset, valp, len32) \
195 	do { \
196 		memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
197 		bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
198 				 offset, len32); \
199 	} while (0)
200 
201 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
202 	REG_WR_DMAE(bp, offset, valp, len32)
203 
204 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
205 	do { \
206 		memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
207 		bnx2x_write_big_buf_wb(bp, addr, len32); \
208 	} while (0)
209 
210 #define SHMEM_ADDR(bp, field)		(bp->common.shmem_base + \
211 					 offsetof(struct shmem_region, field))
212 #define SHMEM_RD(bp, field)		REG_RD(bp, SHMEM_ADDR(bp, field))
213 #define SHMEM_WR(bp, field, val)	REG_WR(bp, SHMEM_ADDR(bp, field), val)
214 
215 #define SHMEM2_ADDR(bp, field)		(bp->common.shmem2_base + \
216 					 offsetof(struct shmem2_region, field))
217 #define SHMEM2_RD(bp, field)		REG_RD(bp, SHMEM2_ADDR(bp, field))
218 #define SHMEM2_WR(bp, field, val)	REG_WR(bp, SHMEM2_ADDR(bp, field), val)
219 #define MF_CFG_ADDR(bp, field)		(bp->common.mf_cfg_base + \
220 					 offsetof(struct mf_cfg, field))
221 #define MF2_CFG_ADDR(bp, field)		(bp->common.mf2_cfg_base + \
222 					 offsetof(struct mf2_cfg, field))
223 
224 #define MF_CFG_RD(bp, field)		REG_RD(bp, MF_CFG_ADDR(bp, field))
225 #define MF_CFG_WR(bp, field, val)	REG_WR(bp,\
226 					       MF_CFG_ADDR(bp, field), (val))
227 #define MF2_CFG_RD(bp, field)		REG_RD(bp, MF2_CFG_ADDR(bp, field))
228 
229 #define SHMEM2_HAS(bp, field)		((bp)->common.shmem2_base &&	\
230 					 (SHMEM2_RD((bp), size) >	\
231 					 offsetof(struct shmem2_region, field)))
232 
233 #define EMAC_RD(bp, reg)		REG_RD(bp, emac_base + reg)
234 #define EMAC_WR(bp, reg, val)		REG_WR(bp, emac_base + reg, val)
235 
236 /* SP SB indices */
237 
238 /* General SP events - stats query, cfc delete, etc  */
239 #define HC_SP_INDEX_ETH_DEF_CONS		3
240 
241 /* EQ completions */
242 #define HC_SP_INDEX_EQ_CONS			7
243 
244 /* FCoE L2 connection completions */
245 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS		6
246 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS		4
247 /* iSCSI L2 */
248 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS		5
249 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS	1
250 
251 /* Special clients parameters */
252 
253 /* SB indices */
254 /* FCoE L2 */
255 #define BNX2X_FCOE_L2_RX_INDEX \
256 	(&bp->def_status_blk->sp_sb.\
257 	index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
258 
259 #define BNX2X_FCOE_L2_TX_INDEX \
260 	(&bp->def_status_blk->sp_sb.\
261 	index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
262 
263 /**
264  *  CIDs and CLIDs:
265  *  CLIDs below is a CLID for func 0, then the CLID for other
266  *  functions will be calculated by the formula:
267  *
268  *  FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
269  *
270  */
271 enum {
272 	BNX2X_ISCSI_ETH_CL_ID_IDX,
273 	BNX2X_FCOE_ETH_CL_ID_IDX,
274 	BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
275 };
276 
277 /* use a value high enough to be above all the PFs, which has least significant
278  * nibble as 8, so when cnic needs to come up with a CID for UIO to use to
279  * calculate doorbell address according to old doorbell configuration scheme
280  * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number
281  * We must avoid coming up with cid 8 for iscsi since according to this method
282  * the designated UIO cid will come out 0 and it has a special handling for that
283  * case which doesn't suit us. Therefore will will cieling to closes cid which
284  * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18.
285  */
286 
287 #define BNX2X_1st_NON_L2_ETH_CID(bp)	(BNX2X_NUM_NON_CNIC_QUEUES(bp) * \
288 					 (bp)->max_cos)
289 /* amount of cids traversed by UIO's DPM addition to doorbell */
290 #define UIO_DPM				8
291 /* roundup to DPM offset */
292 #define UIO_ROUNDUP(bp)			(roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \
293 					 UIO_DPM))
294 /* offset to nearest value which has lsb nibble matching DPM */
295 #define UIO_CID_OFFSET(bp)		((UIO_ROUNDUP(bp) + UIO_DPM) % \
296 					 (UIO_DPM * 2))
297 /* add offset to rounded-up cid to get a value which could be used with UIO */
298 #define UIO_DPM_ALIGN(bp)		(UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp))
299 /* but wait - avoid UIO special case for cid 0 */
300 #define UIO_DPM_CID0_OFFSET(bp)		((UIO_DPM * 2) * \
301 					 (UIO_DPM_ALIGN(bp) == UIO_DPM))
302 /* Properly DPM aligned CID dajusted to cid 0 secal case */
303 #define BNX2X_CNIC_START_ETH_CID(bp)	(UIO_DPM_ALIGN(bp) + \
304 					 (UIO_DPM_CID0_OFFSET(bp)))
305 /* how many cids were wasted  - need this value for cid allocation */
306 #define UIO_CID_PAD(bp)			(BNX2X_CNIC_START_ETH_CID(bp) - \
307 					 BNX2X_1st_NON_L2_ETH_CID(bp))
308 	/* iSCSI L2 */
309 #define	BNX2X_ISCSI_ETH_CID(bp)		(BNX2X_CNIC_START_ETH_CID(bp))
310 	/* FCoE L2 */
311 #define	BNX2X_FCOE_ETH_CID(bp)		(BNX2X_CNIC_START_ETH_CID(bp) + 1)
312 
313 #define CNIC_SUPPORT(bp)		((bp)->cnic_support)
314 #define CNIC_ENABLED(bp)		((bp)->cnic_enabled)
315 #define CNIC_LOADED(bp)			((bp)->cnic_loaded)
316 #define FCOE_INIT(bp)			((bp)->fcoe_init)
317 
318 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
319 	AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
320 
321 #define SM_RX_ID			0
322 #define SM_TX_ID			1
323 
324 /* defines for multiple tx priority indices */
325 #define FIRST_TX_ONLY_COS_INDEX		1
326 #define FIRST_TX_COS_INDEX		0
327 
328 /* rules for calculating the cids of tx-only connections */
329 #define CID_TO_FP(cid, bp)		((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
330 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
331 				(cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
332 
333 /* fp index inside class of service range */
334 #define FP_COS_TO_TXQ(fp, cos, bp) \
335 			((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
336 
337 /* Indexes for transmission queues array:
338  * txdata for RSS i CoS j is at location i + (j * num of RSS)
339  * txdata for FCoE (if exist) is at location max cos * num of RSS
340  * txdata for FWD (if exist) is one location after FCoE
341  * txdata for OOO (if exist) is one location after FWD
342  */
343 enum {
344 	FCOE_TXQ_IDX_OFFSET,
345 	FWD_TXQ_IDX_OFFSET,
346 	OOO_TXQ_IDX_OFFSET,
347 };
348 #define MAX_ETH_TXQ_IDX(bp)	(BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
349 #define FCOE_TXQ_IDX(bp)	(MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
350 
351 /* fast path */
352 /*
353  * This driver uses new build_skb() API :
354  * RX ring buffer contains pointer to kmalloc() data only,
355  * skb are built only after Hardware filled the frame.
356  */
357 struct sw_rx_bd {
358 	u8		*data;
359 	DEFINE_DMA_UNMAP_ADDR(mapping);
360 };
361 
362 struct sw_tx_bd {
363 	struct sk_buff	*skb;
364 	u16		first_bd;
365 	u8		flags;
366 /* Set on the first BD descriptor when there is a split BD */
367 #define BNX2X_TSO_SPLIT_BD		(1<<0)
368 #define BNX2X_HAS_SECOND_PBD		(1<<1)
369 };
370 
371 struct sw_rx_page {
372 	struct page	*page;
373 	DEFINE_DMA_UNMAP_ADDR(mapping);
374 	unsigned int	offset;
375 };
376 
377 union db_prod {
378 	struct doorbell_set_prod data;
379 	u32		raw;
380 };
381 
382 /* dropless fc FW/HW related params */
383 #define BRB_SIZE(bp)		(CHIP_IS_E3(bp) ? 1024 : 512)
384 #define MAX_AGG_QS(bp)		(CHIP_IS_E1(bp) ? \
385 					ETH_MAX_AGGREGATION_QUEUES_E1 :\
386 					ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
387 #define FW_DROP_LEVEL(bp)	(3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
388 #define FW_PREFETCH_CNT		16
389 #define DROPLESS_FC_HEADROOM	100
390 
391 /* MC hsi */
392 #define BCM_PAGE_SHIFT		12
393 #define BCM_PAGE_SIZE		(1 << BCM_PAGE_SHIFT)
394 #define BCM_PAGE_MASK		(~(BCM_PAGE_SIZE - 1))
395 #define BCM_PAGE_ALIGN(addr)	(((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
396 
397 #define PAGES_PER_SGE_SHIFT	0
398 #define PAGES_PER_SGE		(1 << PAGES_PER_SGE_SHIFT)
399 #define SGE_PAGE_SHIFT		12
400 #define SGE_PAGE_SIZE		(1 << SGE_PAGE_SHIFT)
401 #define SGE_PAGE_MASK		(~(SGE_PAGE_SIZE - 1))
402 #define SGE_PAGE_ALIGN(addr)	(((addr) + SGE_PAGE_SIZE - 1) & SGE_PAGE_MASK)
403 #define SGE_PAGES		(SGE_PAGE_SIZE * PAGES_PER_SGE)
404 #define TPA_AGG_SIZE		min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
405 					    SGE_PAGES), 0xffff)
406 
407 /* SGE ring related macros */
408 #define NUM_RX_SGE_PAGES	2
409 #define RX_SGE_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
410 #define NEXT_PAGE_SGE_DESC_CNT	2
411 #define MAX_RX_SGE_CNT		(RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
412 /* RX_SGE_CNT is promised to be a power of 2 */
413 #define RX_SGE_MASK		(RX_SGE_CNT - 1)
414 #define NUM_RX_SGE		(RX_SGE_CNT * NUM_RX_SGE_PAGES)
415 #define MAX_RX_SGE		(NUM_RX_SGE - 1)
416 #define NEXT_SGE_IDX(x)		((((x) & RX_SGE_MASK) == \
417 				  (MAX_RX_SGE_CNT - 1)) ? \
418 					(x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
419 					(x) + 1)
420 #define RX_SGE(x)		((x) & MAX_RX_SGE)
421 
422 /*
423  * Number of required  SGEs is the sum of two:
424  * 1. Number of possible opened aggregations (next packet for
425  *    these aggregations will probably consume SGE immediately)
426  * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
427  *    after placement on BD for new TPA aggregation)
428  *
429  * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
430  */
431 #define NUM_SGE_REQ		(MAX_AGG_QS(bp) + \
432 					(BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
433 #define NUM_SGE_PG_REQ		((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
434 						MAX_RX_SGE_CNT)
435 #define SGE_TH_LO(bp)		(NUM_SGE_REQ + \
436 				 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
437 #define SGE_TH_HI(bp)		(SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
438 
439 /* Manipulate a bit vector defined as an array of u64 */
440 
441 /* Number of bits in one sge_mask array element */
442 #define BIT_VEC64_ELEM_SZ		64
443 #define BIT_VEC64_ELEM_SHIFT		6
444 #define BIT_VEC64_ELEM_MASK		((u64)BIT_VEC64_ELEM_SZ - 1)
445 
446 #define __BIT_VEC64_SET_BIT(el, bit) \
447 	do { \
448 		el = ((el) | ((u64)0x1 << (bit))); \
449 	} while (0)
450 
451 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
452 	do { \
453 		el = ((el) & (~((u64)0x1 << (bit)))); \
454 	} while (0)
455 
456 #define BIT_VEC64_SET_BIT(vec64, idx) \
457 	__BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
458 			   (idx) & BIT_VEC64_ELEM_MASK)
459 
460 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
461 	__BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
462 			     (idx) & BIT_VEC64_ELEM_MASK)
463 
464 #define BIT_VEC64_TEST_BIT(vec64, idx) \
465 	(((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
466 	((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
467 
468 /* Creates a bitmask of all ones in less significant bits.
469    idx - index of the most significant bit in the created mask */
470 #define BIT_VEC64_ONES_MASK(idx) \
471 		(((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
472 #define BIT_VEC64_ELEM_ONE_MASK	((u64)(~0))
473 
474 /*******************************************************/
475 
476 /* Number of u64 elements in SGE mask array */
477 #define RX_SGE_MASK_LEN			(NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
478 #define RX_SGE_MASK_LEN_MASK		(RX_SGE_MASK_LEN - 1)
479 #define NEXT_SGE_MASK_ELEM(el)		(((el) + 1) & RX_SGE_MASK_LEN_MASK)
480 
481 union host_hc_status_block {
482 	/* pointer to fp status block e1x */
483 	struct host_hc_status_block_e1x *e1x_sb;
484 	/* pointer to fp status block e2 */
485 	struct host_hc_status_block_e2  *e2_sb;
486 };
487 
488 struct bnx2x_agg_info {
489 	/*
490 	 * First aggregation buffer is a data buffer, the following - are pages.
491 	 * We will preallocate the data buffer for each aggregation when
492 	 * we open the interface and will replace the BD at the consumer
493 	 * with this one when we receive the TPA_START CQE in order to
494 	 * keep the Rx BD ring consistent.
495 	 */
496 	struct sw_rx_bd		first_buf;
497 	u8			tpa_state;
498 #define BNX2X_TPA_START			1
499 #define BNX2X_TPA_STOP			2
500 #define BNX2X_TPA_ERROR			3
501 	u8			placement_offset;
502 	u16			parsing_flags;
503 	u16			vlan_tag;
504 	u16			len_on_bd;
505 	u32			rxhash;
506 	enum pkt_hash_types	rxhash_type;
507 	u16			gro_size;
508 	u16			full_page;
509 };
510 
511 #define Q_STATS_OFFSET32(stat_name) \
512 			(offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
513 
514 struct bnx2x_fp_txdata {
515 
516 	struct sw_tx_bd		*tx_buf_ring;
517 
518 	union eth_tx_bd_types	*tx_desc_ring;
519 	dma_addr_t		tx_desc_mapping;
520 
521 	u32			cid;
522 
523 	union db_prod		tx_db;
524 
525 	u16			tx_pkt_prod;
526 	u16			tx_pkt_cons;
527 	u16			tx_bd_prod;
528 	u16			tx_bd_cons;
529 
530 	unsigned long		tx_pkt;
531 
532 	__le16			*tx_cons_sb;
533 
534 	int			txq_index;
535 	struct bnx2x_fastpath	*parent_fp;
536 	int			tx_ring_size;
537 };
538 
539 enum bnx2x_tpa_mode_t {
540 	TPA_MODE_DISABLED,
541 	TPA_MODE_LRO,
542 	TPA_MODE_GRO
543 };
544 
545 struct bnx2x_alloc_pool {
546 	struct page	*page;
547 	unsigned int	offset;
548 };
549 
550 struct bnx2x_fastpath {
551 	struct bnx2x		*bp; /* parent */
552 
553 	struct napi_struct	napi;
554 
555 	union host_hc_status_block	status_blk;
556 	/* chip independent shortcuts into sb structure */
557 	__le16			*sb_index_values;
558 	__le16			*sb_running_index;
559 	/* chip independent shortcut into rx_prods_offset memory */
560 	u32			ustorm_rx_prods_offset;
561 
562 	u32			rx_buf_size;
563 	u32			rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
564 	dma_addr_t		status_blk_mapping;
565 
566 	enum bnx2x_tpa_mode_t	mode;
567 
568 	u8			max_cos; /* actual number of active tx coses */
569 	struct bnx2x_fp_txdata	*txdata_ptr[BNX2X_MULTI_TX_COS];
570 
571 	struct sw_rx_bd		*rx_buf_ring;	/* BDs mappings ring */
572 	struct sw_rx_page	*rx_page_ring;	/* SGE pages mappings ring */
573 
574 	struct eth_rx_bd	*rx_desc_ring;
575 	dma_addr_t		rx_desc_mapping;
576 
577 	union eth_rx_cqe	*rx_comp_ring;
578 	dma_addr_t		rx_comp_mapping;
579 
580 	/* SGE ring */
581 	struct eth_rx_sge	*rx_sge_ring;
582 	dma_addr_t		rx_sge_mapping;
583 
584 	u64			sge_mask[RX_SGE_MASK_LEN];
585 
586 	u32			cid;
587 
588 	__le16			fp_hc_idx;
589 
590 	u8			index;		/* number in fp array */
591 	u8			rx_queue;	/* index for skb_record */
592 	u8			cl_id;		/* eth client id */
593 	u8			cl_qzone_id;
594 	u8			fw_sb_id;	/* status block number in FW */
595 	u8			igu_sb_id;	/* status block number in HW */
596 
597 	u16			rx_bd_prod;
598 	u16			rx_bd_cons;
599 	u16			rx_comp_prod;
600 	u16			rx_comp_cons;
601 	u16			rx_sge_prod;
602 	/* The last maximal completed SGE */
603 	u16			last_max_sge;
604 	__le16			*rx_cons_sb;
605 
606 	/* TPA related */
607 	struct bnx2x_agg_info	*tpa_info;
608 #ifdef BNX2X_STOP_ON_ERROR
609 	u64			tpa_queue_used;
610 #endif
611 	/* The size is calculated using the following:
612 	     sizeof name field from netdev structure +
613 	     4 ('-Xx-' string) +
614 	     4 (for the digits and to make it DWORD aligned) */
615 #define FP_NAME_SIZE		(sizeof(((struct net_device *)0)->name) + 8)
616 	char			name[FP_NAME_SIZE];
617 
618 	struct bnx2x_alloc_pool	page_pool;
619 };
620 
621 #define bnx2x_fp(bp, nr, var)	((bp)->fp[(nr)].var)
622 #define bnx2x_sp_obj(bp, fp)	((bp)->sp_objs[(fp)->index])
623 #define bnx2x_fp_stats(bp, fp)	(&((bp)->fp_stats[(fp)->index]))
624 #define bnx2x_fp_qstats(bp, fp)	(&((bp)->fp_stats[(fp)->index].eth_q_stats))
625 
626 /* Use 2500 as a mini-jumbo MTU for FCoE */
627 #define BNX2X_FCOE_MINI_JUMBO_MTU	2500
628 
629 #define	FCOE_IDX_OFFSET		0
630 
631 #define FCOE_IDX(bp)		(BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
632 				 FCOE_IDX_OFFSET)
633 #define bnx2x_fcoe_fp(bp)	(&bp->fp[FCOE_IDX(bp)])
634 #define bnx2x_fcoe(bp, var)	(bnx2x_fcoe_fp(bp)->var)
635 #define bnx2x_fcoe_inner_sp_obj(bp)	(&bp->sp_objs[FCOE_IDX(bp)])
636 #define bnx2x_fcoe_sp_obj(bp, var)	(bnx2x_fcoe_inner_sp_obj(bp)->var)
637 #define bnx2x_fcoe_tx(bp, var)	(bnx2x_fcoe_fp(bp)-> \
638 						txdata_ptr[FIRST_TX_COS_INDEX] \
639 						->var)
640 
641 #define IS_ETH_FP(fp)		((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
642 #define IS_FCOE_FP(fp)		((fp)->index == FCOE_IDX((fp)->bp))
643 #define IS_FCOE_IDX(idx)	((idx) == FCOE_IDX(bp))
644 
645 /* MC hsi */
646 #define MAX_FETCH_BD		13	/* HW max BDs per packet */
647 #define RX_COPY_THRESH		92
648 
649 #define NUM_TX_RINGS		16
650 #define TX_DESC_CNT		(BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
651 #define NEXT_PAGE_TX_DESC_CNT	1
652 #define MAX_TX_DESC_CNT		(TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
653 #define NUM_TX_BD		(TX_DESC_CNT * NUM_TX_RINGS)
654 #define MAX_TX_BD		(NUM_TX_BD - 1)
655 #define MAX_TX_AVAIL		(MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
656 #define NEXT_TX_IDX(x)		((((x) & MAX_TX_DESC_CNT) == \
657 				  (MAX_TX_DESC_CNT - 1)) ? \
658 					(x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
659 					(x) + 1)
660 #define TX_BD(x)		((x) & MAX_TX_BD)
661 #define TX_BD_POFF(x)		((x) & MAX_TX_DESC_CNT)
662 
663 /* number of NEXT_PAGE descriptors may be required during placement */
664 #define NEXT_CNT_PER_TX_PKT(bds)	\
665 				(((bds) + MAX_TX_DESC_CNT - 1) / \
666 				 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
667 /* max BDs per tx packet w/o next_pages:
668  * START_BD		- describes packed
669  * START_BD(splitted)	- includes unpaged data segment for GSO
670  * PARSING_BD		- for TSO and CSUM data
671  * PARSING_BD2		- for encapsulation data
672  * Frag BDs		- describes pages for frags
673  */
674 #define BDS_PER_TX_PKT		4
675 #define MAX_BDS_PER_TX_PKT	(MAX_SKB_FRAGS + BDS_PER_TX_PKT)
676 /* max BDs per tx packet including next pages */
677 #define MAX_DESC_PER_TX_PKT	(MAX_BDS_PER_TX_PKT + \
678 				 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
679 
680 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
681 #define NUM_RX_RINGS		8
682 #define RX_DESC_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
683 #define NEXT_PAGE_RX_DESC_CNT	2
684 #define MAX_RX_DESC_CNT		(RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
685 #define RX_DESC_MASK		(RX_DESC_CNT - 1)
686 #define NUM_RX_BD		(RX_DESC_CNT * NUM_RX_RINGS)
687 #define MAX_RX_BD		(NUM_RX_BD - 1)
688 #define MAX_RX_AVAIL		(MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
689 
690 /* dropless fc calculations for BDs
691  *
692  * Number of BDs should as number of buffers in BRB:
693  * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
694  * "next" elements on each page
695  */
696 #define NUM_BD_REQ		BRB_SIZE(bp)
697 #define NUM_BD_PG_REQ		((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
698 					      MAX_RX_DESC_CNT)
699 #define BD_TH_LO(bp)		(NUM_BD_REQ + \
700 				 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
701 				 FW_DROP_LEVEL(bp))
702 #define BD_TH_HI(bp)		(BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
703 
704 #define MIN_RX_AVAIL		((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
705 
706 #define MIN_RX_SIZE_TPA_HW	(CHIP_IS_E1(bp) ? \
707 					ETH_MIN_RX_CQES_WITH_TPA_E1 : \
708 					ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
709 #define MIN_RX_SIZE_NONTPA_HW   ETH_MIN_RX_CQES_WITHOUT_TPA
710 #define MIN_RX_SIZE_TPA		(max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
711 #define MIN_RX_SIZE_NONTPA	(max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
712 								MIN_RX_AVAIL))
713 
714 #define NEXT_RX_IDX(x)		((((x) & RX_DESC_MASK) == \
715 				  (MAX_RX_DESC_CNT - 1)) ? \
716 					(x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
717 					(x) + 1)
718 #define RX_BD(x)		((x) & MAX_RX_BD)
719 
720 /*
721  * As long as CQE is X times bigger than BD entry we have to allocate X times
722  * more pages for CQ ring in order to keep it balanced with BD ring
723  */
724 #define CQE_BD_REL	(sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
725 #define NUM_RCQ_RINGS		(NUM_RX_RINGS * CQE_BD_REL)
726 #define RCQ_DESC_CNT		(BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
727 #define NEXT_PAGE_RCQ_DESC_CNT	1
728 #define MAX_RCQ_DESC_CNT	(RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
729 #define NUM_RCQ_BD		(RCQ_DESC_CNT * NUM_RCQ_RINGS)
730 #define MAX_RCQ_BD		(NUM_RCQ_BD - 1)
731 #define MAX_RCQ_AVAIL		(MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
732 #define NEXT_RCQ_IDX(x)		((((x) & MAX_RCQ_DESC_CNT) == \
733 				  (MAX_RCQ_DESC_CNT - 1)) ? \
734 					(x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
735 					(x) + 1)
736 #define RCQ_BD(x)		((x) & MAX_RCQ_BD)
737 
738 /* dropless fc calculations for RCQs
739  *
740  * Number of RCQs should be as number of buffers in BRB:
741  * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
742  * "next" elements on each page
743  */
744 #define NUM_RCQ_REQ		BRB_SIZE(bp)
745 #define NUM_RCQ_PG_REQ		((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
746 					      MAX_RCQ_DESC_CNT)
747 #define RCQ_TH_LO(bp)		(NUM_RCQ_REQ + \
748 				 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
749 				 FW_DROP_LEVEL(bp))
750 #define RCQ_TH_HI(bp)		(RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
751 
752 /* This is needed for determining of last_max */
753 #define SUB_S16(a, b)		(s16)((s16)(a) - (s16)(b))
754 #define SUB_S32(a, b)		(s32)((s32)(a) - (s32)(b))
755 
756 #define BNX2X_SWCID_SHIFT	17
757 #define BNX2X_SWCID_MASK	((0x1 << BNX2X_SWCID_SHIFT) - 1)
758 
759 /* used on a CID received from the HW */
760 #define SW_CID(x)			(le32_to_cpu(x) & BNX2X_SWCID_MASK)
761 #define CQE_CMD(x)			(le32_to_cpu(x) >> \
762 					COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
763 
764 #define BD_UNMAP_ADDR(bd)		HILO_U64(le32_to_cpu((bd)->addr_hi), \
765 						 le32_to_cpu((bd)->addr_lo))
766 #define BD_UNMAP_LEN(bd)		(le16_to_cpu((bd)->nbytes))
767 
768 #define BNX2X_DB_MIN_SHIFT		3	/* 8 bytes */
769 #define BNX2X_DB_SHIFT			3	/* 8 bytes*/
770 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
771 #error "Min DB doorbell stride is 8"
772 #endif
773 #define DOORBELL_RELAXED(bp, cid, val) \
774 	writel_relaxed((u32)(val), (bp)->doorbells + ((bp)->db_size * (cid)))
775 
776 /* TX CSUM helpers */
777 #define SKB_CS_OFF(skb)		(offsetof(struct tcphdr, check) - \
778 				 skb->csum_offset)
779 #define SKB_CS(skb)		(*(u16 *)(skb_transport_header(skb) + \
780 					  skb->csum_offset))
781 
782 #define pbd_tcp_flags(tcp_hdr)	(ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
783 
784 #define XMIT_PLAIN		0
785 #define XMIT_CSUM_V4		(1 << 0)
786 #define XMIT_CSUM_V6		(1 << 1)
787 #define XMIT_CSUM_TCP		(1 << 2)
788 #define XMIT_GSO_V4		(1 << 3)
789 #define XMIT_GSO_V6		(1 << 4)
790 #define XMIT_CSUM_ENC_V4	(1 << 5)
791 #define XMIT_CSUM_ENC_V6	(1 << 6)
792 #define XMIT_GSO_ENC_V4		(1 << 7)
793 #define XMIT_GSO_ENC_V6		(1 << 8)
794 
795 #define XMIT_CSUM_ENC		(XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6)
796 #define XMIT_GSO_ENC		(XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6)
797 
798 #define XMIT_CSUM		(XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC)
799 #define XMIT_GSO		(XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC)
800 
801 /* stuff added to make the code fit 80Col */
802 #define CQE_TYPE(cqe_fp_flags)	 ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
803 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
804 #define CQE_TYPE_STOP(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
805 #define CQE_TYPE_SLOW(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
806 #define CQE_TYPE_FAST(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
807 
808 #define ETH_RX_ERROR_FALGS		ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
809 
810 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
811 				(((le16_to_cpu(flags) & \
812 				   PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
813 				  PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
814 				 == PRS_FLAG_OVERETH_IPV4)
815 #define BNX2X_RX_SUM_FIX(cqe) \
816 	BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
817 
818 #define FP_USB_FUNC_OFF	\
819 			offsetof(struct cstorm_status_block_u, func)
820 #define FP_CSB_FUNC_OFF	\
821 			offsetof(struct cstorm_status_block_c, func)
822 
823 #define HC_INDEX_ETH_RX_CQ_CONS		1
824 
825 #define HC_INDEX_OOO_TX_CQ_CONS		4
826 
827 #define HC_INDEX_ETH_TX_CQ_CONS_COS0	5
828 
829 #define HC_INDEX_ETH_TX_CQ_CONS_COS1	6
830 
831 #define HC_INDEX_ETH_TX_CQ_CONS_COS2	7
832 
833 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS	HC_INDEX_ETH_TX_CQ_CONS_COS0
834 
835 #define BNX2X_RX_SB_INDEX \
836 	(&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
837 
838 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
839 
840 #define BNX2X_TX_SB_INDEX_COS0 \
841 	(&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
842 
843 /* end of fast path */
844 
845 /* common */
846 
847 struct bnx2x_common {
848 
849 	u32			chip_id;
850 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
851 #define CHIP_ID(bp)			(bp->common.chip_id & 0xfffffff0)
852 
853 #define CHIP_NUM(bp)			(bp->common.chip_id >> 16)
854 #define CHIP_NUM_57710			0x164e
855 #define CHIP_NUM_57711			0x164f
856 #define CHIP_NUM_57711E			0x1650
857 #define CHIP_NUM_57712			0x1662
858 #define CHIP_NUM_57712_MF		0x1663
859 #define CHIP_NUM_57712_VF		0x166f
860 #define CHIP_NUM_57713			0x1651
861 #define CHIP_NUM_57713E			0x1652
862 #define CHIP_NUM_57800			0x168a
863 #define CHIP_NUM_57800_MF		0x16a5
864 #define CHIP_NUM_57800_VF		0x16a9
865 #define CHIP_NUM_57810			0x168e
866 #define CHIP_NUM_57810_MF		0x16ae
867 #define CHIP_NUM_57810_VF		0x16af
868 #define CHIP_NUM_57811			0x163d
869 #define CHIP_NUM_57811_MF		0x163e
870 #define CHIP_NUM_57811_VF		0x163f
871 #define CHIP_NUM_57840_OBSOLETE		0x168d
872 #define CHIP_NUM_57840_MF_OBSOLETE	0x16ab
873 #define CHIP_NUM_57840_4_10		0x16a1
874 #define CHIP_NUM_57840_2_20		0x16a2
875 #define CHIP_NUM_57840_MF		0x16a4
876 #define CHIP_NUM_57840_VF		0x16ad
877 #define CHIP_IS_E1(bp)			(CHIP_NUM(bp) == CHIP_NUM_57710)
878 #define CHIP_IS_57711(bp)		(CHIP_NUM(bp) == CHIP_NUM_57711)
879 #define CHIP_IS_57711E(bp)		(CHIP_NUM(bp) == CHIP_NUM_57711E)
880 #define CHIP_IS_57712(bp)		(CHIP_NUM(bp) == CHIP_NUM_57712)
881 #define CHIP_IS_57712_VF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57712_VF)
882 #define CHIP_IS_57712_MF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57712_MF)
883 #define CHIP_IS_57800(bp)		(CHIP_NUM(bp) == CHIP_NUM_57800)
884 #define CHIP_IS_57800_MF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57800_MF)
885 #define CHIP_IS_57800_VF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57800_VF)
886 #define CHIP_IS_57810(bp)		(CHIP_NUM(bp) == CHIP_NUM_57810)
887 #define CHIP_IS_57810_MF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57810_MF)
888 #define CHIP_IS_57810_VF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57810_VF)
889 #define CHIP_IS_57811(bp)		(CHIP_NUM(bp) == CHIP_NUM_57811)
890 #define CHIP_IS_57811_MF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57811_MF)
891 #define CHIP_IS_57811_VF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57811_VF)
892 #define CHIP_IS_57840(bp)		\
893 		((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
894 		 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
895 		 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
896 #define CHIP_IS_57840_MF(bp)	((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
897 				 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
898 #define CHIP_IS_57840_VF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57840_VF)
899 #define CHIP_IS_E1H(bp)			(CHIP_IS_57711(bp) || \
900 					 CHIP_IS_57711E(bp))
901 #define CHIP_IS_57811xx(bp)		(CHIP_IS_57811(bp) || \
902 					 CHIP_IS_57811_MF(bp) || \
903 					 CHIP_IS_57811_VF(bp))
904 #define CHIP_IS_E2(bp)			(CHIP_IS_57712(bp) || \
905 					 CHIP_IS_57712_MF(bp) || \
906 					 CHIP_IS_57712_VF(bp))
907 #define CHIP_IS_E3(bp)			(CHIP_IS_57800(bp) || \
908 					 CHIP_IS_57800_MF(bp) || \
909 					 CHIP_IS_57800_VF(bp) || \
910 					 CHIP_IS_57810(bp) || \
911 					 CHIP_IS_57810_MF(bp) || \
912 					 CHIP_IS_57810_VF(bp) || \
913 					 CHIP_IS_57811xx(bp) || \
914 					 CHIP_IS_57840(bp) || \
915 					 CHIP_IS_57840_MF(bp) || \
916 					 CHIP_IS_57840_VF(bp))
917 #define CHIP_IS_E1x(bp)			(CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
918 #define USES_WARPCORE(bp)		(CHIP_IS_E3(bp))
919 #define IS_E1H_OFFSET			(!CHIP_IS_E1(bp))
920 
921 #define CHIP_REV_SHIFT			12
922 #define CHIP_REV_MASK			(0xF << CHIP_REV_SHIFT)
923 #define CHIP_REV_VAL(bp)		(bp->common.chip_id & CHIP_REV_MASK)
924 #define CHIP_REV_Ax			(0x0 << CHIP_REV_SHIFT)
925 #define CHIP_REV_Bx			(0x1 << CHIP_REV_SHIFT)
926 /* assume maximum 5 revisions */
927 #define CHIP_REV_IS_SLOW(bp)		(CHIP_REV_VAL(bp) > 0x00005000)
928 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
929 #define CHIP_REV_IS_EMUL(bp)		((CHIP_REV_IS_SLOW(bp)) && \
930 					 !(CHIP_REV_VAL(bp) & 0x00001000))
931 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
932 #define CHIP_REV_IS_FPGA(bp)		((CHIP_REV_IS_SLOW(bp)) && \
933 					 (CHIP_REV_VAL(bp) & 0x00001000))
934 
935 #define CHIP_TIME(bp)			((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
936 					((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
937 
938 #define CHIP_METAL(bp)			(bp->common.chip_id & 0x00000ff0)
939 #define CHIP_BOND_ID(bp)		(bp->common.chip_id & 0x0000000f)
940 #define CHIP_REV_SIM(bp)		(((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
941 					   (CHIP_REV_SHIFT + 1)) \
942 						<< CHIP_REV_SHIFT)
943 #define CHIP_REV(bp)			(CHIP_REV_IS_SLOW(bp) ? \
944 						CHIP_REV_SIM(bp) :\
945 						CHIP_REV_VAL(bp))
946 #define CHIP_IS_E3B0(bp)		(CHIP_IS_E3(bp) && \
947 					 (CHIP_REV(bp) == CHIP_REV_Bx))
948 #define CHIP_IS_E3A0(bp)		(CHIP_IS_E3(bp) && \
949 					 (CHIP_REV(bp) == CHIP_REV_Ax))
950 /* This define is used in two main places:
951  * 1. In the early stages of nic_load, to know if to configure Parser / Searcher
952  * to nic-only mode or to offload mode. Offload mode is configured if either the
953  * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
954  * registered for this port (which means that the user wants storage services).
955  * 2. During cnic-related load, to know if offload mode is already configured in
956  * the HW or needs to be configured.
957  * Since the transition from nic-mode to offload-mode in HW causes traffic
958  * corruption, nic-mode is configured only in ports on which storage services
959  * where never requested.
960  */
961 #define CONFIGURE_NIC_MODE(bp)		(!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
962 
963 	int			flash_size;
964 #define BNX2X_NVRAM_1MB_SIZE			0x20000	/* 1M bit in bytes */
965 #define BNX2X_NVRAM_TIMEOUT_COUNT		30000
966 #define BNX2X_NVRAM_PAGE_SIZE			256
967 
968 	u32			shmem_base;
969 	u32			shmem2_base;
970 	u32			mf_cfg_base;
971 	u32			mf2_cfg_base;
972 
973 	u32			hw_config;
974 
975 	u32			bc_ver;
976 
977 	u8			int_block;
978 #define INT_BLOCK_HC			0
979 #define INT_BLOCK_IGU			1
980 #define INT_BLOCK_MODE_NORMAL		0
981 #define INT_BLOCK_MODE_BW_COMP		2
982 #define CHIP_INT_MODE_IS_NBC(bp)		\
983 			(!CHIP_IS_E1x(bp) &&	\
984 			!((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
985 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
986 
987 	u8			chip_port_mode;
988 #define CHIP_4_PORT_MODE			0x0
989 #define CHIP_2_PORT_MODE			0x1
990 #define CHIP_PORT_MODE_NONE			0x2
991 #define CHIP_MODE(bp)			(bp->common.chip_port_mode)
992 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
993 
994 	u32			boot_mode;
995 };
996 
997 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
998 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
999 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
1000 
1001 #define MAX_IGU_ATTN_ACK_TO       100
1002 /* end of common */
1003 
1004 /* port */
1005 
1006 struct bnx2x_port {
1007 	u32			pmf;
1008 
1009 	u32			link_config[LINK_CONFIG_SIZE];
1010 
1011 	u32			supported[LINK_CONFIG_SIZE];
1012 
1013 	u32			advertising[LINK_CONFIG_SIZE];
1014 
1015 	u32			phy_addr;
1016 
1017 	/* used to synchronize phy accesses */
1018 	struct mutex		phy_mutex;
1019 
1020 	u32			port_stx;
1021 
1022 	struct nig_stats	old_nig_stats;
1023 };
1024 
1025 /* end of port */
1026 
1027 #define STATS_OFFSET32(stat_name) \
1028 			(offsetof(struct bnx2x_eth_stats, stat_name) / 4)
1029 
1030 /* slow path */
1031 #define BNX2X_MAX_NUM_OF_VFS	64
1032 #define BNX2X_VF_CID_WND	4 /* log num of queues per VF. HW config. */
1033 #define BNX2X_CIDS_PER_VF	(1 << BNX2X_VF_CID_WND)
1034 
1035 /* We need to reserve doorbell addresses for all VF and queue combinations */
1036 #define BNX2X_VF_CIDS		(BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
1037 
1038 /* The doorbell is configured to have the same number of CIDs for PFs and for
1039  * VFs. For this reason the PF CID zone is as large as the VF zone.
1040  */
1041 #define BNX2X_FIRST_VF_CID	BNX2X_VF_CIDS
1042 #define BNX2X_MAX_NUM_VF_QUEUES	64
1043 #define BNX2X_VF_ID_INVALID	0xFF
1044 
1045 /* the number of VF CIDS multiplied by the amount of bytes reserved for each
1046  * cid must not exceed the size of the VF doorbell
1047  */
1048 #define BNX2X_VF_BAR_SIZE	512
1049 #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT))
1050 #error "VF doorbell bar size is 512"
1051 #endif
1052 
1053 /*
1054  * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
1055  * control by the number of fast-path status blocks supported by the
1056  * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
1057  * status block represents an independent interrupts context that can
1058  * serve a regular L2 networking queue. However special L2 queues such
1059  * as the FCoE queue do not require a FP-SB and other components like
1060  * the CNIC may consume FP-SB reducing the number of possible L2 queues
1061  *
1062  * If the maximum number of FP-SB available is X then:
1063  * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
1064  *    regular L2 queues is Y=X-1
1065  * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
1066  * c. If the FCoE L2 queue is supported the actual number of L2 queues
1067  *    is Y+1
1068  * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
1069  *    slow-path interrupts) or Y+2 if CNIC is supported (one additional
1070  *    FP interrupt context for the CNIC).
1071  * e. The number of HW context (CID count) is always X or X+1 if FCoE
1072  *    L2 queue is supported. The cid for the FCoE L2 queue is always X.
1073  */
1074 
1075 /* fast-path interrupt contexts E1x */
1076 #define FP_SB_MAX_E1x		16
1077 /* fast-path interrupt contexts E2 */
1078 #define FP_SB_MAX_E2		HC_SB_MAX_SB_E2
1079 
1080 union cdu_context {
1081 	struct eth_context eth;
1082 	char pad[1024];
1083 };
1084 
1085 /* CDU host DB constants */
1086 #define CDU_ILT_PAGE_SZ_HW	2
1087 #define CDU_ILT_PAGE_SZ		(8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1088 #define ILT_PAGE_CIDS		(CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1089 
1090 #define CNIC_ISCSI_CID_MAX	256
1091 #define CNIC_FCOE_CID_MAX	2048
1092 #define CNIC_CID_MAX		(CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1093 #define CNIC_ILT_LINES		DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1094 
1095 #define QM_ILT_PAGE_SZ_HW	0
1096 #define QM_ILT_PAGE_SZ		(4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1097 #define QM_CID_ROUND		1024
1098 
1099 /* TM (timers) host DB constants */
1100 #define TM_ILT_PAGE_SZ_HW	0
1101 #define TM_ILT_PAGE_SZ		(4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1102 #define TM_CONN_NUM		(BNX2X_FIRST_VF_CID + \
1103 				 BNX2X_VF_CIDS + \
1104 				 CNIC_ISCSI_CID_MAX)
1105 #define TM_ILT_SZ		(8 * TM_CONN_NUM)
1106 #define TM_ILT_LINES		DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1107 
1108 /* SRC (Searcher) host DB constants */
1109 #define SRC_ILT_PAGE_SZ_HW	0
1110 #define SRC_ILT_PAGE_SZ		(4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1111 #define SRC_HASH_BITS		10
1112 #define SRC_CONN_NUM		(1 << SRC_HASH_BITS) /* 1024 */
1113 #define SRC_ILT_SZ		(sizeof(struct src_ent) * SRC_CONN_NUM)
1114 #define SRC_T2_SZ		SRC_ILT_SZ
1115 #define SRC_ILT_LINES		DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1116 
1117 #define MAX_DMAE_C		8
1118 
1119 /* DMA memory not used in fastpath */
1120 struct bnx2x_slowpath {
1121 	union {
1122 		struct mac_configuration_cmd		e1x;
1123 		struct eth_classify_rules_ramrod_data	e2;
1124 	} mac_rdata;
1125 
1126 	union {
1127 		struct eth_classify_rules_ramrod_data	e2;
1128 	} vlan_rdata;
1129 
1130 	union {
1131 		struct tstorm_eth_mac_filter_config	e1x;
1132 		struct eth_filter_rules_ramrod_data	e2;
1133 	} rx_mode_rdata;
1134 
1135 	union {
1136 		struct mac_configuration_cmd		e1;
1137 		struct eth_multicast_rules_ramrod_data  e2;
1138 	} mcast_rdata;
1139 
1140 	struct eth_rss_update_ramrod_data	rss_rdata;
1141 
1142 	/* Queue State related ramrods are always sent under rtnl_lock */
1143 	union {
1144 		struct client_init_ramrod_data  init_data;
1145 		struct client_update_ramrod_data update_data;
1146 		struct tpa_update_ramrod_data tpa_data;
1147 	} q_rdata;
1148 
1149 	union {
1150 		struct function_start_data	func_start;
1151 		/* pfc configuration for DCBX ramrod */
1152 		struct flow_control_configuration pfc_config;
1153 	} func_rdata;
1154 
1155 	/* afex ramrod can not be a part of func_rdata union because these
1156 	 * events might arrive in parallel to other events from func_rdata.
1157 	 * Therefore, if they would have been defined in the same union,
1158 	 * data can get corrupted.
1159 	 */
1160 	union {
1161 		struct afex_vif_list_ramrod_data	viflist_data;
1162 		struct function_update_data		func_update;
1163 	} func_afex_rdata;
1164 
1165 	/* used by dmae command executer */
1166 	struct dmae_command		dmae[MAX_DMAE_C];
1167 
1168 	u32				stats_comp;
1169 	union mac_stats			mac_stats;
1170 	struct nig_stats		nig_stats;
1171 	struct host_port_stats		port_stats;
1172 	struct host_func_stats		func_stats;
1173 
1174 	u32				wb_comp;
1175 	u32				wb_data[4];
1176 
1177 	union drv_info_to_mcp		drv_info_to_mcp;
1178 };
1179 
1180 #define bnx2x_sp(bp, var)		(&bp->slowpath->var)
1181 #define bnx2x_sp_mapping(bp, var) \
1182 		(bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1183 
1184 /* attn group wiring */
1185 #define MAX_DYNAMIC_ATTN_GRPS		8
1186 
1187 struct attn_route {
1188 	u32 sig[5];
1189 };
1190 
1191 struct iro {
1192 	u32 base;
1193 	u16 m1;
1194 	u16 m2;
1195 	u16 m3;
1196 	u16 size;
1197 };
1198 
1199 struct hw_context {
1200 	union cdu_context *vcxt;
1201 	dma_addr_t cxt_mapping;
1202 	size_t size;
1203 };
1204 
1205 /* forward */
1206 struct bnx2x_ilt;
1207 
1208 struct bnx2x_vfdb;
1209 
1210 enum bnx2x_recovery_state {
1211 	BNX2X_RECOVERY_DONE,
1212 	BNX2X_RECOVERY_INIT,
1213 	BNX2X_RECOVERY_WAIT,
1214 	BNX2X_RECOVERY_FAILED,
1215 	BNX2X_RECOVERY_NIC_LOADING
1216 };
1217 
1218 /*
1219  * Event queue (EQ or event ring) MC hsi
1220  * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1221  */
1222 #define NUM_EQ_PAGES		1
1223 #define EQ_DESC_CNT_PAGE	(BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1224 #define EQ_DESC_MAX_PAGE	(EQ_DESC_CNT_PAGE - 1)
1225 #define NUM_EQ_DESC		(EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1226 #define EQ_DESC_MASK		(NUM_EQ_DESC - 1)
1227 #define MAX_EQ_AVAIL		(EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1228 
1229 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1230 #define NEXT_EQ_IDX(x)		((((x) & EQ_DESC_MAX_PAGE) == \
1231 				  (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1232 
1233 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1234 #define EQ_DESC(x)		((x) & EQ_DESC_MASK)
1235 
1236 #define BNX2X_EQ_INDEX \
1237 	(&bp->def_status_blk->sp_sb.\
1238 	index_values[HC_SP_INDEX_EQ_CONS])
1239 
1240 /* This is a data that will be used to create a link report message.
1241  * We will keep the data used for the last link report in order
1242  * to prevent reporting the same link parameters twice.
1243  */
1244 struct bnx2x_link_report_data {
1245 	u16 line_speed;			/* Effective line speed */
1246 	unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1247 };
1248 
1249 enum {
1250 	BNX2X_LINK_REPORT_FD,		/* Full DUPLEX */
1251 	BNX2X_LINK_REPORT_LINK_DOWN,
1252 	BNX2X_LINK_REPORT_RX_FC_ON,
1253 	BNX2X_LINK_REPORT_TX_FC_ON,
1254 };
1255 
1256 enum {
1257 	BNX2X_PORT_QUERY_IDX,
1258 	BNX2X_PF_QUERY_IDX,
1259 	BNX2X_FCOE_QUERY_IDX,
1260 	BNX2X_FIRST_QUEUE_QUERY_IDX,
1261 };
1262 
1263 struct bnx2x_fw_stats_req {
1264 	struct stats_query_header hdr;
1265 	struct stats_query_entry query[FP_SB_MAX_E1x+
1266 		BNX2X_FIRST_QUEUE_QUERY_IDX];
1267 };
1268 
1269 struct bnx2x_fw_stats_data {
1270 	struct stats_counter		storm_counters;
1271 	struct per_port_stats		port;
1272 	struct per_pf_stats		pf;
1273 	struct fcoe_statistics_params	fcoe;
1274 	struct per_queue_stats		queue_stats[];
1275 };
1276 
1277 /* Public slow path states */
1278 enum sp_rtnl_flag {
1279 	BNX2X_SP_RTNL_SETUP_TC,
1280 	BNX2X_SP_RTNL_TX_TIMEOUT,
1281 	BNX2X_SP_RTNL_FAN_FAILURE,
1282 	BNX2X_SP_RTNL_AFEX_F_UPDATE,
1283 	BNX2X_SP_RTNL_ENABLE_SRIOV,
1284 	BNX2X_SP_RTNL_VFPF_MCAST,
1285 	BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
1286 	BNX2X_SP_RTNL_RX_MODE,
1287 	BNX2X_SP_RTNL_HYPERVISOR_VLAN,
1288 	BNX2X_SP_RTNL_TX_STOP,
1289 	BNX2X_SP_RTNL_GET_DRV_VERSION,
1290 	BNX2X_SP_RTNL_UPDATE_SVID,
1291 };
1292 
1293 enum bnx2x_iov_flag {
1294 	BNX2X_IOV_HANDLE_VF_MSG,
1295 	BNX2X_IOV_HANDLE_FLR,
1296 };
1297 
1298 struct bnx2x_prev_path_list {
1299 	struct list_head list;
1300 	u8 bus;
1301 	u8 slot;
1302 	u8 path;
1303 	u8 aer;
1304 	u8 undi;
1305 };
1306 
1307 struct bnx2x_sp_objs {
1308 	/* MACs object */
1309 	struct bnx2x_vlan_mac_obj mac_obj;
1310 
1311 	/* Queue State object */
1312 	struct bnx2x_queue_sp_obj q_obj;
1313 
1314 	/* VLANs object */
1315 	struct bnx2x_vlan_mac_obj vlan_obj;
1316 };
1317 
1318 struct bnx2x_fp_stats {
1319 	struct tstorm_per_queue_stats old_tclient;
1320 	struct ustorm_per_queue_stats old_uclient;
1321 	struct xstorm_per_queue_stats old_xclient;
1322 	struct bnx2x_eth_q_stats eth_q_stats;
1323 	struct bnx2x_eth_q_stats_old eth_q_stats_old;
1324 };
1325 
1326 enum {
1327 	SUB_MF_MODE_UNKNOWN = 0,
1328 	SUB_MF_MODE_UFP,
1329 	SUB_MF_MODE_NPAR1_DOT_5,
1330 	SUB_MF_MODE_BD,
1331 };
1332 
1333 struct bnx2x_vlan_entry {
1334 	struct list_head link;
1335 	u16 vid;
1336 	bool hw;
1337 };
1338 
1339 enum bnx2x_udp_port_type {
1340 	BNX2X_UDP_PORT_VXLAN,
1341 	BNX2X_UDP_PORT_GENEVE,
1342 	BNX2X_UDP_PORT_MAX,
1343 };
1344 
1345 struct bnx2x {
1346 	/* Fields used in the tx and intr/napi performance paths
1347 	 * are grouped together in the beginning of the structure
1348 	 */
1349 	struct bnx2x_fastpath	*fp;
1350 	struct bnx2x_sp_objs	*sp_objs;
1351 	struct bnx2x_fp_stats	*fp_stats;
1352 	struct bnx2x_fp_txdata	*bnx2x_txq;
1353 	void __iomem		*regview;
1354 	void __iomem		*doorbells;
1355 	u16			db_size;
1356 
1357 	u8			pf_num;	/* absolute PF number */
1358 	u8			pfid;	/* per-path PF number */
1359 	int			base_fw_ndsb; /**/
1360 #define BP_PATH(bp)			(CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1361 #define BP_PORT(bp)			(bp->pfid & 1)
1362 #define BP_FUNC(bp)			(bp->pfid)
1363 #define BP_ABS_FUNC(bp)			(bp->pf_num)
1364 #define BP_VN(bp)			((bp)->pfid >> 1)
1365 #define BP_MAX_VN_NUM(bp)		(CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1366 #define BP_L_ID(bp)			(BP_VN(bp) << 2)
1367 #define BP_FW_MB_IDX_VN(bp, vn)		(BP_PORT(bp) +\
1368 	  (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2  : 1))
1369 #define BP_FW_MB_IDX(bp)		BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1370 
1371 #ifdef CONFIG_BNX2X_SRIOV
1372 	/* protects vf2pf mailbox from simultaneous access */
1373 	struct mutex		vf2pf_mutex;
1374 	/* vf pf channel mailbox contains request and response buffers */
1375 	struct bnx2x_vf_mbx_msg	*vf2pf_mbox;
1376 	dma_addr_t		vf2pf_mbox_mapping;
1377 
1378 	/* we set aside a copy of the acquire response */
1379 	struct pfvf_acquire_resp_tlv acquire_resp;
1380 
1381 	/* bulletin board for messages from pf to vf */
1382 	union pf_vf_bulletin   *pf2vf_bulletin;
1383 	dma_addr_t		pf2vf_bulletin_mapping;
1384 
1385 	union pf_vf_bulletin		shadow_bulletin;
1386 	struct pf_vf_bulletin_content	old_bulletin;
1387 
1388 	u16 requested_nr_virtfn;
1389 #endif /* CONFIG_BNX2X_SRIOV */
1390 
1391 	struct net_device	*dev;
1392 	struct pci_dev		*pdev;
1393 
1394 	const struct iro	*iro_arr;
1395 #define IRO (bp->iro_arr)
1396 
1397 	enum bnx2x_recovery_state recovery_state;
1398 	int			is_leader;
1399 	struct msix_entry	*msix_table;
1400 
1401 	int			tx_ring_size;
1402 
1403 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1404 #define ETH_OVERHEAD		(ETH_HLEN + 8 + 8)
1405 #define ETH_MIN_PACKET_SIZE		(ETH_ZLEN - ETH_HLEN)
1406 #define ETH_MAX_PACKET_SIZE		ETH_DATA_LEN
1407 #define ETH_MAX_JUMBO_PACKET_SIZE	9600
1408 /* TCP with Timestamp Option (32) + IPv6 (40) */
1409 #define ETH_MAX_TPA_HEADER_SIZE		72
1410 
1411 	/* Max supported alignment is 256 (8 shift)
1412 	 * minimal alignment shift 6 is optimal for 57xxx HW performance
1413 	 */
1414 #define BNX2X_RX_ALIGN_SHIFT		max(6, min(8, L1_CACHE_SHIFT))
1415 
1416 	/* FW uses 2 Cache lines Alignment for start packet and size
1417 	 *
1418 	 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1419 	 * at the end of skb->data, to avoid wasting a full cache line.
1420 	 * This reduces memory use (skb->truesize).
1421 	 */
1422 #define BNX2X_FW_RX_ALIGN_START	(1UL << BNX2X_RX_ALIGN_SHIFT)
1423 
1424 #define BNX2X_FW_RX_ALIGN_END					\
1425 	max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT,			\
1426 	    SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1427 
1428 #define BNX2X_PXP_DRAM_ALIGN		(BNX2X_RX_ALIGN_SHIFT - 5)
1429 
1430 	struct host_sp_status_block *def_status_blk;
1431 #define DEF_SB_IGU_ID			16
1432 #define DEF_SB_ID			HC_SP_SB_ID
1433 	__le16			def_idx;
1434 	__le16			def_att_idx;
1435 	u32			attn_state;
1436 	struct attn_route	attn_group[MAX_DYNAMIC_ATTN_GRPS];
1437 
1438 	/* slow path ring */
1439 	struct eth_spe		*spq;
1440 	dma_addr_t		spq_mapping;
1441 	u16			spq_prod_idx;
1442 	struct eth_spe		*spq_prod_bd;
1443 	struct eth_spe		*spq_last_bd;
1444 	__le16			*dsb_sp_prod;
1445 	atomic_t		cq_spq_left; /* ETH_XXX ramrods credit */
1446 	/* used to synchronize spq accesses */
1447 	spinlock_t		spq_lock;
1448 
1449 	/* event queue */
1450 	union event_ring_elem	*eq_ring;
1451 	dma_addr_t		eq_mapping;
1452 	u16			eq_prod;
1453 	u16			eq_cons;
1454 	__le16			*eq_cons_sb;
1455 	atomic_t		eq_spq_left; /* COMMON_XXX ramrods credit */
1456 
1457 	/* Counter for marking that there is a STAT_QUERY ramrod pending */
1458 	u16			stats_pending;
1459 	/*  Counter for completed statistics ramrods */
1460 	u16			stats_comp;
1461 
1462 	/* End of fields used in the performance code paths */
1463 
1464 	int			panic;
1465 	int			msg_enable;
1466 
1467 	u32			flags;
1468 #define PCIX_FLAG			(1 << 0)
1469 #define PCI_32BIT_FLAG			(1 << 1)
1470 #define ONE_PORT_FLAG			(1 << 2)
1471 #define NO_WOL_FLAG			(1 << 3)
1472 #define USING_MSIX_FLAG			(1 << 5)
1473 #define USING_MSI_FLAG			(1 << 6)
1474 #define DISABLE_MSI_FLAG		(1 << 7)
1475 #define NO_MCP_FLAG			(1 << 9)
1476 #define MF_FUNC_DIS			(1 << 11)
1477 #define OWN_CNIC_IRQ			(1 << 12)
1478 #define NO_ISCSI_OOO_FLAG		(1 << 13)
1479 #define NO_ISCSI_FLAG			(1 << 14)
1480 #define NO_FCOE_FLAG			(1 << 15)
1481 #define BC_SUPPORTS_PFC_STATS		(1 << 17)
1482 #define TX_SWITCHING			(1 << 18)
1483 #define BC_SUPPORTS_FCOE_FEATURES	(1 << 19)
1484 #define USING_SINGLE_MSIX_FLAG		(1 << 20)
1485 #define BC_SUPPORTS_DCBX_MSG_NON_PMF	(1 << 21)
1486 #define IS_VF_FLAG			(1 << 22)
1487 #define BC_SUPPORTS_RMMOD_CMD		(1 << 23)
1488 #define HAS_PHYS_PORT_ID		(1 << 24)
1489 #define AER_ENABLED			(1 << 25)
1490 #define PTP_SUPPORTED			(1 << 26)
1491 #define TX_TIMESTAMPING_EN		(1 << 27)
1492 
1493 #define BP_NOMCP(bp)			((bp)->flags & NO_MCP_FLAG)
1494 
1495 #ifdef CONFIG_BNX2X_SRIOV
1496 #define IS_VF(bp)			((bp)->flags & IS_VF_FLAG)
1497 #define IS_PF(bp)			(!((bp)->flags & IS_VF_FLAG))
1498 #else
1499 #define IS_VF(bp)			false
1500 #define IS_PF(bp)			true
1501 #endif
1502 
1503 #define NO_ISCSI(bp)		((bp)->flags & NO_ISCSI_FLAG)
1504 #define NO_ISCSI_OOO(bp)	((bp)->flags & NO_ISCSI_OOO_FLAG)
1505 #define NO_FCOE(bp)		((bp)->flags & NO_FCOE_FLAG)
1506 
1507 	u8			cnic_support;
1508 	bool			cnic_enabled;
1509 	bool			cnic_loaded;
1510 	struct cnic_eth_dev	*(*cnic_probe)(struct net_device *);
1511 
1512 	/* Flag that indicates that we can start looking for FCoE L2 queue
1513 	 * completions in the default status block.
1514 	 */
1515 	bool			fcoe_init;
1516 
1517 	int			mrrs;
1518 
1519 	struct delayed_work	sp_task;
1520 	struct delayed_work	iov_task;
1521 
1522 	atomic_t		interrupt_occurred;
1523 	struct delayed_work	sp_rtnl_task;
1524 
1525 	struct delayed_work	period_task;
1526 	struct timer_list	timer;
1527 	int			current_interval;
1528 
1529 	u16			fw_seq;
1530 	u16			fw_drv_pulse_wr_seq;
1531 	u32			func_stx;
1532 
1533 	struct link_params	link_params;
1534 	struct link_vars	link_vars;
1535 	u32			link_cnt;
1536 	struct bnx2x_link_report_data last_reported_link;
1537 	bool			force_link_down;
1538 
1539 	struct mdio_if_info	mdio;
1540 
1541 	struct bnx2x_common	common;
1542 	struct bnx2x_port	port;
1543 
1544 	struct cmng_init	cmng;
1545 
1546 	u32			mf_config[E1HVN_MAX];
1547 	u32			mf_ext_config;
1548 	u32			path_has_ovlan; /* E3 */
1549 	u16			mf_ov;
1550 	u8			mf_mode;
1551 #define IS_MF(bp)		(bp->mf_mode != 0)
1552 #define IS_MF_SI(bp)		(bp->mf_mode == MULTI_FUNCTION_SI)
1553 #define IS_MF_SD(bp)		(bp->mf_mode == MULTI_FUNCTION_SD)
1554 #define IS_MF_AFEX(bp)		(bp->mf_mode == MULTI_FUNCTION_AFEX)
1555 	u8			mf_sub_mode;
1556 #define IS_MF_UFP(bp)		(IS_MF_SD(bp) && \
1557 				 bp->mf_sub_mode == SUB_MF_MODE_UFP)
1558 #define IS_MF_BD(bp)		(IS_MF_SD(bp) && \
1559 				 bp->mf_sub_mode == SUB_MF_MODE_BD)
1560 
1561 	u8			wol;
1562 
1563 	int			rx_ring_size;
1564 
1565 	u16			tx_quick_cons_trip_int;
1566 	u16			tx_quick_cons_trip;
1567 	u16			tx_ticks_int;
1568 	u16			tx_ticks;
1569 
1570 	u16			rx_quick_cons_trip_int;
1571 	u16			rx_quick_cons_trip;
1572 	u16			rx_ticks_int;
1573 	u16			rx_ticks;
1574 /* Maximal coalescing timeout in us */
1575 #define BNX2X_MAX_COALESCE_TOUT		(0xff*BNX2X_BTR)
1576 
1577 	u32			lin_cnt;
1578 
1579 	u16			state;
1580 #define BNX2X_STATE_CLOSED		0
1581 #define BNX2X_STATE_OPENING_WAIT4_LOAD	0x1000
1582 #define BNX2X_STATE_OPENING_WAIT4_PORT	0x2000
1583 #define BNX2X_STATE_OPEN		0x3000
1584 #define BNX2X_STATE_CLOSING_WAIT4_HALT	0x4000
1585 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1586 
1587 #define BNX2X_STATE_DIAG		0xe000
1588 #define BNX2X_STATE_ERROR		0xf000
1589 
1590 #define BNX2X_MAX_PRIORITY		8
1591 	int			num_queues;
1592 	uint			num_ethernet_queues;
1593 	uint			num_cnic_queues;
1594 	int			disable_tpa;
1595 
1596 	u32			rx_mode;
1597 #define BNX2X_RX_MODE_NONE		0
1598 #define BNX2X_RX_MODE_NORMAL		1
1599 #define BNX2X_RX_MODE_ALLMULTI		2
1600 #define BNX2X_RX_MODE_PROMISC		3
1601 #define BNX2X_MAX_MULTICAST		64
1602 
1603 	u8			igu_dsb_id;
1604 	u8			igu_base_sb;
1605 	u8			igu_sb_cnt;
1606 	u8			min_msix_vec_cnt;
1607 
1608 	u32			igu_base_addr;
1609 	dma_addr_t		def_status_blk_mapping;
1610 
1611 	struct bnx2x_slowpath	*slowpath;
1612 	dma_addr_t		slowpath_mapping;
1613 
1614 	/* Mechanism protecting the drv_info_to_mcp */
1615 	struct mutex		drv_info_mutex;
1616 	bool			drv_info_mng_owner;
1617 
1618 	/* Total number of FW statistics requests */
1619 	u8			fw_stats_num;
1620 
1621 	/*
1622 	 * This is a memory buffer that will contain both statistics
1623 	 * ramrod request and data.
1624 	 */
1625 	void			*fw_stats;
1626 	dma_addr_t		fw_stats_mapping;
1627 
1628 	/*
1629 	 * FW statistics request shortcut (points at the
1630 	 * beginning of fw_stats buffer).
1631 	 */
1632 	struct bnx2x_fw_stats_req	*fw_stats_req;
1633 	dma_addr_t			fw_stats_req_mapping;
1634 	int				fw_stats_req_sz;
1635 
1636 	/*
1637 	 * FW statistics data shortcut (points at the beginning of
1638 	 * fw_stats buffer + fw_stats_req_sz).
1639 	 */
1640 	struct bnx2x_fw_stats_data	*fw_stats_data;
1641 	dma_addr_t			fw_stats_data_mapping;
1642 	int				fw_stats_data_sz;
1643 
1644 	/* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB
1645 	 * context size we need 8 ILT entries.
1646 	 */
1647 #define ILT_MAX_L2_LINES	32
1648 	struct hw_context	context[ILT_MAX_L2_LINES];
1649 
1650 	struct bnx2x_ilt	*ilt;
1651 #define BP_ILT(bp)		((bp)->ilt)
1652 #define ILT_MAX_LINES		256
1653 /*
1654  * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1655  * to CNIC.
1656  */
1657 #define BNX2X_MAX_RSS_COUNT(bp)	((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1658 
1659 /*
1660  * Maximum CID count that might be required by the bnx2x:
1661  * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1662  */
1663 
1664 #define BNX2X_L2_CID_COUNT(bp)	(BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1665 				+ CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1666 #define BNX2X_L2_MAX_CID(bp)	(BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1667 				+ CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1668 #define L2_ILT_LINES(bp)	(DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1669 					ILT_PAGE_CIDS))
1670 
1671 	int			qm_cid_count;
1672 
1673 	bool			dropless_fc;
1674 
1675 	void			*t2;
1676 	dma_addr_t		t2_mapping;
1677 	struct cnic_ops	__rcu	*cnic_ops;
1678 	void			*cnic_data;
1679 	u32			cnic_tag;
1680 	struct cnic_eth_dev	cnic_eth_dev;
1681 	union host_hc_status_block cnic_sb;
1682 	dma_addr_t		cnic_sb_mapping;
1683 	struct eth_spe		*cnic_kwq;
1684 	struct eth_spe		*cnic_kwq_prod;
1685 	struct eth_spe		*cnic_kwq_cons;
1686 	struct eth_spe		*cnic_kwq_last;
1687 	u16			cnic_kwq_pending;
1688 	u16			cnic_spq_pending;
1689 	u8			fip_mac[ETH_ALEN];
1690 	struct mutex		cnic_mutex;
1691 	struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1692 
1693 	/* Start index of the "special" (CNIC related) L2 clients */
1694 	u8				cnic_base_cl_id;
1695 
1696 	int			dmae_ready;
1697 	/* used to synchronize dmae accesses */
1698 	spinlock_t		dmae_lock;
1699 
1700 	/* used to protect the FW mail box */
1701 	struct mutex		fw_mb_mutex;
1702 
1703 	/* used to synchronize stats collecting */
1704 	int			stats_state;
1705 
1706 	/* used for synchronization of concurrent threads statistics handling */
1707 	struct semaphore	stats_lock;
1708 
1709 	/* used by dmae command loader */
1710 	struct dmae_command	stats_dmae;
1711 	int			executer_idx;
1712 
1713 	u16			stats_counter;
1714 	struct bnx2x_eth_stats	eth_stats;
1715 	struct host_func_stats		func_stats;
1716 	struct bnx2x_eth_stats_old	eth_stats_old;
1717 	struct bnx2x_net_stats_old	net_stats_old;
1718 	struct bnx2x_fw_port_stats_old	fw_stats_old;
1719 	bool			stats_init;
1720 
1721 	struct z_stream_s	*strm;
1722 	void			*gunzip_buf;
1723 	dma_addr_t		gunzip_mapping;
1724 	int			gunzip_outlen;
1725 #define FW_BUF_SIZE			0x8000
1726 #define GUNZIP_BUF(bp)			(bp->gunzip_buf)
1727 #define GUNZIP_PHYS(bp)			(bp->gunzip_mapping)
1728 #define GUNZIP_OUTLEN(bp)		(bp->gunzip_outlen)
1729 
1730 	struct raw_op		*init_ops;
1731 	/* Init blocks offsets inside init_ops */
1732 	u16			*init_ops_offsets;
1733 	/* Data blob - has 32 bit granularity */
1734 	u32			*init_data;
1735 	u32			init_mode_flags;
1736 #define INIT_MODE_FLAGS(bp)	(bp->init_mode_flags)
1737 	/* Zipped PRAM blobs - raw data */
1738 	const u8		*tsem_int_table_data;
1739 	const u8		*tsem_pram_data;
1740 	const u8		*usem_int_table_data;
1741 	const u8		*usem_pram_data;
1742 	const u8		*xsem_int_table_data;
1743 	const u8		*xsem_pram_data;
1744 	const u8		*csem_int_table_data;
1745 	const u8		*csem_pram_data;
1746 #define INIT_OPS(bp)			(bp->init_ops)
1747 #define INIT_OPS_OFFSETS(bp)		(bp->init_ops_offsets)
1748 #define INIT_DATA(bp)			(bp->init_data)
1749 #define INIT_TSEM_INT_TABLE_DATA(bp)	(bp->tsem_int_table_data)
1750 #define INIT_TSEM_PRAM_DATA(bp)		(bp->tsem_pram_data)
1751 #define INIT_USEM_INT_TABLE_DATA(bp)	(bp->usem_int_table_data)
1752 #define INIT_USEM_PRAM_DATA(bp)		(bp->usem_pram_data)
1753 #define INIT_XSEM_INT_TABLE_DATA(bp)	(bp->xsem_int_table_data)
1754 #define INIT_XSEM_PRAM_DATA(bp)		(bp->xsem_pram_data)
1755 #define INIT_CSEM_INT_TABLE_DATA(bp)	(bp->csem_int_table_data)
1756 #define INIT_CSEM_PRAM_DATA(bp)		(bp->csem_pram_data)
1757 
1758 #define PHY_FW_VER_LEN			20
1759 	char			fw_ver[32];
1760 	const struct firmware	*firmware;
1761 
1762 	struct bnx2x_vfdb	*vfdb;
1763 #define IS_SRIOV(bp)		((bp)->vfdb)
1764 
1765 	/* DCB support on/off */
1766 	u16 dcb_state;
1767 #define BNX2X_DCB_STATE_OFF			0
1768 #define BNX2X_DCB_STATE_ON			1
1769 
1770 	/* DCBX engine mode */
1771 	int dcbx_enabled;
1772 #define BNX2X_DCBX_ENABLED_OFF			0
1773 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF		1
1774 #define BNX2X_DCBX_ENABLED_ON_NEG_ON		2
1775 #define BNX2X_DCBX_ENABLED_INVALID		(-1)
1776 
1777 	bool dcbx_mode_uset;
1778 
1779 	struct bnx2x_config_dcbx_params		dcbx_config_params;
1780 	struct bnx2x_dcbx_port_params		dcbx_port_params;
1781 	int					dcb_version;
1782 
1783 	/* CAM credit pools */
1784 	struct bnx2x_credit_pool_obj		vlans_pool;
1785 
1786 	struct bnx2x_credit_pool_obj		macs_pool;
1787 
1788 	/* RX_MODE object */
1789 	struct bnx2x_rx_mode_obj		rx_mode_obj;
1790 
1791 	/* MCAST object */
1792 	struct bnx2x_mcast_obj			mcast_obj;
1793 
1794 	/* RSS configuration object */
1795 	struct bnx2x_rss_config_obj		rss_conf_obj;
1796 
1797 	/* Function State controlling object */
1798 	struct bnx2x_func_sp_obj		func_obj;
1799 
1800 	unsigned long				sp_state;
1801 
1802 	/* operation indication for the sp_rtnl task */
1803 	unsigned long				sp_rtnl_state;
1804 
1805 	/* Indication of the IOV tasks */
1806 	unsigned long				iov_task_state;
1807 
1808 	/* DCBX Negotiation results */
1809 	struct dcbx_features			dcbx_local_feat;
1810 	u32					dcbx_error;
1811 
1812 #ifdef BCM_DCBNL
1813 	struct dcbx_features			dcbx_remote_feat;
1814 	u32					dcbx_remote_flags;
1815 #endif
1816 	/* AFEX: store default vlan used */
1817 	int					afex_def_vlan_tag;
1818 	enum mf_cfg_afex_vlan_mode		afex_vlan_mode;
1819 	u32					pending_max;
1820 
1821 	/* multiple tx classes of service */
1822 	u8					max_cos;
1823 
1824 	/* priority to cos mapping */
1825 	u8					prio_to_cos[8];
1826 
1827 	int fp_array_size;
1828 	u32 dump_preset_idx;
1829 
1830 	u8					phys_port_id[ETH_ALEN];
1831 
1832 	/* PTP related context */
1833 	struct ptp_clock *ptp_clock;
1834 	struct ptp_clock_info ptp_clock_info;
1835 	struct work_struct ptp_task;
1836 	struct cyclecounter cyclecounter;
1837 	struct timecounter timecounter;
1838 	bool timecounter_init_done;
1839 	struct sk_buff *ptp_tx_skb;
1840 	unsigned long ptp_tx_start;
1841 	bool hwtstamp_ioctl_called;
1842 	u16 tx_type;
1843 	u16 rx_filter;
1844 
1845 	struct bnx2x_link_report_data		vf_link_vars;
1846 	struct list_head vlan_reg;
1847 	u16 vlan_cnt;
1848 	u16 vlan_credit;
1849 	bool accept_any_vlan;
1850 
1851 	/* Vxlan/Geneve related information */
1852 	u16 udp_tunnel_ports[BNX2X_UDP_PORT_MAX];
1853 
1854 #define FW_CAP_INVALIDATE_VF_FP_HSI	BIT(0)
1855 	u32 fw_cap;
1856 
1857 	u32 fw_major;
1858 	u32 fw_minor;
1859 	u32 fw_rev;
1860 	u32 fw_eng;
1861 };
1862 
1863 /* Tx queues may be less or equal to Rx queues */
1864 extern int num_queues;
1865 #define BNX2X_NUM_QUEUES(bp)	(bp->num_queues)
1866 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1867 #define BNX2X_NUM_NON_CNIC_QUEUES(bp)	(BNX2X_NUM_QUEUES(bp) - \
1868 					 (bp)->num_cnic_queues)
1869 #define BNX2X_NUM_RX_QUEUES(bp)	BNX2X_NUM_QUEUES(bp)
1870 
1871 #define is_multi(bp)		(BNX2X_NUM_QUEUES(bp) > 1)
1872 
1873 #define BNX2X_MAX_QUEUES(bp)	BNX2X_MAX_RSS_COUNT(bp)
1874 /* #define is_eth_multi(bp)	(BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1875 
1876 #define RSS_IPV4_CAP_MASK						\
1877 	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1878 
1879 #define RSS_IPV4_TCP_CAP_MASK						\
1880 	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1881 
1882 #define RSS_IPV6_CAP_MASK						\
1883 	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1884 
1885 #define RSS_IPV6_TCP_CAP_MASK						\
1886 	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1887 
1888 struct bnx2x_func_init_params {
1889 	/* dma */
1890 	bool		spq_active;
1891 	dma_addr_t	spq_map;
1892 	u16		spq_prod;
1893 
1894 	u16		func_id;	/* abs fid */
1895 	u16		pf_id;
1896 };
1897 
1898 #define for_each_cnic_queue(bp, var) \
1899 	for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1900 	     (var)++) \
1901 		if (skip_queue(bp, var))	\
1902 			continue;		\
1903 		else
1904 
1905 #define for_each_eth_queue(bp, var) \
1906 	for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1907 
1908 #define for_each_nondefault_eth_queue(bp, var) \
1909 	for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1910 
1911 #define for_each_queue(bp, var) \
1912 	for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1913 		if (skip_queue(bp, var))	\
1914 			continue;		\
1915 		else
1916 
1917 /* Skip forwarding FP */
1918 #define for_each_valid_rx_queue(bp, var)			\
1919 	for ((var) = 0;						\
1920 	     (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) :	\
1921 		      BNX2X_NUM_ETH_QUEUES(bp));		\
1922 	     (var)++)						\
1923 		if (skip_rx_queue(bp, var))			\
1924 			continue;				\
1925 		else
1926 
1927 #define for_each_rx_queue_cnic(bp, var) \
1928 	for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1929 	     (var)++) \
1930 		if (skip_rx_queue(bp, var))	\
1931 			continue;		\
1932 		else
1933 
1934 #define for_each_rx_queue(bp, var) \
1935 	for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1936 		if (skip_rx_queue(bp, var))	\
1937 			continue;		\
1938 		else
1939 
1940 /* Skip OOO FP */
1941 #define for_each_valid_tx_queue(bp, var)			\
1942 	for ((var) = 0;						\
1943 	     (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) :	\
1944 		      BNX2X_NUM_ETH_QUEUES(bp));		\
1945 	     (var)++)						\
1946 		if (skip_tx_queue(bp, var))			\
1947 			continue;				\
1948 		else
1949 
1950 #define for_each_tx_queue_cnic(bp, var) \
1951 	for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1952 	     (var)++) \
1953 		if (skip_tx_queue(bp, var))	\
1954 			continue;		\
1955 		else
1956 
1957 #define for_each_tx_queue(bp, var) \
1958 	for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1959 		if (skip_tx_queue(bp, var))	\
1960 			continue;		\
1961 		else
1962 
1963 #define for_each_nondefault_queue(bp, var) \
1964 	for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1965 		if (skip_queue(bp, var))	\
1966 			continue;		\
1967 		else
1968 
1969 #define for_each_cos_in_tx_queue(fp, var) \
1970 	for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1971 
1972 /* skip rx queue
1973  * if FCOE l2 support is disabled and this is the fcoe L2 queue
1974  */
1975 #define skip_rx_queue(bp, idx)	(NO_FCOE(bp) && IS_FCOE_IDX(idx))
1976 
1977 /* skip tx queue
1978  * if FCOE l2 support is disabled and this is the fcoe L2 queue
1979  */
1980 #define skip_tx_queue(bp, idx)	(NO_FCOE(bp) && IS_FCOE_IDX(idx))
1981 
1982 #define skip_queue(bp, idx)	(NO_FCOE(bp) && IS_FCOE_IDX(idx))
1983 
1984 /*self test*/
1985 int bnx2x_idle_chk(struct bnx2x *bp);
1986 
1987 /**
1988  * bnx2x_set_mac_one - configure a single MAC address
1989  *
1990  * @bp:			driver handle
1991  * @mac:		MAC to configure
1992  * @obj:		MAC object handle
1993  * @set:		if 'true' add a new MAC, otherwise - delete
1994  * @mac_type:		the type of the MAC to configure (e.g. ETH, UC list)
1995  * @ramrod_flags:	RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1996  *
1997  * Configures one MAC according to provided parameters or continues the
1998  * execution of previously scheduled commands if RAMROD_CONT is set in
1999  * ramrod_flags.
2000  *
2001  * Returns zero if operation has successfully completed, a positive value if the
2002  * operation has been successfully scheduled and a negative - if a requested
2003  * operations has failed.
2004  */
2005 int bnx2x_set_mac_one(struct bnx2x *bp, const u8 *mac,
2006 		      struct bnx2x_vlan_mac_obj *obj, bool set,
2007 		      int mac_type, unsigned long *ramrod_flags);
2008 
2009 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
2010 		       struct bnx2x_vlan_mac_obj *obj, bool set,
2011 		       unsigned long *ramrod_flags);
2012 
2013 /**
2014  * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
2015  *
2016  * @bp:			driver handle
2017  * @mac_obj:		MAC object handle
2018  * @mac_type:		type of the MACs to clear (BNX2X_XXX_MAC)
2019  * @wait_for_comp:	if 'true' block until completion
2020  *
2021  * Deletes all MACs of the specific type (e.g. ETH, UC list).
2022  *
2023  * Returns zero if operation has successfully completed, a positive value if the
2024  * operation has been successfully scheduled and a negative - if a requested
2025  * operations has failed.
2026  */
2027 int bnx2x_del_all_macs(struct bnx2x *bp,
2028 		       struct bnx2x_vlan_mac_obj *mac_obj,
2029 		       int mac_type, bool wait_for_comp);
2030 
2031 /* Init Function API  */
2032 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
2033 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
2034 		    u8 vf_valid, int fw_sb_id, int igu_sb_id);
2035 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
2036 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2037 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
2038 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2039 void bnx2x_read_mf_cfg(struct bnx2x *bp);
2040 
2041 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
2042 
2043 /* dmae */
2044 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
2045 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
2046 		      u32 len32);
2047 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
2048 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
2049 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
2050 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
2051 		      bool with_comp, u8 comp_type);
2052 
2053 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2054 			       u8 src_type, u8 dst_type);
2055 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2056 			       u32 *comp);
2057 
2058 /* FLR related routines */
2059 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
2060 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
2061 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
2062 u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
2063 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
2064 				    char *msg, u32 poll_cnt);
2065 
2066 void bnx2x_calc_fc_adv(struct bnx2x *bp);
2067 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2068 		  u32 data_hi, u32 data_lo, int cmd_type);
2069 void bnx2x_update_coalesce(struct bnx2x *bp);
2070 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
2071 
2072 bool bnx2x_port_after_undi(struct bnx2x *bp);
2073 
reg_poll(struct bnx2x * bp,u32 reg,u32 expected,int ms,int wait)2074 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
2075 			   int wait)
2076 {
2077 	u32 val;
2078 
2079 	do {
2080 		val = REG_RD(bp, reg);
2081 		if (val == expected)
2082 			break;
2083 		ms -= wait;
2084 		msleep(wait);
2085 
2086 	} while (ms > 0);
2087 
2088 	return val;
2089 }
2090 
2091 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
2092 			    bool is_pf);
2093 
2094 #define BNX2X_ILT_ZALLOC(x, y, size)					\
2095 	x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL)
2096 
2097 #define BNX2X_ILT_FREE(x, y, size) \
2098 	do { \
2099 		if (x) { \
2100 			dma_free_coherent(&bp->pdev->dev, size, x, y); \
2101 			x = NULL; \
2102 			y = 0; \
2103 		} \
2104 	} while (0)
2105 
2106 #define ILOG2(x)	(ilog2((x)))
2107 
2108 #define ILT_NUM_PAGE_ENTRIES	(3072)
2109 /* In 57710/11 we use whole table since we have 8 func
2110  * In 57712 we have only 4 func, but use same size per func, then only half of
2111  * the table in use
2112  */
2113 #define ILT_PER_FUNC		(ILT_NUM_PAGE_ENTRIES/8)
2114 
2115 #define FUNC_ILT_BASE(func)	(func * ILT_PER_FUNC)
2116 /*
2117  * the phys address is shifted right 12 bits and has an added
2118  * 1=valid bit added to the 53rd bit
2119  * then since this is a wide register(TM)
2120  * we split it into two 32 bit writes
2121  */
2122 #define ONCHIP_ADDR1(x)		((u32)(((u64)x >> 12) & 0xFFFFFFFF))
2123 #define ONCHIP_ADDR2(x)		((u32)((1 << 20) | ((u64)x >> 44)))
2124 
2125 /* load/unload mode */
2126 #define LOAD_NORMAL			0
2127 #define LOAD_OPEN			1
2128 #define LOAD_DIAG			2
2129 #define LOAD_LOOPBACK_EXT		3
2130 #define UNLOAD_NORMAL			0
2131 #define UNLOAD_CLOSE			1
2132 #define UNLOAD_RECOVERY			2
2133 
2134 /* DMAE command defines */
2135 #define DMAE_TIMEOUT			-1
2136 #define DMAE_PCI_ERROR			-2	/* E2 and onward */
2137 #define DMAE_NOT_RDY			-3
2138 #define DMAE_PCI_ERR_FLAG		0x80000000
2139 
2140 #define DMAE_SRC_PCI			0
2141 #define DMAE_SRC_GRC			1
2142 
2143 #define DMAE_DST_NONE			0
2144 #define DMAE_DST_PCI			1
2145 #define DMAE_DST_GRC			2
2146 
2147 #define DMAE_COMP_PCI			0
2148 #define DMAE_COMP_GRC			1
2149 
2150 /* E2 and onward - PCI error handling in the completion */
2151 
2152 #define DMAE_COMP_REGULAR		0
2153 #define DMAE_COM_SET_ERR		1
2154 
2155 #define DMAE_CMD_SRC_PCI		(DMAE_SRC_PCI << \
2156 						DMAE_COMMAND_SRC_SHIFT)
2157 #define DMAE_CMD_SRC_GRC		(DMAE_SRC_GRC << \
2158 						DMAE_COMMAND_SRC_SHIFT)
2159 
2160 #define DMAE_CMD_DST_PCI		(DMAE_DST_PCI << \
2161 						DMAE_COMMAND_DST_SHIFT)
2162 #define DMAE_CMD_DST_GRC		(DMAE_DST_GRC << \
2163 						DMAE_COMMAND_DST_SHIFT)
2164 
2165 #define DMAE_CMD_C_DST_PCI		(DMAE_COMP_PCI << \
2166 						DMAE_COMMAND_C_DST_SHIFT)
2167 #define DMAE_CMD_C_DST_GRC		(DMAE_COMP_GRC << \
2168 						DMAE_COMMAND_C_DST_SHIFT)
2169 
2170 #define DMAE_CMD_C_ENABLE		DMAE_COMMAND_C_TYPE_ENABLE
2171 
2172 #define DMAE_CMD_ENDIANITY_NO_SWAP	(0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2173 #define DMAE_CMD_ENDIANITY_B_SWAP	(1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2174 #define DMAE_CMD_ENDIANITY_DW_SWAP	(2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2175 #define DMAE_CMD_ENDIANITY_B_DW_SWAP	(3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2176 
2177 #define DMAE_CMD_PORT_0			0
2178 #define DMAE_CMD_PORT_1			DMAE_COMMAND_PORT
2179 
2180 #define DMAE_CMD_SRC_RESET		DMAE_COMMAND_SRC_RESET
2181 #define DMAE_CMD_DST_RESET		DMAE_COMMAND_DST_RESET
2182 #define DMAE_CMD_E1HVN_SHIFT		DMAE_COMMAND_E1HVN_SHIFT
2183 
2184 #define DMAE_SRC_PF			0
2185 #define DMAE_SRC_VF			1
2186 
2187 #define DMAE_DST_PF			0
2188 #define DMAE_DST_VF			1
2189 
2190 #define DMAE_C_SRC			0
2191 #define DMAE_C_DST			1
2192 
2193 #define DMAE_LEN32_RD_MAX		0x80
2194 #define DMAE_LEN32_WR_MAX(bp)		(CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2195 
2196 #define DMAE_COMP_VAL			0x60d0d0ae /* E2 and on - upper bit
2197 						    * indicates error
2198 						    */
2199 
2200 #define MAX_DMAE_C_PER_PORT		8
2201 #define INIT_DMAE_C(bp)			(BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2202 					 BP_VN(bp))
2203 #define PMF_DMAE_C(bp)			(BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2204 					 E1HVN_MAX)
2205 
2206 /* Following is the DMAE channel number allocation for the clients.
2207  *   MFW: OCBB/OCSD implementations use DMAE channels 14/15 respectively.
2208  *   Driver: 0-3 and 8-11 (for PF dmae operations)
2209  *           4 and 12 (for stats requests)
2210  */
2211 #define BNX2X_FW_DMAE_C                 13 /* Channel for FW DMAE operations */
2212 
2213 /* PCIE link and speed */
2214 #define PCICFG_LINK_WIDTH		0x1f00000
2215 #define PCICFG_LINK_WIDTH_SHIFT		20
2216 #define PCICFG_LINK_SPEED		0xf0000
2217 #define PCICFG_LINK_SPEED_SHIFT		16
2218 
2219 #define BNX2X_NUM_TESTS_SF		7
2220 #define BNX2X_NUM_TESTS_MF		3
2221 #define BNX2X_NUM_TESTS(bp)		(IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2222 					     IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF)
2223 
2224 #define BNX2X_PHY_LOOPBACK		0
2225 #define BNX2X_MAC_LOOPBACK		1
2226 #define BNX2X_EXT_LOOPBACK		2
2227 #define BNX2X_PHY_LOOPBACK_FAILED	1
2228 #define BNX2X_MAC_LOOPBACK_FAILED	2
2229 #define BNX2X_EXT_LOOPBACK_FAILED	3
2230 #define BNX2X_LOOPBACK_FAILED		(BNX2X_MAC_LOOPBACK_FAILED | \
2231 					 BNX2X_PHY_LOOPBACK_FAILED)
2232 
2233 #define STROM_ASSERT_ARRAY_SIZE		50
2234 
2235 /* must be used on a CID before placing it on a HW ring */
2236 #define HW_CID(bp, x)			((BP_PORT(bp) << 23) | \
2237 					 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2238 					 (x))
2239 
2240 #define SP_DESC_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_spe))
2241 #define MAX_SP_DESC_CNT			(SP_DESC_CNT - 1)
2242 
2243 #define BNX2X_BTR			4
2244 #define MAX_SPQ_PENDING			8
2245 
2246 /* CMNG constants, as derived from system spec calculations */
2247 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2248 #define DEF_MIN_RATE					100
2249 /* resolution of the rate shaping timer - 400 usec */
2250 #define RS_PERIODIC_TIMEOUT_USEC			400
2251 /* number of bytes in single QM arbitration cycle -
2252  * coefficient for calculating the fairness timer */
2253 #define QM_ARB_BYTES					160000
2254 /* resolution of Min algorithm 1:100 */
2255 #define MIN_RES						100
2256 /* how many bytes above threshold for the minimal credit of Min algorithm*/
2257 #define MIN_ABOVE_THRESH				32768
2258 /* Fairness algorithm integration time coefficient -
2259  * for calculating the actual Tfair */
2260 #define T_FAIR_COEF	((MIN_ABOVE_THRESH +  QM_ARB_BYTES) * 8 * MIN_RES)
2261 /* Memory of fairness algorithm . 2 cycles */
2262 #define FAIR_MEM					2
2263 
2264 #define ATTN_NIG_FOR_FUNC		(1L << 8)
2265 #define ATTN_SW_TIMER_4_FUNC		(1L << 9)
2266 #define GPIO_2_FUNC			(1L << 10)
2267 #define GPIO_3_FUNC			(1L << 11)
2268 #define GPIO_4_FUNC			(1L << 12)
2269 #define ATTN_GENERAL_ATTN_1		(1L << 13)
2270 #define ATTN_GENERAL_ATTN_2		(1L << 14)
2271 #define ATTN_GENERAL_ATTN_3		(1L << 15)
2272 #define ATTN_GENERAL_ATTN_4		(1L << 13)
2273 #define ATTN_GENERAL_ATTN_5		(1L << 14)
2274 #define ATTN_GENERAL_ATTN_6		(1L << 15)
2275 
2276 #define ATTN_HARD_WIRED_MASK		0xff00
2277 #define ATTENTION_ID			4
2278 
2279 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \
2280 				 IS_MF_FCOE_AFEX(bp))
2281 
2282 /* stuff added to make the code fit 80Col */
2283 
2284 #define BNX2X_PMF_LINK_ASSERT \
2285 	GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2286 
2287 #define BNX2X_MC_ASSERT_BITS \
2288 	(GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2289 	 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2290 	 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2291 	 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2292 
2293 #define BNX2X_MCP_ASSERT \
2294 	GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2295 
2296 #define BNX2X_GRC_TIMEOUT	GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2297 #define BNX2X_GRC_RSV		(GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2298 				 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2299 				 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2300 				 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2301 				 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2302 				 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2303 
2304 #define HW_INTERRUPT_ASSERT_SET_0 \
2305 				(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2306 				 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2307 				 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2308 				 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
2309 				 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2310 #define HW_PRTY_ASSERT_SET_0	(AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2311 				 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2312 				 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2313 				 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2314 				 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2315 				 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2316 				 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2317 #define HW_INTERRUPT_ASSERT_SET_1 \
2318 				(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2319 				 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2320 				 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2321 				 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2322 				 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2323 				 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2324 				 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2325 				 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2326 				 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2327 				 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2328 				 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2329 #define HW_PRTY_ASSERT_SET_1	(AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2330 				 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2331 				 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2332 				 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2333 				 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2334 				 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2335 				 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2336 				 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2337 			     AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2338 				 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2339 				 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2340 				 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2341 				 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2342 				 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2343 				 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2344 				 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2345 #define HW_INTERRUPT_ASSERT_SET_2 \
2346 				(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2347 				 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2348 				 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2349 			AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2350 				 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2351 #define HW_PRTY_ASSERT_SET_2	(AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2352 				 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2353 			AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2354 				 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2355 				 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2356 				 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2357 				 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2358 				 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2359 
2360 #define HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD \
2361 		(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2362 		 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2363 		 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
2364 
2365 #define HW_PRTY_ASSERT_SET_3 (HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD | \
2366 			      AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2367 
2368 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2369 			      AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2370 
2371 #define MULTI_MASK			0x7f
2372 
2373 #define DEF_USB_FUNC_OFF	offsetof(struct cstorm_def_status_block_u, func)
2374 #define DEF_CSB_FUNC_OFF	offsetof(struct cstorm_def_status_block_c, func)
2375 #define DEF_XSB_FUNC_OFF	offsetof(struct xstorm_def_status_block, func)
2376 #define DEF_TSB_FUNC_OFF	offsetof(struct tstorm_def_status_block, func)
2377 
2378 #define DEF_USB_IGU_INDEX_OFF \
2379 			offsetof(struct cstorm_def_status_block_u, igu_index)
2380 #define DEF_CSB_IGU_INDEX_OFF \
2381 			offsetof(struct cstorm_def_status_block_c, igu_index)
2382 #define DEF_XSB_IGU_INDEX_OFF \
2383 			offsetof(struct xstorm_def_status_block, igu_index)
2384 #define DEF_TSB_IGU_INDEX_OFF \
2385 			offsetof(struct tstorm_def_status_block, igu_index)
2386 
2387 #define DEF_USB_SEGMENT_OFF \
2388 			offsetof(struct cstorm_def_status_block_u, segment)
2389 #define DEF_CSB_SEGMENT_OFF \
2390 			offsetof(struct cstorm_def_status_block_c, segment)
2391 #define DEF_XSB_SEGMENT_OFF \
2392 			offsetof(struct xstorm_def_status_block, segment)
2393 #define DEF_TSB_SEGMENT_OFF \
2394 			offsetof(struct tstorm_def_status_block, segment)
2395 
2396 #define BNX2X_SP_DSB_INDEX \
2397 		(&bp->def_status_blk->sp_sb.\
2398 					index_values[HC_SP_INDEX_ETH_DEF_CONS])
2399 
2400 #define CAM_IS_INVALID(x) \
2401 	(GET_FLAG(x.flags, \
2402 	MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2403 	(T_ETH_MAC_COMMAND_INVALIDATE))
2404 
2405 /* Number of u32 elements in MC hash array */
2406 #define MC_HASH_SIZE			8
2407 #define MC_HASH_OFFSET(bp, i)		(BAR_TSTRORM_INTMEM + \
2408 	TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2409 
2410 #ifndef PXP2_REG_PXP2_INT_STS
2411 #define PXP2_REG_PXP2_INT_STS		PXP2_REG_PXP2_INT_STS_0
2412 #endif
2413 
2414 #ifndef ETH_MAX_RX_CLIENTS_E2
2415 #define ETH_MAX_RX_CLIENTS_E2		ETH_MAX_RX_CLIENTS_E1H
2416 #endif
2417 
2418 #define VENDOR_ID_LEN			4
2419 
2420 #define VF_ACQUIRE_THRESH		3
2421 #define VF_ACQUIRE_MAC_FILTERS		1
2422 #define VF_ACQUIRE_MC_FILTERS		10
2423 #define VF_ACQUIRE_VLAN_FILTERS		2 /* VLAN0 + 'real' VLAN */
2424 
2425 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2426 			    (!((me_reg) & ME_REG_VF_ERR)))
2427 int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err);
2428 
2429 /* Congestion management fairness mode */
2430 #define CMNG_FNS_NONE			0
2431 #define CMNG_FNS_MINMAX			1
2432 
2433 #define HC_SEG_ACCESS_DEF		0   /*Driver decision 0-3*/
2434 #define HC_SEG_ACCESS_ATTN		4
2435 #define HC_SEG_ACCESS_NORM		0   /*Driver decision 0-1*/
2436 
2437 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
2438 void bnx2x_notify_link_changed(struct bnx2x *bp);
2439 
2440 #define BNX2X_MF_SD_PROTOCOL(bp) \
2441 	((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2442 
2443 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2444 	(BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2445 
2446 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2447 	(BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2448 
2449 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2450 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2451 #define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp))
2452 
2453 #define IS_MF_ISCSI_ONLY(bp)    (IS_MF_ISCSI_SD(bp) ||  IS_MF_ISCSI_SI(bp))
2454 
2455 #define BNX2X_MF_EXT_PROTOCOL_MASK					\
2456 				(MACP_FUNC_CFG_FLAGS_ETHERNET |		\
2457 				 MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD |	\
2458 				 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2459 
2460 #define BNX2X_MF_EXT_PROT(bp)	((bp)->mf_ext_config &			\
2461 				 BNX2X_MF_EXT_PROTOCOL_MASK)
2462 
2463 #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp)				\
2464 		(BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2465 
2466 #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)				\
2467 		(BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2468 
2469 #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp)				\
2470 		(BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD)
2471 
2472 #define IS_MF_FCOE_AFEX(bp)						\
2473 		(IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))
2474 
2475 #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)				\
2476 				(IS_MF_SD(bp) &&			\
2477 				 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) ||	\
2478 				  BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2479 
2480 #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp)				\
2481 				(IS_MF_SI(bp) &&			\
2482 				 (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) ||	\
2483 				  BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)))
2484 
2485 #define IS_MF_STORAGE_PERSONALITY_ONLY(bp)				\
2486 			(IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) ||	\
2487 			 IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp))
2488 
2489 /* Determines whether BW configuration arrives in 100Mb units or in
2490  * percentages from actual physical link speed.
2491  */
2492 #define IS_MF_PERCENT_BW(bp) (IS_MF_SI(bp) || IS_MF_UFP(bp) || IS_MF_BD(bp))
2493 
2494 #define SET_FLAG(value, mask, flag) \
2495 	do {\
2496 		(value) &= ~(mask);\
2497 		(value) |= ((flag) << (mask##_SHIFT));\
2498 	} while (0)
2499 
2500 #define GET_FLAG(value, mask) \
2501 	(((value) & (mask)) >> (mask##_SHIFT))
2502 
2503 #define GET_FIELD(value, fname) \
2504 	(((value) & (fname##_MASK)) >> (fname##_SHIFT))
2505 
2506 enum {
2507 	SWITCH_UPDATE,
2508 	AFEX_UPDATE,
2509 };
2510 
2511 #define NUM_MACS	8
2512 
2513 void bnx2x_set_local_cmng(struct bnx2x *bp);
2514 
2515 void bnx2x_update_mng_version(struct bnx2x *bp);
2516 
2517 void bnx2x_update_mfw_dump(struct bnx2x *bp);
2518 
2519 #define MCPR_SCRATCH_BASE(bp) \
2520 	(CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
2521 
2522 #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX))
2523 
2524 void bnx2x_init_ptp(struct bnx2x *bp);
2525 int bnx2x_configure_ptp_filters(struct bnx2x *bp);
2526 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb);
2527 void bnx2x_register_phc(struct bnx2x *bp);
2528 
2529 #define BNX2X_MAX_PHC_DRIFT 31000000
2530 #define BNX2X_PTP_TX_TIMEOUT
2531 
2532 /* Re-configure all previously configured vlan filters.
2533  * Meant for implicit re-load flows.
2534  */
2535 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp);
2536 #endif /* bnx2x.h */
2537