1 /* 2 * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17 * MA 02110-1301, USA. 18 */ 19 20 #ifndef __ASM_ARCH_MXC_H__ 21 #define __ASM_ARCH_MXC_H__ 22 23 #include <linux/types.h> 24 25 #ifndef __ASM_ARCH_MXC_HARDWARE_H__ 26 #error "Do not include directly." 27 #endif 28 29 #define MXC_CPU_MX1 1 30 #define MXC_CPU_MX21 21 31 #define MXC_CPU_MX25 25 32 #define MXC_CPU_MX27 27 33 #define MXC_CPU_MX31 31 34 #define MXC_CPU_MX35 35 35 #define MXC_CPU_MX50 50 36 #define MXC_CPU_MX51 51 37 #define MXC_CPU_MX53 53 38 #define MXC_CPU_MXC91231 91231 39 40 #define IMX_CHIP_REVISION_1_0 0x10 41 #define IMX_CHIP_REVISION_1_1 0x11 42 #define IMX_CHIP_REVISION_1_2 0x12 43 #define IMX_CHIP_REVISION_1_3 0x13 44 #define IMX_CHIP_REVISION_2_0 0x20 45 #define IMX_CHIP_REVISION_2_1 0x21 46 #define IMX_CHIP_REVISION_2_2 0x22 47 #define IMX_CHIP_REVISION_2_3 0x23 48 #define IMX_CHIP_REVISION_3_0 0x30 49 #define IMX_CHIP_REVISION_3_1 0x31 50 #define IMX_CHIP_REVISION_3_2 0x32 51 #define IMX_CHIP_REVISION_3_3 0x33 52 #define IMX_CHIP_REVISION_UNKNOWN 0xff 53 54 #define IMX_CHIP_REVISION_1_0_STRING "1.0" 55 #define IMX_CHIP_REVISION_1_1_STRING "1.1" 56 #define IMX_CHIP_REVISION_1_2_STRING "1.2" 57 #define IMX_CHIP_REVISION_1_3_STRING "1.3" 58 #define IMX_CHIP_REVISION_2_0_STRING "2.0" 59 #define IMX_CHIP_REVISION_2_1_STRING "2.1" 60 #define IMX_CHIP_REVISION_2_2_STRING "2.2" 61 #define IMX_CHIP_REVISION_2_3_STRING "2.3" 62 #define IMX_CHIP_REVISION_3_0_STRING "3.0" 63 #define IMX_CHIP_REVISION_3_1_STRING "3.1" 64 #define IMX_CHIP_REVISION_3_2_STRING "3.2" 65 #define IMX_CHIP_REVISION_3_3_STRING "3.3" 66 #define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown" 67 68 #ifndef __ASSEMBLY__ 69 extern unsigned int __mxc_cpu_type; 70 #endif 71 72 #ifdef CONFIG_ARCH_MX1 73 # ifdef mxc_cpu_type 74 # undef mxc_cpu_type 75 # define mxc_cpu_type __mxc_cpu_type 76 # else 77 # define mxc_cpu_type MXC_CPU_MX1 78 # endif 79 # define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1) 80 #else 81 # define cpu_is_mx1() (0) 82 #endif 83 84 #ifdef CONFIG_MACH_MX21 85 # ifdef mxc_cpu_type 86 # undef mxc_cpu_type 87 # define mxc_cpu_type __mxc_cpu_type 88 # else 89 # define mxc_cpu_type MXC_CPU_MX21 90 # endif 91 # define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21) 92 #else 93 # define cpu_is_mx21() (0) 94 #endif 95 96 #ifdef CONFIG_ARCH_MX25 97 # ifdef mxc_cpu_type 98 # undef mxc_cpu_type 99 # define mxc_cpu_type __mxc_cpu_type 100 # else 101 # define mxc_cpu_type MXC_CPU_MX25 102 # endif 103 # define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25) 104 #else 105 # define cpu_is_mx25() (0) 106 #endif 107 108 #ifdef CONFIG_MACH_MX27 109 # ifdef mxc_cpu_type 110 # undef mxc_cpu_type 111 # define mxc_cpu_type __mxc_cpu_type 112 # else 113 # define mxc_cpu_type MXC_CPU_MX27 114 # endif 115 # define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27) 116 #else 117 # define cpu_is_mx27() (0) 118 #endif 119 120 #ifdef CONFIG_SOC_IMX31 121 # ifdef mxc_cpu_type 122 # undef mxc_cpu_type 123 # define mxc_cpu_type __mxc_cpu_type 124 # else 125 # define mxc_cpu_type MXC_CPU_MX31 126 # endif 127 # define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31) 128 #else 129 # define cpu_is_mx31() (0) 130 #endif 131 132 #ifdef CONFIG_SOC_IMX35 133 # ifdef mxc_cpu_type 134 # undef mxc_cpu_type 135 # define mxc_cpu_type __mxc_cpu_type 136 # else 137 # define mxc_cpu_type MXC_CPU_MX35 138 # endif 139 # define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35) 140 #else 141 # define cpu_is_mx35() (0) 142 #endif 143 144 #ifdef CONFIG_SOC_IMX50 145 # ifdef mxc_cpu_type 146 # undef mxc_cpu_type 147 # define mxc_cpu_type __mxc_cpu_type 148 # else 149 # define mxc_cpu_type MXC_CPU_MX50 150 # endif 151 # define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50) 152 #else 153 # define cpu_is_mx50() (0) 154 #endif 155 156 #ifdef CONFIG_SOC_IMX51 157 # ifdef mxc_cpu_type 158 # undef mxc_cpu_type 159 # define mxc_cpu_type __mxc_cpu_type 160 # else 161 # define mxc_cpu_type MXC_CPU_MX51 162 # endif 163 # define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51) 164 #else 165 # define cpu_is_mx51() (0) 166 #endif 167 168 #ifdef CONFIG_SOC_IMX53 169 # ifdef mxc_cpu_type 170 # undef mxc_cpu_type 171 # define mxc_cpu_type __mxc_cpu_type 172 # else 173 # define mxc_cpu_type MXC_CPU_MX53 174 # endif 175 # define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) 176 #else 177 # define cpu_is_mx53() (0) 178 #endif 179 180 #ifdef CONFIG_ARCH_MXC91231 181 # ifdef mxc_cpu_type 182 # undef mxc_cpu_type 183 # define mxc_cpu_type __mxc_cpu_type 184 # else 185 # define mxc_cpu_type MXC_CPU_MXC91231 186 # endif 187 # define cpu_is_mxc91231() (mxc_cpu_type == MXC_CPU_MXC91231) 188 #else 189 # define cpu_is_mxc91231() (0) 190 #endif 191 192 #ifndef __ASSEMBLY__ 193 194 struct cpu_op { 195 u32 cpu_rate; 196 }; 197 198 int tzic_enable_wake(int is_idle); 199 enum mxc_cpu_pwr_mode { 200 WAIT_CLOCKED, /* wfi only */ 201 WAIT_UNCLOCKED, /* WAIT */ 202 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ 203 STOP_POWER_ON, /* just STOP */ 204 STOP_POWER_OFF, /* STOP + SRPG */ 205 }; 206 207 extern struct cpu_op *(*get_cpu_op)(int *op); 208 #endif 209 210 #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) 211 /* These are deprecated, use mx[23][157]_setup_weimcs instead. */ 212 #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10)) 213 #define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4)) 214 #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8)) 215 #endif 216 217 #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231()) 218 #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) 219 220 #endif /* __ASM_ARCH_MXC_H__ */ 221