1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/module.h>
12 #include <linux/ioport.h>
13 #include <linux/init.h>
14 #include <linux/console.h>
15 #include <linux/sysrq.h>
16 #include <linux/platform_device.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/ktime.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/rational.h>
26 #include <linux/slab.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/io.h>
30 #include <linux/dma-mapping.h>
31
32 #include <asm/irq.h>
33 #include <linux/dma/imx-dma.h>
34
35 #include "serial_mctrl_gpio.h"
36
37 /* Register definitions */
38 #define URXD0 0x0 /* Receiver Register */
39 #define URTX0 0x40 /* Transmitter Register */
40 #define UCR1 0x80 /* Control Register 1 */
41 #define UCR2 0x84 /* Control Register 2 */
42 #define UCR3 0x88 /* Control Register 3 */
43 #define UCR4 0x8c /* Control Register 4 */
44 #define UFCR 0x90 /* FIFO Control Register */
45 #define USR1 0x94 /* Status Register 1 */
46 #define USR2 0x98 /* Status Register 2 */
47 #define UESC 0x9c /* Escape Character Register */
48 #define UTIM 0xa0 /* Escape Timer Register */
49 #define UBIR 0xa4 /* BRM Incremental Register */
50 #define UBMR 0xa8 /* BRM Modulator Register */
51 #define UBRC 0xac /* Baud Rate Count Register */
52 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
53 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55
56 /* UART Control Register Bit Fields.*/
57 #define URXD_DUMMY_READ (1<<16)
58 #define URXD_CHARRDY (1<<15)
59 #define URXD_ERR (1<<14)
60 #define URXD_OVRRUN (1<<13)
61 #define URXD_FRMERR (1<<12)
62 #define URXD_BRK (1<<11)
63 #define URXD_PRERR (1<<10)
64 #define URXD_RX_DATA (0xFF<<0)
65 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72 #define UCR1_IREN (1<<7) /* Infrared interface enable */
73 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75 #define UCR1_SNDBRK (1<<4) /* Send break */
76 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79 #define UCR1_DOZE (1<<1) /* Doze */
80 #define UCR1_UARTEN (1<<0) /* UART enabled */
81 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83 #define UCR2_CTSC (1<<13) /* CTS pin control */
84 #define UCR2_CTS (1<<12) /* Clear to send */
85 #define UCR2_ESCEN (1<<11) /* Escape enable */
86 #define UCR2_PREN (1<<8) /* Parity enable */
87 #define UCR2_PROE (1<<7) /* Parity odd/even */
88 #define UCR2_STPB (1<<6) /* Stop */
89 #define UCR2_WS (1<<5) /* Word size */
90 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
91 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
93 #define UCR2_RXEN (1<<1) /* Receiver enabled */
94 #define UCR2_SRST (1<<0) /* SW reset */
95 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96 #define UCR3_PARERREN (1<<12) /* Parity enable */
97 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98 #define UCR3_DSR (1<<10) /* Data set ready */
99 #define UCR3_DCD (1<<9) /* Data carrier detect */
100 #define UCR3_RI (1<<8) /* Ring indicator */
101 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
105 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108 #define UCR3_BPEN (1<<0) /* Preset registers enable */
109 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
112 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116 #define UCR4_IRSC (1<<5) /* IR special case */
117 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
122 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
123 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
124 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
125 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
126 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
127 #define USR1_RTSS (1<<14) /* RTS pin status */
128 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
129 #define USR1_RTSD (1<<12) /* RTS delta */
130 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
131 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
132 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
133 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
134 #define USR1_DTRD (1<<7) /* DTR Delta */
135 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
136 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
137 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
138 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
139 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
140 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
141 #define USR2_IDLE (1<<12) /* Idle condition */
142 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
143 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
144 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
145 #define USR2_WAKE (1<<7) /* Wake */
146 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
147 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
148 #define USR2_TXDC (1<<3) /* Transmitter complete */
149 #define USR2_BRCD (1<<2) /* Break condition */
150 #define USR2_ORE (1<<1) /* Overrun error */
151 #define USR2_RDR (1<<0) /* Recv data ready */
152 #define UTS_FRCPERR (1<<13) /* Force parity error */
153 #define UTS_LOOP (1<<12) /* Loop tx and rx */
154 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
155 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
156 #define UTS_TXFULL (1<<4) /* TxFIFO full */
157 #define UTS_RXFULL (1<<3) /* RxFIFO full */
158 #define UTS_SOFTRST (1<<0) /* Software reset */
159
160 /* We've been assigned a range on the "Low-density serial ports" major */
161 #define SERIAL_IMX_MAJOR 207
162 #define MINOR_START 16
163 #define DEV_NAME "ttymxc"
164
165 /*
166 * This determines how often we check the modem status signals
167 * for any change. They generally aren't connected to an IRQ
168 * so we have to poll them. We also check immediately before
169 * filling the TX fifo incase CTS has been dropped.
170 */
171 #define MCTRL_TIMEOUT (250*HZ/1000)
172
173 #define DRIVER_NAME "IMX-uart"
174
175 #define UART_NR 8
176
177 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
178 enum imx_uart_type {
179 IMX1_UART,
180 IMX21_UART,
181 IMX53_UART,
182 IMX6Q_UART,
183 };
184
185 /* device type dependent stuff */
186 struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189 };
190
191 enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196 };
197
198 struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* shadow registers */
214 unsigned int ucr1;
215 unsigned int ucr2;
216 unsigned int ucr3;
217 unsigned int ucr4;
218 unsigned int ufcr;
219
220 /* DMA fields */
221 unsigned int dma_is_enabled:1;
222 unsigned int dma_is_rxing:1;
223 unsigned int dma_is_txing:1;
224 struct dma_chan *dma_chan_rx, *dma_chan_tx;
225 struct scatterlist rx_sgl, tx_sgl[2];
226 void *rx_buf;
227 struct circ_buf rx_ring;
228 unsigned int rx_buf_size;
229 unsigned int rx_period_length;
230 unsigned int rx_periods;
231 dma_cookie_t rx_cookie;
232 unsigned int tx_bytes;
233 unsigned int dma_tx_nents;
234 unsigned int saved_reg[10];
235 bool context_saved;
236
237 enum imx_tx_state tx_state;
238 struct hrtimer trigger_start_tx;
239 struct hrtimer trigger_stop_tx;
240 };
241
242 struct imx_port_ucrs {
243 unsigned int ucr1;
244 unsigned int ucr2;
245 unsigned int ucr3;
246 };
247
248 static struct imx_uart_data imx_uart_devdata[] = {
249 [IMX1_UART] = {
250 .uts_reg = IMX1_UTS,
251 .devtype = IMX1_UART,
252 },
253 [IMX21_UART] = {
254 .uts_reg = IMX21_UTS,
255 .devtype = IMX21_UART,
256 },
257 [IMX53_UART] = {
258 .uts_reg = IMX21_UTS,
259 .devtype = IMX53_UART,
260 },
261 [IMX6Q_UART] = {
262 .uts_reg = IMX21_UTS,
263 .devtype = IMX6Q_UART,
264 },
265 };
266
267 static const struct of_device_id imx_uart_dt_ids[] = {
268 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
269 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
270 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
271 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
272 { /* sentinel */ }
273 };
274 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
275
imx_uart_writel(struct imx_port * sport,u32 val,u32 offset)276 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
277 {
278 switch (offset) {
279 case UCR1:
280 sport->ucr1 = val;
281 break;
282 case UCR2:
283 sport->ucr2 = val;
284 break;
285 case UCR3:
286 sport->ucr3 = val;
287 break;
288 case UCR4:
289 sport->ucr4 = val;
290 break;
291 case UFCR:
292 sport->ufcr = val;
293 break;
294 default:
295 break;
296 }
297 writel(val, sport->port.membase + offset);
298 }
299
imx_uart_readl(struct imx_port * sport,u32 offset)300 static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
301 {
302 switch (offset) {
303 case UCR1:
304 return sport->ucr1;
305 break;
306 case UCR2:
307 /*
308 * UCR2_SRST is the only bit in the cached registers that might
309 * differ from the value that was last written. As it only
310 * automatically becomes one after being cleared, reread
311 * conditionally.
312 */
313 if (!(sport->ucr2 & UCR2_SRST))
314 sport->ucr2 = readl(sport->port.membase + offset);
315 return sport->ucr2;
316 break;
317 case UCR3:
318 return sport->ucr3;
319 break;
320 case UCR4:
321 return sport->ucr4;
322 break;
323 case UFCR:
324 return sport->ufcr;
325 break;
326 default:
327 return readl(sport->port.membase + offset);
328 }
329 }
330
imx_uart_uts_reg(struct imx_port * sport)331 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
332 {
333 return sport->devdata->uts_reg;
334 }
335
imx_uart_is_imx1(struct imx_port * sport)336 static inline int imx_uart_is_imx1(struct imx_port *sport)
337 {
338 return sport->devdata->devtype == IMX1_UART;
339 }
340
imx_uart_is_imx21(struct imx_port * sport)341 static inline int imx_uart_is_imx21(struct imx_port *sport)
342 {
343 return sport->devdata->devtype == IMX21_UART;
344 }
345
imx_uart_is_imx53(struct imx_port * sport)346 static inline int imx_uart_is_imx53(struct imx_port *sport)
347 {
348 return sport->devdata->devtype == IMX53_UART;
349 }
350
imx_uart_is_imx6q(struct imx_port * sport)351 static inline int imx_uart_is_imx6q(struct imx_port *sport)
352 {
353 return sport->devdata->devtype == IMX6Q_UART;
354 }
355 /*
356 * Save and restore functions for UCR1, UCR2 and UCR3 registers
357 */
358 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_ucrs_save(struct imx_port * sport,struct imx_port_ucrs * ucr)359 static void imx_uart_ucrs_save(struct imx_port *sport,
360 struct imx_port_ucrs *ucr)
361 {
362 /* save control registers */
363 ucr->ucr1 = imx_uart_readl(sport, UCR1);
364 ucr->ucr2 = imx_uart_readl(sport, UCR2);
365 ucr->ucr3 = imx_uart_readl(sport, UCR3);
366 }
367
imx_uart_ucrs_restore(struct imx_port * sport,struct imx_port_ucrs * ucr)368 static void imx_uart_ucrs_restore(struct imx_port *sport,
369 struct imx_port_ucrs *ucr)
370 {
371 /* restore control registers */
372 imx_uart_writel(sport, ucr->ucr1, UCR1);
373 imx_uart_writel(sport, ucr->ucr2, UCR2);
374 imx_uart_writel(sport, ucr->ucr3, UCR3);
375 }
376 #endif
377
378 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_active(struct imx_port * sport,u32 * ucr2)379 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
380 {
381 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
382
383 sport->port.mctrl |= TIOCM_RTS;
384 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
385 }
386
387 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_inactive(struct imx_port * sport,u32 * ucr2)388 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
389 {
390 *ucr2 &= ~UCR2_CTSC;
391 *ucr2 |= UCR2_CTS;
392
393 sport->port.mctrl &= ~TIOCM_RTS;
394 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
395 }
396
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)397 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
398 {
399 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
400 }
401
402 /* called with port.lock taken and irqs off */
imx_uart_start_rx(struct uart_port * port)403 static void imx_uart_start_rx(struct uart_port *port)
404 {
405 struct imx_port *sport = (struct imx_port *)port;
406 unsigned int ucr1, ucr2;
407
408 ucr1 = imx_uart_readl(sport, UCR1);
409 ucr2 = imx_uart_readl(sport, UCR2);
410
411 ucr2 |= UCR2_RXEN;
412
413 if (sport->dma_is_enabled) {
414 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
415 } else {
416 ucr1 |= UCR1_RRDYEN;
417 ucr2 |= UCR2_ATEN;
418 }
419
420 /* Write UCR2 first as it includes RXEN */
421 imx_uart_writel(sport, ucr2, UCR2);
422 imx_uart_writel(sport, ucr1, UCR1);
423 }
424
425 /* called with port.lock taken and irqs off */
imx_uart_stop_tx(struct uart_port * port)426 static void imx_uart_stop_tx(struct uart_port *port)
427 {
428 struct imx_port *sport = (struct imx_port *)port;
429 u32 ucr1, ucr4, usr2;
430
431 if (sport->tx_state == OFF)
432 return;
433
434 /*
435 * We are maybe in the SMP context, so if the DMA TX thread is running
436 * on other cpu, we have to wait for it to finish.
437 */
438 if (sport->dma_is_txing)
439 return;
440
441 ucr1 = imx_uart_readl(sport, UCR1);
442 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
443
444 usr2 = imx_uart_readl(sport, USR2);
445 if (!(usr2 & USR2_TXDC)) {
446 /* The shifter is still busy, so retry once TC triggers */
447 return;
448 }
449
450 ucr4 = imx_uart_readl(sport, UCR4);
451 ucr4 &= ~UCR4_TCEN;
452 imx_uart_writel(sport, ucr4, UCR4);
453
454 /* in rs485 mode disable transmitter */
455 if (port->rs485.flags & SER_RS485_ENABLED) {
456 if (sport->tx_state == SEND) {
457 sport->tx_state = WAIT_AFTER_SEND;
458
459 if (port->rs485.delay_rts_after_send > 0) {
460 start_hrtimer_ms(&sport->trigger_stop_tx,
461 port->rs485.delay_rts_after_send);
462 return;
463 }
464
465 /* continue without any delay */
466 }
467
468 if (sport->tx_state == WAIT_AFTER_RTS ||
469 sport->tx_state == WAIT_AFTER_SEND) {
470 u32 ucr2;
471
472 hrtimer_try_to_cancel(&sport->trigger_start_tx);
473
474 ucr2 = imx_uart_readl(sport, UCR2);
475 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
476 imx_uart_rts_active(sport, &ucr2);
477 else
478 imx_uart_rts_inactive(sport, &ucr2);
479 imx_uart_writel(sport, ucr2, UCR2);
480
481 imx_uart_start_rx(port);
482
483 sport->tx_state = OFF;
484 }
485 } else {
486 sport->tx_state = OFF;
487 }
488 }
489
490 /* called with port.lock taken and irqs off */
imx_uart_stop_rx(struct uart_port * port)491 static void imx_uart_stop_rx(struct uart_port *port)
492 {
493 struct imx_port *sport = (struct imx_port *)port;
494 u32 ucr1, ucr2, ucr4;
495
496 ucr1 = imx_uart_readl(sport, UCR1);
497 ucr2 = imx_uart_readl(sport, UCR2);
498 ucr4 = imx_uart_readl(sport, UCR4);
499
500 if (sport->dma_is_enabled) {
501 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
502 } else {
503 ucr1 &= ~UCR1_RRDYEN;
504 ucr2 &= ~UCR2_ATEN;
505 ucr4 &= ~UCR4_OREN;
506 }
507 imx_uart_writel(sport, ucr1, UCR1);
508 imx_uart_writel(sport, ucr4, UCR4);
509
510 ucr2 &= ~UCR2_RXEN;
511 imx_uart_writel(sport, ucr2, UCR2);
512 }
513
514 /* called with port.lock taken and irqs off */
imx_uart_enable_ms(struct uart_port * port)515 static void imx_uart_enable_ms(struct uart_port *port)
516 {
517 struct imx_port *sport = (struct imx_port *)port;
518
519 mod_timer(&sport->timer, jiffies);
520
521 mctrl_gpio_enable_ms(sport->gpios);
522 }
523
524 static void imx_uart_dma_tx(struct imx_port *sport);
525
526 /* called with port.lock taken and irqs off */
imx_uart_transmit_buffer(struct imx_port * sport)527 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
528 {
529 struct circ_buf *xmit = &sport->port.state->xmit;
530
531 if (sport->port.x_char) {
532 /* Send next char */
533 imx_uart_writel(sport, sport->port.x_char, URTX0);
534 sport->port.icount.tx++;
535 sport->port.x_char = 0;
536 return;
537 }
538
539 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
540 imx_uart_stop_tx(&sport->port);
541 return;
542 }
543
544 if (sport->dma_is_enabled) {
545 u32 ucr1;
546 /*
547 * We've just sent a X-char Ensure the TX DMA is enabled
548 * and the TX IRQ is disabled.
549 **/
550 ucr1 = imx_uart_readl(sport, UCR1);
551 ucr1 &= ~UCR1_TRDYEN;
552 if (sport->dma_is_txing) {
553 ucr1 |= UCR1_TXDMAEN;
554 imx_uart_writel(sport, ucr1, UCR1);
555 } else {
556 imx_uart_writel(sport, ucr1, UCR1);
557 imx_uart_dma_tx(sport);
558 }
559
560 return;
561 }
562
563 while (!uart_circ_empty(xmit) &&
564 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
565 /* send xmit->buf[xmit->tail]
566 * out the port here */
567 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
568 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
569 sport->port.icount.tx++;
570 }
571
572 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
573 uart_write_wakeup(&sport->port);
574
575 if (uart_circ_empty(xmit))
576 imx_uart_stop_tx(&sport->port);
577 }
578
imx_uart_dma_tx_callback(void * data)579 static void imx_uart_dma_tx_callback(void *data)
580 {
581 struct imx_port *sport = data;
582 struct scatterlist *sgl = &sport->tx_sgl[0];
583 struct circ_buf *xmit = &sport->port.state->xmit;
584 unsigned long flags;
585 u32 ucr1;
586
587 spin_lock_irqsave(&sport->port.lock, flags);
588
589 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
590
591 ucr1 = imx_uart_readl(sport, UCR1);
592 ucr1 &= ~UCR1_TXDMAEN;
593 imx_uart_writel(sport, ucr1, UCR1);
594
595 /* update the stat */
596 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
597 sport->port.icount.tx += sport->tx_bytes;
598
599 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
600
601 sport->dma_is_txing = 0;
602
603 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
604 uart_write_wakeup(&sport->port);
605
606 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
607 imx_uart_dma_tx(sport);
608 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
609 u32 ucr4 = imx_uart_readl(sport, UCR4);
610 ucr4 |= UCR4_TCEN;
611 imx_uart_writel(sport, ucr4, UCR4);
612 }
613
614 spin_unlock_irqrestore(&sport->port.lock, flags);
615 }
616
617 /* called with port.lock taken and irqs off */
imx_uart_dma_tx(struct imx_port * sport)618 static void imx_uart_dma_tx(struct imx_port *sport)
619 {
620 struct circ_buf *xmit = &sport->port.state->xmit;
621 struct scatterlist *sgl = sport->tx_sgl;
622 struct dma_async_tx_descriptor *desc;
623 struct dma_chan *chan = sport->dma_chan_tx;
624 struct device *dev = sport->port.dev;
625 u32 ucr1, ucr4;
626 int ret;
627
628 if (sport->dma_is_txing)
629 return;
630
631 ucr4 = imx_uart_readl(sport, UCR4);
632 ucr4 &= ~UCR4_TCEN;
633 imx_uart_writel(sport, ucr4, UCR4);
634
635 sport->tx_bytes = uart_circ_chars_pending(xmit);
636
637 if (xmit->tail < xmit->head || xmit->head == 0) {
638 sport->dma_tx_nents = 1;
639 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
640 } else {
641 sport->dma_tx_nents = 2;
642 sg_init_table(sgl, 2);
643 sg_set_buf(sgl, xmit->buf + xmit->tail,
644 UART_XMIT_SIZE - xmit->tail);
645 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
646 }
647
648 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
649 if (ret == 0) {
650 dev_err(dev, "DMA mapping error for TX.\n");
651 return;
652 }
653 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
654 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
655 if (!desc) {
656 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
657 DMA_TO_DEVICE);
658 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
659 return;
660 }
661 desc->callback = imx_uart_dma_tx_callback;
662 desc->callback_param = sport;
663
664 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
665 uart_circ_chars_pending(xmit));
666
667 ucr1 = imx_uart_readl(sport, UCR1);
668 ucr1 |= UCR1_TXDMAEN;
669 imx_uart_writel(sport, ucr1, UCR1);
670
671 /* fire it */
672 sport->dma_is_txing = 1;
673 dmaengine_submit(desc);
674 dma_async_issue_pending(chan);
675 return;
676 }
677
678 /* called with port.lock taken and irqs off */
imx_uart_start_tx(struct uart_port * port)679 static void imx_uart_start_tx(struct uart_port *port)
680 {
681 struct imx_port *sport = (struct imx_port *)port;
682 u32 ucr1;
683
684 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
685 return;
686
687 /*
688 * We cannot simply do nothing here if sport->tx_state == SEND already
689 * because UCR1_TXMPTYEN might already have been cleared in
690 * imx_uart_stop_tx(), but tx_state is still SEND.
691 */
692
693 if (port->rs485.flags & SER_RS485_ENABLED) {
694 if (sport->tx_state == OFF) {
695 u32 ucr2 = imx_uart_readl(sport, UCR2);
696 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
697 imx_uart_rts_active(sport, &ucr2);
698 else
699 imx_uart_rts_inactive(sport, &ucr2);
700 imx_uart_writel(sport, ucr2, UCR2);
701
702 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
703 imx_uart_stop_rx(port);
704
705 sport->tx_state = WAIT_AFTER_RTS;
706
707 if (port->rs485.delay_rts_before_send > 0) {
708 start_hrtimer_ms(&sport->trigger_start_tx,
709 port->rs485.delay_rts_before_send);
710 return;
711 }
712
713 /* continue without any delay */
714 }
715
716 if (sport->tx_state == WAIT_AFTER_SEND
717 || sport->tx_state == WAIT_AFTER_RTS) {
718
719 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
720
721 /*
722 * Enable transmitter and shifter empty irq only if DMA
723 * is off. In the DMA case this is done in the
724 * tx-callback.
725 */
726 if (!sport->dma_is_enabled) {
727 u32 ucr4 = imx_uart_readl(sport, UCR4);
728 ucr4 |= UCR4_TCEN;
729 imx_uart_writel(sport, ucr4, UCR4);
730 }
731
732 sport->tx_state = SEND;
733 }
734 } else {
735 sport->tx_state = SEND;
736 }
737
738 if (!sport->dma_is_enabled) {
739 ucr1 = imx_uart_readl(sport, UCR1);
740 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
741 }
742
743 if (sport->dma_is_enabled) {
744 if (sport->port.x_char) {
745 /* We have X-char to send, so enable TX IRQ and
746 * disable TX DMA to let TX interrupt to send X-char */
747 ucr1 = imx_uart_readl(sport, UCR1);
748 ucr1 &= ~UCR1_TXDMAEN;
749 ucr1 |= UCR1_TRDYEN;
750 imx_uart_writel(sport, ucr1, UCR1);
751 return;
752 }
753
754 if (!uart_circ_empty(&port->state->xmit) &&
755 !uart_tx_stopped(port))
756 imx_uart_dma_tx(sport);
757 return;
758 }
759 }
760
__imx_uart_rtsint(int irq,void * dev_id)761 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
762 {
763 struct imx_port *sport = dev_id;
764 u32 usr1;
765
766 imx_uart_writel(sport, USR1_RTSD, USR1);
767 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
768 uart_handle_cts_change(&sport->port, !!usr1);
769 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
770
771 return IRQ_HANDLED;
772 }
773
imx_uart_rtsint(int irq,void * dev_id)774 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
775 {
776 struct imx_port *sport = dev_id;
777 irqreturn_t ret;
778
779 spin_lock(&sport->port.lock);
780
781 ret = __imx_uart_rtsint(irq, dev_id);
782
783 spin_unlock(&sport->port.lock);
784
785 return ret;
786 }
787
imx_uart_txint(int irq,void * dev_id)788 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
789 {
790 struct imx_port *sport = dev_id;
791
792 spin_lock(&sport->port.lock);
793 imx_uart_transmit_buffer(sport);
794 spin_unlock(&sport->port.lock);
795 return IRQ_HANDLED;
796 }
797
__imx_uart_rxint(int irq,void * dev_id)798 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
799 {
800 struct imx_port *sport = dev_id;
801 unsigned int rx, flg, ignored = 0;
802 struct tty_port *port = &sport->port.state->port;
803
804 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
805 u32 usr2;
806
807 flg = TTY_NORMAL;
808 sport->port.icount.rx++;
809
810 rx = imx_uart_readl(sport, URXD0);
811
812 usr2 = imx_uart_readl(sport, USR2);
813 if (usr2 & USR2_BRCD) {
814 imx_uart_writel(sport, USR2_BRCD, USR2);
815 if (uart_handle_break(&sport->port))
816 continue;
817 }
818
819 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
820 continue;
821
822 if (unlikely(rx & URXD_ERR)) {
823 if (rx & URXD_BRK)
824 sport->port.icount.brk++;
825 else if (rx & URXD_PRERR)
826 sport->port.icount.parity++;
827 else if (rx & URXD_FRMERR)
828 sport->port.icount.frame++;
829 if (rx & URXD_OVRRUN)
830 sport->port.icount.overrun++;
831
832 if (rx & sport->port.ignore_status_mask) {
833 if (++ignored > 100)
834 goto out;
835 continue;
836 }
837
838 rx &= (sport->port.read_status_mask | 0xFF);
839
840 if (rx & URXD_BRK)
841 flg = TTY_BREAK;
842 else if (rx & URXD_PRERR)
843 flg = TTY_PARITY;
844 else if (rx & URXD_FRMERR)
845 flg = TTY_FRAME;
846 if (rx & URXD_OVRRUN)
847 flg = TTY_OVERRUN;
848
849 sport->port.sysrq = 0;
850 }
851
852 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
853 goto out;
854
855 if (tty_insert_flip_char(port, rx, flg) == 0)
856 sport->port.icount.buf_overrun++;
857 }
858
859 out:
860 tty_flip_buffer_push(port);
861
862 return IRQ_HANDLED;
863 }
864
imx_uart_rxint(int irq,void * dev_id)865 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
866 {
867 struct imx_port *sport = dev_id;
868 irqreturn_t ret;
869
870 spin_lock(&sport->port.lock);
871
872 ret = __imx_uart_rxint(irq, dev_id);
873
874 spin_unlock(&sport->port.lock);
875
876 return ret;
877 }
878
879 static void imx_uart_clear_rx_errors(struct imx_port *sport);
880
881 /*
882 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
883 */
imx_uart_get_hwmctrl(struct imx_port * sport)884 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
885 {
886 unsigned int tmp = TIOCM_DSR;
887 unsigned usr1 = imx_uart_readl(sport, USR1);
888 unsigned usr2 = imx_uart_readl(sport, USR2);
889
890 if (usr1 & USR1_RTSS)
891 tmp |= TIOCM_CTS;
892
893 /* in DCE mode DCDIN is always 0 */
894 if (!(usr2 & USR2_DCDIN))
895 tmp |= TIOCM_CAR;
896
897 if (sport->dte_mode)
898 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
899 tmp |= TIOCM_RI;
900
901 return tmp;
902 }
903
904 /*
905 * Handle any change of modem status signal since we were last called.
906 */
imx_uart_mctrl_check(struct imx_port * sport)907 static void imx_uart_mctrl_check(struct imx_port *sport)
908 {
909 unsigned int status, changed;
910
911 status = imx_uart_get_hwmctrl(sport);
912 changed = status ^ sport->old_status;
913
914 if (changed == 0)
915 return;
916
917 sport->old_status = status;
918
919 if (changed & TIOCM_RI && status & TIOCM_RI)
920 sport->port.icount.rng++;
921 if (changed & TIOCM_DSR)
922 sport->port.icount.dsr++;
923 if (changed & TIOCM_CAR)
924 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
925 if (changed & TIOCM_CTS)
926 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
927
928 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
929 }
930
imx_uart_int(int irq,void * dev_id)931 static irqreturn_t imx_uart_int(int irq, void *dev_id)
932 {
933 struct imx_port *sport = dev_id;
934 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
935 irqreturn_t ret = IRQ_NONE;
936
937 spin_lock(&sport->port.lock);
938
939 usr1 = imx_uart_readl(sport, USR1);
940 usr2 = imx_uart_readl(sport, USR2);
941 ucr1 = imx_uart_readl(sport, UCR1);
942 ucr2 = imx_uart_readl(sport, UCR2);
943 ucr3 = imx_uart_readl(sport, UCR3);
944 ucr4 = imx_uart_readl(sport, UCR4);
945
946 /*
947 * Even if a condition is true that can trigger an irq only handle it if
948 * the respective irq source is enabled. This prevents some undesired
949 * actions, for example if a character that sits in the RX FIFO and that
950 * should be fetched via DMA is tried to be fetched using PIO. Or the
951 * receiver is currently off and so reading from URXD0 results in an
952 * exception. So just mask the (raw) status bits for disabled irqs.
953 */
954 if ((ucr1 & UCR1_RRDYEN) == 0)
955 usr1 &= ~USR1_RRDY;
956 if ((ucr2 & UCR2_ATEN) == 0)
957 usr1 &= ~USR1_AGTIM;
958 if ((ucr1 & UCR1_TRDYEN) == 0)
959 usr1 &= ~USR1_TRDY;
960 if ((ucr4 & UCR4_TCEN) == 0)
961 usr2 &= ~USR2_TXDC;
962 if ((ucr3 & UCR3_DTRDEN) == 0)
963 usr1 &= ~USR1_DTRD;
964 if ((ucr1 & UCR1_RTSDEN) == 0)
965 usr1 &= ~USR1_RTSD;
966 if ((ucr3 & UCR3_AWAKEN) == 0)
967 usr1 &= ~USR1_AWAKE;
968 if ((ucr4 & UCR4_OREN) == 0)
969 usr2 &= ~USR2_ORE;
970
971 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
972 imx_uart_writel(sport, USR1_AGTIM, USR1);
973
974 __imx_uart_rxint(irq, dev_id);
975 ret = IRQ_HANDLED;
976 }
977
978 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
979 imx_uart_transmit_buffer(sport);
980 ret = IRQ_HANDLED;
981 }
982
983 if (usr1 & USR1_DTRD) {
984 imx_uart_writel(sport, USR1_DTRD, USR1);
985
986 imx_uart_mctrl_check(sport);
987
988 ret = IRQ_HANDLED;
989 }
990
991 if (usr1 & USR1_RTSD) {
992 __imx_uart_rtsint(irq, dev_id);
993 ret = IRQ_HANDLED;
994 }
995
996 if (usr1 & USR1_AWAKE) {
997 imx_uart_writel(sport, USR1_AWAKE, USR1);
998 ret = IRQ_HANDLED;
999 }
1000
1001 if (usr2 & USR2_ORE) {
1002 sport->port.icount.overrun++;
1003 imx_uart_writel(sport, USR2_ORE, USR2);
1004 ret = IRQ_HANDLED;
1005 }
1006
1007 spin_unlock(&sport->port.lock);
1008
1009 return ret;
1010 }
1011
1012 /*
1013 * Return TIOCSER_TEMT when transmitter is not busy.
1014 */
imx_uart_tx_empty(struct uart_port * port)1015 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1016 {
1017 struct imx_port *sport = (struct imx_port *)port;
1018 unsigned int ret;
1019
1020 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1021
1022 /* If the TX DMA is working, return 0. */
1023 if (sport->dma_is_txing)
1024 ret = 0;
1025
1026 return ret;
1027 }
1028
1029 /* called with port.lock taken and irqs off */
imx_uart_get_mctrl(struct uart_port * port)1030 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1031 {
1032 struct imx_port *sport = (struct imx_port *)port;
1033 unsigned int ret = imx_uart_get_hwmctrl(sport);
1034
1035 mctrl_gpio_get(sport->gpios, &ret);
1036
1037 return ret;
1038 }
1039
1040 /* called with port.lock taken and irqs off */
imx_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1041 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1042 {
1043 struct imx_port *sport = (struct imx_port *)port;
1044 u32 ucr3, uts;
1045
1046 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1047 u32 ucr2;
1048
1049 /*
1050 * Turn off autoRTS if RTS is lowered and restore autoRTS
1051 * setting if RTS is raised.
1052 */
1053 ucr2 = imx_uart_readl(sport, UCR2);
1054 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1055 if (mctrl & TIOCM_RTS) {
1056 ucr2 |= UCR2_CTS;
1057 /*
1058 * UCR2_IRTS is unset if and only if the port is
1059 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1060 * to get the state to restore to.
1061 */
1062 if (!(ucr2 & UCR2_IRTS))
1063 ucr2 |= UCR2_CTSC;
1064 }
1065 imx_uart_writel(sport, ucr2, UCR2);
1066 }
1067
1068 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1069 if (!(mctrl & TIOCM_DTR))
1070 ucr3 |= UCR3_DSR;
1071 imx_uart_writel(sport, ucr3, UCR3);
1072
1073 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1074 if (mctrl & TIOCM_LOOP)
1075 uts |= UTS_LOOP;
1076 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1077
1078 mctrl_gpio_set(sport->gpios, mctrl);
1079 }
1080
1081 /*
1082 * Interrupts always disabled.
1083 */
imx_uart_break_ctl(struct uart_port * port,int break_state)1084 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1085 {
1086 struct imx_port *sport = (struct imx_port *)port;
1087 unsigned long flags;
1088 u32 ucr1;
1089
1090 spin_lock_irqsave(&sport->port.lock, flags);
1091
1092 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1093
1094 if (break_state != 0)
1095 ucr1 |= UCR1_SNDBRK;
1096
1097 imx_uart_writel(sport, ucr1, UCR1);
1098
1099 spin_unlock_irqrestore(&sport->port.lock, flags);
1100 }
1101
1102 /*
1103 * This is our per-port timeout handler, for checking the
1104 * modem status signals.
1105 */
imx_uart_timeout(struct timer_list * t)1106 static void imx_uart_timeout(struct timer_list *t)
1107 {
1108 struct imx_port *sport = from_timer(sport, t, timer);
1109 unsigned long flags;
1110
1111 if (sport->port.state) {
1112 spin_lock_irqsave(&sport->port.lock, flags);
1113 imx_uart_mctrl_check(sport);
1114 spin_unlock_irqrestore(&sport->port.lock, flags);
1115
1116 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1117 }
1118 }
1119
1120 /*
1121 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1122 * [1] the RX DMA buffer is full.
1123 * [2] the aging timer expires
1124 *
1125 * Condition [2] is triggered when a character has been sitting in the FIFO
1126 * for at least 8 byte durations.
1127 */
imx_uart_dma_rx_callback(void * data)1128 static void imx_uart_dma_rx_callback(void *data)
1129 {
1130 struct imx_port *sport = data;
1131 struct dma_chan *chan = sport->dma_chan_rx;
1132 struct scatterlist *sgl = &sport->rx_sgl;
1133 struct tty_port *port = &sport->port.state->port;
1134 struct dma_tx_state state;
1135 struct circ_buf *rx_ring = &sport->rx_ring;
1136 enum dma_status status;
1137 unsigned int w_bytes = 0;
1138 unsigned int r_bytes;
1139 unsigned int bd_size;
1140
1141 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1142
1143 if (status == DMA_ERROR) {
1144 imx_uart_clear_rx_errors(sport);
1145 return;
1146 }
1147
1148 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1149
1150 /*
1151 * The state-residue variable represents the empty space
1152 * relative to the entire buffer. Taking this in consideration
1153 * the head is always calculated base on the buffer total
1154 * length - DMA transaction residue. The UART script from the
1155 * SDMA firmware will jump to the next buffer descriptor,
1156 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1157 * Taking this in consideration the tail is always at the
1158 * beginning of the buffer descriptor that contains the head.
1159 */
1160
1161 /* Calculate the head */
1162 rx_ring->head = sg_dma_len(sgl) - state.residue;
1163
1164 /* Calculate the tail. */
1165 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1166 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1167
1168 if (rx_ring->head <= sg_dma_len(sgl) &&
1169 rx_ring->head > rx_ring->tail) {
1170
1171 /* Move data from tail to head */
1172 r_bytes = rx_ring->head - rx_ring->tail;
1173
1174 /* CPU claims ownership of RX DMA buffer */
1175 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1176 DMA_FROM_DEVICE);
1177
1178 w_bytes = tty_insert_flip_string(port,
1179 sport->rx_buf + rx_ring->tail, r_bytes);
1180
1181 /* UART retrieves ownership of RX DMA buffer */
1182 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1183 DMA_FROM_DEVICE);
1184
1185 if (w_bytes != r_bytes)
1186 sport->port.icount.buf_overrun++;
1187
1188 sport->port.icount.rx += w_bytes;
1189 } else {
1190 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1191 WARN_ON(rx_ring->head <= rx_ring->tail);
1192 }
1193 }
1194
1195 if (w_bytes) {
1196 tty_flip_buffer_push(port);
1197 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1198 }
1199 }
1200
imx_uart_start_rx_dma(struct imx_port * sport)1201 static int imx_uart_start_rx_dma(struct imx_port *sport)
1202 {
1203 struct scatterlist *sgl = &sport->rx_sgl;
1204 struct dma_chan *chan = sport->dma_chan_rx;
1205 struct device *dev = sport->port.dev;
1206 struct dma_async_tx_descriptor *desc;
1207 int ret;
1208
1209 sport->rx_ring.head = 0;
1210 sport->rx_ring.tail = 0;
1211
1212 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1213 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1214 if (ret == 0) {
1215 dev_err(dev, "DMA mapping error for RX.\n");
1216 return -EINVAL;
1217 }
1218
1219 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1220 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1221 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1222
1223 if (!desc) {
1224 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1225 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1226 return -EINVAL;
1227 }
1228 desc->callback = imx_uart_dma_rx_callback;
1229 desc->callback_param = sport;
1230
1231 dev_dbg(dev, "RX: prepare for the DMA.\n");
1232 sport->dma_is_rxing = 1;
1233 sport->rx_cookie = dmaengine_submit(desc);
1234 dma_async_issue_pending(chan);
1235 return 0;
1236 }
1237
imx_uart_clear_rx_errors(struct imx_port * sport)1238 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1239 {
1240 struct tty_port *port = &sport->port.state->port;
1241 u32 usr1, usr2;
1242
1243 usr1 = imx_uart_readl(sport, USR1);
1244 usr2 = imx_uart_readl(sport, USR2);
1245
1246 if (usr2 & USR2_BRCD) {
1247 sport->port.icount.brk++;
1248 imx_uart_writel(sport, USR2_BRCD, USR2);
1249 uart_handle_break(&sport->port);
1250 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1251 sport->port.icount.buf_overrun++;
1252 tty_flip_buffer_push(port);
1253 } else {
1254 if (usr1 & USR1_FRAMERR) {
1255 sport->port.icount.frame++;
1256 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1257 } else if (usr1 & USR1_PARITYERR) {
1258 sport->port.icount.parity++;
1259 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1260 }
1261 }
1262
1263 if (usr2 & USR2_ORE) {
1264 sport->port.icount.overrun++;
1265 imx_uart_writel(sport, USR2_ORE, USR2);
1266 }
1267
1268 }
1269
1270 #define TXTL_DEFAULT 2 /* reset default */
1271 #define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1272 #define TXTL_DMA 8 /* DMA burst setting */
1273 #define RXTL_DMA 9 /* DMA burst setting */
1274
imx_uart_setup_ufcr(struct imx_port * sport,unsigned char txwl,unsigned char rxwl)1275 static void imx_uart_setup_ufcr(struct imx_port *sport,
1276 unsigned char txwl, unsigned char rxwl)
1277 {
1278 unsigned int val;
1279
1280 /* set receiver / transmitter trigger level */
1281 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1282 val |= txwl << UFCR_TXTL_SHF | rxwl;
1283 imx_uart_writel(sport, val, UFCR);
1284 }
1285
imx_uart_dma_exit(struct imx_port * sport)1286 static void imx_uart_dma_exit(struct imx_port *sport)
1287 {
1288 if (sport->dma_chan_rx) {
1289 dmaengine_terminate_sync(sport->dma_chan_rx);
1290 dma_release_channel(sport->dma_chan_rx);
1291 sport->dma_chan_rx = NULL;
1292 sport->rx_cookie = -EINVAL;
1293 kfree(sport->rx_buf);
1294 sport->rx_buf = NULL;
1295 }
1296
1297 if (sport->dma_chan_tx) {
1298 dmaengine_terminate_sync(sport->dma_chan_tx);
1299 dma_release_channel(sport->dma_chan_tx);
1300 sport->dma_chan_tx = NULL;
1301 }
1302 }
1303
imx_uart_dma_init(struct imx_port * sport)1304 static int imx_uart_dma_init(struct imx_port *sport)
1305 {
1306 struct dma_slave_config slave_config = {};
1307 struct device *dev = sport->port.dev;
1308 int ret;
1309
1310 /* Prepare for RX : */
1311 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1312 if (!sport->dma_chan_rx) {
1313 dev_dbg(dev, "cannot get the DMA channel.\n");
1314 ret = -EINVAL;
1315 goto err;
1316 }
1317
1318 slave_config.direction = DMA_DEV_TO_MEM;
1319 slave_config.src_addr = sport->port.mapbase + URXD0;
1320 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1321 /* one byte less than the watermark level to enable the aging timer */
1322 slave_config.src_maxburst = RXTL_DMA - 1;
1323 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1324 if (ret) {
1325 dev_err(dev, "error in RX dma configuration.\n");
1326 goto err;
1327 }
1328
1329 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1330 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1331 if (!sport->rx_buf) {
1332 ret = -ENOMEM;
1333 goto err;
1334 }
1335 sport->rx_ring.buf = sport->rx_buf;
1336
1337 /* Prepare for TX : */
1338 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1339 if (!sport->dma_chan_tx) {
1340 dev_err(dev, "cannot get the TX DMA channel!\n");
1341 ret = -EINVAL;
1342 goto err;
1343 }
1344
1345 slave_config.direction = DMA_MEM_TO_DEV;
1346 slave_config.dst_addr = sport->port.mapbase + URTX0;
1347 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1348 slave_config.dst_maxburst = TXTL_DMA;
1349 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1350 if (ret) {
1351 dev_err(dev, "error in TX dma configuration.");
1352 goto err;
1353 }
1354
1355 return 0;
1356 err:
1357 imx_uart_dma_exit(sport);
1358 return ret;
1359 }
1360
imx_uart_enable_dma(struct imx_port * sport)1361 static void imx_uart_enable_dma(struct imx_port *sport)
1362 {
1363 u32 ucr1;
1364
1365 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1366
1367 /* set UCR1 */
1368 ucr1 = imx_uart_readl(sport, UCR1);
1369 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1370 imx_uart_writel(sport, ucr1, UCR1);
1371
1372 sport->dma_is_enabled = 1;
1373 }
1374
imx_uart_disable_dma(struct imx_port * sport)1375 static void imx_uart_disable_dma(struct imx_port *sport)
1376 {
1377 u32 ucr1;
1378
1379 /* clear UCR1 */
1380 ucr1 = imx_uart_readl(sport, UCR1);
1381 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1382 imx_uart_writel(sport, ucr1, UCR1);
1383
1384 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1385
1386 sport->dma_is_enabled = 0;
1387 }
1388
1389 /* half the RX buffer size */
1390 #define CTSTL 16
1391
imx_uart_startup(struct uart_port * port)1392 static int imx_uart_startup(struct uart_port *port)
1393 {
1394 struct imx_port *sport = (struct imx_port *)port;
1395 int retval, i;
1396 unsigned long flags;
1397 int dma_is_inited = 0;
1398 u32 ucr1, ucr2, ucr3, ucr4;
1399
1400 retval = clk_prepare_enable(sport->clk_per);
1401 if (retval)
1402 return retval;
1403 retval = clk_prepare_enable(sport->clk_ipg);
1404 if (retval) {
1405 clk_disable_unprepare(sport->clk_per);
1406 return retval;
1407 }
1408
1409 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1410
1411 /* disable the DREN bit (Data Ready interrupt enable) before
1412 * requesting IRQs
1413 */
1414 ucr4 = imx_uart_readl(sport, UCR4);
1415
1416 /* set the trigger level for CTS */
1417 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1418 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1419
1420 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1421
1422 /* Can we enable the DMA support? */
1423 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1424 dma_is_inited = 1;
1425
1426 spin_lock_irqsave(&sport->port.lock, flags);
1427 /* Reset fifo's and state machines */
1428 i = 100;
1429
1430 ucr2 = imx_uart_readl(sport, UCR2);
1431 ucr2 &= ~UCR2_SRST;
1432 imx_uart_writel(sport, ucr2, UCR2);
1433
1434 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1435 udelay(1);
1436
1437 /*
1438 * Finally, clear and enable interrupts
1439 */
1440 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1441 imx_uart_writel(sport, USR2_ORE, USR2);
1442
1443 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1444 ucr1 |= UCR1_UARTEN;
1445 if (sport->have_rtscts)
1446 ucr1 |= UCR1_RTSDEN;
1447
1448 imx_uart_writel(sport, ucr1, UCR1);
1449
1450 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1451 if (!dma_is_inited)
1452 ucr4 |= UCR4_OREN;
1453 if (sport->inverted_rx)
1454 ucr4 |= UCR4_INVR;
1455 imx_uart_writel(sport, ucr4, UCR4);
1456
1457 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1458 /*
1459 * configure tx polarity before enabling tx
1460 */
1461 if (sport->inverted_tx)
1462 ucr3 |= UCR3_INVT;
1463
1464 if (!imx_uart_is_imx1(sport)) {
1465 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1466
1467 if (sport->dte_mode)
1468 /* disable broken interrupts */
1469 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1470 }
1471 imx_uart_writel(sport, ucr3, UCR3);
1472
1473 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1474 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1475 if (!sport->have_rtscts)
1476 ucr2 |= UCR2_IRTS;
1477 /*
1478 * make sure the edge sensitive RTS-irq is disabled,
1479 * we're using RTSD instead.
1480 */
1481 if (!imx_uart_is_imx1(sport))
1482 ucr2 &= ~UCR2_RTSEN;
1483 imx_uart_writel(sport, ucr2, UCR2);
1484
1485 /*
1486 * Enable modem status interrupts
1487 */
1488 imx_uart_enable_ms(&sport->port);
1489
1490 if (dma_is_inited) {
1491 imx_uart_enable_dma(sport);
1492 imx_uart_start_rx_dma(sport);
1493 } else {
1494 ucr1 = imx_uart_readl(sport, UCR1);
1495 ucr1 |= UCR1_RRDYEN;
1496 imx_uart_writel(sport, ucr1, UCR1);
1497
1498 ucr2 = imx_uart_readl(sport, UCR2);
1499 ucr2 |= UCR2_ATEN;
1500 imx_uart_writel(sport, ucr2, UCR2);
1501 }
1502
1503 spin_unlock_irqrestore(&sport->port.lock, flags);
1504
1505 return 0;
1506 }
1507
imx_uart_shutdown(struct uart_port * port)1508 static void imx_uart_shutdown(struct uart_port *port)
1509 {
1510 struct imx_port *sport = (struct imx_port *)port;
1511 unsigned long flags;
1512 u32 ucr1, ucr2, ucr4;
1513
1514 if (sport->dma_is_enabled) {
1515 dmaengine_terminate_sync(sport->dma_chan_tx);
1516 if (sport->dma_is_txing) {
1517 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1518 sport->dma_tx_nents, DMA_TO_DEVICE);
1519 sport->dma_is_txing = 0;
1520 }
1521 dmaengine_terminate_sync(sport->dma_chan_rx);
1522 if (sport->dma_is_rxing) {
1523 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1524 1, DMA_FROM_DEVICE);
1525 sport->dma_is_rxing = 0;
1526 }
1527
1528 spin_lock_irqsave(&sport->port.lock, flags);
1529 imx_uart_stop_tx(port);
1530 imx_uart_stop_rx(port);
1531 imx_uart_disable_dma(sport);
1532 spin_unlock_irqrestore(&sport->port.lock, flags);
1533 imx_uart_dma_exit(sport);
1534 }
1535
1536 mctrl_gpio_disable_ms(sport->gpios);
1537
1538 spin_lock_irqsave(&sport->port.lock, flags);
1539 ucr2 = imx_uart_readl(sport, UCR2);
1540 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1541 imx_uart_writel(sport, ucr2, UCR2);
1542 spin_unlock_irqrestore(&sport->port.lock, flags);
1543
1544 /*
1545 * Stop our timer.
1546 */
1547 del_timer_sync(&sport->timer);
1548
1549 /*
1550 * Disable all interrupts, port and break condition.
1551 */
1552
1553 spin_lock_irqsave(&sport->port.lock, flags);
1554
1555 ucr1 = imx_uart_readl(sport, UCR1);
1556 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1557 imx_uart_writel(sport, ucr1, UCR1);
1558
1559 ucr4 = imx_uart_readl(sport, UCR4);
1560 ucr4 &= ~UCR4_TCEN;
1561 imx_uart_writel(sport, ucr4, UCR4);
1562
1563 spin_unlock_irqrestore(&sport->port.lock, flags);
1564
1565 clk_disable_unprepare(sport->clk_per);
1566 clk_disable_unprepare(sport->clk_ipg);
1567 }
1568
1569 /* called with port.lock taken and irqs off */
imx_uart_flush_buffer(struct uart_port * port)1570 static void imx_uart_flush_buffer(struct uart_port *port)
1571 {
1572 struct imx_port *sport = (struct imx_port *)port;
1573 struct scatterlist *sgl = &sport->tx_sgl[0];
1574 u32 ucr2;
1575 int i = 100, ubir, ubmr, uts;
1576
1577 if (!sport->dma_chan_tx)
1578 return;
1579
1580 sport->tx_bytes = 0;
1581 dmaengine_terminate_all(sport->dma_chan_tx);
1582 if (sport->dma_is_txing) {
1583 u32 ucr1;
1584
1585 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1586 DMA_TO_DEVICE);
1587 ucr1 = imx_uart_readl(sport, UCR1);
1588 ucr1 &= ~UCR1_TXDMAEN;
1589 imx_uart_writel(sport, ucr1, UCR1);
1590 sport->dma_is_txing = 0;
1591 }
1592
1593 /*
1594 * According to the Reference Manual description of the UART SRST bit:
1595 *
1596 * "Reset the transmit and receive state machines,
1597 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1598 * and UTS[6-3]".
1599 *
1600 * We don't need to restore the old values from USR1, USR2, URXD and
1601 * UTXD. UBRC is read only, so only save/restore the other three
1602 * registers.
1603 */
1604 ubir = imx_uart_readl(sport, UBIR);
1605 ubmr = imx_uart_readl(sport, UBMR);
1606 uts = imx_uart_readl(sport, IMX21_UTS);
1607
1608 ucr2 = imx_uart_readl(sport, UCR2);
1609 ucr2 &= ~UCR2_SRST;
1610 imx_uart_writel(sport, ucr2, UCR2);
1611
1612 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1613 udelay(1);
1614
1615 /* Restore the registers */
1616 imx_uart_writel(sport, ubir, UBIR);
1617 imx_uart_writel(sport, ubmr, UBMR);
1618 imx_uart_writel(sport, uts, IMX21_UTS);
1619 }
1620
1621 static void
imx_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)1622 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1623 struct ktermios *old)
1624 {
1625 struct imx_port *sport = (struct imx_port *)port;
1626 unsigned long flags;
1627 u32 ucr2, old_ucr2, ufcr;
1628 unsigned int baud, quot;
1629 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1630 unsigned long div;
1631 unsigned long num, denom, old_ubir, old_ubmr;
1632 uint64_t tdiv64;
1633
1634 /*
1635 * We only support CS7 and CS8.
1636 */
1637 while ((termios->c_cflag & CSIZE) != CS7 &&
1638 (termios->c_cflag & CSIZE) != CS8) {
1639 termios->c_cflag &= ~CSIZE;
1640 termios->c_cflag |= old_csize;
1641 old_csize = CS8;
1642 }
1643
1644 del_timer_sync(&sport->timer);
1645
1646 /*
1647 * Ask the core to calculate the divisor for us.
1648 */
1649 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1650 quot = uart_get_divisor(port, baud);
1651
1652 spin_lock_irqsave(&sport->port.lock, flags);
1653
1654 /*
1655 * Read current UCR2 and save it for future use, then clear all the bits
1656 * except those we will or may need to preserve.
1657 */
1658 old_ucr2 = imx_uart_readl(sport, UCR2);
1659 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1660
1661 ucr2 |= UCR2_SRST | UCR2_IRTS;
1662 if ((termios->c_cflag & CSIZE) == CS8)
1663 ucr2 |= UCR2_WS;
1664
1665 if (!sport->have_rtscts)
1666 termios->c_cflag &= ~CRTSCTS;
1667
1668 if (port->rs485.flags & SER_RS485_ENABLED) {
1669 /*
1670 * RTS is mandatory for rs485 operation, so keep
1671 * it under manual control and keep transmitter
1672 * disabled.
1673 */
1674 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1675 imx_uart_rts_active(sport, &ucr2);
1676 else
1677 imx_uart_rts_inactive(sport, &ucr2);
1678
1679 } else if (termios->c_cflag & CRTSCTS) {
1680 /*
1681 * Only let receiver control RTS output if we were not requested
1682 * to have RTS inactive (which then should take precedence).
1683 */
1684 if (ucr2 & UCR2_CTS)
1685 ucr2 |= UCR2_CTSC;
1686 }
1687
1688 if (termios->c_cflag & CRTSCTS)
1689 ucr2 &= ~UCR2_IRTS;
1690 if (termios->c_cflag & CSTOPB)
1691 ucr2 |= UCR2_STPB;
1692 if (termios->c_cflag & PARENB) {
1693 ucr2 |= UCR2_PREN;
1694 if (termios->c_cflag & PARODD)
1695 ucr2 |= UCR2_PROE;
1696 }
1697
1698 sport->port.read_status_mask = 0;
1699 if (termios->c_iflag & INPCK)
1700 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1701 if (termios->c_iflag & (BRKINT | PARMRK))
1702 sport->port.read_status_mask |= URXD_BRK;
1703
1704 /*
1705 * Characters to ignore
1706 */
1707 sport->port.ignore_status_mask = 0;
1708 if (termios->c_iflag & IGNPAR)
1709 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1710 if (termios->c_iflag & IGNBRK) {
1711 sport->port.ignore_status_mask |= URXD_BRK;
1712 /*
1713 * If we're ignoring parity and break indicators,
1714 * ignore overruns too (for real raw support).
1715 */
1716 if (termios->c_iflag & IGNPAR)
1717 sport->port.ignore_status_mask |= URXD_OVRRUN;
1718 }
1719
1720 if ((termios->c_cflag & CREAD) == 0)
1721 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1722
1723 /*
1724 * Update the per-port timeout.
1725 */
1726 uart_update_timeout(port, termios->c_cflag, baud);
1727
1728 /* custom-baudrate handling */
1729 div = sport->port.uartclk / (baud * 16);
1730 if (baud == 38400 && quot != div)
1731 baud = sport->port.uartclk / (quot * 16);
1732
1733 div = sport->port.uartclk / (baud * 16);
1734 if (div > 7)
1735 div = 7;
1736 if (!div)
1737 div = 1;
1738
1739 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1740 1 << 16, 1 << 16, &num, &denom);
1741
1742 tdiv64 = sport->port.uartclk;
1743 tdiv64 *= num;
1744 do_div(tdiv64, denom * 16 * div);
1745 tty_termios_encode_baud_rate(termios,
1746 (speed_t)tdiv64, (speed_t)tdiv64);
1747
1748 num -= 1;
1749 denom -= 1;
1750
1751 ufcr = imx_uart_readl(sport, UFCR);
1752 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1753 imx_uart_writel(sport, ufcr, UFCR);
1754
1755 /*
1756 * Two registers below should always be written both and in this
1757 * particular order. One consequence is that we need to check if any of
1758 * them changes and then update both. We do need the check for change
1759 * as even writing the same values seem to "restart"
1760 * transmission/receiving logic in the hardware, that leads to data
1761 * breakage even when rate doesn't in fact change. E.g., user switches
1762 * RTS/CTS handshake and suddenly gets broken bytes.
1763 */
1764 old_ubir = imx_uart_readl(sport, UBIR);
1765 old_ubmr = imx_uart_readl(sport, UBMR);
1766 if (old_ubir != num || old_ubmr != denom) {
1767 imx_uart_writel(sport, num, UBIR);
1768 imx_uart_writel(sport, denom, UBMR);
1769 }
1770
1771 if (!imx_uart_is_imx1(sport))
1772 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1773 IMX21_ONEMS);
1774
1775 imx_uart_writel(sport, ucr2, UCR2);
1776
1777 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1778 imx_uart_enable_ms(&sport->port);
1779
1780 spin_unlock_irqrestore(&sport->port.lock, flags);
1781 }
1782
imx_uart_type(struct uart_port * port)1783 static const char *imx_uart_type(struct uart_port *port)
1784 {
1785 struct imx_port *sport = (struct imx_port *)port;
1786
1787 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1788 }
1789
1790 /*
1791 * Configure/autoconfigure the port.
1792 */
imx_uart_config_port(struct uart_port * port,int flags)1793 static void imx_uart_config_port(struct uart_port *port, int flags)
1794 {
1795 struct imx_port *sport = (struct imx_port *)port;
1796
1797 if (flags & UART_CONFIG_TYPE)
1798 sport->port.type = PORT_IMX;
1799 }
1800
1801 /*
1802 * Verify the new serial_struct (for TIOCSSERIAL).
1803 * The only change we allow are to the flags and type, and
1804 * even then only between PORT_IMX and PORT_UNKNOWN
1805 */
1806 static int
imx_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1807 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1808 {
1809 struct imx_port *sport = (struct imx_port *)port;
1810 int ret = 0;
1811
1812 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1813 ret = -EINVAL;
1814 if (sport->port.irq != ser->irq)
1815 ret = -EINVAL;
1816 if (ser->io_type != UPIO_MEM)
1817 ret = -EINVAL;
1818 if (sport->port.uartclk / 16 != ser->baud_base)
1819 ret = -EINVAL;
1820 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1821 ret = -EINVAL;
1822 if (sport->port.iobase != ser->port)
1823 ret = -EINVAL;
1824 if (ser->hub6 != 0)
1825 ret = -EINVAL;
1826 return ret;
1827 }
1828
1829 #if defined(CONFIG_CONSOLE_POLL)
1830
imx_uart_poll_init(struct uart_port * port)1831 static int imx_uart_poll_init(struct uart_port *port)
1832 {
1833 struct imx_port *sport = (struct imx_port *)port;
1834 unsigned long flags;
1835 u32 ucr1, ucr2;
1836 int retval;
1837
1838 retval = clk_prepare_enable(sport->clk_ipg);
1839 if (retval)
1840 return retval;
1841 retval = clk_prepare_enable(sport->clk_per);
1842 if (retval)
1843 clk_disable_unprepare(sport->clk_ipg);
1844
1845 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1846
1847 spin_lock_irqsave(&sport->port.lock, flags);
1848
1849 /*
1850 * Be careful about the order of enabling bits here. First enable the
1851 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1852 * This prevents that a character that already sits in the RX fifo is
1853 * triggering an irq but the try to fetch it from there results in an
1854 * exception because UARTEN or RXEN is still off.
1855 */
1856 ucr1 = imx_uart_readl(sport, UCR1);
1857 ucr2 = imx_uart_readl(sport, UCR2);
1858
1859 if (imx_uart_is_imx1(sport))
1860 ucr1 |= IMX1_UCR1_UARTCLKEN;
1861
1862 ucr1 |= UCR1_UARTEN;
1863 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1864
1865 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1866 ucr2 &= ~UCR2_ATEN;
1867
1868 imx_uart_writel(sport, ucr1, UCR1);
1869 imx_uart_writel(sport, ucr2, UCR2);
1870
1871 /* now enable irqs */
1872 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1873 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1874
1875 spin_unlock_irqrestore(&sport->port.lock, flags);
1876
1877 return 0;
1878 }
1879
imx_uart_poll_get_char(struct uart_port * port)1880 static int imx_uart_poll_get_char(struct uart_port *port)
1881 {
1882 struct imx_port *sport = (struct imx_port *)port;
1883 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1884 return NO_POLL_CHAR;
1885
1886 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1887 }
1888
imx_uart_poll_put_char(struct uart_port * port,unsigned char c)1889 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1890 {
1891 struct imx_port *sport = (struct imx_port *)port;
1892 unsigned int status;
1893
1894 /* drain */
1895 do {
1896 status = imx_uart_readl(sport, USR1);
1897 } while (~status & USR1_TRDY);
1898
1899 /* write */
1900 imx_uart_writel(sport, c, URTX0);
1901
1902 /* flush */
1903 do {
1904 status = imx_uart_readl(sport, USR2);
1905 } while (~status & USR2_TXDC);
1906 }
1907 #endif
1908
1909 /* called with port.lock taken and irqs off or from .probe without locking */
imx_uart_rs485_config(struct uart_port * port,struct serial_rs485 * rs485conf)1910 static int imx_uart_rs485_config(struct uart_port *port,
1911 struct serial_rs485 *rs485conf)
1912 {
1913 struct imx_port *sport = (struct imx_port *)port;
1914 u32 ucr2;
1915
1916 /* RTS is required to control the transmitter */
1917 if (!sport->have_rtscts && !sport->have_rtsgpio)
1918 rs485conf->flags &= ~SER_RS485_ENABLED;
1919
1920 if (rs485conf->flags & SER_RS485_ENABLED) {
1921 /* Enable receiver if low-active RTS signal is requested */
1922 if (sport->have_rtscts && !sport->have_rtsgpio &&
1923 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1924 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1925
1926 /* disable transmitter */
1927 ucr2 = imx_uart_readl(sport, UCR2);
1928 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1929 imx_uart_rts_active(sport, &ucr2);
1930 else
1931 imx_uart_rts_inactive(sport, &ucr2);
1932 imx_uart_writel(sport, ucr2, UCR2);
1933 }
1934
1935 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1936 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1937 rs485conf->flags & SER_RS485_RX_DURING_TX)
1938 imx_uart_start_rx(port);
1939
1940 return 0;
1941 }
1942
1943 static const struct uart_ops imx_uart_pops = {
1944 .tx_empty = imx_uart_tx_empty,
1945 .set_mctrl = imx_uart_set_mctrl,
1946 .get_mctrl = imx_uart_get_mctrl,
1947 .stop_tx = imx_uart_stop_tx,
1948 .start_tx = imx_uart_start_tx,
1949 .stop_rx = imx_uart_stop_rx,
1950 .enable_ms = imx_uart_enable_ms,
1951 .break_ctl = imx_uart_break_ctl,
1952 .startup = imx_uart_startup,
1953 .shutdown = imx_uart_shutdown,
1954 .flush_buffer = imx_uart_flush_buffer,
1955 .set_termios = imx_uart_set_termios,
1956 .type = imx_uart_type,
1957 .config_port = imx_uart_config_port,
1958 .verify_port = imx_uart_verify_port,
1959 #if defined(CONFIG_CONSOLE_POLL)
1960 .poll_init = imx_uart_poll_init,
1961 .poll_get_char = imx_uart_poll_get_char,
1962 .poll_put_char = imx_uart_poll_put_char,
1963 #endif
1964 };
1965
1966 static struct imx_port *imx_uart_ports[UART_NR];
1967
1968 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_console_putchar(struct uart_port * port,unsigned char ch)1969 static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
1970 {
1971 struct imx_port *sport = (struct imx_port *)port;
1972
1973 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1974 barrier();
1975
1976 imx_uart_writel(sport, ch, URTX0);
1977 }
1978
1979 /*
1980 * Interrupts are disabled on entering
1981 */
1982 static void
imx_uart_console_write(struct console * co,const char * s,unsigned int count)1983 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1984 {
1985 struct imx_port *sport = imx_uart_ports[co->index];
1986 struct imx_port_ucrs old_ucr;
1987 unsigned long flags;
1988 unsigned int ucr1;
1989 int locked = 1;
1990
1991 if (sport->port.sysrq)
1992 locked = 0;
1993 else if (oops_in_progress)
1994 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1995 else
1996 spin_lock_irqsave(&sport->port.lock, flags);
1997
1998 /*
1999 * First, save UCR1/2/3 and then disable interrupts
2000 */
2001 imx_uart_ucrs_save(sport, &old_ucr);
2002 ucr1 = old_ucr.ucr1;
2003
2004 if (imx_uart_is_imx1(sport))
2005 ucr1 |= IMX1_UCR1_UARTCLKEN;
2006 ucr1 |= UCR1_UARTEN;
2007 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2008
2009 imx_uart_writel(sport, ucr1, UCR1);
2010
2011 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2012
2013 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2014
2015 /*
2016 * Finally, wait for transmitter to become empty
2017 * and restore UCR1/2/3
2018 */
2019 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2020
2021 imx_uart_ucrs_restore(sport, &old_ucr);
2022
2023 if (locked)
2024 spin_unlock_irqrestore(&sport->port.lock, flags);
2025 }
2026
2027 /*
2028 * If the port was already initialised (eg, by a boot loader),
2029 * try to determine the current setup.
2030 */
2031 static void
imx_uart_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)2032 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2033 int *parity, int *bits)
2034 {
2035
2036 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2037 /* ok, the port was enabled */
2038 unsigned int ucr2, ubir, ubmr, uartclk;
2039 unsigned int baud_raw;
2040 unsigned int ucfr_rfdiv;
2041
2042 ucr2 = imx_uart_readl(sport, UCR2);
2043
2044 *parity = 'n';
2045 if (ucr2 & UCR2_PREN) {
2046 if (ucr2 & UCR2_PROE)
2047 *parity = 'o';
2048 else
2049 *parity = 'e';
2050 }
2051
2052 if (ucr2 & UCR2_WS)
2053 *bits = 8;
2054 else
2055 *bits = 7;
2056
2057 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2058 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2059
2060 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2061 if (ucfr_rfdiv == 6)
2062 ucfr_rfdiv = 7;
2063 else
2064 ucfr_rfdiv = 6 - ucfr_rfdiv;
2065
2066 uartclk = clk_get_rate(sport->clk_per);
2067 uartclk /= ucfr_rfdiv;
2068
2069 { /*
2070 * The next code provides exact computation of
2071 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2072 * without need of float support or long long division,
2073 * which would be required to prevent 32bit arithmetic overflow
2074 */
2075 unsigned int mul = ubir + 1;
2076 unsigned int div = 16 * (ubmr + 1);
2077 unsigned int rem = uartclk % div;
2078
2079 baud_raw = (uartclk / div) * mul;
2080 baud_raw += (rem * mul + div / 2) / div;
2081 *baud = (baud_raw + 50) / 100 * 100;
2082 }
2083
2084 if (*baud != baud_raw)
2085 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2086 baud_raw, *baud);
2087 }
2088 }
2089
2090 static int
imx_uart_console_setup(struct console * co,char * options)2091 imx_uart_console_setup(struct console *co, char *options)
2092 {
2093 struct imx_port *sport;
2094 int baud = 9600;
2095 int bits = 8;
2096 int parity = 'n';
2097 int flow = 'n';
2098 int retval;
2099
2100 /*
2101 * Check whether an invalid uart number has been specified, and
2102 * if so, search for the first available port that does have
2103 * console support.
2104 */
2105 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2106 co->index = 0;
2107 sport = imx_uart_ports[co->index];
2108 if (sport == NULL)
2109 return -ENODEV;
2110
2111 /* For setting the registers, we only need to enable the ipg clock. */
2112 retval = clk_prepare_enable(sport->clk_ipg);
2113 if (retval)
2114 goto error_console;
2115
2116 if (options)
2117 uart_parse_options(options, &baud, &parity, &bits, &flow);
2118 else
2119 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2120
2121 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2122
2123 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2124
2125 if (retval) {
2126 clk_disable_unprepare(sport->clk_ipg);
2127 goto error_console;
2128 }
2129
2130 retval = clk_prepare_enable(sport->clk_per);
2131 if (retval)
2132 clk_disable_unprepare(sport->clk_ipg);
2133
2134 error_console:
2135 return retval;
2136 }
2137
2138 static int
imx_uart_console_exit(struct console * co)2139 imx_uart_console_exit(struct console *co)
2140 {
2141 struct imx_port *sport = imx_uart_ports[co->index];
2142
2143 clk_disable_unprepare(sport->clk_per);
2144 clk_disable_unprepare(sport->clk_ipg);
2145
2146 return 0;
2147 }
2148
2149 static struct uart_driver imx_uart_uart_driver;
2150 static struct console imx_uart_console = {
2151 .name = DEV_NAME,
2152 .write = imx_uart_console_write,
2153 .device = uart_console_device,
2154 .setup = imx_uart_console_setup,
2155 .exit = imx_uart_console_exit,
2156 .flags = CON_PRINTBUFFER,
2157 .index = -1,
2158 .data = &imx_uart_uart_driver,
2159 };
2160
2161 #define IMX_CONSOLE &imx_uart_console
2162
2163 #else
2164 #define IMX_CONSOLE NULL
2165 #endif
2166
2167 static struct uart_driver imx_uart_uart_driver = {
2168 .owner = THIS_MODULE,
2169 .driver_name = DRIVER_NAME,
2170 .dev_name = DEV_NAME,
2171 .major = SERIAL_IMX_MAJOR,
2172 .minor = MINOR_START,
2173 .nr = ARRAY_SIZE(imx_uart_ports),
2174 .cons = IMX_CONSOLE,
2175 };
2176
imx_trigger_start_tx(struct hrtimer * t)2177 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2178 {
2179 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2180 unsigned long flags;
2181
2182 spin_lock_irqsave(&sport->port.lock, flags);
2183 if (sport->tx_state == WAIT_AFTER_RTS)
2184 imx_uart_start_tx(&sport->port);
2185 spin_unlock_irqrestore(&sport->port.lock, flags);
2186
2187 return HRTIMER_NORESTART;
2188 }
2189
imx_trigger_stop_tx(struct hrtimer * t)2190 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2191 {
2192 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2193 unsigned long flags;
2194
2195 spin_lock_irqsave(&sport->port.lock, flags);
2196 if (sport->tx_state == WAIT_AFTER_SEND)
2197 imx_uart_stop_tx(&sport->port);
2198 spin_unlock_irqrestore(&sport->port.lock, flags);
2199
2200 return HRTIMER_NORESTART;
2201 }
2202
2203 /* Default RX DMA buffer configuration */
2204 #define RX_DMA_PERIODS 16
2205 #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2206
imx_uart_probe(struct platform_device * pdev)2207 static int imx_uart_probe(struct platform_device *pdev)
2208 {
2209 struct device_node *np = pdev->dev.of_node;
2210 struct imx_port *sport;
2211 void __iomem *base;
2212 u32 dma_buf_conf[2];
2213 int ret = 0;
2214 u32 ucr1;
2215 struct resource *res;
2216 int txirq, rxirq, rtsirq;
2217
2218 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2219 if (!sport)
2220 return -ENOMEM;
2221
2222 sport->devdata = of_device_get_match_data(&pdev->dev);
2223
2224 ret = of_alias_get_id(np, "serial");
2225 if (ret < 0) {
2226 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2227 return ret;
2228 }
2229 sport->port.line = ret;
2230
2231 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2232 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2233 sport->have_rtscts = 1;
2234
2235 if (of_get_property(np, "fsl,dte-mode", NULL))
2236 sport->dte_mode = 1;
2237
2238 if (of_get_property(np, "rts-gpios", NULL))
2239 sport->have_rtsgpio = 1;
2240
2241 if (of_get_property(np, "fsl,inverted-tx", NULL))
2242 sport->inverted_tx = 1;
2243
2244 if (of_get_property(np, "fsl,inverted-rx", NULL))
2245 sport->inverted_rx = 1;
2246
2247 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2248 sport->rx_period_length = dma_buf_conf[0];
2249 sport->rx_periods = dma_buf_conf[1];
2250 } else {
2251 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2252 sport->rx_periods = RX_DMA_PERIODS;
2253 }
2254
2255 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2256 dev_err(&pdev->dev, "serial%d out of range\n",
2257 sport->port.line);
2258 return -EINVAL;
2259 }
2260
2261 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2262 base = devm_ioremap_resource(&pdev->dev, res);
2263 if (IS_ERR(base))
2264 return PTR_ERR(base);
2265
2266 rxirq = platform_get_irq(pdev, 0);
2267 if (rxirq < 0)
2268 return rxirq;
2269 txirq = platform_get_irq_optional(pdev, 1);
2270 rtsirq = platform_get_irq_optional(pdev, 2);
2271
2272 sport->port.dev = &pdev->dev;
2273 sport->port.mapbase = res->start;
2274 sport->port.membase = base;
2275 sport->port.type = PORT_IMX;
2276 sport->port.iotype = UPIO_MEM;
2277 sport->port.irq = rxirq;
2278 sport->port.fifosize = 32;
2279 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2280 sport->port.ops = &imx_uart_pops;
2281 sport->port.rs485_config = imx_uart_rs485_config;
2282 sport->port.flags = UPF_BOOT_AUTOCONF;
2283 timer_setup(&sport->timer, imx_uart_timeout, 0);
2284
2285 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2286 if (IS_ERR(sport->gpios))
2287 return PTR_ERR(sport->gpios);
2288
2289 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2290 if (IS_ERR(sport->clk_ipg)) {
2291 ret = PTR_ERR(sport->clk_ipg);
2292 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2293 return ret;
2294 }
2295
2296 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2297 if (IS_ERR(sport->clk_per)) {
2298 ret = PTR_ERR(sport->clk_per);
2299 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2300 return ret;
2301 }
2302
2303 sport->port.uartclk = clk_get_rate(sport->clk_per);
2304
2305 /* For register access, we only need to enable the ipg clock. */
2306 ret = clk_prepare_enable(sport->clk_ipg);
2307 if (ret) {
2308 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2309 return ret;
2310 }
2311
2312 /* initialize shadow register values */
2313 sport->ucr1 = readl(sport->port.membase + UCR1);
2314 sport->ucr2 = readl(sport->port.membase + UCR2);
2315 sport->ucr3 = readl(sport->port.membase + UCR3);
2316 sport->ucr4 = readl(sport->port.membase + UCR4);
2317 sport->ufcr = readl(sport->port.membase + UFCR);
2318
2319 ret = uart_get_rs485_mode(&sport->port);
2320 if (ret) {
2321 clk_disable_unprepare(sport->clk_ipg);
2322 return ret;
2323 }
2324
2325 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2326 (!sport->have_rtscts && !sport->have_rtsgpio))
2327 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2328
2329 /*
2330 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2331 * signal cannot be set low during transmission in case the
2332 * receiver is off (limitation of the i.MX UART IP).
2333 */
2334 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2335 sport->have_rtscts && !sport->have_rtsgpio &&
2336 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2337 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2338 dev_err(&pdev->dev,
2339 "low-active RTS not possible when receiver is off, enabling receiver\n");
2340
2341 imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2342
2343 /* Disable interrupts before requesting them */
2344 ucr1 = imx_uart_readl(sport, UCR1);
2345 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2346 imx_uart_writel(sport, ucr1, UCR1);
2347
2348 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2349 /*
2350 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2351 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2352 * and DCD (when they are outputs) or enables the respective
2353 * irqs. So set this bit early, i.e. before requesting irqs.
2354 */
2355 u32 ufcr = imx_uart_readl(sport, UFCR);
2356 if (!(ufcr & UFCR_DCEDTE))
2357 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2358
2359 /*
2360 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2361 * enabled later because they cannot be cleared
2362 * (confirmed on i.MX25) which makes them unusable.
2363 */
2364 imx_uart_writel(sport,
2365 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2366 UCR3);
2367
2368 } else {
2369 u32 ucr3 = UCR3_DSR;
2370 u32 ufcr = imx_uart_readl(sport, UFCR);
2371 if (ufcr & UFCR_DCEDTE)
2372 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2373
2374 if (!imx_uart_is_imx1(sport))
2375 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2376 imx_uart_writel(sport, ucr3, UCR3);
2377 }
2378
2379 clk_disable_unprepare(sport->clk_ipg);
2380
2381 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2382 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2383 sport->trigger_start_tx.function = imx_trigger_start_tx;
2384 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2385
2386 /*
2387 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2388 * chips only have one interrupt.
2389 */
2390 if (txirq > 0) {
2391 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2392 dev_name(&pdev->dev), sport);
2393 if (ret) {
2394 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2395 ret);
2396 return ret;
2397 }
2398
2399 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2400 dev_name(&pdev->dev), sport);
2401 if (ret) {
2402 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2403 ret);
2404 return ret;
2405 }
2406
2407 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2408 dev_name(&pdev->dev), sport);
2409 if (ret) {
2410 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2411 ret);
2412 return ret;
2413 }
2414 } else {
2415 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2416 dev_name(&pdev->dev), sport);
2417 if (ret) {
2418 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2419 return ret;
2420 }
2421 }
2422
2423 imx_uart_ports[sport->port.line] = sport;
2424
2425 platform_set_drvdata(pdev, sport);
2426
2427 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2428 }
2429
imx_uart_remove(struct platform_device * pdev)2430 static int imx_uart_remove(struct platform_device *pdev)
2431 {
2432 struct imx_port *sport = platform_get_drvdata(pdev);
2433
2434 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2435 }
2436
imx_uart_restore_context(struct imx_port * sport)2437 static void imx_uart_restore_context(struct imx_port *sport)
2438 {
2439 unsigned long flags;
2440
2441 spin_lock_irqsave(&sport->port.lock, flags);
2442 if (!sport->context_saved) {
2443 spin_unlock_irqrestore(&sport->port.lock, flags);
2444 return;
2445 }
2446
2447 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2448 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2449 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2450 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2451 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2452 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2453 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2454 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2455 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2456 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2457 sport->context_saved = false;
2458 spin_unlock_irqrestore(&sport->port.lock, flags);
2459 }
2460
imx_uart_save_context(struct imx_port * sport)2461 static void imx_uart_save_context(struct imx_port *sport)
2462 {
2463 unsigned long flags;
2464
2465 /* Save necessary regs */
2466 spin_lock_irqsave(&sport->port.lock, flags);
2467 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2468 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2469 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2470 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2471 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2472 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2473 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2474 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2475 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2476 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2477 sport->context_saved = true;
2478 spin_unlock_irqrestore(&sport->port.lock, flags);
2479 }
2480
imx_uart_enable_wakeup(struct imx_port * sport,bool on)2481 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2482 {
2483 u32 ucr3;
2484
2485 ucr3 = imx_uart_readl(sport, UCR3);
2486 if (on) {
2487 imx_uart_writel(sport, USR1_AWAKE, USR1);
2488 ucr3 |= UCR3_AWAKEN;
2489 } else {
2490 ucr3 &= ~UCR3_AWAKEN;
2491 }
2492 imx_uart_writel(sport, ucr3, UCR3);
2493
2494 if (sport->have_rtscts) {
2495 u32 ucr1 = imx_uart_readl(sport, UCR1);
2496 if (on) {
2497 imx_uart_writel(sport, USR1_RTSD, USR1);
2498 ucr1 |= UCR1_RTSDEN;
2499 } else {
2500 ucr1 &= ~UCR1_RTSDEN;
2501 }
2502 imx_uart_writel(sport, ucr1, UCR1);
2503 }
2504 }
2505
imx_uart_suspend_noirq(struct device * dev)2506 static int imx_uart_suspend_noirq(struct device *dev)
2507 {
2508 struct imx_port *sport = dev_get_drvdata(dev);
2509
2510 imx_uart_save_context(sport);
2511
2512 clk_disable(sport->clk_ipg);
2513
2514 pinctrl_pm_select_sleep_state(dev);
2515
2516 return 0;
2517 }
2518
imx_uart_resume_noirq(struct device * dev)2519 static int imx_uart_resume_noirq(struct device *dev)
2520 {
2521 struct imx_port *sport = dev_get_drvdata(dev);
2522 int ret;
2523
2524 pinctrl_pm_select_default_state(dev);
2525
2526 ret = clk_enable(sport->clk_ipg);
2527 if (ret)
2528 return ret;
2529
2530 imx_uart_restore_context(sport);
2531
2532 return 0;
2533 }
2534
imx_uart_suspend(struct device * dev)2535 static int imx_uart_suspend(struct device *dev)
2536 {
2537 struct imx_port *sport = dev_get_drvdata(dev);
2538 int ret;
2539
2540 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2541 disable_irq(sport->port.irq);
2542
2543 ret = clk_prepare_enable(sport->clk_ipg);
2544 if (ret)
2545 return ret;
2546
2547 /* enable wakeup from i.MX UART */
2548 imx_uart_enable_wakeup(sport, true);
2549
2550 return 0;
2551 }
2552
imx_uart_resume(struct device * dev)2553 static int imx_uart_resume(struct device *dev)
2554 {
2555 struct imx_port *sport = dev_get_drvdata(dev);
2556
2557 /* disable wakeup from i.MX UART */
2558 imx_uart_enable_wakeup(sport, false);
2559
2560 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2561 enable_irq(sport->port.irq);
2562
2563 clk_disable_unprepare(sport->clk_ipg);
2564
2565 return 0;
2566 }
2567
imx_uart_freeze(struct device * dev)2568 static int imx_uart_freeze(struct device *dev)
2569 {
2570 struct imx_port *sport = dev_get_drvdata(dev);
2571
2572 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2573
2574 return clk_prepare_enable(sport->clk_ipg);
2575 }
2576
imx_uart_thaw(struct device * dev)2577 static int imx_uart_thaw(struct device *dev)
2578 {
2579 struct imx_port *sport = dev_get_drvdata(dev);
2580
2581 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2582
2583 clk_disable_unprepare(sport->clk_ipg);
2584
2585 return 0;
2586 }
2587
2588 static const struct dev_pm_ops imx_uart_pm_ops = {
2589 .suspend_noirq = imx_uart_suspend_noirq,
2590 .resume_noirq = imx_uart_resume_noirq,
2591 .freeze_noirq = imx_uart_suspend_noirq,
2592 .restore_noirq = imx_uart_resume_noirq,
2593 .suspend = imx_uart_suspend,
2594 .resume = imx_uart_resume,
2595 .freeze = imx_uart_freeze,
2596 .thaw = imx_uart_thaw,
2597 .restore = imx_uart_thaw,
2598 };
2599
2600 static struct platform_driver imx_uart_platform_driver = {
2601 .probe = imx_uart_probe,
2602 .remove = imx_uart_remove,
2603
2604 .driver = {
2605 .name = "imx-uart",
2606 .of_match_table = imx_uart_dt_ids,
2607 .pm = &imx_uart_pm_ops,
2608 },
2609 };
2610
imx_uart_init(void)2611 static int __init imx_uart_init(void)
2612 {
2613 int ret = uart_register_driver(&imx_uart_uart_driver);
2614
2615 if (ret)
2616 return ret;
2617
2618 ret = platform_driver_register(&imx_uart_platform_driver);
2619 if (ret != 0)
2620 uart_unregister_driver(&imx_uart_uart_driver);
2621
2622 return ret;
2623 }
2624
imx_uart_exit(void)2625 static void __exit imx_uart_exit(void)
2626 {
2627 platform_driver_unregister(&imx_uart_platform_driver);
2628 uart_unregister_driver(&imx_uart_uart_driver);
2629 }
2630
2631 module_init(imx_uart_init);
2632 module_exit(imx_uart_exit);
2633
2634 MODULE_AUTHOR("Sascha Hauer");
2635 MODULE_DESCRIPTION("IMX generic serial port driver");
2636 MODULE_LICENSE("GPL");
2637 MODULE_ALIAS("platform:imx-uart");
2638