1 /* bnx2x_reg.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * The registers description starts with the register Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
11 * R - Read only
12 * RC - Clear on read
13 * RW - Read/Write
14 * ST - Statistics register (clear on read)
15 * W - Write only
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
19 *
20 */
21 #ifndef BNX2X_REG_H
22 #define BNX2X_REG_H
23
24 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
25 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
26 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
27 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
28 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
29 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
30 /* [RW 1] Initiate the ATC array - reset all the valid bits */
31 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
32 /* [R 1] ATC initalization done */
33 #define ATC_REG_ATC_INIT_DONE 0x1100bc
34 /* [RC 6] Interrupt register #0 read clear */
35 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
36 /* [RW 19] Interrupt mask register #0 read/write */
37 #define BRB1_REG_BRB1_INT_MASK 0x60128
38 /* [R 19] Interrupt register #0 read */
39 #define BRB1_REG_BRB1_INT_STS 0x6011c
40 /* [RW 4] Parity mask register #0 read/write */
41 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
42 /* [R 4] Parity register #0 read */
43 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
44 /* [RC 4] Parity register #0 read clear */
45 #define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
46 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
47 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
48 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
49 * following reset the first rbc access to this reg must be write; there can
50 * be no more rbc writes after the first one; there can be any number of rbc
51 * read following the first write; rbc access not following these rules will
52 * result in hang condition. */
53 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
54 /* [RW 10] The number of free blocks below which the full signal to class 0
55 * is asserted */
56 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
57 /* [RW 10] The number of free blocks above which the full signal to class 0
58 * is de-asserted */
59 #define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
60 /* [RW 10] The number of free blocks below which the full signal to class 1
61 * is asserted */
62 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
63 /* [RW 10] The number of free blocks above which the full signal to class 1
64 * is de-asserted */
65 #define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
66 /* [RW 10] The number of free blocks below which the full signal to the LB
67 * port is asserted */
68 #define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
69 /* [RW 10] The number of free blocks above which the full signal to the LB
70 * port is de-asserted */
71 #define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4
72 /* [RW 10] The number of free blocks above which the High_llfc signal to
73 interface #n is de-asserted. */
74 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
75 /* [RW 10] The number of free blocks below which the High_llfc signal to
76 interface #n is asserted. */
77 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
78 /* [RW 23] LL RAM data. */
79 #define BRB1_REG_LL_RAM 0x61000
80 /* [RW 10] The number of free blocks above which the Low_llfc signal to
81 interface #n is de-asserted. */
82 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
83 /* [RW 10] The number of free blocks below which the Low_llfc signal to
84 interface #n is asserted. */
85 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
86 /* [RW 10] The number of blocks guarantied for the MAC port */
87 #define BRB1_REG_MAC_GUARANTIED_0 0x601e8
88 #define BRB1_REG_MAC_GUARANTIED_1 0x60240
89 /* [R 24] The number of full blocks. */
90 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
91 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
92 was asserted. */
93 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
94 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
95 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
96 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
97 asserted. */
98 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
99 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
100 /* [RW 10] The number of free blocks below which the pause signal to class 0
101 * is asserted */
102 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
103 /* [RW 10] The number of free blocks above which the pause signal to class 0
104 * is de-asserted */
105 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
106 /* [RW 10] The number of free blocks below which the pause signal to class 1
107 * is asserted */
108 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
109 /* [RW 10] The number of free blocks above which the pause signal to class 1
110 * is de-asserted */
111 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
112 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
113 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
114 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
115 /* [RW 10] Write client 0: Assert pause threshold. */
116 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
117 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
118 /* [R 24] The number of full blocks occupied by port. */
119 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
120 /* [RW 1] Reset the design by software. */
121 #define BRB1_REG_SOFT_RESET 0x600dc
122 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
123 #define CCM_REG_CAM_OCCUP 0xd0188
124 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
125 acknowledge output is deasserted; all other signals are treated as usual;
126 if 1 - normal activity. */
127 #define CCM_REG_CCM_CFC_IFEN 0xd003c
128 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
129 disregarded; valid is deasserted; all other signals are treated as usual;
130 if 1 - normal activity. */
131 #define CCM_REG_CCM_CQM_IFEN 0xd000c
132 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
133 Otherwise 0 is inserted. */
134 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
135 /* [RW 11] Interrupt mask register #0 read/write */
136 #define CCM_REG_CCM_INT_MASK 0xd01e4
137 /* [R 11] Interrupt register #0 read */
138 #define CCM_REG_CCM_INT_STS 0xd01d8
139 /* [RW 27] Parity mask register #0 read/write */
140 #define CCM_REG_CCM_PRTY_MASK 0xd01f4
141 /* [R 27] Parity register #0 read */
142 #define CCM_REG_CCM_PRTY_STS 0xd01e8
143 /* [RC 27] Parity register #0 read clear */
144 #define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
145 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
146 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
147 Is used to determine the number of the AG context REG-pairs written back;
148 when the input message Reg1WbFlg isn't set. */
149 #define CCM_REG_CCM_REG0_SZ 0xd00c4
150 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
151 disregarded; valid is deasserted; all other signals are treated as usual;
152 if 1 - normal activity. */
153 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
154 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
155 disregarded; valid is deasserted; all other signals are treated as usual;
156 if 1 - normal activity. */
157 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
158 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
159 disregarded; valid output is deasserted; all other signals are treated as
160 usual; if 1 - normal activity. */
161 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
162 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
163 are disregarded; all other signals are treated as usual; if 1 - normal
164 activity. */
165 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
166 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
167 disregarded; valid output is deasserted; all other signals are treated as
168 usual; if 1 - normal activity. */
169 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
170 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
171 input is disregarded; all other signals are treated as usual; if 1 -
172 normal activity. */
173 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
174 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
175 the initial credit value; read returns the current value of the credit
176 counter. Must be initialized to 1 at start-up. */
177 #define CCM_REG_CFC_INIT_CRD 0xd0204
178 /* [RW 2] Auxiliary counter flag Q number 1. */
179 #define CCM_REG_CNT_AUX1_Q 0xd00c8
180 /* [RW 2] Auxiliary counter flag Q number 2. */
181 #define CCM_REG_CNT_AUX2_Q 0xd00cc
182 /* [RW 28] The CM header value for QM request (primary). */
183 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
184 /* [RW 28] The CM header value for QM request (secondary). */
185 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
186 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
187 acknowledge output is deasserted; all other signals are treated as usual;
188 if 1 - normal activity. */
189 #define CCM_REG_CQM_CCM_IFEN 0xd0014
190 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
191 the initial credit value; read returns the current value of the credit
192 counter. Must be initialized to 32 at start-up. */
193 #define CCM_REG_CQM_INIT_CRD 0xd020c
194 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
195 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
196 prioritised); 2 stands for weight 2; tc. */
197 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
198 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
199 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
200 prioritised); 2 stands for weight 2; tc. */
201 #define CCM_REG_CQM_S_WEIGHT 0xd00bc
202 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
203 acknowledge output is deasserted; all other signals are treated as usual;
204 if 1 - normal activity. */
205 #define CCM_REG_CSDM_IFEN 0xd0018
206 /* [RC 1] Set when the message length mismatch (relative to last indication)
207 at the SDM interface is detected. */
208 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
209 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
210 weight 8 (the most prioritised); 1 stands for weight 1(least
211 prioritised); 2 stands for weight 2; tc. */
212 #define CCM_REG_CSDM_WEIGHT 0xd00b4
213 /* [RW 28] The CM header for QM formatting in case of an error in the QM
214 inputs. */
215 #define CCM_REG_ERR_CCM_HDR 0xd0094
216 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
217 #define CCM_REG_ERR_EVNT_ID 0xd0098
218 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
219 writes the initial credit value; read returns the current value of the
220 credit counter. Must be initialized to 64 at start-up. */
221 #define CCM_REG_FIC0_INIT_CRD 0xd0210
222 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
223 writes the initial credit value; read returns the current value of the
224 credit counter. Must be initialized to 64 at start-up. */
225 #define CCM_REG_FIC1_INIT_CRD 0xd0214
226 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
227 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
228 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
229 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
230 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
231 #define CCM_REG_GR_ARB_TYPE 0xd015c
232 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
233 highest priority is 3. It is supposed; that the Store channel priority is
234 the compliment to 4 of the rest priorities - Aggregation channel; Load
235 (FIC0) channel and Load (FIC1). */
236 #define CCM_REG_GR_LD0_PR 0xd0164
237 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
238 highest priority is 3. It is supposed; that the Store channel priority is
239 the compliment to 4 of the rest priorities - Aggregation channel; Load
240 (FIC0) channel and Load (FIC1). */
241 #define CCM_REG_GR_LD1_PR 0xd0168
242 /* [RW 2] General flags index. */
243 #define CCM_REG_INV_DONE_Q 0xd0108
244 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
245 context and sent to STORM; for a specific connection type. The double
246 REG-pairs are used in order to align to STORM context row size of 128
247 bits. The offset of these data in the STORM context is always 0. Index
248 _(0..15) stands for the connection type (one of 16). */
249 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
250 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
251 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
252 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
253 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
254 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
255 acknowledge output is deasserted; all other signals are treated as usual;
256 if 1 - normal activity. */
257 #define CCM_REG_PBF_IFEN 0xd0028
258 /* [RC 1] Set when the message length mismatch (relative to last indication)
259 at the pbf interface is detected. */
260 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
261 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
262 weight 8 (the most prioritised); 1 stands for weight 1(least
263 prioritised); 2 stands for weight 2; tc. */
264 #define CCM_REG_PBF_WEIGHT 0xd00ac
265 #define CCM_REG_PHYS_QNUM1_0 0xd0134
266 #define CCM_REG_PHYS_QNUM1_1 0xd0138
267 #define CCM_REG_PHYS_QNUM2_0 0xd013c
268 #define CCM_REG_PHYS_QNUM2_1 0xd0140
269 #define CCM_REG_PHYS_QNUM3_0 0xd0144
270 #define CCM_REG_PHYS_QNUM3_1 0xd0148
271 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
272 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
273 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
274 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
275 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
276 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
277 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
278 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
279 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
280 disregarded; acknowledge output is deasserted; all other signals are
281 treated as usual; if 1 - normal activity. */
282 #define CCM_REG_STORM_CCM_IFEN 0xd0010
283 /* [RC 1] Set when the message length mismatch (relative to last indication)
284 at the STORM interface is detected. */
285 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
286 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
287 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
288 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
289 tc. */
290 #define CCM_REG_STORM_WEIGHT 0xd009c
291 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
292 disregarded; acknowledge output is deasserted; all other signals are
293 treated as usual; if 1 - normal activity. */
294 #define CCM_REG_TSEM_IFEN 0xd001c
295 /* [RC 1] Set when the message length mismatch (relative to last indication)
296 at the tsem interface is detected. */
297 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
298 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
299 weight 8 (the most prioritised); 1 stands for weight 1(least
300 prioritised); 2 stands for weight 2; tc. */
301 #define CCM_REG_TSEM_WEIGHT 0xd00a0
302 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
303 disregarded; acknowledge output is deasserted; all other signals are
304 treated as usual; if 1 - normal activity. */
305 #define CCM_REG_USEM_IFEN 0xd0024
306 /* [RC 1] Set when message length mismatch (relative to last indication) at
307 the usem interface is detected. */
308 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
309 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
310 weight 8 (the most prioritised); 1 stands for weight 1(least
311 prioritised); 2 stands for weight 2; tc. */
312 #define CCM_REG_USEM_WEIGHT 0xd00a8
313 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
314 disregarded; acknowledge output is deasserted; all other signals are
315 treated as usual; if 1 - normal activity. */
316 #define CCM_REG_XSEM_IFEN 0xd0020
317 /* [RC 1] Set when the message length mismatch (relative to last indication)
318 at the xsem interface is detected. */
319 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
320 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
321 weight 8 (the most prioritised); 1 stands for weight 1(least
322 prioritised); 2 stands for weight 2; tc. */
323 #define CCM_REG_XSEM_WEIGHT 0xd00a4
324 /* [RW 19] Indirect access to the descriptor table of the XX protection
325 mechanism. The fields are: [5:0] - message length; [12:6] - message
326 pointer; 18:13] - next pointer. */
327 #define CCM_REG_XX_DESCR_TABLE 0xd0300
328 #define CCM_REG_XX_DESCR_TABLE_SIZE 36
329 /* [R 7] Used to read the value of XX protection Free counter. */
330 #define CCM_REG_XX_FREE 0xd0184
331 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
332 of the Input Stage XX protection buffer by the XX protection pending
333 messages. Max credit available - 127. Write writes the initial credit
334 value; read returns the current value of the credit counter. Must be
335 initialized to maximum XX protected message size - 2 at start-up. */
336 #define CCM_REG_XX_INIT_CRD 0xd0220
337 /* [RW 7] The maximum number of pending messages; which may be stored in XX
338 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
339 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
340 counter. */
341 #define CCM_REG_XX_MSG_NUM 0xd0224
342 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
343 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
344 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
345 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
346 header pointer. */
347 #define CCM_REG_XX_TABLE 0xd0280
348 #define CDU_REG_CDU_CHK_MASK0 0x101000
349 #define CDU_REG_CDU_CHK_MASK1 0x101004
350 #define CDU_REG_CDU_CONTROL0 0x101008
351 #define CDU_REG_CDU_DEBUG 0x101010
352 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
353 /* [RW 7] Interrupt mask register #0 read/write */
354 #define CDU_REG_CDU_INT_MASK 0x10103c
355 /* [R 7] Interrupt register #0 read */
356 #define CDU_REG_CDU_INT_STS 0x101030
357 /* [RW 5] Parity mask register #0 read/write */
358 #define CDU_REG_CDU_PRTY_MASK 0x10104c
359 /* [R 5] Parity register #0 read */
360 #define CDU_REG_CDU_PRTY_STS 0x101040
361 /* [RC 5] Parity register #0 read clear */
362 #define CDU_REG_CDU_PRTY_STS_CLR 0x101044
363 /* [RC 32] logging of error data in case of a CDU load error:
364 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
365 ype_error; ctual_active; ctual_compressed_context}; */
366 #define CDU_REG_ERROR_DATA 0x101014
367 /* [WB 216] L1TT ram access. each entry has the following format :
368 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
369 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
370 #define CDU_REG_L1TT 0x101800
371 /* [WB 24] MATT ram access. each entry has the following
372 format:{RegionLength[11:0]; egionOffset[11:0]} */
373 #define CDU_REG_MATT 0x101100
374 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */
375 #define CDU_REG_MF_MODE 0x101050
376 /* [R 1] indication the initializing the activity counter by the hardware
377 was done. */
378 #define CFC_REG_AC_INIT_DONE 0x104078
379 /* [RW 13] activity counter ram access */
380 #define CFC_REG_ACTIVITY_COUNTER 0x104400
381 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
382 /* [R 1] indication the initializing the cams by the hardware was done. */
383 #define CFC_REG_CAM_INIT_DONE 0x10407c
384 /* [RW 2] Interrupt mask register #0 read/write */
385 #define CFC_REG_CFC_INT_MASK 0x104108
386 /* [R 2] Interrupt register #0 read */
387 #define CFC_REG_CFC_INT_STS 0x1040fc
388 /* [RC 2] Interrupt register #0 read clear */
389 #define CFC_REG_CFC_INT_STS_CLR 0x104100
390 /* [RW 4] Parity mask register #0 read/write */
391 #define CFC_REG_CFC_PRTY_MASK 0x104118
392 /* [R 4] Parity register #0 read */
393 #define CFC_REG_CFC_PRTY_STS 0x10410c
394 /* [RC 4] Parity register #0 read clear */
395 #define CFC_REG_CFC_PRTY_STS_CLR 0x104110
396 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
397 #define CFC_REG_CID_CAM 0x104800
398 #define CFC_REG_CONTROL0 0x104028
399 #define CFC_REG_DEBUG0 0x104050
400 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
401 vector) whether the cfc should be disabled upon it */
402 #define CFC_REG_DISABLE_ON_ERROR 0x104044
403 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
404 set one of these bits. the bit description can be found in CFC
405 specifications */
406 #define CFC_REG_ERROR_VECTOR 0x10403c
407 /* [WB 93] LCID info ram access */
408 #define CFC_REG_INFO_RAM 0x105000
409 #define CFC_REG_INFO_RAM_SIZE 1024
410 #define CFC_REG_INIT_REG 0x10404c
411 #define CFC_REG_INTERFACES 0x104058
412 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
413 field allows changing the priorities of the weighted-round-robin arbiter
414 which selects which CFC load client should be served next */
415 #define CFC_REG_LCREQ_WEIGHTS 0x104084
416 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
417 #define CFC_REG_LINK_LIST 0x104c00
418 #define CFC_REG_LINK_LIST_SIZE 256
419 /* [R 1] indication the initializing the link list by the hardware was done. */
420 #define CFC_REG_LL_INIT_DONE 0x104074
421 /* [R 9] Number of allocated LCIDs which are at empty state */
422 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
423 /* [R 9] Number of Arriving LCIDs in Link List Block */
424 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
425 /* [R 9] Number of Leaving LCIDs in Link List Block */
426 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
427 #define CFC_REG_WEAK_ENABLE_PF 0x104124
428 /* [RW 8] The event id for aggregated interrupt 0 */
429 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
430 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060
431 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064
432 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068
433 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c
434 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070
435 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074
436 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078
437 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040
438 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044
439 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048
440 #define CSDM_REG_AGG_INT_EVENT_5 0xc204c
441 #define CSDM_REG_AGG_INT_EVENT_6 0xc2050
442 #define CSDM_REG_AGG_INT_EVENT_7 0xc2054
443 #define CSDM_REG_AGG_INT_EVENT_8 0xc2058
444 #define CSDM_REG_AGG_INT_EVENT_9 0xc205c
445 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
446 or auto-mask-mode (1) */
447 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0
448 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4
449 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8
450 #define CSDM_REG_AGG_INT_MODE_13 0xc21ec
451 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0
452 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4
453 #define CSDM_REG_AGG_INT_MODE_16 0xc21f8
454 #define CSDM_REG_AGG_INT_MODE_6 0xc21d0
455 #define CSDM_REG_AGG_INT_MODE_7 0xc21d4
456 #define CSDM_REG_AGG_INT_MODE_8 0xc21d8
457 #define CSDM_REG_AGG_INT_MODE_9 0xc21dc
458 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
459 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
460 /* [RW 16] The maximum value of the completion counter #0 */
461 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
462 /* [RW 16] The maximum value of the completion counter #1 */
463 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
464 /* [RW 16] The maximum value of the completion counter #2 */
465 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
466 /* [RW 16] The maximum value of the completion counter #3 */
467 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
468 /* [RW 13] The start address in the internal RAM for the completion
469 counters. */
470 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
471 /* [RW 32] Interrupt mask register #0 read/write */
472 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
473 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
474 /* [R 32] Interrupt register #0 read */
475 #define CSDM_REG_CSDM_INT_STS_0 0xc2290
476 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0
477 /* [RW 11] Parity mask register #0 read/write */
478 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
479 /* [R 11] Parity register #0 read */
480 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
481 /* [RC 11] Parity register #0 read clear */
482 #define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
483 #define CSDM_REG_ENABLE_IN1 0xc2238
484 #define CSDM_REG_ENABLE_IN2 0xc223c
485 #define CSDM_REG_ENABLE_OUT1 0xc2240
486 #define CSDM_REG_ENABLE_OUT2 0xc2244
487 /* [RW 4] The initial number of messages that can be sent to the pxp control
488 interface without receiving any ACK. */
489 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
490 /* [ST 32] The number of ACK after placement messages received */
491 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
492 /* [ST 32] The number of packet end messages received from the parser */
493 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
494 /* [ST 32] The number of requests received from the pxp async if */
495 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
496 /* [ST 32] The number of commands received in queue 0 */
497 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
498 /* [ST 32] The number of commands received in queue 10 */
499 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
500 /* [ST 32] The number of commands received in queue 11 */
501 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
502 /* [ST 32] The number of commands received in queue 1 */
503 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
504 /* [ST 32] The number of commands received in queue 3 */
505 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
506 /* [ST 32] The number of commands received in queue 4 */
507 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
508 /* [ST 32] The number of commands received in queue 5 */
509 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
510 /* [ST 32] The number of commands received in queue 6 */
511 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
512 /* [ST 32] The number of commands received in queue 7 */
513 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
514 /* [ST 32] The number of commands received in queue 8 */
515 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
516 /* [ST 32] The number of commands received in queue 9 */
517 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
518 /* [RW 13] The start address in the internal RAM for queue counters */
519 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
520 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
521 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
522 /* [R 1] parser fifo empty in sdm_sync block */
523 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
524 /* [R 1] parser serial fifo empty in sdm_sync block */
525 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
526 /* [RW 32] Tick for timer counter. Applicable only when
527 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
528 #define CSDM_REG_TIMER_TICK 0xc2000
529 /* [RW 5] The number of time_slots in the arbitration cycle */
530 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
531 /* [RW 3] The source that is associated with arbitration element 0. Source
532 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
533 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
534 #define CSEM_REG_ARB_ELEMENT0 0x200020
535 /* [RW 3] The source that is associated with arbitration element 1. Source
536 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
537 sleeping thread with priority 1; 4- sleeping thread with priority 2.
538 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
539 #define CSEM_REG_ARB_ELEMENT1 0x200024
540 /* [RW 3] The source that is associated with arbitration element 2. Source
541 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
542 sleeping thread with priority 1; 4- sleeping thread with priority 2.
543 Could not be equal to register ~csem_registers_arb_element0.arb_element0
544 and ~csem_registers_arb_element1.arb_element1 */
545 #define CSEM_REG_ARB_ELEMENT2 0x200028
546 /* [RW 3] The source that is associated with arbitration element 3. Source
547 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
548 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
549 not be equal to register ~csem_registers_arb_element0.arb_element0 and
550 ~csem_registers_arb_element1.arb_element1 and
551 ~csem_registers_arb_element2.arb_element2 */
552 #define CSEM_REG_ARB_ELEMENT3 0x20002c
553 /* [RW 3] The source that is associated with arbitration element 4. Source
554 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
555 sleeping thread with priority 1; 4- sleeping thread with priority 2.
556 Could not be equal to register ~csem_registers_arb_element0.arb_element0
557 and ~csem_registers_arb_element1.arb_element1 and
558 ~csem_registers_arb_element2.arb_element2 and
559 ~csem_registers_arb_element3.arb_element3 */
560 #define CSEM_REG_ARB_ELEMENT4 0x200030
561 /* [RW 32] Interrupt mask register #0 read/write */
562 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
563 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
564 /* [R 32] Interrupt register #0 read */
565 #define CSEM_REG_CSEM_INT_STS_0 0x200104
566 #define CSEM_REG_CSEM_INT_STS_1 0x200114
567 /* [RW 32] Parity mask register #0 read/write */
568 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
569 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
570 /* [R 32] Parity register #0 read */
571 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
572 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
573 /* [RC 32] Parity register #0 read clear */
574 #define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
575 #define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
576 #define CSEM_REG_ENABLE_IN 0x2000a4
577 #define CSEM_REG_ENABLE_OUT 0x2000a8
578 /* [RW 32] This address space contains all registers and memories that are
579 placed in SEM_FAST block. The SEM_FAST registers are described in
580 appendix B. In order to access the sem_fast registers the base address
581 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
582 #define CSEM_REG_FAST_MEMORY 0x220000
583 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
584 by the microcode */
585 #define CSEM_REG_FIC0_DISABLE 0x200224
586 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
587 by the microcode */
588 #define CSEM_REG_FIC1_DISABLE 0x200234
589 /* [RW 15] Interrupt table Read and write access to it is not possible in
590 the middle of the work */
591 #define CSEM_REG_INT_TABLE 0x200400
592 /* [ST 24] Statistics register. The number of messages that entered through
593 FIC0 */
594 #define CSEM_REG_MSG_NUM_FIC0 0x200000
595 /* [ST 24] Statistics register. The number of messages that entered through
596 FIC1 */
597 #define CSEM_REG_MSG_NUM_FIC1 0x200004
598 /* [ST 24] Statistics register. The number of messages that were sent to
599 FOC0 */
600 #define CSEM_REG_MSG_NUM_FOC0 0x200008
601 /* [ST 24] Statistics register. The number of messages that were sent to
602 FOC1 */
603 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
604 /* [ST 24] Statistics register. The number of messages that were sent to
605 FOC2 */
606 #define CSEM_REG_MSG_NUM_FOC2 0x200010
607 /* [ST 24] Statistics register. The number of messages that were sent to
608 FOC3 */
609 #define CSEM_REG_MSG_NUM_FOC3 0x200014
610 /* [RW 1] Disables input messages from the passive buffer May be updated
611 during run_time by the microcode */
612 #define CSEM_REG_PAS_DISABLE 0x20024c
613 /* [WB 128] Debug only. Passive buffer memory */
614 #define CSEM_REG_PASSIVE_BUFFER 0x202000
615 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
616 #define CSEM_REG_PRAM 0x240000
617 /* [R 16] Valid sleeping threads indication have bit per thread */
618 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
619 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
620 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
621 /* [RW 16] List of free threads . There is a bit per thread. */
622 #define CSEM_REG_THREADS_LIST 0x2002e4
623 /* [RW 3] The arbitration scheme of time_slot 0 */
624 #define CSEM_REG_TS_0_AS 0x200038
625 /* [RW 3] The arbitration scheme of time_slot 10 */
626 #define CSEM_REG_TS_10_AS 0x200060
627 /* [RW 3] The arbitration scheme of time_slot 11 */
628 #define CSEM_REG_TS_11_AS 0x200064
629 /* [RW 3] The arbitration scheme of time_slot 12 */
630 #define CSEM_REG_TS_12_AS 0x200068
631 /* [RW 3] The arbitration scheme of time_slot 13 */
632 #define CSEM_REG_TS_13_AS 0x20006c
633 /* [RW 3] The arbitration scheme of time_slot 14 */
634 #define CSEM_REG_TS_14_AS 0x200070
635 /* [RW 3] The arbitration scheme of time_slot 15 */
636 #define CSEM_REG_TS_15_AS 0x200074
637 /* [RW 3] The arbitration scheme of time_slot 16 */
638 #define CSEM_REG_TS_16_AS 0x200078
639 /* [RW 3] The arbitration scheme of time_slot 17 */
640 #define CSEM_REG_TS_17_AS 0x20007c
641 /* [RW 3] The arbitration scheme of time_slot 18 */
642 #define CSEM_REG_TS_18_AS 0x200080
643 /* [RW 3] The arbitration scheme of time_slot 1 */
644 #define CSEM_REG_TS_1_AS 0x20003c
645 /* [RW 3] The arbitration scheme of time_slot 2 */
646 #define CSEM_REG_TS_2_AS 0x200040
647 /* [RW 3] The arbitration scheme of time_slot 3 */
648 #define CSEM_REG_TS_3_AS 0x200044
649 /* [RW 3] The arbitration scheme of time_slot 4 */
650 #define CSEM_REG_TS_4_AS 0x200048
651 /* [RW 3] The arbitration scheme of time_slot 5 */
652 #define CSEM_REG_TS_5_AS 0x20004c
653 /* [RW 3] The arbitration scheme of time_slot 6 */
654 #define CSEM_REG_TS_6_AS 0x200050
655 /* [RW 3] The arbitration scheme of time_slot 7 */
656 #define CSEM_REG_TS_7_AS 0x200054
657 /* [RW 3] The arbitration scheme of time_slot 8 */
658 #define CSEM_REG_TS_8_AS 0x200058
659 /* [RW 3] The arbitration scheme of time_slot 9 */
660 #define CSEM_REG_TS_9_AS 0x20005c
661 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
662 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
663 #define CSEM_REG_VFPF_ERR_NUM 0x200380
664 /* [RW 1] Parity mask register #0 read/write */
665 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
666 /* [R 1] Parity register #0 read */
667 #define DBG_REG_DBG_PRTY_STS 0xc09c
668 /* [RC 1] Parity register #0 read clear */
669 #define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
670 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
671 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
672 * 4.Completion function=0; 5.Error handling=0 */
673 #define DMAE_REG_BACKWARD_COMP_EN 0x10207c
674 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
675 as 14*X+Y. */
676 #define DMAE_REG_CMD_MEM 0x102400
677 #define DMAE_REG_CMD_MEM_SIZE 224
678 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
679 initial value is all ones. */
680 #define DMAE_REG_CRC16C_INIT 0x10201c
681 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
682 CRC-16 T10 initial value is all ones. */
683 #define DMAE_REG_CRC16T10_INIT 0x102020
684 /* [RW 2] Interrupt mask register #0 read/write */
685 #define DMAE_REG_DMAE_INT_MASK 0x102054
686 /* [RW 4] Parity mask register #0 read/write */
687 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
688 /* [R 4] Parity register #0 read */
689 #define DMAE_REG_DMAE_PRTY_STS 0x102058
690 /* [RC 4] Parity register #0 read clear */
691 #define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
692 /* [RW 1] Command 0 go. */
693 #define DMAE_REG_GO_C0 0x102080
694 /* [RW 1] Command 1 go. */
695 #define DMAE_REG_GO_C1 0x102084
696 /* [RW 1] Command 10 go. */
697 #define DMAE_REG_GO_C10 0x102088
698 /* [RW 1] Command 11 go. */
699 #define DMAE_REG_GO_C11 0x10208c
700 /* [RW 1] Command 12 go. */
701 #define DMAE_REG_GO_C12 0x102090
702 /* [RW 1] Command 13 go. */
703 #define DMAE_REG_GO_C13 0x102094
704 /* [RW 1] Command 14 go. */
705 #define DMAE_REG_GO_C14 0x102098
706 /* [RW 1] Command 15 go. */
707 #define DMAE_REG_GO_C15 0x10209c
708 /* [RW 1] Command 2 go. */
709 #define DMAE_REG_GO_C2 0x1020a0
710 /* [RW 1] Command 3 go. */
711 #define DMAE_REG_GO_C3 0x1020a4
712 /* [RW 1] Command 4 go. */
713 #define DMAE_REG_GO_C4 0x1020a8
714 /* [RW 1] Command 5 go. */
715 #define DMAE_REG_GO_C5 0x1020ac
716 /* [RW 1] Command 6 go. */
717 #define DMAE_REG_GO_C6 0x1020b0
718 /* [RW 1] Command 7 go. */
719 #define DMAE_REG_GO_C7 0x1020b4
720 /* [RW 1] Command 8 go. */
721 #define DMAE_REG_GO_C8 0x1020b8
722 /* [RW 1] Command 9 go. */
723 #define DMAE_REG_GO_C9 0x1020bc
724 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
725 input is disregarded; valid is deasserted; all other signals are treated
726 as usual; if 1 - normal activity. */
727 #define DMAE_REG_GRC_IFEN 0x102008
728 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
729 acknowledge input is disregarded; valid is deasserted; full is asserted;
730 all other signals are treated as usual; if 1 - normal activity. */
731 #define DMAE_REG_PCI_IFEN 0x102004
732 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
733 initial value to the credit counter; related to the address. Read returns
734 the current value of the counter. */
735 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
736 /* [RW 8] Aggregation command. */
737 #define DORQ_REG_AGG_CMD0 0x170060
738 /* [RW 8] Aggregation command. */
739 #define DORQ_REG_AGG_CMD1 0x170064
740 /* [RW 8] Aggregation command. */
741 #define DORQ_REG_AGG_CMD2 0x170068
742 /* [RW 8] Aggregation command. */
743 #define DORQ_REG_AGG_CMD3 0x17006c
744 /* [RW 28] UCM Header. */
745 #define DORQ_REG_CMHEAD_RX 0x170050
746 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
747 #define DORQ_REG_DB_ADDR0 0x17008c
748 /* [RW 5] Interrupt mask register #0 read/write */
749 #define DORQ_REG_DORQ_INT_MASK 0x170180
750 /* [R 5] Interrupt register #0 read */
751 #define DORQ_REG_DORQ_INT_STS 0x170174
752 /* [RC 5] Interrupt register #0 read clear */
753 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
754 /* [RW 2] Parity mask register #0 read/write */
755 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
756 /* [R 2] Parity register #0 read */
757 #define DORQ_REG_DORQ_PRTY_STS 0x170184
758 /* [RC 2] Parity register #0 read clear */
759 #define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
760 /* [RW 8] The address to write the DPM CID to STORM. */
761 #define DORQ_REG_DPM_CID_ADDR 0x170044
762 /* [RW 5] The DPM mode CID extraction offset. */
763 #define DORQ_REG_DPM_CID_OFST 0x170030
764 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
765 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
766 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
767 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
768 /* [R 13] Current value of the DQ FIFO fill level according to following
769 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
770 doorbell. */
771 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
772 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
773 equal to full threshold; reset on full clear. */
774 #define DORQ_REG_DQ_FULL_ST 0x1700c0
775 /* [RW 28] The value sent to CM header in the case of CFC load error. */
776 #define DORQ_REG_ERR_CMHEAD 0x170058
777 #define DORQ_REG_IF_EN 0x170004
778 #define DORQ_REG_MODE_ACT 0x170008
779 /* [RW 5] The normal mode CID extraction offset. */
780 #define DORQ_REG_NORM_CID_OFST 0x17002c
781 /* [RW 28] TCM Header when only TCP context is loaded. */
782 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
783 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
784 Interface. */
785 #define DORQ_REG_OUTST_REQ 0x17003c
786 #define DORQ_REG_REGN 0x170038
787 /* [R 4] Current value of response A counter credit. Initial credit is
788 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
789 register. */
790 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
791 /* [R 4] Current value of response B counter credit. Initial credit is
792 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
793 register. */
794 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
795 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
796 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
797 read reads this written value. */
798 #define DORQ_REG_RSP_INIT_CRD 0x170048
799 /* [RW 4] Initial activity counter value on the load request; when the
800 shortcut is done. */
801 #define DORQ_REG_SHRT_ACT_CNT 0x170070
802 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
803 #define DORQ_REG_SHRT_CMHEAD 0x170054
804 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
805 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
806 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
807 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
808 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
809 #define HC_REG_AGG_INT_0 0x108050
810 #define HC_REG_AGG_INT_1 0x108054
811 #define HC_REG_ATTN_BIT 0x108120
812 #define HC_REG_ATTN_IDX 0x108100
813 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
814 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
815 #define HC_REG_ATTN_NUM_P0 0x108038
816 #define HC_REG_ATTN_NUM_P1 0x10803c
817 #define HC_REG_COMMAND_REG 0x108180
818 #define HC_REG_CONFIG_0 0x108000
819 #define HC_REG_CONFIG_1 0x108004
820 #define HC_REG_FUNC_NUM_P0 0x1080ac
821 #define HC_REG_FUNC_NUM_P1 0x1080b0
822 /* [RW 3] Parity mask register #0 read/write */
823 #define HC_REG_HC_PRTY_MASK 0x1080a0
824 /* [R 3] Parity register #0 read */
825 #define HC_REG_HC_PRTY_STS 0x108094
826 /* [RC 3] Parity register #0 read clear */
827 #define HC_REG_HC_PRTY_STS_CLR 0x108098
828 #define HC_REG_INT_MASK 0x108108
829 #define HC_REG_LEADING_EDGE_0 0x108040
830 #define HC_REG_LEADING_EDGE_1 0x108048
831 #define HC_REG_MAIN_MEMORY 0x108800
832 #define HC_REG_MAIN_MEMORY_SIZE 152
833 #define HC_REG_P0_PROD_CONS 0x108200
834 #define HC_REG_P1_PROD_CONS 0x108400
835 #define HC_REG_PBA_COMMAND 0x108140
836 #define HC_REG_PCI_CONFIG_0 0x108010
837 #define HC_REG_PCI_CONFIG_1 0x108014
838 #define HC_REG_STATISTIC_COUNTERS 0x109000
839 #define HC_REG_TRAILING_EDGE_0 0x108044
840 #define HC_REG_TRAILING_EDGE_1 0x10804c
841 #define HC_REG_UC_RAM_ADDR_0 0x108028
842 #define HC_REG_UC_RAM_ADDR_1 0x108030
843 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
844 #define HC_REG_VQID_0 0x108008
845 #define HC_REG_VQID_1 0x10800c
846 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
847 #define IGU_REG_ATTENTION_ACK_BITS 0x130108
848 /* [R 4] Debug: attn_fsm */
849 #define IGU_REG_ATTN_FSM 0x130054
850 #define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
851 #define IGU_REG_ATTN_MSG_ADDR_L 0x130120
852 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
853 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
854 * write done didn't receive. */
855 #define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
856 #define IGU_REG_BLOCK_CONFIGURATION 0x130000
857 #define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
858 #define IGU_REG_COMMAND_REG_CTRL 0x13012c
859 /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
860 * is clear. The bits in this registers are set and clear via the producer
861 * command. Data valid only in addresses 0-4. all the rest are zero. */
862 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
863 /* [R 5] Debug: ctrl_fsm */
864 #define IGU_REG_CTRL_FSM 0x130064
865 /* [R 1] data available for error memory. If this bit is clear do not red
866 * from error_handling_memory. */
867 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
868 /* [RW 11] Parity mask register #0 read/write */
869 #define IGU_REG_IGU_PRTY_MASK 0x1300a8
870 /* [R 11] Parity register #0 read */
871 #define IGU_REG_IGU_PRTY_STS 0x13009c
872 /* [RC 11] Parity register #0 read clear */
873 #define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
874 /* [R 4] Debug: int_handle_fsm */
875 #define IGU_REG_INT_HANDLE_FSM 0x130050
876 #define IGU_REG_LEADING_EDGE_LATCH 0x130134
877 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
878 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
879 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
880 #define IGU_REG_MAPPING_MEMORY 0x131000
881 #define IGU_REG_MAPPING_MEMORY_SIZE 136
882 #define IGU_REG_PBA_STATUS_LSB 0x130138
883 #define IGU_REG_PBA_STATUS_MSB 0x13013c
884 #define IGU_REG_PCI_PF_MSI_EN 0x130140
885 #define IGU_REG_PCI_PF_MSIX_EN 0x130144
886 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
887 /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
888 * pending; 1 = pending. Pendings means interrupt was asserted; and write
889 * done was not received. Data valid only in addresses 0-4. all the rest are
890 * zero. */
891 #define IGU_REG_PENDING_BITS_STATUS 0x130300
892 #define IGU_REG_PF_CONFIGURATION 0x130154
893 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
894 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
895 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
896 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
897 * - In backward compatible mode; for non default SB; each even line in the
898 * memory holds the U producer and each odd line hold the C producer. The
899 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
900 * last 20 producers are for the DSB for each PF. each PF has five segments
901 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
902 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
903 #define IGU_REG_PROD_CONS_MEMORY 0x132000
904 /* [R 3] Debug: pxp_arb_fsm */
905 #define IGU_REG_PXP_ARB_FSM 0x130068
906 /* [RW 6] Write one for each bit will reset the appropriate memory. When the
907 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
908 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
909 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
910 #define IGU_REG_RESET_MEMORIES 0x130158
911 /* [R 4] Debug: sb_ctrl_fsm */
912 #define IGU_REG_SB_CTRL_FSM 0x13004c
913 #define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
914 #define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
915 #define IGU_REG_SB_MASK_LSB 0x130164
916 #define IGU_REG_SB_MASK_MSB 0x130168
917 /* [RW 16] Number of command that were dropped without causing an interrupt
918 * due to: read access for WO BAR address; or write access for RO BAR
919 * address or any access for reserved address or PCI function error is set
920 * and address is not MSIX; PBA or cleanup */
921 #define IGU_REG_SILENT_DROP 0x13016c
922 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
923 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
924 * PF; 68-71 number of ATTN messages per PF */
925 #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
926 /* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
927 * timer mask command arrives. Value must be bigger than 100. */
928 #define IGU_REG_TIMER_MASKING_VALUE 0x13003c
929 #define IGU_REG_TRAILING_EDGE_LATCH 0x130104
930 #define IGU_REG_VF_CONFIGURATION 0x130170
931 /* [WB_R 32] Each bit represent write done pending bits status for that SB
932 * (MSI/MSIX message was sent and write done was not received yet). 0 =
933 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
934 #define IGU_REG_WRITE_DONE_PENDING 0x130480
935 #define MCP_A_REG_MCPR_SCRATCH 0x3a0000
936 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
937 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
938 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
939 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
940 #define MCP_REG_MCPR_NVM_READ 0x86410
941 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
942 #define MCP_REG_MCPR_NVM_WRITE 0x86408
943 #define MCP_REG_MCPR_SCRATCH 0xa0000
944 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
945 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
946 /* [R 32] read first 32 bit after inversion of function 0. mapped as
947 follows: [0] NIG attention for function0; [1] NIG attention for
948 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
949 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
950 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
951 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
952 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
953 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
954 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
955 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
956 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
957 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
958 Parity error; [31] PBF Hw interrupt; */
959 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
960 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
961 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
962 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
963 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
964 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
965 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
966 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
967 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
968 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
969 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
970 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
971 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
972 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
973 interrupt; */
974 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
975 /* [R 32] read second 32 bit after inversion of function 0. mapped as
976 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
977 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
978 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
979 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
980 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
981 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
982 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
983 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
984 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
985 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
986 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
987 interrupt; */
988 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
989 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
990 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
991 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
992 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
993 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
994 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
995 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
996 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
997 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
998 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
999 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1000 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1001 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1002 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
1003 /* [R 32] read third 32 bit after inversion of function 0. mapped as
1004 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
1005 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
1006 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1007 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1008 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1009 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1010 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1011 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1012 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1013 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1014 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1015 attn1; */
1016 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
1017 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
1018 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
1019 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
1020 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
1021 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
1022 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
1023 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
1024 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
1025 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
1026 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
1027 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
1028 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
1029 timers attn_4 func1; [30] General attn0; [31] General attn1; */
1030 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
1031 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
1032 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1033 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1034 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1035 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1036 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1037 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1038 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1039 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1040 Latched timeout attention; [27] GRC Latched reserved access attention;
1041 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1042 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1043 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
1044 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
1045 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
1046 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
1047 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
1048 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
1049 General attn13; [12] General attn14; [13] General attn15; [14] General
1050 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
1051 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
1052 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
1053 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
1054 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
1055 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
1056 ump_tx_parity; [31] MCP Latched scpad_parity; */
1057 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
1058 /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
1059 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1060 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1061 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1062 #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
1063 /* [W 14] write to this register results with the clear of the latched
1064 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
1065 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
1066 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
1067 GRC Latched reserved access attention; one in d7 clears Latched
1068 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
1069 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
1070 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
1071 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
1072 from this register return zero */
1073 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
1074 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1075 as follows: [0] NIG attention for function0; [1] NIG attention for
1076 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1077 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1078 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1079 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1080 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1081 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1082 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1083 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1084 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1085 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1086 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1087 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
1088 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
1089 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
1090 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
1091 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
1092 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
1093 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
1094 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
1095 as follows: [0] NIG attention for function0; [1] NIG attention for
1096 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1097 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1098 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1099 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1100 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1101 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
1102 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1103 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1104 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1105 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1106 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1107 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
1108 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
1109 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
1110 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
1111 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
1112 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
1113 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
1114 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped
1115 as follows: [0] NIG attention for function0; [1] NIG attention for
1116 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1117 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1118 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1119 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1120 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1121 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1122 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1123 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1124 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1125 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1126 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1127 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
1128 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
1129 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
1130 as follows: [0] NIG attention for function0; [1] NIG attention for
1131 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1132 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1133 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1134 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1135 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1136 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1137 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1138 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1139 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1140 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1141 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1142 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
1143 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
1144 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1145 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1146 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1147 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1148 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1149 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1150 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1151 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1152 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1153 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1154 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1155 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1156 interrupt; */
1157 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1158 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1159 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1160 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1161 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1162 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1163 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1164 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1165 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1166 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1167 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1168 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1169 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1170 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1171 interrupt; */
1172 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1173 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
1174 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1175 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1176 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1177 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1178 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1179 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1180 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1181 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1182 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1183 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1184 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1185 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1186 interrupt; */
1187 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1188 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1189 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1190 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1191 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1192 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1193 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1194 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1195 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1196 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1197 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1198 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1199 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1200 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1201 interrupt; */
1202 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1203 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1204 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1205 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1206 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1207 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1208 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1209 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1210 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1211 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1212 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1213 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1214 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1215 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1216 attn1; */
1217 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1218 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1219 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1220 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1221 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1222 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1223 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1224 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1225 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1226 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1227 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1228 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1229 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1230 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1231 attn1; */
1232 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1233 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1234 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1235 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1236 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1237 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1238 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1239 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1240 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1241 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1242 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1243 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1244 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1245 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1246 attn1; */
1247 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1248 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1249 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1250 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1251 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1252 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1253 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1254 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1255 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1256 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1257 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1258 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1259 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1260 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1261 attn1; */
1262 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1263 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1264 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1265 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1266 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1267 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1268 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1269 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1270 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1271 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1272 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1273 Latched timeout attention; [27] GRC Latched reserved access attention;
1274 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1275 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1276 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1277 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1278 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1279 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1280 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1281 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1282 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1283 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1284 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1285 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1286 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1287 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1288 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1289 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1290 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1291 Latched timeout attention; [27] GRC Latched reserved access attention;
1292 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1293 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1294 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1295 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1296 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1297 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1298 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1299 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1300 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1301 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1302 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1303 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1304 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1305 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1306 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1307 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1308 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1309 Latched timeout attention; [27] GRC Latched reserved access attention;
1310 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1311 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1312 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1313 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1314 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1315 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1316 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1317 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1318 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1319 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1320 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1321 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1322 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1323 Latched timeout attention; [27] GRC Latched reserved access attention;
1324 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1325 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1326 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1327 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1328 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1329 128 bit vector */
1330 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1331 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1332 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1333 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1334 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1335 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1336 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1337 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1338 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1339 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1340 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1341 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1342 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1343 #define MISC_REG_AEU_GENERAL_MASK 0xa61c
1344 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1345 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1346 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1347 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1348 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1349 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1350 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1351 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1352 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1353 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1354 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1355 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1356 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1357 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1358 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1359 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1360 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1361 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1362 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1363 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1364 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1365 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1366 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1367 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1368 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1369 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1370 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1371 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1372 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1373 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1374 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1375 [9:8] = raserved. Zero = mask; one = unmask */
1376 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1377 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1378 /* [RW 1] If set a system kill occurred */
1379 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1380 /* [RW 32] Represent the status of the input vector to the AEU when a system
1381 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1382 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1383 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1384 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1385 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1386 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1387 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1388 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1389 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1390 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1391 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1392 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1393 interrupt; */
1394 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1395 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1396 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1397 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1398 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1399 Port. */
1400 #define MISC_REG_BOND_ID 0xa400
1401 /* [R 8] These bits indicate the metal revision of the chip. This value
1402 starts at 0x00 for each all-layer tape-out and increments by one for each
1403 tape-out. */
1404 #define MISC_REG_CHIP_METAL 0xa404
1405 /* [R 16] These bits indicate the part number for the chip. */
1406 #define MISC_REG_CHIP_NUM 0xa408
1407 /* [R 4] These bits indicate the base revision of the chip. This value
1408 starts at 0x0 for the A0 tape-out and increments by one for each
1409 all-layer tape-out. */
1410 #define MISC_REG_CHIP_REV 0xa40c
1411 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1412 32 clients. Each client can be controlled by one driver only. One in each
1413 bit represent that this driver control the appropriate client (Ex: bit 5
1414 is set means this driver control client number 5). addr1 = set; addr0 =
1415 clear; read from both addresses will give the same result = status. write
1416 to address 1 will set a request to control all the clients that their
1417 appropriate bit (in the write command) is set. if the client is free (the
1418 appropriate bit in all the other drivers is clear) one will be written to
1419 that driver register; if the client isn't free the bit will remain zero.
1420 if the appropriate bit is set (the driver request to gain control on a
1421 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1422 interrupt will be asserted). write to address 0 will set a request to
1423 free all the clients that their appropriate bit (in the write command) is
1424 set. if the appropriate bit is clear (the driver request to free a client
1425 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1426 be asserted). */
1427 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1428 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1429 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1430 only. */
1431 #define MISC_REG_E1HMF_MODE 0xa5f8
1432 /* [RW 32] Debug only: spare RW register reset by core reset */
1433 #define MISC_REG_GENERIC_CR_0 0xa460
1434 #define MISC_REG_GENERIC_CR_1 0xa464
1435 /* [RW 32] Debug only: spare RW register reset by por reset */
1436 #define MISC_REG_GENERIC_POR_1 0xa474
1437 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1438 these bits is written as a '1'; the corresponding SPIO bit will turn off
1439 it's drivers and become an input. This is the reset state of all GPIO
1440 pins. The read value of these bits will be a '1' if that last command
1441 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1442 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1443 as a '1'; the corresponding GPIO bit will drive low. The read value of
1444 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1445 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1446 SET When any of these bits is written as a '1'; the corresponding GPIO
1447 bit will drive high (if it has that capability). The read value of these
1448 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1449 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1450 RO; These bits indicate the read value of each of the eight GPIO pins.
1451 This is the result value of the pin; not the drive value. Writing these
1452 bits will have not effect. */
1453 #define MISC_REG_GPIO 0xa490
1454 /* [RW 8] These bits enable the GPIO_INTs to signals event to the
1455 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1456 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1457 [7] p1_gpio_3; */
1458 #define MISC_REG_GPIO_EVENT_EN 0xa2bc
1459 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1460 '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1461 This will acknowledge an interrupt on the falling edge of corresponding
1462 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1463 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1464 register. This will acknowledge an interrupt on the rising edge of
1465 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1466 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1467 value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1468 of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1469 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1470 is '1'; then the interrupt is due to a high to low edge (reset value 0).
1471 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1472 current GPIO interrupt state for each GPIO pin. This bit is cleared when
1473 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1474 set when the GPIO input does not match the current value in #OLD_VALUE
1475 (reset value 0). */
1476 #define MISC_REG_GPIO_INT 0xa494
1477 /* [R 28] this field hold the last information that caused reserved
1478 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1479 [27:24] the master that caused the attention - according to the following
1480 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1481 dbu; 8 = dmae */
1482 #define MISC_REG_GRC_RSV_ATTN 0xa3c0
1483 /* [R 28] this field hold the last information that caused timeout
1484 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1485 [27:24] the master that caused the attention - according to the following
1486 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1487 dbu; 8 = dmae */
1488 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1489 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1490 access that does not finish within
1491 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1492 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1493 assert it attention output. */
1494 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1495 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1496 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1497 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1498 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1499 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1500 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1501 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1502 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1503 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1504 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1505 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1506 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1507 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1508 connected to RESET input directly. [15] capRetry_en (reset value 0)
1509 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1510 value 0) bit to continuously monitor vco freq (inverted). [17]
1511 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1512 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1513 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1514 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1515 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1516 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1517 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1518 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1519 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1520 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1521 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1522 register bits. */
1523 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1524 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1525 /* [RW 4] Interrupt mask register #0 read/write */
1526 #define MISC_REG_MISC_INT_MASK 0xa388
1527 /* [RW 1] Parity mask register #0 read/write */
1528 #define MISC_REG_MISC_PRTY_MASK 0xa398
1529 /* [R 1] Parity register #0 read */
1530 #define MISC_REG_MISC_PRTY_STS 0xa38c
1531 /* [RC 1] Parity register #0 read clear */
1532 #define MISC_REG_MISC_PRTY_STS_CLR 0xa390
1533 #define MISC_REG_NIG_WOL_P0 0xa270
1534 #define MISC_REG_NIG_WOL_P1 0xa274
1535 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1536 assertion */
1537 #define MISC_REG_PCIE_HOT_RESET 0xa618
1538 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1539 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1540 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1541 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1542 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1543 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1544 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1545 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1546 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1547 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1548 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1549 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1550 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1551 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1552 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1553 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1554 testa_en (reset value 0); */
1555 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1556 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1557 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1558 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1559 /* [R 1] Status of 4 port mode enable input pin. */
1560 #define MISC_REG_PORT4MODE_EN 0xa750
1561 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1562 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1563 * the port4mode_en output is equal to bit[1] of this register; [1] -
1564 * Overwrite value. If bit[0] of this register is 1 this is the value that
1565 * receives the port4mode_en output . */
1566 #define MISC_REG_PORT4MODE_EN_OVWR 0xa720
1567 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1568 write/read zero = the specific block is in reset; addr 0-wr- the write
1569 value will be written to the register; addr 1-set - one will be written
1570 to all the bits that have the value of one in the data written (bits that
1571 have the value of zero will not be change) ; addr 2-clear - zero will be
1572 written to all the bits that have the value of one in the data written
1573 (bits that have the value of zero will not be change); addr 3-ignore;
1574 read ignore from all addr except addr 00; inside order of the bits is:
1575 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1576 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1577 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1578 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1579 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1580 rst_pxp_rq_rd_wr; 31:17] reserved */
1581 #define MISC_REG_RESET_REG_2 0xa590
1582 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1583 shared with the driver resides */
1584 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1585 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1586 the corresponding SPIO bit will turn off it's drivers and become an
1587 input. This is the reset state of all SPIO pins. The read value of these
1588 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1589 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1590 is written as a '1'; the corresponding SPIO bit will drive low. The read
1591 value of these bits will be a '1' if that last command (#SET; #CLR; or
1592 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1593 these bits is written as a '1'; the corresponding SPIO bit will drive
1594 high (if it has that capability). The read value of these bits will be a
1595 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1596 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1597 each of the eight SPIO pins. This is the result value of the pin; not the
1598 drive value. Writing these bits will have not effect. Each 8 bits field
1599 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1600 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1601 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1602 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1603 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1604 select VAUX supply. (This is an output pin only; it is not controlled by
1605 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1606 field is not applicable for this pin; only the VALUE fields is relevant -
1607 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1608 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1609 device ID select; read by UMP firmware. */
1610 #define MISC_REG_SPIO 0xa4fc
1611 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1612 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1613 [7:0] reserved */
1614 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1615 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1616 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1617 interrupt on the falling edge of corresponding SPIO input (reset value
1618 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1619 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1620 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1621 RO; These bits indicate the old value of the SPIO input value. When the
1622 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1623 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1624 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1625 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1626 RO; These bits indicate the current SPIO interrupt state for each SPIO
1627 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1628 command bit is written. This bit is set when the SPIO input does not
1629 match the current value in #OLD_VALUE (reset value 0). */
1630 #define MISC_REG_SPIO_INT 0xa500
1631 /* [RW 32] reload value for counter 4 if reload; the value will be reload if
1632 the counter reached zero and the reload bit
1633 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1634 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1635 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1636 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
1637 timer 8 */
1638 #define MISC_REG_SW_TIMER_VAL 0xa5c0
1639 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1640 loaded; 0-prepare; -unprepare */
1641 #define MISC_REG_UNPREPARED 0xa424
1642 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1643 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1644 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1645 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1646 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1647 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
1648 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
1649 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1650 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1651 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1652 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1653 /* [RW 1] Input enable for RX_BMAC0 IF */
1654 #define NIG_REG_BMAC0_IN_EN 0x100ac
1655 /* [RW 1] output enable for TX_BMAC0 IF */
1656 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1657 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1658 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1659 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1660 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1661 /* [RW 1] output enable for RX BRB1 port0 IF */
1662 #define NIG_REG_BRB0_OUT_EN 0x100f8
1663 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1664 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1665 /* [RW 1] output enable for RX BRB1 port1 IF */
1666 #define NIG_REG_BRB1_OUT_EN 0x100fc
1667 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1668 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1669 /* [RW 1] output enable for RX BRB1 LP IF */
1670 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1671 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1672 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1673 72:73]-vnic_num; 81:74]-sideband_info */
1674 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1675 /* [RW 1] Input enable for TX Debug packet */
1676 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1677 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1678 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1679 First packet may be deleted from the middle. And last packet will be
1680 always deleted till the end. */
1681 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1682 /* [RW 1] Output enable to EMAC0 */
1683 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1684 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1685 to emac for port0; other way to bmac for port0 */
1686 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1687 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1688 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1689 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1690 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1691 /* [RW 1] Input enable for TX UMP management packet port0 IF */
1692 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
1693 /* [RW 1] Input enable for RX_EMAC0 IF */
1694 #define NIG_REG_EMAC0_IN_EN 0x100a4
1695 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1696 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1697 /* [R 1] status from emac0. This bit is set when MDINT from either the
1698 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1699 be cleared in the attached PHY device that is driving the MINT pin. */
1700 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1701 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1702 are described in appendix A. In order to access the BMAC0 registers; the
1703 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1704 added to each BMAC register offset */
1705 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1706 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1707 are described in appendix A. In order to access the BMAC0 registers; the
1708 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1709 added to each BMAC register offset */
1710 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1711 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1712 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1713 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1714 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1715 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1716 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
1717 logic for interrupts must be used. Enable per bit of interrupt of
1718 ~latch_status.latch_status */
1719 #define NIG_REG_LATCH_BC_0 0x16210
1720 /* [RW 27] Latch for each interrupt from Unicore.b[0]
1721 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
1722 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
1723 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
1724 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
1725 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
1726 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
1727 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
1728 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
1729 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
1730 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
1731 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
1732 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
1733 #define NIG_REG_LATCH_STATUS_0 0x18000
1734 /* [RW 1] led 10g for port 0 */
1735 #define NIG_REG_LED_10G_P0 0x10320
1736 /* [RW 1] led 10g for port 1 */
1737 #define NIG_REG_LED_10G_P1 0x10324
1738 /* [RW 1] Port0: This bit is set to enable the use of the
1739 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1740 defined below. If this bit is cleared; then the blink rate will be about
1741 8Hz. */
1742 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1743 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1744 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1745 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1746 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1747 /* [RW 1] Port0: If set along with the
1748 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1749 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1750 bit; the Traffic LED will blink with the blink rate specified in
1751 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1752 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1753 fields. */
1754 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1755 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1756 Traffic LED will then be controlled via bit ~nig_registers_
1757 led_control_traffic_p0.led_control_traffic_p0 and bit
1758 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1759 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1760 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1761 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1762 set; the LED will blink with blink rate specified in
1763 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1764 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1765 fields. */
1766 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1767 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1768 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1769 #define NIG_REG_LED_MODE_P0 0x102f0
1770 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
1771 tsdm enable; b2- usdm enable */
1772 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
1773 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
1774 /* [RW 1] SAFC enable for port0. This register may get 1 only when
1775 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
1776 port */
1777 #define NIG_REG_LLFC_ENABLE_0 0x16208
1778 #define NIG_REG_LLFC_ENABLE_1 0x1620c
1779 /* [RW 16] classes are high-priority for port0 */
1780 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
1781 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
1782 /* [RW 16] classes are low-priority for port0 */
1783 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
1784 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
1785 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
1786 #define NIG_REG_LLFC_OUT_EN_0 0x160c8
1787 #define NIG_REG_LLFC_OUT_EN_1 0x160cc
1788 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1789 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
1790 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1791 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
1792 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1793 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1794 /* [RW 2] Determine the classification participants. 0: no classification.1:
1795 classification upon VLAN id. 2: classification upon MAC address. 3:
1796 classification upon both VLAN id & MAC addr. */
1797 #define NIG_REG_LLH0_CLS_TYPE 0x16080
1798 /* [RW 32] cm header for llh0 */
1799 #define NIG_REG_LLH0_CM_HEADER 0x1007c
1800 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1801 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1802 /* [RW 16] destination TCP address 1. The LLH will look for this address in
1803 all incoming packets. */
1804 #define NIG_REG_LLH0_DEST_TCP_0 0x10220
1805 /* [RW 16] destination UDP address 1 The LLH will look for this address in
1806 all incoming packets. */
1807 #define NIG_REG_LLH0_DEST_UDP_0 0x10214
1808 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
1809 /* [RW 8] event id for llh0 */
1810 #define NIG_REG_LLH0_EVENT_ID 0x10084
1811 #define NIG_REG_LLH0_FUNC_EN 0x160fc
1812 #define NIG_REG_LLH0_FUNC_MEM 0x16180
1813 #define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
1814 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1815 /* [RW 1] Determine the IP version to look for in
1816 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1817 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1818 /* [RW 1] t bit for llh0 */
1819 #define NIG_REG_LLH0_T_BIT 0x10074
1820 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1821 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c
1822 /* [RW 8] init credit counter for port0 in LLH */
1823 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1824 #define NIG_REG_LLH0_XCM_MASK 0x10130
1825 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
1826 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1827 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1828 /* [RW 2] Determine the classification participants. 0: no classification.1:
1829 classification upon VLAN id. 2: classification upon MAC address. 3:
1830 classification upon both VLAN id & MAC addr. */
1831 #define NIG_REG_LLH1_CLS_TYPE 0x16084
1832 /* [RW 32] cm header for llh1 */
1833 #define NIG_REG_LLH1_CM_HEADER 0x10080
1834 #define NIG_REG_LLH1_ERROR_MASK 0x10090
1835 /* [RW 8] event id for llh1 */
1836 #define NIG_REG_LLH1_EVENT_ID 0x10088
1837 #define NIG_REG_LLH1_FUNC_MEM 0x161c0
1838 #define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
1839 #define NIG_REG_LLH1_FUNC_MEM_SIZE 16
1840 /* [RW 8] init credit counter for port1 in LLH */
1841 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1842 #define NIG_REG_LLH1_XCM_MASK 0x10134
1843 /* [RW 1] When this bit is set; the LLH will expect all packets to be with
1844 e1hov */
1845 #define NIG_REG_LLH_E1HOV_MODE 0x160d8
1846 /* [RW 1] When this bit is set; the LLH will classify the packet before
1847 sending it to the BRB or calculating WoL on it. */
1848 #define NIG_REG_LLH_MF_MODE 0x16024
1849 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1850 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1851 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1852 #define NIG_REG_NIG_EMAC0_EN 0x1003c
1853 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1854 #define NIG_REG_NIG_EMAC1_EN 0x10040
1855 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1856 EMAC0 to strip the CRC from the ingress packets. */
1857 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1858 /* [R 32] Interrupt register #0 read */
1859 #define NIG_REG_NIG_INT_STS_0 0x103b0
1860 #define NIG_REG_NIG_INT_STS_1 0x103c0
1861 /* [R 32] Legacy E1 and E1H location for parity error status register. */
1862 #define NIG_REG_NIG_PRTY_STS 0x103d0
1863 /* [R 32] Parity register #0 read */
1864 #define NIG_REG_NIG_PRTY_STS_0 0x183bc
1865 #define NIG_REG_NIG_PRTY_STS_1 0x183cc
1866 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
1867 * Ethernet header. */
1868 #define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
1869 /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
1870 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
1871 * disabled when this bit is set. */
1872 #define NIG_REG_P0_HWPFC_ENABLE 0x18078
1873 #define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
1874 #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
1875 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
1876 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
1877 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
1878 * priority field is extracted from the outer-most VLAN in receive packet.
1879 * Only COS 0 and COS 1 are supported in E2. */
1880 #define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
1881 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
1882 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
1883 * than one bit may be set; allowing multiple priorities to be mapped to one
1884 * COS. */
1885 #define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
1886 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
1887 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
1888 * than one bit may be set; allowing multiple priorities to be mapped to one
1889 * COS. */
1890 #define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
1891 /* [RW 15] Specify which of the credit registers the client is to be mapped
1892 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
1893 * clients that are not subject to WFQ credit blocking - their
1894 * specifications here are not used. */
1895 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
1896 /* [RW 5] Specify whether the client competes directly in the strict
1897 * priority arbiter. The bits are mapped according to client ID (client IDs
1898 * are defined in tx_arb_priority_client). Default value is set to enable
1899 * strict priorities for clients 0-2 -- management and debug traffic. */
1900 #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
1901 /* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
1902 * bits are mapped according to client ID (client IDs are defined in
1903 * tx_arb_priority_client). Default value is 0 for not using WFQ credit
1904 * blocking. */
1905 #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
1906 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
1907 * reach. */
1908 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
1909 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
1910 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
1911 * when it is time to increment. */
1912 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
1913 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
1914 /* [RW 12] Specify the number of strict priority arbitration slots between
1915 * two round-robin arbitration slots to avoid starvation. A value of 0 means
1916 * no strict priority cycles - the strict priority with anti-starvation
1917 * arbiter becomes a round-robin arbiter. */
1918 #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
1919 /* [RW 15] Specify the client number to be assigned to each priority of the
1920 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
1921 * are for priority 0 client; bits [14:12] are for priority 4 client. The
1922 * clients are assigned the following IDs: 0-management; 1-debug traffic
1923 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
1924 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
1925 * for management at priority 0; debug traffic at priorities 1 and 2; COS0
1926 * traffic at priority 3; and COS1 traffic at priority 4. */
1927 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
1928 #define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
1929 #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460
1930 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
1931 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
1932 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
1933 * priority field is extracted from the outer-most VLAN in receive packet.
1934 * Only COS 0 and COS 1 are supported in E2. */
1935 #define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
1936 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
1937 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
1938 * than one bit may be set; allowing multiple priorities to be mapped to one
1939 * COS. */
1940 #define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
1941 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
1942 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
1943 * than one bit may be set; allowing multiple priorities to be mapped to one
1944 * COS. */
1945 #define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
1946 /* [RW 1] Pause enable for port0. This register may get 1 only when
1947 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
1948 port */
1949 #define NIG_REG_PAUSE_ENABLE_0 0x160c0
1950 #define NIG_REG_PAUSE_ENABLE_1 0x160c4
1951 /* [RW 1] Input enable for RX PBF LP IF */
1952 #define NIG_REG_PBF_LB_IN_EN 0x100b4
1953 /* [RW 1] Value of this register will be transmitted to port swap when
1954 ~nig_registers_strap_override.strap_override =1 */
1955 #define NIG_REG_PORT_SWAP 0x10394
1956 /* [RW 1] PPP enable for port0. This register may get 1 only when
1957 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
1958 * same port */
1959 #define NIG_REG_PPP_ENABLE_0 0x160b0
1960 #define NIG_REG_PPP_ENABLE_1 0x160b4
1961 /* [RW 1] output enable for RX parser descriptor IF */
1962 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
1963 /* [RW 1] Input enable for RX parser request IF */
1964 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
1965 /* [RW 5] control to serdes - CL45 DEVAD */
1966 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
1967 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
1968 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
1969 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
1970 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
1971 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
1972 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
1973 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1974 for port0 */
1975 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1976 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
1977 for port0 */
1978 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
1979 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1980 between 1024 and 1522 bytes for port0 */
1981 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
1982 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1983 between 1523 bytes and above for port0 */
1984 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
1985 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1986 for port1 */
1987 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
1988 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1989 between 1024 and 1522 bytes for port1 */
1990 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
1991 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1992 between 1523 bytes and above for port1 */
1993 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
1994 /* [WB_R 64] Rx statistics : User octets received for LP */
1995 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
1996 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
1997 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
1998 /* [RW 1] port swap mux selection. If this register equal to 0 then port
1999 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
2000 ort swap is equal to ~nig_registers_port_swap.port_swap */
2001 #define NIG_REG_STRAP_OVERRIDE 0x10398
2002 /* [RW 1] output enable for RX_XCM0 IF */
2003 #define NIG_REG_XCM0_OUT_EN 0x100f0
2004 /* [RW 1] output enable for RX_XCM1 IF */
2005 #define NIG_REG_XCM1_OUT_EN 0x100f4
2006 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
2007 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
2008 /* [RW 5] control to xgxs - CL45 DEVAD */
2009 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
2010 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2011 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
2012 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2013 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
2014 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
2015 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
2016 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
2017 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
2018 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
2019 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
2020 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
2021 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
2022 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
2023 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
2024 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
2025 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
2026 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
2027 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
2028 #define PBF_REG_COS0_UPPER_BOUND 0x15c05c
2029 /* [RW 31] The weight of COS0 in the ETS command arbiter. */
2030 #define PBF_REG_COS0_WEIGHT 0x15c054
2031 /* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2032 #define PBF_REG_COS1_UPPER_BOUND 0x15c060
2033 /* [RW 31] The weight of COS1 in the ETS command arbiter. */
2034 #define PBF_REG_COS1_WEIGHT 0x15c058
2035 /* [RW 1] Disable processing further tasks from port 0 (after ending the
2036 current task in process). */
2037 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
2038 /* [RW 1] Disable processing further tasks from port 1 (after ending the
2039 current task in process). */
2040 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
2041 /* [RW 1] Disable processing further tasks from port 4 (after ending the
2042 current task in process). */
2043 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
2044 #define PBF_REG_DISABLE_PF 0x1402e8
2045 /* [RW 1] Indicates that ETS is performed between the COSes in the command
2046 * arbiter. If reset strict priority w/ anti-starvation will be performed
2047 * w/o WFQ. */
2048 #define PBF_REG_ETS_ENABLED 0x15c050
2049 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2050 * Ethernet header. */
2051 #define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
2052 /* [RW 1] Indicates which COS is conncted to the highest priority in the
2053 * command arbiter. */
2054 #define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
2055 #define PBF_REG_IF_ENABLE_REG 0x140044
2056 /* [RW 1] Init bit. When set the initial credits are copied to the credit
2057 registers (except the port credits). Should be set and then reset after
2058 the configuration of the block has ended. */
2059 #define PBF_REG_INIT 0x140000
2060 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2061 copied to the credit register. Should be set and then reset after the
2062 configuration of the port has ended. */
2063 #define PBF_REG_INIT_P0 0x140004
2064 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
2065 copied to the credit register. Should be set and then reset after the
2066 configuration of the port has ended. */
2067 #define PBF_REG_INIT_P1 0x140008
2068 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
2069 copied to the credit register. Should be set and then reset after the
2070 configuration of the port has ended. */
2071 #define PBF_REG_INIT_P4 0x14000c
2072 /* [RW 1] Enable for mac interface 0. */
2073 #define PBF_REG_MAC_IF0_ENABLE 0x140030
2074 /* [RW 1] Enable for mac interface 1. */
2075 #define PBF_REG_MAC_IF1_ENABLE 0x140034
2076 /* [RW 1] Enable for the loopback interface. */
2077 #define PBF_REG_MAC_LB_ENABLE 0x140040
2078 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2079 #define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
2080 /* [RW 16] The number of strict priority arbitration slots between 2 RR
2081 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
2082 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2083 #define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
2084 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2085 not suppoterd. */
2086 #define PBF_REG_P0_ARB_THRSH 0x1400e4
2087 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
2088 #define PBF_REG_P0_CREDIT 0x140200
2089 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2090 lines. */
2091 #define PBF_REG_P0_INIT_CRD 0x1400d0
2092 /* [RW 1] Indication that pause is enabled for port 0. */
2093 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
2094 /* [R 8] Number of tasks in port 0 task queue. */
2095 #define PBF_REG_P0_TASK_CNT 0x140204
2096 /* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
2097 #define PBF_REG_P1_CREDIT 0x140208
2098 /* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte
2099 lines. */
2100 #define PBF_REG_P1_INIT_CRD 0x1400d4
2101 /* [R 8] Number of tasks in port 1 task queue. */
2102 #define PBF_REG_P1_TASK_CNT 0x14020c
2103 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
2104 #define PBF_REG_P4_CREDIT 0x140210
2105 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2106 lines. */
2107 #define PBF_REG_P4_INIT_CRD 0x1400e0
2108 /* [R 8] Number of tasks in port 4 task queue. */
2109 #define PBF_REG_P4_TASK_CNT 0x140214
2110 /* [RW 5] Interrupt mask register #0 read/write */
2111 #define PBF_REG_PBF_INT_MASK 0x1401d4
2112 /* [R 5] Interrupt register #0 read */
2113 #define PBF_REG_PBF_INT_STS 0x1401c8
2114 /* [RW 20] Parity mask register #0 read/write */
2115 #define PBF_REG_PBF_PRTY_MASK 0x1401e4
2116 /* [RC 20] Parity register #0 read clear */
2117 #define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
2118 #define PB_REG_CONTROL 0
2119 /* [RW 2] Interrupt mask register #0 read/write */
2120 #define PB_REG_PB_INT_MASK 0x28
2121 /* [R 2] Interrupt register #0 read */
2122 #define PB_REG_PB_INT_STS 0x1c
2123 /* [RW 4] Parity mask register #0 read/write */
2124 #define PB_REG_PB_PRTY_MASK 0x38
2125 /* [R 4] Parity register #0 read */
2126 #define PB_REG_PB_PRTY_STS 0x2c
2127 /* [RC 4] Parity register #0 read clear */
2128 #define PB_REG_PB_PRTY_STS_CLR 0x30
2129 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2130 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
2131 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
2132 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
2133 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
2134 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
2135 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
2136 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
2137 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
2138 /* [R 8] Config space A attention dirty bits. Each bit indicates that the
2139 * corresponding PF generates config space A attention. Set by PXP. Reset by
2140 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
2141 * from both paths. */
2142 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
2143 /* [R 8] Config space B attention dirty bits. Each bit indicates that the
2144 * corresponding PF generates config space B attention. Set by PXP. Reset by
2145 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
2146 * from both paths. */
2147 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
2148 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2149 * - enable. */
2150 #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194
2151 /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
2152 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
2153 #define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c
2154 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
2155 * - enable. */
2156 #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c
2157 /* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
2158 #define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100
2159 /* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
2160 #define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108
2161 /* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
2162 #define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110
2163 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2164 #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac
2165 /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
2166 * that the FLR register of the corresponding PF was set. Set by PXP. Reset
2167 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
2168 * from both paths. */
2169 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
2170 /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
2171 * to a bit in this register in order to clear the corresponding bit in
2172 * flr_request_pf_7_0 register. Note: register contains bits from both
2173 * paths. */
2174 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
2175 /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
2176 * indicates that the FLR register of the corresponding VF was set. Set by
2177 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
2178 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
2179 /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
2180 * indicates that the FLR register of the corresponding VF was set. Set by
2181 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
2182 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
2183 /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
2184 * indicates that the FLR register of the corresponding VF was set. Set by
2185 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
2186 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
2187 /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
2188 * indicates that the FLR register of the corresponding VF was set. Set by
2189 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
2190 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
2191 /* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
2192 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
2193 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
2194 * arrived with a correctable error. Bit 3 - Configuration RW arrived with
2195 * an uncorrectable error. Bit 4 - Completion with Configuration Request
2196 * Retry Status. Bit 5 - Expansion ROM access received with a write request.
2197 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
2198 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
2199 * and pcie_rx_last not asserted. */
2200 #define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
2201 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
2202 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
2203 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434
2204 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
2205 /* [R 9] Interrupt register #0 read */
2206 #define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
2207 /* [RC 9] Interrupt register #0 read clear */
2208 #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
2209 /* [R 2] Parity register #0 read */
2210 #define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
2211 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
2212 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
2213 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
2214 * completer abort. 3 - Illegal value for this field. [12] valid - indicates
2215 * if there was a completion error since the last time this register was
2216 * cleared. */
2217 #define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
2218 /* [R 18] Details of first ATS Translation Completion request received with
2219 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
2220 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
2221 * unsupported request. 2 - completer abort. 3 - Illegal value for this
2222 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
2223 * completion error since the last time this register was cleared. */
2224 #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
2225 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
2226 * a bit in this register in order to clear the corresponding bit in
2227 * shadow_bme_pf_7_0 register. MCP should never use this unless a
2228 * work-around is needed. Note: register contains bits from both paths. */
2229 #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
2230 /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
2231 * VF enable register of the corresponding PF is written to 0 and was
2232 * previously 1. Set by PXP. Reset by MCP writing 1 to
2233 * sr_iov_disabled_request_clr. Note: register contains bits from both
2234 * paths. */
2235 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
2236 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
2237 * completion did not return yet. 1 - tag is unused. Same functionality as
2238 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
2239 #define PGLUE_B_REG_TAGS_63_32 0x9244
2240 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
2241 * - enable. */
2242 #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170
2243 /* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
2244 #define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4
2245 /* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
2246 #define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc
2247 /* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
2248 #define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4
2249 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2250 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0
2251 /* [R 32] Address [31:0] of first read request not submitted due to error */
2252 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
2253 /* [R 32] Address [63:32] of first read request not submitted due to error */
2254 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
2255 /* [R 31] Details of first read request not submitted due to error. [4:0]
2256 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
2257 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
2258 * VFID. */
2259 #define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
2260 /* [R 26] Details of first read request not submitted due to error. [15:0]
2261 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2262 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2263 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2264 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2265 * indicates if there was a request not submitted due to error since the
2266 * last time this register was cleared. */
2267 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
2268 /* [R 32] Address [31:0] of first write request not submitted due to error */
2269 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
2270 /* [R 32] Address [63:32] of first write request not submitted due to error */
2271 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
2272 /* [R 31] Details of first write request not submitted due to error. [4:0]
2273 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
2274 * - VFID. */
2275 #define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
2276 /* [R 26] Details of first write request not submitted due to error. [15:0]
2277 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2278 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2279 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2280 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2281 * indicates if there was a request not submitted due to error since the
2282 * last time this register was cleared. */
2283 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
2284 /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
2285 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
2286 * value (Byte resolution address). */
2287 #define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128
2288 #define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c
2289 #define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130
2290 #define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134
2291 #define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138
2292 #define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c
2293 #define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140
2294 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
2295 * - enable. */
2296 #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c
2297 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
2298 * - enable. */
2299 #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180
2300 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
2301 * - enable. */
2302 #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184
2303 /* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
2304 #define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8
2305 /* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
2306 #define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0
2307 /* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
2308 #define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8
2309 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2310 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4
2311 /* [R 26] Details of first target VF request accessing VF GRC space that
2312 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
2313 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
2314 * request accessing VF GRC space that failed permission check since the
2315 * last time this register was cleared. Permission checks are: function
2316 * permission; R/W permission; address range permission. */
2317 #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
2318 /* [R 31] Details of first target VF request with length violation (too many
2319 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
2320 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
2321 * valid - indicates if there was a request with length violation since the
2322 * last time this register was cleared. Length violations: length of more
2323 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
2324 * length is more than 1 DW. */
2325 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
2326 /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
2327 * that there was a completion with uncorrectable error for the
2328 * corresponding PF. Set by PXP. Reset by MCP writing 1 to
2329 * was_error_pf_7_0_clr. */
2330 #define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
2331 /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
2332 * to a bit in this register in order to clear the corresponding bit in
2333 * flr_request_pf_7_0 register. */
2334 #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
2335 /* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
2336 * indicates that there was a completion with uncorrectable error for the
2337 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2338 * was_error_vf_127_96_clr. */
2339 #define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
2340 /* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
2341 * writes 1 to a bit in this register in order to clear the corresponding
2342 * bit in was_error_vf_127_96 register. */
2343 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
2344 /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
2345 * indicates that there was a completion with uncorrectable error for the
2346 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2347 * was_error_vf_31_0_clr. */
2348 #define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
2349 /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
2350 * 1 to a bit in this register in order to clear the corresponding bit in
2351 * was_error_vf_31_0 register. */
2352 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
2353 /* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
2354 * indicates that there was a completion with uncorrectable error for the
2355 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2356 * was_error_vf_63_32_clr. */
2357 #define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
2358 /* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
2359 * 1 to a bit in this register in order to clear the corresponding bit in
2360 * was_error_vf_63_32 register. */
2361 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
2362 /* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
2363 * indicates that there was a completion with uncorrectable error for the
2364 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2365 * was_error_vf_95_64_clr. */
2366 #define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
2367 /* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
2368 * 1 to a bit in this register in order to clear the corresponding bit in
2369 * was_error_vf_95_64 register. */
2370 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
2371 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
2372 * - enable. */
2373 #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188
2374 /* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
2375 #define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec
2376 /* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
2377 #define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4
2378 /* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
2379 #define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc
2380 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2381 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8
2382 #define PRS_REG_A_PRSU_20 0x40134
2383 /* [R 8] debug only: CFC load request current credit. Transaction based. */
2384 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
2385 /* [R 8] debug only: CFC search request current credit. Transaction based. */
2386 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
2387 /* [RW 6] The initial credit for the search message to the CFC interface.
2388 Credit is transaction based. */
2389 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
2390 /* [RW 24] CID for port 0 if no match */
2391 #define PRS_REG_CID_PORT_0 0x400fc
2392 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2393 load response is reset and packet type is 0. Used in packet start message
2394 to TCM. */
2395 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
2396 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
2397 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
2398 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
2399 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
2400 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
2401 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2402 load response is set and packet type is 0. Used in packet start message
2403 to TCM. */
2404 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
2405 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
2406 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
2407 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
2408 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
2409 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
2410 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
2411 Used in packet start message to TCM. */
2412 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
2413 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
2414 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
2415 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
2416 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
2417 message to TCM. */
2418 #define PRS_REG_CM_HDR_TYPE_0 0x40078
2419 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
2420 #define PRS_REG_CM_HDR_TYPE_2 0x40080
2421 #define PRS_REG_CM_HDR_TYPE_3 0x40084
2422 #define PRS_REG_CM_HDR_TYPE_4 0x40088
2423 /* [RW 32] The CM header in case there was not a match on the connection */
2424 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
2425 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
2426 #define PRS_REG_E1HOV_MODE 0x401c8
2427 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
2428 start message to TCM. */
2429 #define PRS_REG_EVENT_ID_1 0x40054
2430 #define PRS_REG_EVENT_ID_2 0x40058
2431 #define PRS_REG_EVENT_ID_3 0x4005c
2432 /* [RW 16] The Ethernet type value for FCoE */
2433 #define PRS_REG_FCOE_TYPE 0x401d0
2434 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
2435 load request message. */
2436 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
2437 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
2438 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
2439 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
2440 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
2441 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
2442 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
2443 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
2444 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2445 * Ethernet header. */
2446 #define PRS_REG_HDRS_AFTER_BASIC 0x40238
2447 /* [RW 4] The increment value to send in the CFC load request message */
2448 #define PRS_REG_INC_VALUE 0x40048
2449 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2450 #define PRS_REG_MUST_HAVE_HDRS 0x40254
2451 #define PRS_REG_NIC_MODE 0x40138
2452 /* [RW 8] The 8-bit event ID for cases where there is no match on the
2453 connection. Used in packet start message to TCM. */
2454 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
2455 /* [ST 24] The number of input CFC flush packets */
2456 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
2457 /* [ST 32] The number of cycles the Parser halted its operation since it
2458 could not allocate the next serial number */
2459 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
2460 /* [ST 24] The number of input packets */
2461 #define PRS_REG_NUM_OF_PACKETS 0x40124
2462 /* [ST 24] The number of input transparent flush packets */
2463 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
2464 /* [RW 8] Context region for received Ethernet packet with a match and
2465 packet type 0. Used in CFC load request message */
2466 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
2467 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
2468 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
2469 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
2470 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
2471 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
2472 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
2473 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
2474 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
2475 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
2476 /* [R 2] debug only: Number of pending requests for header parsing. */
2477 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
2478 /* [R 1] Interrupt register #0 read */
2479 #define PRS_REG_PRS_INT_STS 0x40188
2480 /* [RW 8] Parity mask register #0 read/write */
2481 #define PRS_REG_PRS_PRTY_MASK 0x401a4
2482 /* [R 8] Parity register #0 read */
2483 #define PRS_REG_PRS_PRTY_STS 0x40198
2484 /* [RC 8] Parity register #0 read clear */
2485 #define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
2486 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
2487 request message */
2488 #define PRS_REG_PURE_REGIONS 0x40024
2489 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
2490 serail number was released by SDM but cannot be used because a previous
2491 serial number was not released. */
2492 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
2493 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
2494 serail number was released by SDM but cannot be used because a previous
2495 serial number was not released. */
2496 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
2497 /* [R 4] debug only: SRC current credit. Transaction based. */
2498 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
2499 /* [R 8] debug only: TCM current credit. Cycle based. */
2500 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
2501 /* [R 8] debug only: TSDM current credit. Transaction based. */
2502 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
2503 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
2504 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
2505 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
2506 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
2507 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
2508 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
2509 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
2510 /* [R 6] Debug only: Number of used entries in the data FIFO */
2511 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
2512 /* [R 7] Debug only: Number of used entries in the header FIFO */
2513 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
2514 #define PXP2_REG_PGL_ADDR_88_F0 0x120534
2515 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538
2516 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c
2517 #define PXP2_REG_PGL_ADDR_94_F0 0x120540
2518 #define PXP2_REG_PGL_CONTROL0 0x120490
2519 #define PXP2_REG_PGL_CONTROL1 0x120514
2520 #define PXP2_REG_PGL_DEBUG 0x120520
2521 /* [RW 32] third dword data of expansion rom request. this register is
2522 special. reading from it provides a vector outstanding read requests. if
2523 a bit is zero it means that a read request on the corresponding tag did
2524 not finish yet (not all completions have arrived for it) */
2525 #define PXP2_REG_PGL_EXP_ROM2 0x120808
2526 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
2527 its[15:0]-address */
2528 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
2529 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
2530 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
2531 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
2532 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
2533 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
2534 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
2535 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
2536 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
2537 its[15:0]-address */
2538 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
2539 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
2540 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
2541 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
2542 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
2543 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
2544 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
2545 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
2546 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
2547 its[15:0]-address */
2548 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
2549 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
2550 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
2551 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
2552 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
2553 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
2554 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
2555 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
2556 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
2557 its[15:0]-address */
2558 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
2559 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
2560 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
2561 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
2562 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
2563 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
2564 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
2565 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
2566 /* [RW 3] this field allows one function to pretend being another function
2567 when accessing any BAR mapped resource within the device. the value of
2568 the field is the number of the function that will be accessed
2569 effectively. after software write to this bit it must read it in order to
2570 know that the new value is updated */
2571 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
2572 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
2573 #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
2574 #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
2575 #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
2576 #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
2577 #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
2578 #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
2579 /* [R 1] this bit indicates that a read request was blocked because of
2580 bus_master_en was deasserted */
2581 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
2582 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
2583 /* [R 18] debug only */
2584 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
2585 /* [R 1] this bit indicates that a write request was blocked because of
2586 bus_master_en was deasserted */
2587 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
2588 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
2589 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2590 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2591 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
2592 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2593 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
2594 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
2595 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
2596 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
2597 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
2598 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
2599 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
2600 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2601 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2602 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
2603 #define PXP2_REG_PSWRQ_BW_L28 0x120318
2604 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
2605 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
2606 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
2607 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
2608 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
2609 #define PXP2_REG_PSWRQ_BW_RD 0x120324
2610 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
2611 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2612 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
2613 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
2614 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2615 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
2616 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
2617 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
2618 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
2619 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
2620 #define PXP2_REG_PSWRQ_BW_WR 0x120328
2621 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
2622 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
2623 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
2624 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
2625 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
2626 /* [RW 32] Interrupt mask register #0 read/write */
2627 #define PXP2_REG_PXP2_INT_MASK_0 0x120578
2628 /* [R 32] Interrupt register #0 read */
2629 #define PXP2_REG_PXP2_INT_STS_0 0x12056c
2630 #define PXP2_REG_PXP2_INT_STS_1 0x120608
2631 /* [RC 32] Interrupt register #0 read clear */
2632 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
2633 /* [RW 32] Parity mask register #0 read/write */
2634 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
2635 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
2636 /* [R 32] Parity register #0 read */
2637 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
2638 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
2639 /* [RC 32] Parity register #0 read clear */
2640 #define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
2641 #define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
2642 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
2643 indication about backpressure) */
2644 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
2645 /* [R 8] Debug only: The blocks counter - number of unused block ids */
2646 #define PXP2_REG_RD_BLK_CNT 0x120418
2647 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
2648 Must be bigger than 6. Normally should not be changed. */
2649 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
2650 /* [RW 2] CDU byte swapping mode configuration for master read requests */
2651 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
2652 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
2653 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
2654 /* [R 1] PSWRD internal memories initialization is done */
2655 #define PXP2_REG_RD_INIT_DONE 0x120370
2656 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2657 allocated for vq10 */
2658 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
2659 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2660 allocated for vq11 */
2661 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
2662 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2663 allocated for vq17 */
2664 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
2665 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2666 allocated for vq18 */
2667 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
2668 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2669 allocated for vq19 */
2670 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
2671 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2672 allocated for vq22 */
2673 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
2674 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2675 allocated for vq25 */
2676 #define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
2677 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2678 allocated for vq6 */
2679 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
2680 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2681 allocated for vq9 */
2682 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
2683 /* [RW 2] PBF byte swapping mode configuration for master read requests */
2684 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
2685 /* [R 1] Debug only: Indication if delivery ports are idle */
2686 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
2687 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
2688 /* [RW 2] QM byte swapping mode configuration for master read requests */
2689 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
2690 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
2691 #define PXP2_REG_RD_SR_CNT 0x120414
2692 /* [RW 2] SRC byte swapping mode configuration for master read requests */
2693 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
2694 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
2695 be bigger than 1. Normally should not be changed. */
2696 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
2697 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
2698 #define PXP2_REG_RD_START_INIT 0x12036c
2699 /* [RW 2] TM byte swapping mode configuration for master read requests */
2700 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
2701 /* [RW 10] Bandwidth addition to VQ0 write requests */
2702 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
2703 /* [RW 10] Bandwidth addition to VQ12 read requests */
2704 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
2705 /* [RW 10] Bandwidth addition to VQ13 read requests */
2706 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
2707 /* [RW 10] Bandwidth addition to VQ14 read requests */
2708 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
2709 /* [RW 10] Bandwidth addition to VQ15 read requests */
2710 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
2711 /* [RW 10] Bandwidth addition to VQ16 read requests */
2712 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
2713 /* [RW 10] Bandwidth addition to VQ17 read requests */
2714 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
2715 /* [RW 10] Bandwidth addition to VQ18 read requests */
2716 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
2717 /* [RW 10] Bandwidth addition to VQ19 read requests */
2718 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
2719 /* [RW 10] Bandwidth addition to VQ20 read requests */
2720 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
2721 /* [RW 10] Bandwidth addition to VQ22 read requests */
2722 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
2723 /* [RW 10] Bandwidth addition to VQ23 read requests */
2724 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
2725 /* [RW 10] Bandwidth addition to VQ24 read requests */
2726 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
2727 /* [RW 10] Bandwidth addition to VQ25 read requests */
2728 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
2729 /* [RW 10] Bandwidth addition to VQ26 read requests */
2730 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
2731 /* [RW 10] Bandwidth addition to VQ27 read requests */
2732 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
2733 /* [RW 10] Bandwidth addition to VQ4 read requests */
2734 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
2735 /* [RW 10] Bandwidth addition to VQ5 read requests */
2736 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
2737 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
2738 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
2739 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
2740 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
2741 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
2742 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
2743 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
2744 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
2745 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
2746 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
2747 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
2748 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
2749 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
2750 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
2751 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
2752 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
2753 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
2754 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
2755 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
2756 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
2757 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
2758 #define PXP2_REG_RQ_BW_RD_L22 0x120300
2759 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
2760 #define PXP2_REG_RQ_BW_RD_L23 0x120304
2761 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
2762 #define PXP2_REG_RQ_BW_RD_L24 0x120308
2763 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
2764 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
2765 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
2766 #define PXP2_REG_RQ_BW_RD_L26 0x120310
2767 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
2768 #define PXP2_REG_RQ_BW_RD_L27 0x120314
2769 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
2770 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
2771 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
2772 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
2773 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
2774 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
2775 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
2776 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
2777 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
2778 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
2779 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
2780 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
2781 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
2782 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
2783 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
2784 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
2785 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
2786 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
2787 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
2788 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
2789 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
2790 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
2791 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
2792 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
2793 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
2794 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
2795 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
2796 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
2797 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
2798 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
2799 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
2800 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
2801 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
2802 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
2803 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
2804 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
2805 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
2806 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
2807 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
2808 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
2809 /* [RW 10] Bandwidth addition to VQ29 write requests */
2810 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
2811 /* [RW 10] Bandwidth addition to VQ30 write requests */
2812 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
2813 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
2814 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
2815 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
2816 #define PXP2_REG_RQ_BW_WR_L30 0x120320
2817 /* [RW 7] Bandwidth upper bound for VQ29 */
2818 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
2819 /* [RW 7] Bandwidth upper bound for VQ30 */
2820 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
2821 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
2822 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
2823 /* [RW 2] Endian mode for cdu */
2824 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
2825 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
2826 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
2827 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
2828 -128k */
2829 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
2830 /* [R 1] 1' indicates that the requester has finished its internal
2831 configuration */
2832 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
2833 /* [RW 2] Endian mode for debug */
2834 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
2835 /* [RW 1] When '1'; requests will enter input buffers but wont get out
2836 towards the glue */
2837 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
2838 /* [RW 4] Determines alignment of write SRs when a request is split into
2839 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
2840 * aligned. 4 - 512B aligned. */
2841 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
2842 /* [RW 4] Determines alignment of read SRs when a request is split into
2843 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
2844 * aligned. 4 - 512B aligned. */
2845 #define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
2846 /* [RW 1] when set the new alignment method (E2) will be applied; when reset
2847 * the original alignment method (E1 E1H) will be applied */
2848 #define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
2849 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
2850 be asserted */
2851 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c
2852 /* [RW 2] Endian mode for hc */
2853 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
2854 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
2855 compatibility needs; Note that different registers are used per mode */
2856 #define PXP2_REG_RQ_ILT_MODE 0x1205b4
2857 /* [WB 53] Onchip address table */
2858 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
2859 /* [WB 53] Onchip address table - B0 */
2860 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
2861 /* [RW 13] Pending read limiter threshold; in Dwords */
2862 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
2863 /* [RW 2] Endian mode for qm */
2864 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
2865 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
2866 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638
2867 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2868 -128k */
2869 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
2870 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
2871 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
2872 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
2873 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2874 #define PXP2_REG_RQ_RD_MBS0 0x120160
2875 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
2876 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2877 #define PXP2_REG_RQ_RD_MBS1 0x120168
2878 /* [RW 2] Endian mode for src */
2879 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
2880 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
2881 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
2882 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
2883 -128k */
2884 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
2885 /* [RW 2] Endian mode for tm */
2886 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
2887 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
2888 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648
2889 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
2890 -128k */
2891 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
2892 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
2893 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
2894 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
2895 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
2896 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
2897 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
2898 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
2899 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
2900 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
2901 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
2902 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
2903 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
2904 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
2905 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
2906 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
2907 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
2908 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
2909 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
2910 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
2911 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
2912 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
2913 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
2914 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
2915 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
2916 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
2917 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
2918 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
2919 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
2920 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
2921 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
2922 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
2923 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
2924 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
2925 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
2926 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
2927 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
2928 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
2929 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
2930 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
2931 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
2932 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
2933 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
2934 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
2935 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
2936 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
2937 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
2938 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
2939 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
2940 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
2941 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
2942 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
2943 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
2944 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
2945 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
2946 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
2947 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
2948 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
2949 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
2950 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
2951 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
2952 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
2953 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
2954 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
2955 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
2956 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
2957 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
2958 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
2959 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
2960 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
2961 001:256B; 010: 512B; */
2962 #define PXP2_REG_RQ_WR_MBS0 0x12015c
2963 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
2964 001:256B; 010: 512B; */
2965 #define PXP2_REG_RQ_WR_MBS1 0x120164
2966 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2967 buffer reaches this number has_payload will be asserted */
2968 #define PXP2_REG_WR_CDU_MPS 0x1205f0
2969 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2970 buffer reaches this number has_payload will be asserted */
2971 #define PXP2_REG_WR_CSDM_MPS 0x1205d0
2972 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2973 buffer reaches this number has_payload will be asserted */
2974 #define PXP2_REG_WR_DBG_MPS 0x1205e8
2975 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2976 buffer reaches this number has_payload will be asserted */
2977 #define PXP2_REG_WR_DMAE_MPS 0x1205ec
2978 /* [RW 10] if Number of entries in dmae fifo will be higher than this
2979 threshold then has_payload indication will be asserted; the default value
2980 should be equal to > write MBS size! */
2981 #define PXP2_REG_WR_DMAE_TH 0x120368
2982 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2983 buffer reaches this number has_payload will be asserted */
2984 #define PXP2_REG_WR_HC_MPS 0x1205c8
2985 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2986 buffer reaches this number has_payload will be asserted */
2987 #define PXP2_REG_WR_QM_MPS 0x1205dc
2988 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
2989 #define PXP2_REG_WR_REV_MODE 0x120670
2990 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2991 buffer reaches this number has_payload will be asserted */
2992 #define PXP2_REG_WR_SRC_MPS 0x1205e4
2993 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2994 buffer reaches this number has_payload will be asserted */
2995 #define PXP2_REG_WR_TM_MPS 0x1205e0
2996 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2997 buffer reaches this number has_payload will be asserted */
2998 #define PXP2_REG_WR_TSDM_MPS 0x1205d4
2999 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this
3000 threshold then has_payload indication will be asserted; the default value
3001 should be equal to > write MBS size! */
3002 #define PXP2_REG_WR_USDMDP_TH 0x120348
3003 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3004 buffer reaches this number has_payload will be asserted */
3005 #define PXP2_REG_WR_USDM_MPS 0x1205cc
3006 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3007 buffer reaches this number has_payload will be asserted */
3008 #define PXP2_REG_WR_XSDM_MPS 0x1205d8
3009 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
3010 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
3011 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
3012 this client is waiting for the arbiter. */
3013 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
3014 /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
3015 block. Should be used for close the gates. */
3016 #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
3017 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
3018 should update according to 'hst_discard_doorbells' register when the state
3019 machine is idle */
3020 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
3021 /* [RW 1] When 1; new internal writes arriving to the block are discarded.
3022 Should be used for close the gates. */
3023 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
3024 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
3025 means this PSWHST is discarding inputs from this client. Each bit should
3026 update according to 'hst_discard_internal_writes' register when the state
3027 machine is idle. */
3028 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
3029 /* [WB 160] Used for initialization of the inbound interrupts memory */
3030 #define PXP_REG_HST_INBOUND_INT 0x103800
3031 /* [RW 32] Interrupt mask register #0 read/write */
3032 #define PXP_REG_PXP_INT_MASK_0 0x103074
3033 #define PXP_REG_PXP_INT_MASK_1 0x103084
3034 /* [R 32] Interrupt register #0 read */
3035 #define PXP_REG_PXP_INT_STS_0 0x103068
3036 #define PXP_REG_PXP_INT_STS_1 0x103078
3037 /* [RC 32] Interrupt register #0 read clear */
3038 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
3039 #define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
3040 /* [RW 27] Parity mask register #0 read/write */
3041 #define PXP_REG_PXP_PRTY_MASK 0x103094
3042 /* [R 26] Parity register #0 read */
3043 #define PXP_REG_PXP_PRTY_STS 0x103088
3044 /* [RC 27] Parity register #0 read clear */
3045 #define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
3046 /* [RW 4] The activity counter initial increment value sent in the load
3047 request */
3048 #define QM_REG_ACTCTRINITVAL_0 0x168040
3049 #define QM_REG_ACTCTRINITVAL_1 0x168044
3050 #define QM_REG_ACTCTRINITVAL_2 0x168048
3051 #define QM_REG_ACTCTRINITVAL_3 0x16804c
3052 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3053 index I represents the physical queue number. The 12 lsbs are ignore and
3054 considered zero so practically there are only 20 bits in this register;
3055 queues 63-0 */
3056 #define QM_REG_BASEADDR 0x168900
3057 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3058 index I represents the physical queue number. The 12 lsbs are ignore and
3059 considered zero so practically there are only 20 bits in this register;
3060 queues 127-64 */
3061 #define QM_REG_BASEADDR_EXT_A 0x16e100
3062 /* [RW 16] The byte credit cost for each task. This value is for both ports */
3063 #define QM_REG_BYTECRDCOST 0x168234
3064 /* [RW 16] The initial byte credit value for both ports. */
3065 #define QM_REG_BYTECRDINITVAL 0x168238
3066 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3067 queue uses port 0 else it uses port 1; queues 31-0 */
3068 #define QM_REG_BYTECRDPORT_LSB 0x168228
3069 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3070 queue uses port 0 else it uses port 1; queues 95-64 */
3071 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
3072 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3073 queue uses port 0 else it uses port 1; queues 63-32 */
3074 #define QM_REG_BYTECRDPORT_MSB 0x168224
3075 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3076 queue uses port 0 else it uses port 1; queues 127-96 */
3077 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
3078 /* [RW 16] The byte credit value that if above the QM is considered almost
3079 full */
3080 #define QM_REG_BYTECREDITAFULLTHR 0x168094
3081 /* [RW 4] The initial credit for interface */
3082 #define QM_REG_CMINITCRD_0 0x1680cc
3083 #define QM_REG_CMINITCRD_1 0x1680d0
3084 #define QM_REG_CMINITCRD_2 0x1680d4
3085 #define QM_REG_CMINITCRD_3 0x1680d8
3086 #define QM_REG_CMINITCRD_4 0x1680dc
3087 #define QM_REG_CMINITCRD_5 0x1680e0
3088 #define QM_REG_CMINITCRD_6 0x1680e4
3089 #define QM_REG_CMINITCRD_7 0x1680e8
3090 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
3091 is masked */
3092 #define QM_REG_CMINTEN 0x1680ec
3093 /* [RW 12] A bit vector which indicates which one of the queues are tied to
3094 interface 0 */
3095 #define QM_REG_CMINTVOQMASK_0 0x1681f4
3096 #define QM_REG_CMINTVOQMASK_1 0x1681f8
3097 #define QM_REG_CMINTVOQMASK_2 0x1681fc
3098 #define QM_REG_CMINTVOQMASK_3 0x168200
3099 #define QM_REG_CMINTVOQMASK_4 0x168204
3100 #define QM_REG_CMINTVOQMASK_5 0x168208
3101 #define QM_REG_CMINTVOQMASK_6 0x16820c
3102 #define QM_REG_CMINTVOQMASK_7 0x168210
3103 /* [RW 20] The number of connections divided by 16 which dictates the size
3104 of each queue which belongs to even function number. */
3105 #define QM_REG_CONNNUM_0 0x168020
3106 /* [R 6] Keep the fill level of the fifo from write client 4 */
3107 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
3108 /* [RW 8] The context regions sent in the CFC load request */
3109 #define QM_REG_CTXREG_0 0x168030
3110 #define QM_REG_CTXREG_1 0x168034
3111 #define QM_REG_CTXREG_2 0x168038
3112 #define QM_REG_CTXREG_3 0x16803c
3113 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
3114 bypass enable */
3115 #define QM_REG_ENBYPVOQMASK 0x16823c
3116 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3117 physical queue uses the byte credit; queues 31-0 */
3118 #define QM_REG_ENBYTECRD_LSB 0x168220
3119 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3120 physical queue uses the byte credit; queues 95-64 */
3121 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
3122 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3123 physical queue uses the byte credit; queues 63-32 */
3124 #define QM_REG_ENBYTECRD_MSB 0x16821c
3125 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3126 physical queue uses the byte credit; queues 127-96 */
3127 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
3128 /* [RW 4] If cleared then the secondary interface will not be served by the
3129 RR arbiter */
3130 #define QM_REG_ENSEC 0x1680f0
3131 /* [RW 32] NA */
3132 #define QM_REG_FUNCNUMSEL_LSB 0x168230
3133 /* [RW 32] NA */
3134 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
3135 /* [RW 32] A mask register to mask the Almost empty signals which will not
3136 be use for the almost empty indication to the HW block; queues 31:0 */
3137 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
3138 /* [RW 32] A mask register to mask the Almost empty signals which will not
3139 be use for the almost empty indication to the HW block; queues 95-64 */
3140 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
3141 /* [RW 32] A mask register to mask the Almost empty signals which will not
3142 be use for the almost empty indication to the HW block; queues 63:32 */
3143 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
3144 /* [RW 32] A mask register to mask the Almost empty signals which will not
3145 be use for the almost empty indication to the HW block; queues 127-96 */
3146 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
3147 /* [RW 4] The number of outstanding request to CFC */
3148 #define QM_REG_OUTLDREQ 0x168804
3149 /* [RC 1] A flag to indicate that overflow error occurred in one of the
3150 queues. */
3151 #define QM_REG_OVFERROR 0x16805c
3152 /* [RC 7] the Q where the overflow occurs */
3153 #define QM_REG_OVFQNUM 0x168058
3154 /* [R 16] Pause state for physical queues 15-0 */
3155 #define QM_REG_PAUSESTATE0 0x168410
3156 /* [R 16] Pause state for physical queues 31-16 */
3157 #define QM_REG_PAUSESTATE1 0x168414
3158 /* [R 16] Pause state for physical queues 47-32 */
3159 #define QM_REG_PAUSESTATE2 0x16e684
3160 /* [R 16] Pause state for physical queues 63-48 */
3161 #define QM_REG_PAUSESTATE3 0x16e688
3162 /* [R 16] Pause state for physical queues 79-64 */
3163 #define QM_REG_PAUSESTATE4 0x16e68c
3164 /* [R 16] Pause state for physical queues 95-80 */
3165 #define QM_REG_PAUSESTATE5 0x16e690
3166 /* [R 16] Pause state for physical queues 111-96 */
3167 #define QM_REG_PAUSESTATE6 0x16e694
3168 /* [R 16] Pause state for physical queues 127-112 */
3169 #define QM_REG_PAUSESTATE7 0x16e698
3170 /* [RW 2] The PCI attributes field used in the PCI request. */
3171 #define QM_REG_PCIREQAT 0x168054
3172 #define QM_REG_PF_EN 0x16e70c
3173 /* [R 16] The byte credit of port 0 */
3174 #define QM_REG_PORT0BYTECRD 0x168300
3175 /* [R 16] The byte credit of port 1 */
3176 #define QM_REG_PORT1BYTECRD 0x168304
3177 /* [RW 3] pci function number of queues 15-0 */
3178 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc
3179 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0
3180 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4
3181 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8
3182 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc
3183 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0
3184 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4
3185 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8
3186 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
3187 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3188 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3189 #define QM_REG_PTRTBL 0x168a00
3190 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
3191 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3192 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3193 #define QM_REG_PTRTBL_EXT_A 0x16e200
3194 /* [RW 2] Interrupt mask register #0 read/write */
3195 #define QM_REG_QM_INT_MASK 0x168444
3196 /* [R 2] Interrupt register #0 read */
3197 #define QM_REG_QM_INT_STS 0x168438
3198 /* [RW 12] Parity mask register #0 read/write */
3199 #define QM_REG_QM_PRTY_MASK 0x168454
3200 /* [R 12] Parity register #0 read */
3201 #define QM_REG_QM_PRTY_STS 0x168448
3202 /* [RC 12] Parity register #0 read clear */
3203 #define QM_REG_QM_PRTY_STS_CLR 0x16844c
3204 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
3205 #define QM_REG_QSTATUS_HIGH 0x16802c
3206 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
3207 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
3208 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
3209 #define QM_REG_QSTATUS_LOW 0x168028
3210 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */
3211 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
3212 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
3213 #define QM_REG_QTASKCTR_0 0x168308
3214 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
3215 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584
3216 /* [RW 4] Queue tied to VOQ */
3217 #define QM_REG_QVOQIDX_0 0x1680f4
3218 #define QM_REG_QVOQIDX_10 0x16811c
3219 #define QM_REG_QVOQIDX_100 0x16e49c
3220 #define QM_REG_QVOQIDX_101 0x16e4a0
3221 #define QM_REG_QVOQIDX_102 0x16e4a4
3222 #define QM_REG_QVOQIDX_103 0x16e4a8
3223 #define QM_REG_QVOQIDX_104 0x16e4ac
3224 #define QM_REG_QVOQIDX_105 0x16e4b0
3225 #define QM_REG_QVOQIDX_106 0x16e4b4
3226 #define QM_REG_QVOQIDX_107 0x16e4b8
3227 #define QM_REG_QVOQIDX_108 0x16e4bc
3228 #define QM_REG_QVOQIDX_109 0x16e4c0
3229 #define QM_REG_QVOQIDX_11 0x168120
3230 #define QM_REG_QVOQIDX_110 0x16e4c4
3231 #define QM_REG_QVOQIDX_111 0x16e4c8
3232 #define QM_REG_QVOQIDX_112 0x16e4cc
3233 #define QM_REG_QVOQIDX_113 0x16e4d0
3234 #define QM_REG_QVOQIDX_114 0x16e4d4
3235 #define QM_REG_QVOQIDX_115 0x16e4d8
3236 #define QM_REG_QVOQIDX_116 0x16e4dc
3237 #define QM_REG_QVOQIDX_117 0x16e4e0
3238 #define QM_REG_QVOQIDX_118 0x16e4e4
3239 #define QM_REG_QVOQIDX_119 0x16e4e8
3240 #define QM_REG_QVOQIDX_12 0x168124
3241 #define QM_REG_QVOQIDX_120 0x16e4ec
3242 #define QM_REG_QVOQIDX_121 0x16e4f0
3243 #define QM_REG_QVOQIDX_122 0x16e4f4
3244 #define QM_REG_QVOQIDX_123 0x16e4f8
3245 #define QM_REG_QVOQIDX_124 0x16e4fc
3246 #define QM_REG_QVOQIDX_125 0x16e500
3247 #define QM_REG_QVOQIDX_126 0x16e504
3248 #define QM_REG_QVOQIDX_127 0x16e508
3249 #define QM_REG_QVOQIDX_13 0x168128
3250 #define QM_REG_QVOQIDX_14 0x16812c
3251 #define QM_REG_QVOQIDX_15 0x168130
3252 #define QM_REG_QVOQIDX_16 0x168134
3253 #define QM_REG_QVOQIDX_17 0x168138
3254 #define QM_REG_QVOQIDX_21 0x168148
3255 #define QM_REG_QVOQIDX_22 0x16814c
3256 #define QM_REG_QVOQIDX_23 0x168150
3257 #define QM_REG_QVOQIDX_24 0x168154
3258 #define QM_REG_QVOQIDX_25 0x168158
3259 #define QM_REG_QVOQIDX_26 0x16815c
3260 #define QM_REG_QVOQIDX_27 0x168160
3261 #define QM_REG_QVOQIDX_28 0x168164
3262 #define QM_REG_QVOQIDX_29 0x168168
3263 #define QM_REG_QVOQIDX_30 0x16816c
3264 #define QM_REG_QVOQIDX_31 0x168170
3265 #define QM_REG_QVOQIDX_32 0x168174
3266 #define QM_REG_QVOQIDX_33 0x168178
3267 #define QM_REG_QVOQIDX_34 0x16817c
3268 #define QM_REG_QVOQIDX_35 0x168180
3269 #define QM_REG_QVOQIDX_36 0x168184
3270 #define QM_REG_QVOQIDX_37 0x168188
3271 #define QM_REG_QVOQIDX_38 0x16818c
3272 #define QM_REG_QVOQIDX_39 0x168190
3273 #define QM_REG_QVOQIDX_40 0x168194
3274 #define QM_REG_QVOQIDX_41 0x168198
3275 #define QM_REG_QVOQIDX_42 0x16819c
3276 #define QM_REG_QVOQIDX_43 0x1681a0
3277 #define QM_REG_QVOQIDX_44 0x1681a4
3278 #define QM_REG_QVOQIDX_45 0x1681a8
3279 #define QM_REG_QVOQIDX_46 0x1681ac
3280 #define QM_REG_QVOQIDX_47 0x1681b0
3281 #define QM_REG_QVOQIDX_48 0x1681b4
3282 #define QM_REG_QVOQIDX_49 0x1681b8
3283 #define QM_REG_QVOQIDX_5 0x168108
3284 #define QM_REG_QVOQIDX_50 0x1681bc
3285 #define QM_REG_QVOQIDX_51 0x1681c0
3286 #define QM_REG_QVOQIDX_52 0x1681c4
3287 #define QM_REG_QVOQIDX_53 0x1681c8
3288 #define QM_REG_QVOQIDX_54 0x1681cc
3289 #define QM_REG_QVOQIDX_55 0x1681d0
3290 #define QM_REG_QVOQIDX_56 0x1681d4
3291 #define QM_REG_QVOQIDX_57 0x1681d8
3292 #define QM_REG_QVOQIDX_58 0x1681dc
3293 #define QM_REG_QVOQIDX_59 0x1681e0
3294 #define QM_REG_QVOQIDX_6 0x16810c
3295 #define QM_REG_QVOQIDX_60 0x1681e4
3296 #define QM_REG_QVOQIDX_61 0x1681e8
3297 #define QM_REG_QVOQIDX_62 0x1681ec
3298 #define QM_REG_QVOQIDX_63 0x1681f0
3299 #define QM_REG_QVOQIDX_64 0x16e40c
3300 #define QM_REG_QVOQIDX_65 0x16e410
3301 #define QM_REG_QVOQIDX_69 0x16e420
3302 #define QM_REG_QVOQIDX_7 0x168110
3303 #define QM_REG_QVOQIDX_70 0x16e424
3304 #define QM_REG_QVOQIDX_71 0x16e428
3305 #define QM_REG_QVOQIDX_72 0x16e42c
3306 #define QM_REG_QVOQIDX_73 0x16e430
3307 #define QM_REG_QVOQIDX_74 0x16e434
3308 #define QM_REG_QVOQIDX_75 0x16e438
3309 #define QM_REG_QVOQIDX_76 0x16e43c
3310 #define QM_REG_QVOQIDX_77 0x16e440
3311 #define QM_REG_QVOQIDX_78 0x16e444
3312 #define QM_REG_QVOQIDX_79 0x16e448
3313 #define QM_REG_QVOQIDX_8 0x168114
3314 #define QM_REG_QVOQIDX_80 0x16e44c
3315 #define QM_REG_QVOQIDX_81 0x16e450
3316 #define QM_REG_QVOQIDX_85 0x16e460
3317 #define QM_REG_QVOQIDX_86 0x16e464
3318 #define QM_REG_QVOQIDX_87 0x16e468
3319 #define QM_REG_QVOQIDX_88 0x16e46c
3320 #define QM_REG_QVOQIDX_89 0x16e470
3321 #define QM_REG_QVOQIDX_9 0x168118
3322 #define QM_REG_QVOQIDX_90 0x16e474
3323 #define QM_REG_QVOQIDX_91 0x16e478
3324 #define QM_REG_QVOQIDX_92 0x16e47c
3325 #define QM_REG_QVOQIDX_93 0x16e480
3326 #define QM_REG_QVOQIDX_94 0x16e484
3327 #define QM_REG_QVOQIDX_95 0x16e488
3328 #define QM_REG_QVOQIDX_96 0x16e48c
3329 #define QM_REG_QVOQIDX_97 0x16e490
3330 #define QM_REG_QVOQIDX_98 0x16e494
3331 #define QM_REG_QVOQIDX_99 0x16e498
3332 /* [RW 1] Initialization bit command */
3333 #define QM_REG_SOFT_RESET 0x168428
3334 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
3335 #define QM_REG_TASKCRDCOST_0 0x16809c
3336 #define QM_REG_TASKCRDCOST_1 0x1680a0
3337 #define QM_REG_TASKCRDCOST_2 0x1680a4
3338 #define QM_REG_TASKCRDCOST_4 0x1680ac
3339 #define QM_REG_TASKCRDCOST_5 0x1680b0
3340 /* [R 6] Keep the fill level of the fifo from write client 3 */
3341 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
3342 /* [R 6] Keep the fill level of the fifo from write client 2 */
3343 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
3344 /* [RC 32] Credit update error register */
3345 #define QM_REG_VOQCRDERRREG 0x168408
3346 /* [R 16] The credit value for each VOQ */
3347 #define QM_REG_VOQCREDIT_0 0x1682d0
3348 #define QM_REG_VOQCREDIT_1 0x1682d4
3349 #define QM_REG_VOQCREDIT_4 0x1682e0
3350 /* [RW 16] The credit value that if above the QM is considered almost full */
3351 #define QM_REG_VOQCREDITAFULLTHR 0x168090
3352 /* [RW 16] The init and maximum credit for each VoQ */
3353 #define QM_REG_VOQINITCREDIT_0 0x168060
3354 #define QM_REG_VOQINITCREDIT_1 0x168064
3355 #define QM_REG_VOQINITCREDIT_2 0x168068
3356 #define QM_REG_VOQINITCREDIT_4 0x168070
3357 #define QM_REG_VOQINITCREDIT_5 0x168074
3358 /* [RW 1] The port of which VOQ belongs */
3359 #define QM_REG_VOQPORT_0 0x1682a0
3360 #define QM_REG_VOQPORT_1 0x1682a4
3361 #define QM_REG_VOQPORT_2 0x1682a8
3362 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3363 #define QM_REG_VOQQMASK_0_LSB 0x168240
3364 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3365 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
3366 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3367 #define QM_REG_VOQQMASK_0_MSB 0x168244
3368 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3369 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
3370 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3371 #define QM_REG_VOQQMASK_10_LSB 0x168290
3372 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3373 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
3374 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3375 #define QM_REG_VOQQMASK_10_MSB 0x168294
3376 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3377 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
3378 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3379 #define QM_REG_VOQQMASK_11_LSB 0x168298
3380 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3381 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
3382 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3383 #define QM_REG_VOQQMASK_11_MSB 0x16829c
3384 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3385 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
3386 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3387 #define QM_REG_VOQQMASK_1_LSB 0x168248
3388 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3389 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
3390 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3391 #define QM_REG_VOQQMASK_1_MSB 0x16824c
3392 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3393 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
3394 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3395 #define QM_REG_VOQQMASK_2_LSB 0x168250
3396 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3397 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
3398 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3399 #define QM_REG_VOQQMASK_2_MSB 0x168254
3400 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3401 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
3402 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3403 #define QM_REG_VOQQMASK_3_LSB 0x168258
3404 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3405 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
3406 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3407 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
3408 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3409 #define QM_REG_VOQQMASK_4_LSB 0x168260
3410 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3411 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
3412 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3413 #define QM_REG_VOQQMASK_4_MSB 0x168264
3414 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3415 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
3416 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3417 #define QM_REG_VOQQMASK_5_LSB 0x168268
3418 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3419 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
3420 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3421 #define QM_REG_VOQQMASK_5_MSB 0x16826c
3422 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3423 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
3424 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3425 #define QM_REG_VOQQMASK_6_LSB 0x168270
3426 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3427 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
3428 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3429 #define QM_REG_VOQQMASK_6_MSB 0x168274
3430 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3431 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
3432 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3433 #define QM_REG_VOQQMASK_7_LSB 0x168278
3434 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3435 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
3436 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3437 #define QM_REG_VOQQMASK_7_MSB 0x16827c
3438 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3439 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
3440 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3441 #define QM_REG_VOQQMASK_8_LSB 0x168280
3442 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3443 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
3444 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3445 #define QM_REG_VOQQMASK_8_MSB 0x168284
3446 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3447 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
3448 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3449 #define QM_REG_VOQQMASK_9_LSB 0x168288
3450 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3451 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
3452 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3453 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
3454 /* [RW 32] Wrr weights */
3455 #define QM_REG_WRRWEIGHTS_0 0x16880c
3456 #define QM_REG_WRRWEIGHTS_1 0x168810
3457 #define QM_REG_WRRWEIGHTS_10 0x168814
3458 #define QM_REG_WRRWEIGHTS_11 0x168818
3459 #define QM_REG_WRRWEIGHTS_12 0x16881c
3460 #define QM_REG_WRRWEIGHTS_13 0x168820
3461 #define QM_REG_WRRWEIGHTS_14 0x168824
3462 #define QM_REG_WRRWEIGHTS_15 0x168828
3463 #define QM_REG_WRRWEIGHTS_16 0x16e000
3464 #define QM_REG_WRRWEIGHTS_17 0x16e004
3465 #define QM_REG_WRRWEIGHTS_18 0x16e008
3466 #define QM_REG_WRRWEIGHTS_19 0x16e00c
3467 #define QM_REG_WRRWEIGHTS_2 0x16882c
3468 #define QM_REG_WRRWEIGHTS_20 0x16e010
3469 #define QM_REG_WRRWEIGHTS_21 0x16e014
3470 #define QM_REG_WRRWEIGHTS_22 0x16e018
3471 #define QM_REG_WRRWEIGHTS_23 0x16e01c
3472 #define QM_REG_WRRWEIGHTS_24 0x16e020
3473 #define QM_REG_WRRWEIGHTS_25 0x16e024
3474 #define QM_REG_WRRWEIGHTS_26 0x16e028
3475 #define QM_REG_WRRWEIGHTS_27 0x16e02c
3476 #define QM_REG_WRRWEIGHTS_28 0x16e030
3477 #define QM_REG_WRRWEIGHTS_29 0x16e034
3478 #define QM_REG_WRRWEIGHTS_3 0x168830
3479 #define QM_REG_WRRWEIGHTS_30 0x16e038
3480 #define QM_REG_WRRWEIGHTS_31 0x16e03c
3481 #define QM_REG_WRRWEIGHTS_4 0x168834
3482 #define QM_REG_WRRWEIGHTS_5 0x168838
3483 #define QM_REG_WRRWEIGHTS_6 0x16883c
3484 #define QM_REG_WRRWEIGHTS_7 0x168840
3485 #define QM_REG_WRRWEIGHTS_8 0x168844
3486 #define QM_REG_WRRWEIGHTS_9 0x168848
3487 /* [R 6] Keep the fill level of the fifo from write client 1 */
3488 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
3489 /* [W 1] reset to parity interrupt */
3490 #define SEM_FAST_REG_PARITY_RST 0x18840
3491 #define SRC_REG_COUNTFREE0 0x40500
3492 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3493 ports. If set the searcher support 8 functions. */
3494 #define SRC_REG_E1HMF_ENABLE 0x404cc
3495 #define SRC_REG_FIRSTFREE0 0x40510
3496 #define SRC_REG_KEYRSS0_0 0x40408
3497 #define SRC_REG_KEYRSS0_7 0x40424
3498 #define SRC_REG_KEYRSS1_9 0x40454
3499 #define SRC_REG_KEYSEARCH_0 0x40458
3500 #define SRC_REG_KEYSEARCH_1 0x4045c
3501 #define SRC_REG_KEYSEARCH_2 0x40460
3502 #define SRC_REG_KEYSEARCH_3 0x40464
3503 #define SRC_REG_KEYSEARCH_4 0x40468
3504 #define SRC_REG_KEYSEARCH_5 0x4046c
3505 #define SRC_REG_KEYSEARCH_6 0x40470
3506 #define SRC_REG_KEYSEARCH_7 0x40474
3507 #define SRC_REG_KEYSEARCH_8 0x40478
3508 #define SRC_REG_KEYSEARCH_9 0x4047c
3509 #define SRC_REG_LASTFREE0 0x40530
3510 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
3511 /* [RW 1] Reset internal state machines. */
3512 #define SRC_REG_SOFT_RST 0x4049c
3513 /* [R 3] Interrupt register #0 read */
3514 #define SRC_REG_SRC_INT_STS 0x404ac
3515 /* [RW 3] Parity mask register #0 read/write */
3516 #define SRC_REG_SRC_PRTY_MASK 0x404c8
3517 /* [R 3] Parity register #0 read */
3518 #define SRC_REG_SRC_PRTY_STS 0x404bc
3519 /* [RC 3] Parity register #0 read clear */
3520 #define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
3521 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
3522 #define TCM_REG_CAM_OCCUP 0x5017c
3523 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3524 disregarded; valid output is deasserted; all other signals are treated as
3525 usual; if 1 - normal activity. */
3526 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
3527 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3528 are disregarded; all other signals are treated as usual; if 1 - normal
3529 activity. */
3530 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
3531 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3532 disregarded; valid output is deasserted; all other signals are treated as
3533 usual; if 1 - normal activity. */
3534 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
3535 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3536 input is disregarded; all other signals are treated as usual; if 1 -
3537 normal activity. */
3538 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
3539 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3540 the initial credit value; read returns the current value of the credit
3541 counter. Must be initialized to 1 at start-up. */
3542 #define TCM_REG_CFC_INIT_CRD 0x50204
3543 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3544 weight 8 (the most prioritised); 1 stands for weight 1(least
3545 prioritised); 2 stands for weight 2; tc. */
3546 #define TCM_REG_CP_WEIGHT 0x500c0
3547 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3548 disregarded; acknowledge output is deasserted; all other signals are
3549 treated as usual; if 1 - normal activity. */
3550 #define TCM_REG_CSEM_IFEN 0x5002c
3551 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
3552 interface. */
3553 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
3554 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3555 weight 8 (the most prioritised); 1 stands for weight 1(least
3556 prioritised); 2 stands for weight 2; tc. */
3557 #define TCM_REG_CSEM_WEIGHT 0x500bc
3558 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
3559 #define TCM_REG_ERR_EVNT_ID 0x500a0
3560 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3561 #define TCM_REG_ERR_TCM_HDR 0x5009c
3562 /* [RW 8] The Event ID for Timers expiration. */
3563 #define TCM_REG_EXPR_EVNT_ID 0x500a4
3564 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3565 writes the initial credit value; read returns the current value of the
3566 credit counter. Must be initialized to 64 at start-up. */
3567 #define TCM_REG_FIC0_INIT_CRD 0x5020c
3568 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3569 writes the initial credit value; read returns the current value of the
3570 credit counter. Must be initialized to 64 at start-up. */
3571 #define TCM_REG_FIC1_INIT_CRD 0x50210
3572 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
3573 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
3574 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
3575 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
3576 #define TCM_REG_GR_ARB_TYPE 0x50114
3577 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3578 highest priority is 3. It is supposed that the Store channel is the
3579 compliment of the other 3 groups. */
3580 #define TCM_REG_GR_LD0_PR 0x5011c
3581 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3582 highest priority is 3. It is supposed that the Store channel is the
3583 compliment of the other 3 groups. */
3584 #define TCM_REG_GR_LD1_PR 0x50120
3585 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
3586 sent to STORM; for a specific connection type. The double REG-pairs are
3587 used to align to STORM context row size of 128 bits. The offset of these
3588 data in the STORM context is always 0. Index _i stands for the connection
3589 type (one of 16). */
3590 #define TCM_REG_N_SM_CTX_LD_0 0x50050
3591 #define TCM_REG_N_SM_CTX_LD_1 0x50054
3592 #define TCM_REG_N_SM_CTX_LD_2 0x50058
3593 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
3594 #define TCM_REG_N_SM_CTX_LD_4 0x50060
3595 #define TCM_REG_N_SM_CTX_LD_5 0x50064
3596 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3597 acknowledge output is deasserted; all other signals are treated as usual;
3598 if 1 - normal activity. */
3599 #define TCM_REG_PBF_IFEN 0x50024
3600 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
3601 interface. */
3602 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
3603 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3604 weight 8 (the most prioritised); 1 stands for weight 1(least
3605 prioritised); 2 stands for weight 2; tc. */
3606 #define TCM_REG_PBF_WEIGHT 0x500b4
3607 #define TCM_REG_PHYS_QNUM0_0 0x500e0
3608 #define TCM_REG_PHYS_QNUM0_1 0x500e4
3609 #define TCM_REG_PHYS_QNUM1_0 0x500e8
3610 #define TCM_REG_PHYS_QNUM1_1 0x500ec
3611 #define TCM_REG_PHYS_QNUM2_0 0x500f0
3612 #define TCM_REG_PHYS_QNUM2_1 0x500f4
3613 #define TCM_REG_PHYS_QNUM3_0 0x500f8
3614 #define TCM_REG_PHYS_QNUM3_1 0x500fc
3615 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
3616 acknowledge output is deasserted; all other signals are treated as usual;
3617 if 1 - normal activity. */
3618 #define TCM_REG_PRS_IFEN 0x50020
3619 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
3620 interface. */
3621 #define TCM_REG_PRS_LENGTH_MIS 0x50168
3622 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
3623 weight 8 (the most prioritised); 1 stands for weight 1(least
3624 prioritised); 2 stands for weight 2; tc. */
3625 #define TCM_REG_PRS_WEIGHT 0x500b0
3626 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3627 #define TCM_REG_STOP_EVNT_ID 0x500a8
3628 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
3629 interface. */
3630 #define TCM_REG_STORM_LENGTH_MIS 0x50160
3631 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3632 disregarded; acknowledge output is deasserted; all other signals are
3633 treated as usual; if 1 - normal activity. */
3634 #define TCM_REG_STORM_TCM_IFEN 0x50010
3635 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3636 weight 8 (the most prioritised); 1 stands for weight 1(least
3637 prioritised); 2 stands for weight 2; tc. */
3638 #define TCM_REG_STORM_WEIGHT 0x500ac
3639 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3640 acknowledge output is deasserted; all other signals are treated as usual;
3641 if 1 - normal activity. */
3642 #define TCM_REG_TCM_CFC_IFEN 0x50040
3643 /* [RW 11] Interrupt mask register #0 read/write */
3644 #define TCM_REG_TCM_INT_MASK 0x501dc
3645 /* [R 11] Interrupt register #0 read */
3646 #define TCM_REG_TCM_INT_STS 0x501d0
3647 /* [RW 27] Parity mask register #0 read/write */
3648 #define TCM_REG_TCM_PRTY_MASK 0x501ec
3649 /* [R 27] Parity register #0 read */
3650 #define TCM_REG_TCM_PRTY_STS 0x501e0
3651 /* [RC 27] Parity register #0 read clear */
3652 #define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
3653 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
3654 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3655 Is used to determine the number of the AG context REG-pairs written back;
3656 when the input message Reg1WbFlg isn't set. */
3657 #define TCM_REG_TCM_REG0_SZ 0x500d8
3658 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3659 disregarded; valid is deasserted; all other signals are treated as usual;
3660 if 1 - normal activity. */
3661 #define TCM_REG_TCM_STORM0_IFEN 0x50004
3662 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3663 disregarded; valid is deasserted; all other signals are treated as usual;
3664 if 1 - normal activity. */
3665 #define TCM_REG_TCM_STORM1_IFEN 0x50008
3666 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3667 disregarded; valid is deasserted; all other signals are treated as usual;
3668 if 1 - normal activity. */
3669 #define TCM_REG_TCM_TQM_IFEN 0x5000c
3670 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3671 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
3672 /* [RW 28] The CM header for Timers expiration command. */
3673 #define TCM_REG_TM_TCM_HDR 0x50098
3674 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3675 disregarded; acknowledge output is deasserted; all other signals are
3676 treated as usual; if 1 - normal activity. */
3677 #define TCM_REG_TM_TCM_IFEN 0x5001c
3678 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
3679 weight 8 (the most prioritised); 1 stands for weight 1(least
3680 prioritised); 2 stands for weight 2; tc. */
3681 #define TCM_REG_TM_WEIGHT 0x500d0
3682 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3683 the initial credit value; read returns the current value of the credit
3684 counter. Must be initialized to 32 at start-up. */
3685 #define TCM_REG_TQM_INIT_CRD 0x5021c
3686 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3687 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3688 prioritised); 2 stands for weight 2; tc. */
3689 #define TCM_REG_TQM_P_WEIGHT 0x500c8
3690 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
3691 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3692 prioritised); 2 stands for weight 2; tc. */
3693 #define TCM_REG_TQM_S_WEIGHT 0x500cc
3694 /* [RW 28] The CM header value for QM request (primary). */
3695 #define TCM_REG_TQM_TCM_HDR_P 0x50090
3696 /* [RW 28] The CM header value for QM request (secondary). */
3697 #define TCM_REG_TQM_TCM_HDR_S 0x50094
3698 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3699 acknowledge output is deasserted; all other signals are treated as usual;
3700 if 1 - normal activity. */
3701 #define TCM_REG_TQM_TCM_IFEN 0x50014
3702 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3703 acknowledge output is deasserted; all other signals are treated as usual;
3704 if 1 - normal activity. */
3705 #define TCM_REG_TSDM_IFEN 0x50018
3706 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
3707 interface. */
3708 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
3709 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3710 weight 8 (the most prioritised); 1 stands for weight 1(least
3711 prioritised); 2 stands for weight 2; tc. */
3712 #define TCM_REG_TSDM_WEIGHT 0x500c4
3713 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
3714 disregarded; acknowledge output is deasserted; all other signals are
3715 treated as usual; if 1 - normal activity. */
3716 #define TCM_REG_USEM_IFEN 0x50028
3717 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
3718 interface. */
3719 #define TCM_REG_USEM_LENGTH_MIS 0x50170
3720 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
3721 weight 8 (the most prioritised); 1 stands for weight 1(least
3722 prioritised); 2 stands for weight 2; tc. */
3723 #define TCM_REG_USEM_WEIGHT 0x500b8
3724 /* [RW 21] Indirect access to the descriptor table of the XX protection
3725 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
3726 pointer; 20:16] - next pointer. */
3727 #define TCM_REG_XX_DESCR_TABLE 0x50280
3728 #define TCM_REG_XX_DESCR_TABLE_SIZE 32
3729 /* [R 6] Use to read the value of XX protection Free counter. */
3730 #define TCM_REG_XX_FREE 0x50178
3731 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3732 of the Input Stage XX protection buffer by the XX protection pending
3733 messages. Max credit available - 127.Write writes the initial credit
3734 value; read returns the current value of the credit counter. Must be
3735 initialized to 19 at start-up. */
3736 #define TCM_REG_XX_INIT_CRD 0x50220
3737 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
3738 protection. */
3739 #define TCM_REG_XX_MAX_LL_SZ 0x50044
3740 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3741 protection. ~tcm_registers_xx_free.xx_free is read on read. */
3742 #define TCM_REG_XX_MSG_NUM 0x50224
3743 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3744 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
3745 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3746 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
3747 header pointer. */
3748 #define TCM_REG_XX_TABLE 0x50240
3749 /* [RW 4] Load value for cfc ac credit cnt. */
3750 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
3751 /* [RW 4] Load value for cfc cld credit cnt. */
3752 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
3753 /* [RW 8] Client0 context region. */
3754 #define TM_REG_CL0_CONT_REGION 0x164030
3755 /* [RW 8] Client1 context region. */
3756 #define TM_REG_CL1_CONT_REGION 0x164034
3757 /* [RW 8] Client2 context region. */
3758 #define TM_REG_CL2_CONT_REGION 0x164038
3759 /* [RW 2] Client in High priority client number. */
3760 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
3761 /* [RW 4] Load value for clout0 cred cnt. */
3762 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
3763 /* [RW 4] Load value for clout1 cred cnt. */
3764 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
3765 /* [RW 4] Load value for clout2 cred cnt. */
3766 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
3767 /* [RW 1] Enable client0 input. */
3768 #define TM_REG_EN_CL0_INPUT 0x164008
3769 /* [RW 1] Enable client1 input. */
3770 #define TM_REG_EN_CL1_INPUT 0x16400c
3771 /* [RW 1] Enable client2 input. */
3772 #define TM_REG_EN_CL2_INPUT 0x164010
3773 #define TM_REG_EN_LINEAR0_TIMER 0x164014
3774 /* [RW 1] Enable real time counter. */
3775 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
3776 /* [RW 1] Enable for Timers state machines. */
3777 #define TM_REG_EN_TIMERS 0x164000
3778 /* [RW 4] Load value for expiration credit cnt. CFC max number of
3779 outstanding load requests for timers (expiration) context loading. */
3780 #define TM_REG_EXP_CRDCNT_VAL 0x164238
3781 /* [RW 32] Linear0 logic address. */
3782 #define TM_REG_LIN0_LOGIC_ADDR 0x164240
3783 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
3784 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
3785 /* [WB 64] Linear0 phy address. */
3786 #define TM_REG_LIN0_PHY_ADDR 0x164270
3787 /* [RW 1] Linear0 physical address valid. */
3788 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
3789 #define TM_REG_LIN0_SCAN_ON 0x1640d0
3790 /* [RW 24] Linear0 array scan timeout. */
3791 #define TM_REG_LIN0_SCAN_TIME 0x16403c
3792 /* [RW 32] Linear1 logic address. */
3793 #define TM_REG_LIN1_LOGIC_ADDR 0x164250
3794 /* [WB 64] Linear1 phy address. */
3795 #define TM_REG_LIN1_PHY_ADDR 0x164280
3796 /* [RW 1] Linear1 physical address valid. */
3797 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
3798 /* [RW 6] Linear timer set_clear fifo threshold. */
3799 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
3800 /* [RW 2] Load value for pci arbiter credit cnt. */
3801 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
3802 /* [RW 20] The amount of hardware cycles for each timer tick. */
3803 #define TM_REG_TIMER_TICK_SIZE 0x16401c
3804 /* [RW 8] Timers Context region. */
3805 #define TM_REG_TM_CONTEXT_REGION 0x164044
3806 /* [RW 1] Interrupt mask register #0 read/write */
3807 #define TM_REG_TM_INT_MASK 0x1640fc
3808 /* [R 1] Interrupt register #0 read */
3809 #define TM_REG_TM_INT_STS 0x1640f0
3810 /* [RW 7] Parity mask register #0 read/write */
3811 #define TM_REG_TM_PRTY_MASK 0x16410c
3812 /* [RC 7] Parity register #0 read clear */
3813 #define TM_REG_TM_PRTY_STS_CLR 0x164104
3814 /* [RW 8] The event id for aggregated interrupt 0 */
3815 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
3816 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c
3817 #define TSDM_REG_AGG_INT_EVENT_2 0x42040
3818 #define TSDM_REG_AGG_INT_EVENT_3 0x42044
3819 #define TSDM_REG_AGG_INT_EVENT_4 0x42048
3820 /* [RW 1] The T bit for aggregated interrupt 0 */
3821 #define TSDM_REG_AGG_INT_T_0 0x420b8
3822 #define TSDM_REG_AGG_INT_T_1 0x420bc
3823 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3824 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
3825 /* [RW 16] The maximum value of the completion counter #0 */
3826 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
3827 /* [RW 16] The maximum value of the completion counter #1 */
3828 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
3829 /* [RW 16] The maximum value of the completion counter #2 */
3830 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
3831 /* [RW 16] The maximum value of the completion counter #3 */
3832 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
3833 /* [RW 13] The start address in the internal RAM for the completion
3834 counters. */
3835 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
3836 #define TSDM_REG_ENABLE_IN1 0x42238
3837 #define TSDM_REG_ENABLE_IN2 0x4223c
3838 #define TSDM_REG_ENABLE_OUT1 0x42240
3839 #define TSDM_REG_ENABLE_OUT2 0x42244
3840 /* [RW 4] The initial number of messages that can be sent to the pxp control
3841 interface without receiving any ACK. */
3842 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
3843 /* [ST 32] The number of ACK after placement messages received */
3844 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
3845 /* [ST 32] The number of packet end messages received from the parser */
3846 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
3847 /* [ST 32] The number of requests received from the pxp async if */
3848 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
3849 /* [ST 32] The number of commands received in queue 0 */
3850 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
3851 /* [ST 32] The number of commands received in queue 10 */
3852 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
3853 /* [ST 32] The number of commands received in queue 11 */
3854 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
3855 /* [ST 32] The number of commands received in queue 1 */
3856 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
3857 /* [ST 32] The number of commands received in queue 3 */
3858 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
3859 /* [ST 32] The number of commands received in queue 4 */
3860 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
3861 /* [ST 32] The number of commands received in queue 5 */
3862 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
3863 /* [ST 32] The number of commands received in queue 6 */
3864 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
3865 /* [ST 32] The number of commands received in queue 7 */
3866 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
3867 /* [ST 32] The number of commands received in queue 8 */
3868 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
3869 /* [ST 32] The number of commands received in queue 9 */
3870 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
3871 /* [RW 13] The start address in the internal RAM for the packet end message */
3872 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
3873 /* [RW 13] The start address in the internal RAM for queue counters */
3874 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
3875 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3876 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
3877 /* [R 1] parser fifo empty in sdm_sync block */
3878 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
3879 /* [R 1] parser serial fifo empty in sdm_sync block */
3880 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
3881 /* [RW 32] Tick for timer counter. Applicable only when
3882 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
3883 #define TSDM_REG_TIMER_TICK 0x42000
3884 /* [RW 32] Interrupt mask register #0 read/write */
3885 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
3886 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
3887 /* [R 32] Interrupt register #0 read */
3888 #define TSDM_REG_TSDM_INT_STS_0 0x42290
3889 #define TSDM_REG_TSDM_INT_STS_1 0x422a0
3890 /* [RW 11] Parity mask register #0 read/write */
3891 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
3892 /* [R 11] Parity register #0 read */
3893 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
3894 /* [RC 11] Parity register #0 read clear */
3895 #define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
3896 /* [RW 5] The number of time_slots in the arbitration cycle */
3897 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
3898 /* [RW 3] The source that is associated with arbitration element 0. Source
3899 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3900 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3901 #define TSEM_REG_ARB_ELEMENT0 0x180020
3902 /* [RW 3] The source that is associated with arbitration element 1. Source
3903 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3904 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3905 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
3906 #define TSEM_REG_ARB_ELEMENT1 0x180024
3907 /* [RW 3] The source that is associated with arbitration element 2. Source
3908 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3909 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3910 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
3911 and ~tsem_registers_arb_element1.arb_element1 */
3912 #define TSEM_REG_ARB_ELEMENT2 0x180028
3913 /* [RW 3] The source that is associated with arbitration element 3. Source
3914 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3915 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3916 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
3917 ~tsem_registers_arb_element1.arb_element1 and
3918 ~tsem_registers_arb_element2.arb_element2 */
3919 #define TSEM_REG_ARB_ELEMENT3 0x18002c
3920 /* [RW 3] The source that is associated with arbitration element 4. Source
3921 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3922 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3923 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
3924 and ~tsem_registers_arb_element1.arb_element1 and
3925 ~tsem_registers_arb_element2.arb_element2 and
3926 ~tsem_registers_arb_element3.arb_element3 */
3927 #define TSEM_REG_ARB_ELEMENT4 0x180030
3928 #define TSEM_REG_ENABLE_IN 0x1800a4
3929 #define TSEM_REG_ENABLE_OUT 0x1800a8
3930 /* [RW 32] This address space contains all registers and memories that are
3931 placed in SEM_FAST block. The SEM_FAST registers are described in
3932 appendix B. In order to access the sem_fast registers the base address
3933 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
3934 #define TSEM_REG_FAST_MEMORY 0x1a0000
3935 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
3936 by the microcode */
3937 #define TSEM_REG_FIC0_DISABLE 0x180224
3938 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
3939 by the microcode */
3940 #define TSEM_REG_FIC1_DISABLE 0x180234
3941 /* [RW 15] Interrupt table Read and write access to it is not possible in
3942 the middle of the work */
3943 #define TSEM_REG_INT_TABLE 0x180400
3944 /* [ST 24] Statistics register. The number of messages that entered through
3945 FIC0 */
3946 #define TSEM_REG_MSG_NUM_FIC0 0x180000
3947 /* [ST 24] Statistics register. The number of messages that entered through
3948 FIC1 */
3949 #define TSEM_REG_MSG_NUM_FIC1 0x180004
3950 /* [ST 24] Statistics register. The number of messages that were sent to
3951 FOC0 */
3952 #define TSEM_REG_MSG_NUM_FOC0 0x180008
3953 /* [ST 24] Statistics register. The number of messages that were sent to
3954 FOC1 */
3955 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
3956 /* [ST 24] Statistics register. The number of messages that were sent to
3957 FOC2 */
3958 #define TSEM_REG_MSG_NUM_FOC2 0x180010
3959 /* [ST 24] Statistics register. The number of messages that were sent to
3960 FOC3 */
3961 #define TSEM_REG_MSG_NUM_FOC3 0x180014
3962 /* [RW 1] Disables input messages from the passive buffer May be updated
3963 during run_time by the microcode */
3964 #define TSEM_REG_PAS_DISABLE 0x18024c
3965 /* [WB 128] Debug only. Passive buffer memory */
3966 #define TSEM_REG_PASSIVE_BUFFER 0x181000
3967 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3968 #define TSEM_REG_PRAM 0x1c0000
3969 /* [R 8] Valid sleeping threads indication have bit per thread */
3970 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
3971 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3972 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
3973 /* [RW 8] List of free threads . There is a bit per thread. */
3974 #define TSEM_REG_THREADS_LIST 0x1802e4
3975 /* [RC 32] Parity register #0 read clear */
3976 #define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
3977 #define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
3978 /* [RW 3] The arbitration scheme of time_slot 0 */
3979 #define TSEM_REG_TS_0_AS 0x180038
3980 /* [RW 3] The arbitration scheme of time_slot 10 */
3981 #define TSEM_REG_TS_10_AS 0x180060
3982 /* [RW 3] The arbitration scheme of time_slot 11 */
3983 #define TSEM_REG_TS_11_AS 0x180064
3984 /* [RW 3] The arbitration scheme of time_slot 12 */
3985 #define TSEM_REG_TS_12_AS 0x180068
3986 /* [RW 3] The arbitration scheme of time_slot 13 */
3987 #define TSEM_REG_TS_13_AS 0x18006c
3988 /* [RW 3] The arbitration scheme of time_slot 14 */
3989 #define TSEM_REG_TS_14_AS 0x180070
3990 /* [RW 3] The arbitration scheme of time_slot 15 */
3991 #define TSEM_REG_TS_15_AS 0x180074
3992 /* [RW 3] The arbitration scheme of time_slot 16 */
3993 #define TSEM_REG_TS_16_AS 0x180078
3994 /* [RW 3] The arbitration scheme of time_slot 17 */
3995 #define TSEM_REG_TS_17_AS 0x18007c
3996 /* [RW 3] The arbitration scheme of time_slot 18 */
3997 #define TSEM_REG_TS_18_AS 0x180080
3998 /* [RW 3] The arbitration scheme of time_slot 1 */
3999 #define TSEM_REG_TS_1_AS 0x18003c
4000 /* [RW 3] The arbitration scheme of time_slot 2 */
4001 #define TSEM_REG_TS_2_AS 0x180040
4002 /* [RW 3] The arbitration scheme of time_slot 3 */
4003 #define TSEM_REG_TS_3_AS 0x180044
4004 /* [RW 3] The arbitration scheme of time_slot 4 */
4005 #define TSEM_REG_TS_4_AS 0x180048
4006 /* [RW 3] The arbitration scheme of time_slot 5 */
4007 #define TSEM_REG_TS_5_AS 0x18004c
4008 /* [RW 3] The arbitration scheme of time_slot 6 */
4009 #define TSEM_REG_TS_6_AS 0x180050
4010 /* [RW 3] The arbitration scheme of time_slot 7 */
4011 #define TSEM_REG_TS_7_AS 0x180054
4012 /* [RW 3] The arbitration scheme of time_slot 8 */
4013 #define TSEM_REG_TS_8_AS 0x180058
4014 /* [RW 3] The arbitration scheme of time_slot 9 */
4015 #define TSEM_REG_TS_9_AS 0x18005c
4016 /* [RW 32] Interrupt mask register #0 read/write */
4017 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
4018 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
4019 /* [R 32] Interrupt register #0 read */
4020 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4021 #define TSEM_REG_TSEM_INT_STS_1 0x180104
4022 /* [RW 32] Parity mask register #0 read/write */
4023 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
4024 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
4025 /* [R 32] Parity register #0 read */
4026 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114
4027 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124
4028 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4029 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4030 #define TSEM_REG_VFPF_ERR_NUM 0x180380
4031 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4032 * [10:8] of the address should be the offset within the accessed LCID
4033 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4034 * LCID100. The RBC address should be 12'ha64. */
4035 #define UCM_REG_AG_CTX 0xe2000
4036 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4037 #define UCM_REG_CAM_OCCUP 0xe0170
4038 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4039 disregarded; valid output is deasserted; all other signals are treated as
4040 usual; if 1 - normal activity. */
4041 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
4042 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4043 are disregarded; all other signals are treated as usual; if 1 - normal
4044 activity. */
4045 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
4046 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4047 disregarded; valid output is deasserted; all other signals are treated as
4048 usual; if 1 - normal activity. */
4049 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
4050 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4051 input is disregarded; all other signals are treated as usual; if 1 -
4052 normal activity. */
4053 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
4054 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4055 the initial credit value; read returns the current value of the credit
4056 counter. Must be initialized to 1 at start-up. */
4057 #define UCM_REG_CFC_INIT_CRD 0xe0204
4058 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4059 weight 8 (the most prioritised); 1 stands for weight 1(least
4060 prioritised); 2 stands for weight 2; tc. */
4061 #define UCM_REG_CP_WEIGHT 0xe00c4
4062 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4063 disregarded; acknowledge output is deasserted; all other signals are
4064 treated as usual; if 1 - normal activity. */
4065 #define UCM_REG_CSEM_IFEN 0xe0028
4066 /* [RC 1] Set when the message length mismatch (relative to last indication)
4067 at the csem interface is detected. */
4068 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4069 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4070 weight 8 (the most prioritised); 1 stands for weight 1(least
4071 prioritised); 2 stands for weight 2; tc. */
4072 #define UCM_REG_CSEM_WEIGHT 0xe00b8
4073 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4074 disregarded; acknowledge output is deasserted; all other signals are
4075 treated as usual; if 1 - normal activity. */
4076 #define UCM_REG_DORQ_IFEN 0xe0030
4077 /* [RC 1] Set when the message length mismatch (relative to last indication)
4078 at the dorq interface is detected. */
4079 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
4080 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4081 weight 8 (the most prioritised); 1 stands for weight 1(least
4082 prioritised); 2 stands for weight 2; tc. */
4083 #define UCM_REG_DORQ_WEIGHT 0xe00c0
4084 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4085 #define UCM_REG_ERR_EVNT_ID 0xe00a4
4086 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4087 #define UCM_REG_ERR_UCM_HDR 0xe00a0
4088 /* [RW 8] The Event ID for Timers expiration. */
4089 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
4090 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4091 writes the initial credit value; read returns the current value of the
4092 credit counter. Must be initialized to 64 at start-up. */
4093 #define UCM_REG_FIC0_INIT_CRD 0xe020c
4094 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4095 writes the initial credit value; read returns the current value of the
4096 credit counter. Must be initialized to 64 at start-up. */
4097 #define UCM_REG_FIC1_INIT_CRD 0xe0210
4098 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4099 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
4100 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
4101 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
4102 #define UCM_REG_GR_ARB_TYPE 0xe0144
4103 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4104 highest priority is 3. It is supposed that the Store channel group is
4105 compliment to the others. */
4106 #define UCM_REG_GR_LD0_PR 0xe014c
4107 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4108 highest priority is 3. It is supposed that the Store channel group is
4109 compliment to the others. */
4110 #define UCM_REG_GR_LD1_PR 0xe0150
4111 /* [RW 2] The queue index for invalidate counter flag decision. */
4112 #define UCM_REG_INV_CFLG_Q 0xe00e4
4113 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4114 sent to STORM; for a specific connection type. the double REG-pairs are
4115 used in order to align to STORM context row size of 128 bits. The offset
4116 of these data in the STORM context is always 0. Index _i stands for the
4117 connection type (one of 16). */
4118 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
4119 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
4120 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
4121 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
4122 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
4123 #define UCM_REG_N_SM_CTX_LD_5 0xe0068
4124 #define UCM_REG_PHYS_QNUM0_0 0xe0110
4125 #define UCM_REG_PHYS_QNUM0_1 0xe0114
4126 #define UCM_REG_PHYS_QNUM1_0 0xe0118
4127 #define UCM_REG_PHYS_QNUM1_1 0xe011c
4128 #define UCM_REG_PHYS_QNUM2_0 0xe0120
4129 #define UCM_REG_PHYS_QNUM2_1 0xe0124
4130 #define UCM_REG_PHYS_QNUM3_0 0xe0128
4131 #define UCM_REG_PHYS_QNUM3_1 0xe012c
4132 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4133 #define UCM_REG_STOP_EVNT_ID 0xe00ac
4134 /* [RC 1] Set when the message length mismatch (relative to last indication)
4135 at the STORM interface is detected. */
4136 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
4137 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4138 disregarded; acknowledge output is deasserted; all other signals are
4139 treated as usual; if 1 - normal activity. */
4140 #define UCM_REG_STORM_UCM_IFEN 0xe0010
4141 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4142 weight 8 (the most prioritised); 1 stands for weight 1(least
4143 prioritised); 2 stands for weight 2; tc. */
4144 #define UCM_REG_STORM_WEIGHT 0xe00b0
4145 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4146 writes the initial credit value; read returns the current value of the
4147 credit counter. Must be initialized to 4 at start-up. */
4148 #define UCM_REG_TM_INIT_CRD 0xe021c
4149 /* [RW 28] The CM header for Timers expiration command. */
4150 #define UCM_REG_TM_UCM_HDR 0xe009c
4151 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4152 disregarded; acknowledge output is deasserted; all other signals are
4153 treated as usual; if 1 - normal activity. */
4154 #define UCM_REG_TM_UCM_IFEN 0xe001c
4155 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4156 weight 8 (the most prioritised); 1 stands for weight 1(least
4157 prioritised); 2 stands for weight 2; tc. */
4158 #define UCM_REG_TM_WEIGHT 0xe00d4
4159 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4160 disregarded; acknowledge output is deasserted; all other signals are
4161 treated as usual; if 1 - normal activity. */
4162 #define UCM_REG_TSEM_IFEN 0xe0024
4163 /* [RC 1] Set when the message length mismatch (relative to last indication)
4164 at the tsem interface is detected. */
4165 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
4166 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4167 weight 8 (the most prioritised); 1 stands for weight 1(least
4168 prioritised); 2 stands for weight 2; tc. */
4169 #define UCM_REG_TSEM_WEIGHT 0xe00b4
4170 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4171 acknowledge output is deasserted; all other signals are treated as usual;
4172 if 1 - normal activity. */
4173 #define UCM_REG_UCM_CFC_IFEN 0xe0044
4174 /* [RW 11] Interrupt mask register #0 read/write */
4175 #define UCM_REG_UCM_INT_MASK 0xe01d4
4176 /* [R 11] Interrupt register #0 read */
4177 #define UCM_REG_UCM_INT_STS 0xe01c8
4178 /* [R 27] Parity register #0 read */
4179 #define UCM_REG_UCM_PRTY_STS 0xe01d8
4180 /* [RC 27] Parity register #0 read clear */
4181 #define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc
4182 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4183 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4184 Is used to determine the number of the AG context REG-pairs written back;
4185 when the Reg1WbFlg isn't set. */
4186 #define UCM_REG_UCM_REG0_SZ 0xe00dc
4187 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4188 disregarded; valid is deasserted; all other signals are treated as usual;
4189 if 1 - normal activity. */
4190 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
4191 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4192 disregarded; valid is deasserted; all other signals are treated as usual;
4193 if 1 - normal activity. */
4194 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
4195 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4196 disregarded; acknowledge output is deasserted; all other signals are
4197 treated as usual; if 1 - normal activity. */
4198 #define UCM_REG_UCM_TM_IFEN 0xe0020
4199 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4200 disregarded; valid is deasserted; all other signals are treated as usual;
4201 if 1 - normal activity. */
4202 #define UCM_REG_UCM_UQM_IFEN 0xe000c
4203 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4204 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
4205 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4206 the initial credit value; read returns the current value of the credit
4207 counter. Must be initialized to 32 at start-up. */
4208 #define UCM_REG_UQM_INIT_CRD 0xe0220
4209 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4210 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4211 prioritised); 2 stands for weight 2; tc. */
4212 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
4213 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4214 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4215 prioritised); 2 stands for weight 2; tc. */
4216 #define UCM_REG_UQM_S_WEIGHT 0xe00d0
4217 /* [RW 28] The CM header value for QM request (primary). */
4218 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
4219 /* [RW 28] The CM header value for QM request (secondary). */
4220 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
4221 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4222 acknowledge output is deasserted; all other signals are treated as usual;
4223 if 1 - normal activity. */
4224 #define UCM_REG_UQM_UCM_IFEN 0xe0014
4225 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4226 acknowledge output is deasserted; all other signals are treated as usual;
4227 if 1 - normal activity. */
4228 #define UCM_REG_USDM_IFEN 0xe0018
4229 /* [RC 1] Set when the message length mismatch (relative to last indication)
4230 at the SDM interface is detected. */
4231 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
4232 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4233 weight 8 (the most prioritised); 1 stands for weight 1(least
4234 prioritised); 2 stands for weight 2; tc. */
4235 #define UCM_REG_USDM_WEIGHT 0xe00c8
4236 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4237 disregarded; acknowledge output is deasserted; all other signals are
4238 treated as usual; if 1 - normal activity. */
4239 #define UCM_REG_XSEM_IFEN 0xe002c
4240 /* [RC 1] Set when the message length mismatch (relative to last indication)
4241 at the xsem interface isdetected. */
4242 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
4243 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
4244 weight 8 (the most prioritised); 1 stands for weight 1(least
4245 prioritised); 2 stands for weight 2; tc. */
4246 #define UCM_REG_XSEM_WEIGHT 0xe00bc
4247 /* [RW 20] Indirect access to the descriptor table of the XX protection
4248 mechanism. The fields are:[5:0] - message length; 14:6] - message
4249 pointer; 19:15] - next pointer. */
4250 #define UCM_REG_XX_DESCR_TABLE 0xe0280
4251 #define UCM_REG_XX_DESCR_TABLE_SIZE 32
4252 /* [R 6] Use to read the XX protection Free counter. */
4253 #define UCM_REG_XX_FREE 0xe016c
4254 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4255 of the Input Stage XX protection buffer by the XX protection pending
4256 messages. Write writes the initial credit value; read returns the current
4257 value of the credit counter. Must be initialized to 12 at start-up. */
4258 #define UCM_REG_XX_INIT_CRD 0xe0224
4259 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4260 protection. ~ucm_registers_xx_free.xx_free read on read. */
4261 #define UCM_REG_XX_MSG_NUM 0xe0228
4262 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4263 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
4264 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4265 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4266 header pointer. */
4267 #define UCM_REG_XX_TABLE 0xe0300
4268 /* [RW 8] The event id for aggregated interrupt 0 */
4269 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
4270 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
4271 #define USDM_REG_AGG_INT_EVENT_2 0xc4040
4272 #define USDM_REG_AGG_INT_EVENT_4 0xc4048
4273 #define USDM_REG_AGG_INT_EVENT_5 0xc404c
4274 #define USDM_REG_AGG_INT_EVENT_6 0xc4050
4275 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4276 or auto-mask-mode (1) */
4277 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
4278 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
4279 #define USDM_REG_AGG_INT_MODE_4 0xc41c8
4280 #define USDM_REG_AGG_INT_MODE_5 0xc41cc
4281 #define USDM_REG_AGG_INT_MODE_6 0xc41d0
4282 /* [RW 1] The T bit for aggregated interrupt 5 */
4283 #define USDM_REG_AGG_INT_T_5 0xc40cc
4284 #define USDM_REG_AGG_INT_T_6 0xc40d0
4285 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4286 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
4287 /* [RW 16] The maximum value of the completion counter #0 */
4288 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
4289 /* [RW 16] The maximum value of the completion counter #1 */
4290 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
4291 /* [RW 16] The maximum value of the completion counter #2 */
4292 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
4293 /* [RW 16] The maximum value of the completion counter #3 */
4294 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
4295 /* [RW 13] The start address in the internal RAM for the completion
4296 counters. */
4297 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
4298 #define USDM_REG_ENABLE_IN1 0xc4238
4299 #define USDM_REG_ENABLE_IN2 0xc423c
4300 #define USDM_REG_ENABLE_OUT1 0xc4240
4301 #define USDM_REG_ENABLE_OUT2 0xc4244
4302 /* [RW 4] The initial number of messages that can be sent to the pxp control
4303 interface without receiving any ACK. */
4304 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
4305 /* [ST 32] The number of ACK after placement messages received */
4306 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
4307 /* [ST 32] The number of packet end messages received from the parser */
4308 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
4309 /* [ST 32] The number of requests received from the pxp async if */
4310 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
4311 /* [ST 32] The number of commands received in queue 0 */
4312 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
4313 /* [ST 32] The number of commands received in queue 10 */
4314 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
4315 /* [ST 32] The number of commands received in queue 11 */
4316 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
4317 /* [ST 32] The number of commands received in queue 1 */
4318 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
4319 /* [ST 32] The number of commands received in queue 2 */
4320 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
4321 /* [ST 32] The number of commands received in queue 3 */
4322 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
4323 /* [ST 32] The number of commands received in queue 4 */
4324 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
4325 /* [ST 32] The number of commands received in queue 5 */
4326 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
4327 /* [ST 32] The number of commands received in queue 6 */
4328 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
4329 /* [ST 32] The number of commands received in queue 7 */
4330 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
4331 /* [ST 32] The number of commands received in queue 8 */
4332 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
4333 /* [ST 32] The number of commands received in queue 9 */
4334 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
4335 /* [RW 13] The start address in the internal RAM for the packet end message */
4336 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
4337 /* [RW 13] The start address in the internal RAM for queue counters */
4338 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
4339 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4340 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
4341 /* [R 1] parser fifo empty in sdm_sync block */
4342 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
4343 /* [R 1] parser serial fifo empty in sdm_sync block */
4344 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
4345 /* [RW 32] Tick for timer counter. Applicable only when
4346 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
4347 #define USDM_REG_TIMER_TICK 0xc4000
4348 /* [RW 32] Interrupt mask register #0 read/write */
4349 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
4350 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
4351 /* [R 32] Interrupt register #0 read */
4352 #define USDM_REG_USDM_INT_STS_0 0xc4294
4353 #define USDM_REG_USDM_INT_STS_1 0xc42a4
4354 /* [RW 11] Parity mask register #0 read/write */
4355 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
4356 /* [R 11] Parity register #0 read */
4357 #define USDM_REG_USDM_PRTY_STS 0xc42b4
4358 /* [RC 11] Parity register #0 read clear */
4359 #define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8
4360 /* [RW 5] The number of time_slots in the arbitration cycle */
4361 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
4362 /* [RW 3] The source that is associated with arbitration element 0. Source
4363 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4364 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4365 #define USEM_REG_ARB_ELEMENT0 0x300020
4366 /* [RW 3] The source that is associated with arbitration element 1. Source
4367 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4368 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4369 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
4370 #define USEM_REG_ARB_ELEMENT1 0x300024
4371 /* [RW 3] The source that is associated with arbitration element 2. Source
4372 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4373 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4374 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4375 and ~usem_registers_arb_element1.arb_element1 */
4376 #define USEM_REG_ARB_ELEMENT2 0x300028
4377 /* [RW 3] The source that is associated with arbitration element 3. Source
4378 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4379 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4380 not be equal to register ~usem_registers_arb_element0.arb_element0 and
4381 ~usem_registers_arb_element1.arb_element1 and
4382 ~usem_registers_arb_element2.arb_element2 */
4383 #define USEM_REG_ARB_ELEMENT3 0x30002c
4384 /* [RW 3] The source that is associated with arbitration element 4. Source
4385 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4386 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4387 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4388 and ~usem_registers_arb_element1.arb_element1 and
4389 ~usem_registers_arb_element2.arb_element2 and
4390 ~usem_registers_arb_element3.arb_element3 */
4391 #define USEM_REG_ARB_ELEMENT4 0x300030
4392 #define USEM_REG_ENABLE_IN 0x3000a4
4393 #define USEM_REG_ENABLE_OUT 0x3000a8
4394 /* [RW 32] This address space contains all registers and memories that are
4395 placed in SEM_FAST block. The SEM_FAST registers are described in
4396 appendix B. In order to access the sem_fast registers the base address
4397 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4398 #define USEM_REG_FAST_MEMORY 0x320000
4399 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4400 by the microcode */
4401 #define USEM_REG_FIC0_DISABLE 0x300224
4402 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4403 by the microcode */
4404 #define USEM_REG_FIC1_DISABLE 0x300234
4405 /* [RW 15] Interrupt table Read and write access to it is not possible in
4406 the middle of the work */
4407 #define USEM_REG_INT_TABLE 0x300400
4408 /* [ST 24] Statistics register. The number of messages that entered through
4409 FIC0 */
4410 #define USEM_REG_MSG_NUM_FIC0 0x300000
4411 /* [ST 24] Statistics register. The number of messages that entered through
4412 FIC1 */
4413 #define USEM_REG_MSG_NUM_FIC1 0x300004
4414 /* [ST 24] Statistics register. The number of messages that were sent to
4415 FOC0 */
4416 #define USEM_REG_MSG_NUM_FOC0 0x300008
4417 /* [ST 24] Statistics register. The number of messages that were sent to
4418 FOC1 */
4419 #define USEM_REG_MSG_NUM_FOC1 0x30000c
4420 /* [ST 24] Statistics register. The number of messages that were sent to
4421 FOC2 */
4422 #define USEM_REG_MSG_NUM_FOC2 0x300010
4423 /* [ST 24] Statistics register. The number of messages that were sent to
4424 FOC3 */
4425 #define USEM_REG_MSG_NUM_FOC3 0x300014
4426 /* [RW 1] Disables input messages from the passive buffer May be updated
4427 during run_time by the microcode */
4428 #define USEM_REG_PAS_DISABLE 0x30024c
4429 /* [WB 128] Debug only. Passive buffer memory */
4430 #define USEM_REG_PASSIVE_BUFFER 0x302000
4431 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4432 #define USEM_REG_PRAM 0x340000
4433 /* [R 16] Valid sleeping threads indication have bit per thread */
4434 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
4435 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4436 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
4437 /* [RW 16] List of free threads . There is a bit per thread. */
4438 #define USEM_REG_THREADS_LIST 0x3002e4
4439 /* [RW 3] The arbitration scheme of time_slot 0 */
4440 #define USEM_REG_TS_0_AS 0x300038
4441 /* [RW 3] The arbitration scheme of time_slot 10 */
4442 #define USEM_REG_TS_10_AS 0x300060
4443 /* [RW 3] The arbitration scheme of time_slot 11 */
4444 #define USEM_REG_TS_11_AS 0x300064
4445 /* [RW 3] The arbitration scheme of time_slot 12 */
4446 #define USEM_REG_TS_12_AS 0x300068
4447 /* [RW 3] The arbitration scheme of time_slot 13 */
4448 #define USEM_REG_TS_13_AS 0x30006c
4449 /* [RW 3] The arbitration scheme of time_slot 14 */
4450 #define USEM_REG_TS_14_AS 0x300070
4451 /* [RW 3] The arbitration scheme of time_slot 15 */
4452 #define USEM_REG_TS_15_AS 0x300074
4453 /* [RW 3] The arbitration scheme of time_slot 16 */
4454 #define USEM_REG_TS_16_AS 0x300078
4455 /* [RW 3] The arbitration scheme of time_slot 17 */
4456 #define USEM_REG_TS_17_AS 0x30007c
4457 /* [RW 3] The arbitration scheme of time_slot 18 */
4458 #define USEM_REG_TS_18_AS 0x300080
4459 /* [RW 3] The arbitration scheme of time_slot 1 */
4460 #define USEM_REG_TS_1_AS 0x30003c
4461 /* [RW 3] The arbitration scheme of time_slot 2 */
4462 #define USEM_REG_TS_2_AS 0x300040
4463 /* [RW 3] The arbitration scheme of time_slot 3 */
4464 #define USEM_REG_TS_3_AS 0x300044
4465 /* [RW 3] The arbitration scheme of time_slot 4 */
4466 #define USEM_REG_TS_4_AS 0x300048
4467 /* [RW 3] The arbitration scheme of time_slot 5 */
4468 #define USEM_REG_TS_5_AS 0x30004c
4469 /* [RW 3] The arbitration scheme of time_slot 6 */
4470 #define USEM_REG_TS_6_AS 0x300050
4471 /* [RW 3] The arbitration scheme of time_slot 7 */
4472 #define USEM_REG_TS_7_AS 0x300054
4473 /* [RW 3] The arbitration scheme of time_slot 8 */
4474 #define USEM_REG_TS_8_AS 0x300058
4475 /* [RW 3] The arbitration scheme of time_slot 9 */
4476 #define USEM_REG_TS_9_AS 0x30005c
4477 /* [RW 32] Interrupt mask register #0 read/write */
4478 #define USEM_REG_USEM_INT_MASK_0 0x300110
4479 #define USEM_REG_USEM_INT_MASK_1 0x300120
4480 /* [R 32] Interrupt register #0 read */
4481 #define USEM_REG_USEM_INT_STS_0 0x300104
4482 #define USEM_REG_USEM_INT_STS_1 0x300114
4483 /* [RW 32] Parity mask register #0 read/write */
4484 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
4485 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
4486 /* [R 32] Parity register #0 read */
4487 #define USEM_REG_USEM_PRTY_STS_0 0x300124
4488 #define USEM_REG_USEM_PRTY_STS_1 0x300134
4489 /* [RC 32] Parity register #0 read clear */
4490 #define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128
4491 #define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138
4492 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4493 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4494 #define USEM_REG_VFPF_ERR_NUM 0x300380
4495 #define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)
4496 #define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)
4497 #define VFC_REG_MEMORIES_RST 0x1943c
4498 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4499 * [12:8] of the address should be the offset within the accessed LCID
4500 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4501 * LCID100. The RBC address should be 13'ha64. */
4502 #define XCM_REG_AG_CTX 0x28000
4503 /* [RW 2] The queue index for registration on Aux1 counter flag. */
4504 #define XCM_REG_AUX1_Q 0x20134
4505 /* [RW 2] Per each decision rule the queue index to register to. */
4506 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
4507 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4508 #define XCM_REG_CAM_OCCUP 0x20244
4509 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4510 disregarded; valid output is deasserted; all other signals are treated as
4511 usual; if 1 - normal activity. */
4512 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
4513 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4514 are disregarded; all other signals are treated as usual; if 1 - normal
4515 activity. */
4516 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
4517 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4518 disregarded; valid output is deasserted; all other signals are treated as
4519 usual; if 1 - normal activity. */
4520 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
4521 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4522 input is disregarded; all other signals are treated as usual; if 1 -
4523 normal activity. */
4524 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
4525 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4526 the initial credit value; read returns the current value of the credit
4527 counter. Must be initialized to 1 at start-up. */
4528 #define XCM_REG_CFC_INIT_CRD 0x20404
4529 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4530 weight 8 (the most prioritised); 1 stands for weight 1(least
4531 prioritised); 2 stands for weight 2; tc. */
4532 #define XCM_REG_CP_WEIGHT 0x200dc
4533 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4534 disregarded; acknowledge output is deasserted; all other signals are
4535 treated as usual; if 1 - normal activity. */
4536 #define XCM_REG_CSEM_IFEN 0x20028
4537 /* [RC 1] Set at message length mismatch (relative to last indication) at
4538 the csem interface. */
4539 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
4540 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4541 weight 8 (the most prioritised); 1 stands for weight 1(least
4542 prioritised); 2 stands for weight 2; tc. */
4543 #define XCM_REG_CSEM_WEIGHT 0x200c4
4544 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4545 disregarded; acknowledge output is deasserted; all other signals are
4546 treated as usual; if 1 - normal activity. */
4547 #define XCM_REG_DORQ_IFEN 0x20030
4548 /* [RC 1] Set at message length mismatch (relative to last indication) at
4549 the dorq interface. */
4550 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
4551 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4552 weight 8 (the most prioritised); 1 stands for weight 1(least
4553 prioritised); 2 stands for weight 2; tc. */
4554 #define XCM_REG_DORQ_WEIGHT 0x200cc
4555 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
4556 #define XCM_REG_ERR_EVNT_ID 0x200b0
4557 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4558 #define XCM_REG_ERR_XCM_HDR 0x200ac
4559 /* [RW 8] The Event ID for Timers expiration. */
4560 #define XCM_REG_EXPR_EVNT_ID 0x200b4
4561 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4562 writes the initial credit value; read returns the current value of the
4563 credit counter. Must be initialized to 64 at start-up. */
4564 #define XCM_REG_FIC0_INIT_CRD 0x2040c
4565 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4566 writes the initial credit value; read returns the current value of the
4567 credit counter. Must be initialized to 64 at start-up. */
4568 #define XCM_REG_FIC1_INIT_CRD 0x20410
4569 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
4570 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
4571 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
4572 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
4573 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
4574 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
4575 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
4576 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
4577 #define XCM_REG_GR_ARB_TYPE 0x2020c
4578 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4579 highest priority is 3. It is supposed that the Channel group is the
4580 compliment of the other 3 groups. */
4581 #define XCM_REG_GR_LD0_PR 0x20214
4582 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4583 highest priority is 3. It is supposed that the Channel group is the
4584 compliment of the other 3 groups. */
4585 #define XCM_REG_GR_LD1_PR 0x20218
4586 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
4587 disregarded; acknowledge output is deasserted; all other signals are
4588 treated as usual; if 1 - normal activity. */
4589 #define XCM_REG_NIG0_IFEN 0x20038
4590 /* [RC 1] Set at message length mismatch (relative to last indication) at
4591 the nig0 interface. */
4592 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
4593 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
4594 weight 8 (the most prioritised); 1 stands for weight 1(least
4595 prioritised); 2 stands for weight 2; tc. */
4596 #define XCM_REG_NIG0_WEIGHT 0x200d4
4597 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
4598 disregarded; acknowledge output is deasserted; all other signals are
4599 treated as usual; if 1 - normal activity. */
4600 #define XCM_REG_NIG1_IFEN 0x2003c
4601 /* [RC 1] Set at message length mismatch (relative to last indication) at
4602 the nig1 interface. */
4603 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
4604 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4605 sent to STORM; for a specific connection type. The double REG-pairs are
4606 used in order to align to STORM context row size of 128 bits. The offset
4607 of these data in the STORM context is always 0. Index _i stands for the
4608 connection type (one of 16). */
4609 #define XCM_REG_N_SM_CTX_LD_0 0x20060
4610 #define XCM_REG_N_SM_CTX_LD_1 0x20064
4611 #define XCM_REG_N_SM_CTX_LD_2 0x20068
4612 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
4613 #define XCM_REG_N_SM_CTX_LD_4 0x20070
4614 #define XCM_REG_N_SM_CTX_LD_5 0x20074
4615 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4616 acknowledge output is deasserted; all other signals are treated as usual;
4617 if 1 - normal activity. */
4618 #define XCM_REG_PBF_IFEN 0x20034
4619 /* [RC 1] Set at message length mismatch (relative to last indication) at
4620 the pbf interface. */
4621 #define XCM_REG_PBF_LENGTH_MIS 0x20234
4622 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4623 weight 8 (the most prioritised); 1 stands for weight 1(least
4624 prioritised); 2 stands for weight 2; tc. */
4625 #define XCM_REG_PBF_WEIGHT 0x200d0
4626 #define XCM_REG_PHYS_QNUM3_0 0x20100
4627 #define XCM_REG_PHYS_QNUM3_1 0x20104
4628 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4629 #define XCM_REG_STOP_EVNT_ID 0x200b8
4630 /* [RC 1] Set at message length mismatch (relative to last indication) at
4631 the STORM interface. */
4632 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
4633 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4634 weight 8 (the most prioritised); 1 stands for weight 1(least
4635 prioritised); 2 stands for weight 2; tc. */
4636 #define XCM_REG_STORM_WEIGHT 0x200bc
4637 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4638 disregarded; acknowledge output is deasserted; all other signals are
4639 treated as usual; if 1 - normal activity. */
4640 #define XCM_REG_STORM_XCM_IFEN 0x20010
4641 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4642 writes the initial credit value; read returns the current value of the
4643 credit counter. Must be initialized to 4 at start-up. */
4644 #define XCM_REG_TM_INIT_CRD 0x2041c
4645 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4646 weight 8 (the most prioritised); 1 stands for weight 1(least
4647 prioritised); 2 stands for weight 2; tc. */
4648 #define XCM_REG_TM_WEIGHT 0x200ec
4649 /* [RW 28] The CM header for Timers expiration command. */
4650 #define XCM_REG_TM_XCM_HDR 0x200a8
4651 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4652 disregarded; acknowledge output is deasserted; all other signals are
4653 treated as usual; if 1 - normal activity. */
4654 #define XCM_REG_TM_XCM_IFEN 0x2001c
4655 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4656 disregarded; acknowledge output is deasserted; all other signals are
4657 treated as usual; if 1 - normal activity. */
4658 #define XCM_REG_TSEM_IFEN 0x20024
4659 /* [RC 1] Set at message length mismatch (relative to last indication) at
4660 the tsem interface. */
4661 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
4662 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4663 weight 8 (the most prioritised); 1 stands for weight 1(least
4664 prioritised); 2 stands for weight 2; tc. */
4665 #define XCM_REG_TSEM_WEIGHT 0x200c0
4666 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
4667 #define XCM_REG_UNA_GT_NXT_Q 0x20120
4668 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4669 disregarded; acknowledge output is deasserted; all other signals are
4670 treated as usual; if 1 - normal activity. */
4671 #define XCM_REG_USEM_IFEN 0x2002c
4672 /* [RC 1] Message length mismatch (relative to last indication) at the usem
4673 interface. */
4674 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
4675 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4676 weight 8 (the most prioritised); 1 stands for weight 1(least
4677 prioritised); 2 stands for weight 2; tc. */
4678 #define XCM_REG_USEM_WEIGHT 0x200c8
4679 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
4680 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
4681 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
4682 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
4683 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
4684 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
4685 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
4686 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
4687 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
4688 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
4689 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
4690 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
4691 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4692 acknowledge output is deasserted; all other signals are treated as usual;
4693 if 1 - normal activity. */
4694 #define XCM_REG_XCM_CFC_IFEN 0x20050
4695 /* [RW 14] Interrupt mask register #0 read/write */
4696 #define XCM_REG_XCM_INT_MASK 0x202b4
4697 /* [R 14] Interrupt register #0 read */
4698 #define XCM_REG_XCM_INT_STS 0x202a8
4699 /* [R 30] Parity register #0 read */
4700 #define XCM_REG_XCM_PRTY_STS 0x202b8
4701 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
4702 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4703 Is used to determine the number of the AG context REG-pairs written back;
4704 when the Reg1WbFlg isn't set. */
4705 #define XCM_REG_XCM_REG0_SZ 0x200f4
4706 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4707 disregarded; valid is deasserted; all other signals are treated as usual;
4708 if 1 - normal activity. */
4709 #define XCM_REG_XCM_STORM0_IFEN 0x20004
4710 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4711 disregarded; valid is deasserted; all other signals are treated as usual;
4712 if 1 - normal activity. */
4713 #define XCM_REG_XCM_STORM1_IFEN 0x20008
4714 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4715 disregarded; acknowledge output is deasserted; all other signals are
4716 treated as usual; if 1 - normal activity. */
4717 #define XCM_REG_XCM_TM_IFEN 0x20020
4718 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4719 disregarded; valid is deasserted; all other signals are treated as usual;
4720 if 1 - normal activity. */
4721 #define XCM_REG_XCM_XQM_IFEN 0x2000c
4722 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4723 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
4724 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
4725 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
4726 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4727 the initial credit value; read returns the current value of the credit
4728 counter. Must be initialized to 32 at start-up. */
4729 #define XCM_REG_XQM_INIT_CRD 0x20420
4730 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4731 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4732 prioritised); 2 stands for weight 2; tc. */
4733 #define XCM_REG_XQM_P_WEIGHT 0x200e4
4734 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4735 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4736 prioritised); 2 stands for weight 2; tc. */
4737 #define XCM_REG_XQM_S_WEIGHT 0x200e8
4738 /* [RW 28] The CM header value for QM request (primary). */
4739 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
4740 /* [RW 28] The CM header value for QM request (secondary). */
4741 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
4742 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4743 acknowledge output is deasserted; all other signals are treated as usual;
4744 if 1 - normal activity. */
4745 #define XCM_REG_XQM_XCM_IFEN 0x20014
4746 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4747 acknowledge output is deasserted; all other signals are treated as usual;
4748 if 1 - normal activity. */
4749 #define XCM_REG_XSDM_IFEN 0x20018
4750 /* [RC 1] Set at message length mismatch (relative to last indication) at
4751 the SDM interface. */
4752 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
4753 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4754 weight 8 (the most prioritised); 1 stands for weight 1(least
4755 prioritised); 2 stands for weight 2; tc. */
4756 #define XCM_REG_XSDM_WEIGHT 0x200e0
4757 /* [RW 17] Indirect access to the descriptor table of the XX protection
4758 mechanism. The fields are: [5:0] - message length; 11:6] - message
4759 pointer; 16:12] - next pointer. */
4760 #define XCM_REG_XX_DESCR_TABLE 0x20480
4761 #define XCM_REG_XX_DESCR_TABLE_SIZE 32
4762 /* [R 6] Used to read the XX protection Free counter. */
4763 #define XCM_REG_XX_FREE 0x20240
4764 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4765 of the Input Stage XX protection buffer by the XX protection pending
4766 messages. Max credit available - 3.Write writes the initial credit value;
4767 read returns the current value of the credit counter. Must be initialized
4768 to 2 at start-up. */
4769 #define XCM_REG_XX_INIT_CRD 0x20424
4770 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4771 protection. ~xcm_registers_xx_free.xx_free read on read. */
4772 #define XCM_REG_XX_MSG_NUM 0x20428
4773 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4774 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
4775 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4776 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
4777 header pointer. */
4778 #define XCM_REG_XX_TABLE 0x20500
4779 /* [RW 8] The event id for aggregated interrupt 0 */
4780 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
4781 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
4782 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
4783 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
4784 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
4785 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4786 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
4787 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
4788 #define XSDM_REG_AGG_INT_EVENT_3 0x166044
4789 #define XSDM_REG_AGG_INT_EVENT_4 0x166048
4790 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c
4791 #define XSDM_REG_AGG_INT_EVENT_6 0x166050
4792 #define XSDM_REG_AGG_INT_EVENT_7 0x166054
4793 #define XSDM_REG_AGG_INT_EVENT_8 0x166058
4794 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c
4795 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4796 or auto-mask-mode (1) */
4797 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
4798 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
4799 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4800 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
4801 /* [RW 16] The maximum value of the completion counter #0 */
4802 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
4803 /* [RW 16] The maximum value of the completion counter #1 */
4804 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
4805 /* [RW 16] The maximum value of the completion counter #2 */
4806 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
4807 /* [RW 16] The maximum value of the completion counter #3 */
4808 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
4809 /* [RW 13] The start address in the internal RAM for the completion
4810 counters. */
4811 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
4812 #define XSDM_REG_ENABLE_IN1 0x166238
4813 #define XSDM_REG_ENABLE_IN2 0x16623c
4814 #define XSDM_REG_ENABLE_OUT1 0x166240
4815 #define XSDM_REG_ENABLE_OUT2 0x166244
4816 /* [RW 4] The initial number of messages that can be sent to the pxp control
4817 interface without receiving any ACK. */
4818 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
4819 /* [ST 32] The number of ACK after placement messages received */
4820 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
4821 /* [ST 32] The number of packet end messages received from the parser */
4822 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
4823 /* [ST 32] The number of requests received from the pxp async if */
4824 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
4825 /* [ST 32] The number of commands received in queue 0 */
4826 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
4827 /* [ST 32] The number of commands received in queue 10 */
4828 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
4829 /* [ST 32] The number of commands received in queue 11 */
4830 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
4831 /* [ST 32] The number of commands received in queue 1 */
4832 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
4833 /* [ST 32] The number of commands received in queue 3 */
4834 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
4835 /* [ST 32] The number of commands received in queue 4 */
4836 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
4837 /* [ST 32] The number of commands received in queue 5 */
4838 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
4839 /* [ST 32] The number of commands received in queue 6 */
4840 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
4841 /* [ST 32] The number of commands received in queue 7 */
4842 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
4843 /* [ST 32] The number of commands received in queue 8 */
4844 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
4845 /* [ST 32] The number of commands received in queue 9 */
4846 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
4847 /* [RW 13] The start address in the internal RAM for queue counters */
4848 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
4849 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4850 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
4851 /* [R 1] parser fifo empty in sdm_sync block */
4852 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
4853 /* [R 1] parser serial fifo empty in sdm_sync block */
4854 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
4855 /* [RW 32] Tick for timer counter. Applicable only when
4856 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4857 #define XSDM_REG_TIMER_TICK 0x166000
4858 /* [RW 32] Interrupt mask register #0 read/write */
4859 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
4860 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
4861 /* [R 32] Interrupt register #0 read */
4862 #define XSDM_REG_XSDM_INT_STS_0 0x166290
4863 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0
4864 /* [RW 11] Parity mask register #0 read/write */
4865 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
4866 /* [R 11] Parity register #0 read */
4867 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0
4868 /* [RC 11] Parity register #0 read clear */
4869 #define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4
4870 /* [RW 5] The number of time_slots in the arbitration cycle */
4871 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
4872 /* [RW 3] The source that is associated with arbitration element 0. Source
4873 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4874 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4875 #define XSEM_REG_ARB_ELEMENT0 0x280020
4876 /* [RW 3] The source that is associated with arbitration element 1. Source
4877 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4878 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4879 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
4880 #define XSEM_REG_ARB_ELEMENT1 0x280024
4881 /* [RW 3] The source that is associated with arbitration element 2. Source
4882 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4883 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4884 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
4885 and ~xsem_registers_arb_element1.arb_element1 */
4886 #define XSEM_REG_ARB_ELEMENT2 0x280028
4887 /* [RW 3] The source that is associated with arbitration element 3. Source
4888 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4889 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4890 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
4891 ~xsem_registers_arb_element1.arb_element1 and
4892 ~xsem_registers_arb_element2.arb_element2 */
4893 #define XSEM_REG_ARB_ELEMENT3 0x28002c
4894 /* [RW 3] The source that is associated with arbitration element 4. Source
4895 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4896 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4897 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
4898 and ~xsem_registers_arb_element1.arb_element1 and
4899 ~xsem_registers_arb_element2.arb_element2 and
4900 ~xsem_registers_arb_element3.arb_element3 */
4901 #define XSEM_REG_ARB_ELEMENT4 0x280030
4902 #define XSEM_REG_ENABLE_IN 0x2800a4
4903 #define XSEM_REG_ENABLE_OUT 0x2800a8
4904 /* [RW 32] This address space contains all registers and memories that are
4905 placed in SEM_FAST block. The SEM_FAST registers are described in
4906 appendix B. In order to access the sem_fast registers the base address
4907 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4908 #define XSEM_REG_FAST_MEMORY 0x2a0000
4909 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4910 by the microcode */
4911 #define XSEM_REG_FIC0_DISABLE 0x280224
4912 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4913 by the microcode */
4914 #define XSEM_REG_FIC1_DISABLE 0x280234
4915 /* [RW 15] Interrupt table Read and write access to it is not possible in
4916 the middle of the work */
4917 #define XSEM_REG_INT_TABLE 0x280400
4918 /* [ST 24] Statistics register. The number of messages that entered through
4919 FIC0 */
4920 #define XSEM_REG_MSG_NUM_FIC0 0x280000
4921 /* [ST 24] Statistics register. The number of messages that entered through
4922 FIC1 */
4923 #define XSEM_REG_MSG_NUM_FIC1 0x280004
4924 /* [ST 24] Statistics register. The number of messages that were sent to
4925 FOC0 */
4926 #define XSEM_REG_MSG_NUM_FOC0 0x280008
4927 /* [ST 24] Statistics register. The number of messages that were sent to
4928 FOC1 */
4929 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
4930 /* [ST 24] Statistics register. The number of messages that were sent to
4931 FOC2 */
4932 #define XSEM_REG_MSG_NUM_FOC2 0x280010
4933 /* [ST 24] Statistics register. The number of messages that were sent to
4934 FOC3 */
4935 #define XSEM_REG_MSG_NUM_FOC3 0x280014
4936 /* [RW 1] Disables input messages from the passive buffer May be updated
4937 during run_time by the microcode */
4938 #define XSEM_REG_PAS_DISABLE 0x28024c
4939 /* [WB 128] Debug only. Passive buffer memory */
4940 #define XSEM_REG_PASSIVE_BUFFER 0x282000
4941 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4942 #define XSEM_REG_PRAM 0x2c0000
4943 /* [R 16] Valid sleeping threads indication have bit per thread */
4944 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
4945 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4946 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
4947 /* [RW 16] List of free threads . There is a bit per thread. */
4948 #define XSEM_REG_THREADS_LIST 0x2802e4
4949 /* [RW 3] The arbitration scheme of time_slot 0 */
4950 #define XSEM_REG_TS_0_AS 0x280038
4951 /* [RW 3] The arbitration scheme of time_slot 10 */
4952 #define XSEM_REG_TS_10_AS 0x280060
4953 /* [RW 3] The arbitration scheme of time_slot 11 */
4954 #define XSEM_REG_TS_11_AS 0x280064
4955 /* [RW 3] The arbitration scheme of time_slot 12 */
4956 #define XSEM_REG_TS_12_AS 0x280068
4957 /* [RW 3] The arbitration scheme of time_slot 13 */
4958 #define XSEM_REG_TS_13_AS 0x28006c
4959 /* [RW 3] The arbitration scheme of time_slot 14 */
4960 #define XSEM_REG_TS_14_AS 0x280070
4961 /* [RW 3] The arbitration scheme of time_slot 15 */
4962 #define XSEM_REG_TS_15_AS 0x280074
4963 /* [RW 3] The arbitration scheme of time_slot 16 */
4964 #define XSEM_REG_TS_16_AS 0x280078
4965 /* [RW 3] The arbitration scheme of time_slot 17 */
4966 #define XSEM_REG_TS_17_AS 0x28007c
4967 /* [RW 3] The arbitration scheme of time_slot 18 */
4968 #define XSEM_REG_TS_18_AS 0x280080
4969 /* [RW 3] The arbitration scheme of time_slot 1 */
4970 #define XSEM_REG_TS_1_AS 0x28003c
4971 /* [RW 3] The arbitration scheme of time_slot 2 */
4972 #define XSEM_REG_TS_2_AS 0x280040
4973 /* [RW 3] The arbitration scheme of time_slot 3 */
4974 #define XSEM_REG_TS_3_AS 0x280044
4975 /* [RW 3] The arbitration scheme of time_slot 4 */
4976 #define XSEM_REG_TS_4_AS 0x280048
4977 /* [RW 3] The arbitration scheme of time_slot 5 */
4978 #define XSEM_REG_TS_5_AS 0x28004c
4979 /* [RW 3] The arbitration scheme of time_slot 6 */
4980 #define XSEM_REG_TS_6_AS 0x280050
4981 /* [RW 3] The arbitration scheme of time_slot 7 */
4982 #define XSEM_REG_TS_7_AS 0x280054
4983 /* [RW 3] The arbitration scheme of time_slot 8 */
4984 #define XSEM_REG_TS_8_AS 0x280058
4985 /* [RW 3] The arbitration scheme of time_slot 9 */
4986 #define XSEM_REG_TS_9_AS 0x28005c
4987 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4988 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4989 #define XSEM_REG_VFPF_ERR_NUM 0x280380
4990 /* [RW 32] Interrupt mask register #0 read/write */
4991 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
4992 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
4993 /* [R 32] Interrupt register #0 read */
4994 #define XSEM_REG_XSEM_INT_STS_0 0x280104
4995 #define XSEM_REG_XSEM_INT_STS_1 0x280114
4996 /* [RW 32] Parity mask register #0 read/write */
4997 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
4998 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
4999 /* [R 32] Parity register #0 read */
5000 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124
5001 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134
5002 /* [RC 32] Parity register #0 read clear */
5003 #define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
5004 #define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
5005 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5006 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
5007 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
5008 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
5009 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
5010 #define MCPR_NVM_COMMAND_DONE (1L<<3)
5011 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
5012 #define MCPR_NVM_COMMAND_LAST (1L<<8)
5013 #define MCPR_NVM_COMMAND_WR (1L<<5)
5014 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
5015 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
5016 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
5017 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
5018 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5019 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
5020 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
5021 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
5022 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
5023 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
5024 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
5025 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
5026 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
5027 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
5028 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
5029 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
5030 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
5031 #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
5032 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5033 #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
5034 #define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
5035 #define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
5036 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
5037 #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
5038 #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
5039 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
5040 #define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3)
5041 #define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
5042 #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
5043 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
5044 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
5045 #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
5046 #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
5047 #define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3)
5048 #define EMAC_LED_1000MB_OVERRIDE (1L<<1)
5049 #define EMAC_LED_100MB_OVERRIDE (1L<<2)
5050 #define EMAC_LED_10MB_OVERRIDE (1L<<3)
5051 #define EMAC_LED_2500MB_OVERRIDE (1L<<12)
5052 #define EMAC_LED_OVERRIDE (1L<<0)
5053 #define EMAC_LED_TRAFFIC (1L<<6)
5054 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
5055 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
5056 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
5057 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
5058 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
5059 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
5060 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
5061 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
5062 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
5063 #define EMAC_MODE_25G_MODE (1L<<5)
5064 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
5065 #define EMAC_MODE_PORT_GMII (2L<<2)
5066 #define EMAC_MODE_PORT_MII (1L<<2)
5067 #define EMAC_MODE_PORT_MII_10M (3L<<2)
5068 #define EMAC_MODE_RESET (1L<<0)
5069 #define EMAC_REG_EMAC_LED 0xc
5070 #define EMAC_REG_EMAC_MAC_MATCH 0x10
5071 #define EMAC_REG_EMAC_MDIO_COMM 0xac
5072 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
5073 #define EMAC_REG_EMAC_MODE 0x0
5074 #define EMAC_REG_EMAC_RX_MODE 0xc8
5075 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
5076 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
5077 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
5078 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
5079 #define EMAC_REG_EMAC_TX_MODE 0xbc
5080 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
5081 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
5082 #define EMAC_REG_RX_PFC_MODE 0x320
5083 #define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
5084 #define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
5085 #define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
5086 #define EMAC_REG_RX_PFC_PARAM 0x324
5087 #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
5088 #define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
5089 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
5090 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
5091 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
5092 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
5093 #define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
5094 #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
5095 #define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
5096 #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
5097 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
5098 #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
5099 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
5100 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
5101 #define EMAC_RX_MODE_RESET (1L<<0)
5102 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
5103 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
5104 #define EMAC_TX_MODE_FLOW_EN (1L<<4)
5105 #define EMAC_TX_MODE_RESET (1L<<0)
5106 #define MISC_REGISTERS_GPIO_0 0
5107 #define MISC_REGISTERS_GPIO_1 1
5108 #define MISC_REGISTERS_GPIO_2 2
5109 #define MISC_REGISTERS_GPIO_3 3
5110 #define MISC_REGISTERS_GPIO_CLR_POS 16
5111 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
5112 #define MISC_REGISTERS_GPIO_FLOAT_POS 24
5113 #define MISC_REGISTERS_GPIO_HIGH 1
5114 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
5115 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24
5116 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
5117 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
5118 #define MISC_REGISTERS_GPIO_INT_SET_POS 16
5119 #define MISC_REGISTERS_GPIO_LOW 0
5120 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
5121 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
5122 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4
5123 #define MISC_REGISTERS_GPIO_SET_POS 8
5124 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
5125 #define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
5126 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
5127 #define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
5128 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
5129 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
5130 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
5131 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
5132 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
5133 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
5134 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
5135 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
5136 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
5137 #define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
5138 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
5139 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
5140 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
5141 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5142 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5143 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
5144 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
5145 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
5146 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
5147 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
5148 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
5149 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
5150 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
5151 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
5152 #define MISC_REGISTERS_SPIO_4 4
5153 #define MISC_REGISTERS_SPIO_5 5
5154 #define MISC_REGISTERS_SPIO_7 7
5155 #define MISC_REGISTERS_SPIO_CLR_POS 16
5156 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
5157 #define MISC_REGISTERS_SPIO_FLOAT_POS 24
5158 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5159 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
5160 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5161 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5162 #define MISC_REGISTERS_SPIO_SET_POS 8
5163 #define HW_LOCK_MAX_RESOURCE_VALUE 31
5164 #define HW_LOCK_RESOURCE_GPIO 1
5165 #define HW_LOCK_RESOURCE_MDIO 0
5166 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5167 #define HW_LOCK_RESOURCE_RESERVED_08 8
5168 #define HW_LOCK_RESOURCE_SPIO 2
5169 #define HW_LOCK_RESOURCE_UNDI 5
5170 #define PRS_FLAG_OVERETH_IPV4 1
5171 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
5172 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
5173 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
5174 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
5175 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
5176 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
5177 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
5178 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
5179 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
5180 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
5181 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
5182 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
5183 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
5184 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
5185 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
5186 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
5187 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1<<5)
5188 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1<<9)
5189 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
5190 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (1<<28)
5191 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (1<<31)
5192 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (1<<29)
5193 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (1<<30)
5194 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
5195 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
5196 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
5197 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
5198 #define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
5199 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
5200 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
5201 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
5202 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
5203 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
5204 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
5205 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
5206 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
5207 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
5208 #define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15)
5209 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
5210 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
5211 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
5212 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
5213 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
5214 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
5215 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
5216 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
5217 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
5218 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
5219 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
5220 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
5221 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
5222 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
5223 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
5224 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
5225 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
5226 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
5227 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
5228 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
5229
5230 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0
5231 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5232
5233 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
5234 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
5235 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
5236 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
5237 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
5238 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
5239 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
5240 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
5241 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
5242 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
5243 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
5244 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
5245 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
5246 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
5247 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
5248 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
5249
5250 /* storm asserts attention bits */
5251 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
5252 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
5253 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
5254 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
5255
5256 /* mcp error attention bit */
5257 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
5258
5259 /*E1H NIG status sync attention mapped to group 4-7*/
5260 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5261 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5262 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5263 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5264 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5265 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5266 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5267 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5268
5269
5270 #define LATCHED_ATTN_RBCR 23
5271 #define LATCHED_ATTN_RBCT 24
5272 #define LATCHED_ATTN_RBCN 25
5273 #define LATCHED_ATTN_RBCU 26
5274 #define LATCHED_ATTN_RBCP 27
5275 #define LATCHED_ATTN_TIMEOUT_GRC 28
5276 #define LATCHED_ATTN_RSVD_GRC 29
5277 #define LATCHED_ATTN_ROM_PARITY_MCP 30
5278 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
5279 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
5280 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
5281
5282 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
5283 #define GENERAL_ATTEN_OFFSET(atten_name)\
5284 (1UL << ((94 + atten_name) % 32))
5285 /*
5286 * This file defines GRC base address for every block.
5287 * This file is included by chipsim, asm microcode and cpp microcode.
5288 * These values are used in Design.xml on regBase attribute
5289 * Use the base with the generated offsets of specific registers.
5290 */
5291
5292 #define GRCBASE_PXPCS 0x000000
5293 #define GRCBASE_PCICONFIG 0x002000
5294 #define GRCBASE_PCIREG 0x002400
5295 #define GRCBASE_EMAC0 0x008000
5296 #define GRCBASE_EMAC1 0x008400
5297 #define GRCBASE_DBU 0x008800
5298 #define GRCBASE_MISC 0x00A000
5299 #define GRCBASE_DBG 0x00C000
5300 #define GRCBASE_NIG 0x010000
5301 #define GRCBASE_XCM 0x020000
5302 #define GRCBASE_PRS 0x040000
5303 #define GRCBASE_SRCH 0x040400
5304 #define GRCBASE_TSDM 0x042000
5305 #define GRCBASE_TCM 0x050000
5306 #define GRCBASE_BRB1 0x060000
5307 #define GRCBASE_MCP 0x080000
5308 #define GRCBASE_UPB 0x0C1000
5309 #define GRCBASE_CSDM 0x0C2000
5310 #define GRCBASE_USDM 0x0C4000
5311 #define GRCBASE_CCM 0x0D0000
5312 #define GRCBASE_UCM 0x0E0000
5313 #define GRCBASE_CDU 0x101000
5314 #define GRCBASE_DMAE 0x102000
5315 #define GRCBASE_PXP 0x103000
5316 #define GRCBASE_CFC 0x104000
5317 #define GRCBASE_HC 0x108000
5318 #define GRCBASE_PXP2 0x120000
5319 #define GRCBASE_PBF 0x140000
5320 #define GRCBASE_XPB 0x161000
5321 #define GRCBASE_TIMERS 0x164000
5322 #define GRCBASE_XSDM 0x166000
5323 #define GRCBASE_QM 0x168000
5324 #define GRCBASE_DQ 0x170000
5325 #define GRCBASE_TSEM 0x180000
5326 #define GRCBASE_CSEM 0x200000
5327 #define GRCBASE_XSEM 0x280000
5328 #define GRCBASE_USEM 0x300000
5329 #define GRCBASE_MISC_AEU GRCBASE_MISC
5330
5331
5332 /* offset of configuration space in the pci core register */
5333 #define PCICFG_OFFSET 0x2000
5334 #define PCICFG_VENDOR_ID_OFFSET 0x00
5335 #define PCICFG_DEVICE_ID_OFFSET 0x02
5336 #define PCICFG_COMMAND_OFFSET 0x04
5337 #define PCICFG_COMMAND_IO_SPACE (1<<0)
5338 #define PCICFG_COMMAND_MEM_SPACE (1<<1)
5339 #define PCICFG_COMMAND_BUS_MASTER (1<<2)
5340 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5341 #define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5342 #define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5343 #define PCICFG_COMMAND_PERR_ENA (1<<6)
5344 #define PCICFG_COMMAND_STEPPING (1<<7)
5345 #define PCICFG_COMMAND_SERR_ENA (1<<8)
5346 #define PCICFG_COMMAND_FAST_B2B (1<<9)
5347 #define PCICFG_COMMAND_INT_DISABLE (1<<10)
5348 #define PCICFG_COMMAND_RESERVED (0x1f<<11)
5349 #define PCICFG_STATUS_OFFSET 0x06
5350 #define PCICFG_REVESION_ID_OFFSET 0x08
5351 #define PCICFG_CACHE_LINE_SIZE 0x0c
5352 #define PCICFG_LATENCY_TIMER 0x0d
5353 #define PCICFG_BAR_1_LOW 0x10
5354 #define PCICFG_BAR_1_HIGH 0x14
5355 #define PCICFG_BAR_2_LOW 0x18
5356 #define PCICFG_BAR_2_HIGH 0x1c
5357 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
5358 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
5359 #define PCICFG_INT_LINE 0x3c
5360 #define PCICFG_INT_PIN 0x3d
5361 #define PCICFG_PM_CAPABILITY 0x48
5362 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
5363 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
5364 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
5365 #define PCICFG_PM_CAPABILITY_DSI (1<<21)
5366 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
5367 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
5368 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
5369 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
5370 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
5371 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
5372 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
5373 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
5374 #define PCICFG_PM_CSR_OFFSET 0x4c
5375 #define PCICFG_PM_CSR_STATE (0x3<<0)
5376 #define PCICFG_PM_CSR_PME_ENABLE (1<<8)
5377 #define PCICFG_PM_CSR_PME_STATUS (1<<15)
5378 #define PCICFG_MSI_CAP_ID_OFFSET 0x58
5379 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
5380 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
5381 #define PCICFG_MSI_CONTROL_MENA (0x7<<20)
5382 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
5383 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
5384 #define PCICFG_GRC_ADDRESS 0x78
5385 #define PCICFG_GRC_DATA 0x80
5386 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
5387 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
5388 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
5389 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
5390 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
5391
5392 #define PCICFG_DEVICE_CONTROL 0xb4
5393 #define PCICFG_DEVICE_STATUS 0xb6
5394 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
5395 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
5396 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
5397 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
5398 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
5399 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
5400 #define PCICFG_LINK_CONTROL 0xbc
5401
5402
5403 #define BAR_USTRORM_INTMEM 0x400000
5404 #define BAR_CSTRORM_INTMEM 0x410000
5405 #define BAR_XSTRORM_INTMEM 0x420000
5406 #define BAR_TSTRORM_INTMEM 0x430000
5407
5408 /* for accessing the IGU in case of status block ACK */
5409 #define BAR_IGU_INTMEM 0x440000
5410
5411 #define BAR_DOORBELL_OFFSET 0x800000
5412
5413 #define BAR_ME_REGISTER 0x450000
5414
5415 /* config_2 offset */
5416 #define GRC_CONFIG_2_SIZE_REG 0x408
5417 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
5418 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
5419 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
5420 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
5421 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
5422 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
5423 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
5424 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
5425 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
5426 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
5427 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
5428 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
5429 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
5430 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
5431 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
5432 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
5433 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
5434 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
5435 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
5436 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
5437 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
5438 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
5439 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
5440 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
5441 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
5442 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
5443 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
5444 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
5445 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
5446 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
5447 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
5448 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
5449 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
5450 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
5451 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
5452 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
5453 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
5454 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
5455 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
5456 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
5457
5458 /* config_3 offset */
5459 #define GRC_CONFIG_3_SIZE_REG 0x40c
5460 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
5461 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
5462 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
5463 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
5464 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
5465 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
5466 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
5467
5468 #define GRC_BAR2_CONFIG 0x4e0
5469 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
5470 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
5471 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
5472 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
5473 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
5474 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
5475 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
5476 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
5477 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
5478 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
5479 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
5480 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
5481 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
5482 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
5483 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
5484 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
5485 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
5486 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
5487
5488 #define PCI_PM_DATA_A 0x410
5489 #define PCI_PM_DATA_B 0x414
5490 #define PCI_ID_VAL1 0x434
5491 #define PCI_ID_VAL2 0x438
5492
5493 #define PXPCS_TL_CONTROL_5 0x814
5494 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/
5495 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/
5496 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/
5497 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/
5498 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/
5499 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/
5500 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/
5501 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/
5502 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/
5503 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/
5504 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/
5505 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/
5506 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/
5507 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/
5508 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/
5509 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/
5510 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/
5511 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/
5512 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/
5513 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/
5514 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/
5515 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/
5516 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/
5517 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/
5518 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/
5519 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/
5520 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/
5521 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/
5522 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/
5523 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/
5524
5525
5526 #define PXPCS_TL_FUNC345_STAT 0x854
5527 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */
5528 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\
5529 (1 << 28) /* Unsupported Request Error Status in function4, if \
5530 set, generate pcie_err_attn output when this error is seen. WC */
5531 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\
5532 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
5533 generate pcie_err_attn output when this error is seen.. WC */
5534 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\
5535 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \
5536 generate pcie_err_attn output when this error is seen.. WC */
5537 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\
5538 (1 << 25) /* Receiver Overflow Status Status in function 4, if \
5539 set, generate pcie_err_attn output when this error is seen.. WC \
5540 */
5541 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\
5542 (1 << 24) /* Unexpected Completion Status Status in function 4, \
5543 if set, generate pcie_err_attn output when this error is seen. WC \
5544 */
5545 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\
5546 (1 << 23) /* Receive UR Statusin function 4. If set, generate \
5547 pcie_err_attn output when this error is seen. WC */
5548 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\
5549 (1 << 22) /* Completer Timeout Status Status in function 4, if \
5550 set, generate pcie_err_attn output when this error is seen. WC */
5551 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\
5552 (1 << 21) /* Flow Control Protocol Error Status Status in \
5553 function 4, if set, generate pcie_err_attn output when this error \
5554 is seen. WC */
5555 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\
5556 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \
5557 generate pcie_err_attn output when this error is seen.. WC */
5558 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */
5559 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\
5560 (1 << 18) /* Unsupported Request Error Status in function3, if \
5561 set, generate pcie_err_attn output when this error is seen. WC */
5562 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\
5563 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
5564 generate pcie_err_attn output when this error is seen.. WC */
5565 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\
5566 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \
5567 generate pcie_err_attn output when this error is seen.. WC */
5568 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\
5569 (1 << 15) /* Receiver Overflow Status Status in function 3, if \
5570 set, generate pcie_err_attn output when this error is seen.. WC \
5571 */
5572 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\
5573 (1 << 14) /* Unexpected Completion Status Status in function 3, \
5574 if set, generate pcie_err_attn output when this error is seen. WC \
5575 */
5576 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\
5577 (1 << 13) /* Receive UR Statusin function 3. If set, generate \
5578 pcie_err_attn output when this error is seen. WC */
5579 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\
5580 (1 << 12) /* Completer Timeout Status Status in function 3, if \
5581 set, generate pcie_err_attn output when this error is seen. WC */
5582 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\
5583 (1 << 11) /* Flow Control Protocol Error Status Status in \
5584 function 3, if set, generate pcie_err_attn output when this error \
5585 is seen. WC */
5586 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\
5587 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \
5588 generate pcie_err_attn output when this error is seen.. WC */
5589 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */
5590 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\
5591 (1 << 8) /* Unsupported Request Error Status for Function 2, if \
5592 set, generate pcie_err_attn output when this error is seen. WC */
5593 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\
5594 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
5595 generate pcie_err_attn output when this error is seen.. WC */
5596 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\
5597 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
5598 generate pcie_err_attn output when this error is seen.. WC */
5599 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\
5600 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \
5601 set, generate pcie_err_attn output when this error is seen.. WC \
5602 */
5603 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\
5604 (1 << 4) /* Unexpected Completion Status Status for Function 2, \
5605 if set, generate pcie_err_attn output when this error is seen. WC \
5606 */
5607 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\
5608 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
5609 pcie_err_attn output when this error is seen. WC */
5610 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\
5611 (1 << 2) /* Completer Timeout Status Status for Function 2, if \
5612 set, generate pcie_err_attn output when this error is seen. WC */
5613 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\
5614 (1 << 1) /* Flow Control Protocol Error Status Status for \
5615 Function 2, if set, generate pcie_err_attn output when this error \
5616 is seen. WC */
5617 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\
5618 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
5619 generate pcie_err_attn output when this error is seen.. WC */
5620
5621
5622 #define PXPCS_TL_FUNC678_STAT 0x85C
5623 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */
5624 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\
5625 (1 << 28) /* Unsupported Request Error Status in function7, if \
5626 set, generate pcie_err_attn output when this error is seen. WC */
5627 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\
5628 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
5629 generate pcie_err_attn output when this error is seen.. WC */
5630 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\
5631 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \
5632 generate pcie_err_attn output when this error is seen.. WC */
5633 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\
5634 (1 << 25) /* Receiver Overflow Status Status in function 7, if \
5635 set, generate pcie_err_attn output when this error is seen.. WC \
5636 */
5637 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\
5638 (1 << 24) /* Unexpected Completion Status Status in function 7, \
5639 if set, generate pcie_err_attn output when this error is seen. WC \
5640 */
5641 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\
5642 (1 << 23) /* Receive UR Statusin function 7. If set, generate \
5643 pcie_err_attn output when this error is seen. WC */
5644 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\
5645 (1 << 22) /* Completer Timeout Status Status in function 7, if \
5646 set, generate pcie_err_attn output when this error is seen. WC */
5647 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\
5648 (1 << 21) /* Flow Control Protocol Error Status Status in \
5649 function 7, if set, generate pcie_err_attn output when this error \
5650 is seen. WC */
5651 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\
5652 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \
5653 generate pcie_err_attn output when this error is seen.. WC */
5654 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */
5655 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\
5656 (1 << 18) /* Unsupported Request Error Status in function6, if \
5657 set, generate pcie_err_attn output when this error is seen. WC */
5658 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\
5659 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
5660 generate pcie_err_attn output when this error is seen.. WC */
5661 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\
5662 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \
5663 generate pcie_err_attn output when this error is seen.. WC */
5664 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\
5665 (1 << 15) /* Receiver Overflow Status Status in function 6, if \
5666 set, generate pcie_err_attn output when this error is seen.. WC \
5667 */
5668 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\
5669 (1 << 14) /* Unexpected Completion Status Status in function 6, \
5670 if set, generate pcie_err_attn output when this error is seen. WC \
5671 */
5672 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\
5673 (1 << 13) /* Receive UR Statusin function 6. If set, generate \
5674 pcie_err_attn output when this error is seen. WC */
5675 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\
5676 (1 << 12) /* Completer Timeout Status Status in function 6, if \
5677 set, generate pcie_err_attn output when this error is seen. WC */
5678 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\
5679 (1 << 11) /* Flow Control Protocol Error Status Status in \
5680 function 6, if set, generate pcie_err_attn output when this error \
5681 is seen. WC */
5682 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\
5683 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \
5684 generate pcie_err_attn output when this error is seen.. WC */
5685 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */
5686 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\
5687 (1 << 8) /* Unsupported Request Error Status for Function 5, if \
5688 set, generate pcie_err_attn output when this error is seen. WC */
5689 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\
5690 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
5691 generate pcie_err_attn output when this error is seen.. WC */
5692 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\
5693 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
5694 generate pcie_err_attn output when this error is seen.. WC */
5695 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\
5696 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \
5697 set, generate pcie_err_attn output when this error is seen.. WC \
5698 */
5699 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\
5700 (1 << 4) /* Unexpected Completion Status Status for Function 5, \
5701 if set, generate pcie_err_attn output when this error is seen. WC \
5702 */
5703 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\
5704 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
5705 pcie_err_attn output when this error is seen. WC */
5706 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\
5707 (1 << 2) /* Completer Timeout Status Status for Function 5, if \
5708 set, generate pcie_err_attn output when this error is seen. WC */
5709 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\
5710 (1 << 1) /* Flow Control Protocol Error Status Status for \
5711 Function 5, if set, generate pcie_err_attn output when this error \
5712 is seen. WC */
5713 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\
5714 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
5715 generate pcie_err_attn output when this error is seen.. WC */
5716
5717
5718 #define BAR_USTRORM_INTMEM 0x400000
5719 #define BAR_CSTRORM_INTMEM 0x410000
5720 #define BAR_XSTRORM_INTMEM 0x420000
5721 #define BAR_TSTRORM_INTMEM 0x430000
5722
5723 /* for accessing the IGU in case of status block ACK */
5724 #define BAR_IGU_INTMEM 0x440000
5725
5726 #define BAR_DOORBELL_OFFSET 0x800000
5727
5728 #define BAR_ME_REGISTER 0x450000
5729 #define ME_REG_PF_NUM_SHIFT 0
5730 #define ME_REG_PF_NUM\
5731 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
5732 #define ME_REG_VF_VALID (1<<8)
5733 #define ME_REG_VF_NUM_SHIFT 9
5734 #define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
5735 #define ME_REG_VF_ERR (0x1<<3)
5736 #define ME_REG_ABS_PF_NUM_SHIFT 16
5737 #define ME_REG_ABS_PF_NUM\
5738 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
5739
5740
5741 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
5742 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
5743 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
5744 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
5745 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
5746
5747 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
5748 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
5749 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
5750 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
5751 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
5752 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
5753 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
5754 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
5755 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
5756 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
5757 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
5758 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
5759 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
5760 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
5761 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
5762 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
5763
5764 #define MDIO_REG_BANK_RX0 0x80b0
5765 #define MDIO_RX0_RX_STATUS 0x10
5766 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
5767 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
5768 #define MDIO_RX0_RX_EQ_BOOST 0x1c
5769 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5770 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
5771
5772 #define MDIO_REG_BANK_RX1 0x80c0
5773 #define MDIO_RX1_RX_EQ_BOOST 0x1c
5774 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5775 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
5776
5777 #define MDIO_REG_BANK_RX2 0x80d0
5778 #define MDIO_RX2_RX_EQ_BOOST 0x1c
5779 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5780 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
5781
5782 #define MDIO_REG_BANK_RX3 0x80e0
5783 #define MDIO_RX3_RX_EQ_BOOST 0x1c
5784 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5785 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
5786
5787 #define MDIO_REG_BANK_RX_ALL 0x80f0
5788 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
5789 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5790 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
5791
5792 #define MDIO_REG_BANK_TX0 0x8060
5793 #define MDIO_TX0_TX_DRIVER 0x17
5794 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5795 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5796 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5797 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5798 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5799 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5800 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5801 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5802 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5803
5804 #define MDIO_REG_BANK_TX1 0x8070
5805 #define MDIO_TX1_TX_DRIVER 0x17
5806 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5807 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5808 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5809 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5810 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5811 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5812 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5813 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5814 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5815
5816 #define MDIO_REG_BANK_TX2 0x8080
5817 #define MDIO_TX2_TX_DRIVER 0x17
5818 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5819 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5820 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5821 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5822 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5823 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5824 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5825 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5826 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5827
5828 #define MDIO_REG_BANK_TX3 0x8090
5829 #define MDIO_TX3_TX_DRIVER 0x17
5830 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5831 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5832 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5833 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5834 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5835 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5836 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5837 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5838 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5839
5840 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
5841 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
5842
5843 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
5844 #define MDIO_BLOCK1_LANE_CTRL0 0x15
5845 #define MDIO_BLOCK1_LANE_CTRL1 0x16
5846 #define MDIO_BLOCK1_LANE_CTRL2 0x17
5847 #define MDIO_BLOCK1_LANE_PRBS 0x19
5848
5849 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
5850 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
5851 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
5852 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
5853 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
5854 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
5855 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
5856 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
5857 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
5858 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
5859
5860 #define MDIO_REG_BANK_GP_STATUS 0x8120
5861 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
5862 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
5863 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
5864 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
5865 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
5866 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
5867 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
5868 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
5869 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
5870 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
5871 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
5872 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
5873 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
5874 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
5875 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
5876 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
5877 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
5878 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
5879 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
5880 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
5881 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
5882 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
5883 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
5884 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
5885 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
5886
5887
5888 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
5889 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
5890 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
5891 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
5892 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
5893 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
5894 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
5895
5896 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
5897 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
5898 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
5899 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
5900 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
5901 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
5902 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
5903 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
5904 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
5905 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
5906 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
5907 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
5908 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
5909 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
5910 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
5911 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
5912 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
5913 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
5914 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
5915 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
5916 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
5917 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
5918 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
5919 #define MDIO_SERDES_DIGITAL_MISC1 0x18
5920 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
5921 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
5922 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
5923 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
5924 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
5925 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
5926 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
5927 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
5928 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
5929 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
5930 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
5931 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
5932 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
5933 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
5934 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
5935 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
5936 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
5937 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
5938
5939 #define MDIO_REG_BANK_OVER_1G 0x8320
5940 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
5941 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
5942 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
5943 #define MDIO_OVER_1G_UP1 0x19
5944 #define MDIO_OVER_1G_UP1_2_5G 0x0001
5945 #define MDIO_OVER_1G_UP1_5G 0x0002
5946 #define MDIO_OVER_1G_UP1_6G 0x0004
5947 #define MDIO_OVER_1G_UP1_10G 0x0010
5948 #define MDIO_OVER_1G_UP1_10GH 0x0008
5949 #define MDIO_OVER_1G_UP1_12G 0x0020
5950 #define MDIO_OVER_1G_UP1_12_5G 0x0040
5951 #define MDIO_OVER_1G_UP1_13G 0x0080
5952 #define MDIO_OVER_1G_UP1_15G 0x0100
5953 #define MDIO_OVER_1G_UP1_16G 0x0200
5954 #define MDIO_OVER_1G_UP2 0x1A
5955 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
5956 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
5957 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
5958 #define MDIO_OVER_1G_UP3 0x1B
5959 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
5960 #define MDIO_OVER_1G_LP_UP1 0x1C
5961 #define MDIO_OVER_1G_LP_UP2 0x1D
5962 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
5963 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
5964 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
5965 #define MDIO_OVER_1G_LP_UP3 0x1E
5966
5967 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
5968 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
5969 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
5970 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
5971
5972 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
5973 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
5974 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
5975 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
5976
5977 #define MDIO_REG_BANK_CL73_USERB0 0x8370
5978 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
5979 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
5980 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
5981 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
5982 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
5983 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
5984 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
5985 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
5986 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
5987 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
5988 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
5989
5990 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
5991 #define MDIO_AER_BLOCK_AER_REG 0x1E
5992
5993 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
5994 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
5995 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
5996 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
5997 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
5998 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
5999 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
6000 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
6001 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
6002 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
6003 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
6004 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
6005 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
6006 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
6007 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
6008 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
6009 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
6010 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
6011 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
6012 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
6013 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
6014 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
6015 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
6016 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
6017 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
6018 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
6019 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
6020 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
6021 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
6022 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
6023 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
6024 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
6025 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
6026 Theotherbitsarereservedandshouldbezero*/
6027 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
6028
6029
6030 #define MDIO_PMA_DEVAD 0x1
6031 /*ieee*/
6032 #define MDIO_PMA_REG_CTRL 0x0
6033 #define MDIO_PMA_REG_STATUS 0x1
6034 #define MDIO_PMA_REG_10G_CTRL2 0x7
6035 #define MDIO_PMA_REG_RX_SD 0xa
6036 /*bcm*/
6037 #define MDIO_PMA_REG_BCM_CTRL 0x0096
6038 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
6039 #define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000
6040 #define MDIO_PMA_REG_LASI_CTRL 0x9002
6041 #define MDIO_PMA_REG_RX_ALARM 0x9003
6042 #define MDIO_PMA_REG_TX_ALARM 0x9004
6043 #define MDIO_PMA_REG_LASI_STATUS 0x9005
6044 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
6045 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
6046 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
6047 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
6048 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
6049 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
6050 #define MDIO_PMA_REG_GEN_CTRL 0xca10
6051 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
6052 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
6053 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
6054 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
6055 #define MDIO_PMA_REG_ROM_VER1 0xca19
6056 #define MDIO_PMA_REG_ROM_VER2 0xca1a
6057 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
6058 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
6059 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
6060 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
6061 #define MDIO_PMA_REG_LRM_MODE 0xca3f
6062 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
6063 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
6064
6065 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
6066 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
6067 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
6068 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
6069 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
6070 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
6071 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
6072 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
6073 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
6074 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
6075 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
6076 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
6077
6078 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
6079 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
6080 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
6081 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
6082 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
6083 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
6084 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
6085 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
6086 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
6087
6088 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
6089
6090 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
6091 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
6092 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
6093 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
6094
6095 #define MDIO_PMA_REG_7101_RESET 0xc000
6096 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
6097 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
6098 #define MDIO_PMA_REG_7101_VER1 0xc026
6099 #define MDIO_PMA_REG_7101_VER2 0xc027
6100
6101 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
6102 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
6103 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
6104 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
6105 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
6106 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
6107 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
6108 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
6109 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
6110 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
6111
6112
6113 #define MDIO_WIS_DEVAD 0x2
6114 /*bcm*/
6115 #define MDIO_WIS_REG_LASI_CNTL 0x9002
6116 #define MDIO_WIS_REG_LASI_STATUS 0x9005
6117
6118 #define MDIO_PCS_DEVAD 0x3
6119 #define MDIO_PCS_REG_STATUS 0x0020
6120 #define MDIO_PCS_REG_LASI_STATUS 0x9005
6121 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
6122 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
6123 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
6124 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
6125 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
6126 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
6127 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
6128 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
6129 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
6130
6131
6132 #define MDIO_XS_DEVAD 0x4
6133 #define MDIO_XS_PLL_SEQUENCER 0x8000
6134 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
6135
6136 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
6137 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
6138 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
6139 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
6140 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
6141
6142 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
6143
6144 #define MDIO_AN_DEVAD 0x7
6145 /*ieee*/
6146 #define MDIO_AN_REG_CTRL 0x0000
6147 #define MDIO_AN_REG_STATUS 0x0001
6148 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
6149 #define MDIO_AN_REG_ADV_PAUSE 0x0010
6150 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
6151 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
6152 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
6153 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
6154 #define MDIO_AN_REG_ADV 0x0011
6155 #define MDIO_AN_REG_ADV2 0x0012
6156 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
6157 #define MDIO_AN_REG_MASTER_STATUS 0x0021
6158 /*bcm*/
6159 #define MDIO_AN_REG_LINK_STATUS 0x8304
6160 #define MDIO_AN_REG_CL37_CL73 0x8370
6161 #define MDIO_AN_REG_CL37_AN 0xffe0
6162 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
6163 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
6164
6165 #define MDIO_AN_REG_8073_2_5G 0x8329
6166 #define MDIO_AN_REG_8073_BAM 0x8350
6167
6168 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
6169 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
6170 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
6171 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
6172 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
6173 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
6174 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
6175 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
6176 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
6177 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
6178
6179 /* BCM84823 only */
6180 #define MDIO_CTL_DEVAD 0x1e
6181 #define MDIO_CTL_REG_84823_MEDIA 0x401a
6182 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
6183 /* These pins configure the BCM84823 interface to MAC after reset. */
6184 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
6185 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
6186 /* These pins configure the BCM84823 interface to Line after reset. */
6187 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
6188 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
6189 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
6190 /* When this pin is active high during reset, 10GBASE-T core is power
6191 * down, When it is active low the 10GBASE-T is power up
6192 */
6193 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
6194 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
6195 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
6196 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
6197 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
6198 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
6199 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
6200
6201 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
6202 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
6203
6204 #define IGU_FUNC_BASE 0x0400
6205
6206 #define IGU_ADDR_MSIX 0x0000
6207 #define IGU_ADDR_INT_ACK 0x0200
6208 #define IGU_ADDR_PROD_UPD 0x0201
6209 #define IGU_ADDR_ATTN_BITS_UPD 0x0202
6210 #define IGU_ADDR_ATTN_BITS_SET 0x0203
6211 #define IGU_ADDR_ATTN_BITS_CLR 0x0204
6212 #define IGU_ADDR_COALESCE_NOW 0x0205
6213 #define IGU_ADDR_SIMD_MASK 0x0206
6214 #define IGU_ADDR_SIMD_NOMASK 0x0207
6215 #define IGU_ADDR_MSI_CTL 0x0210
6216 #define IGU_ADDR_MSI_ADDR_LO 0x0211
6217 #define IGU_ADDR_MSI_ADDR_HI 0x0212
6218 #define IGU_ADDR_MSI_DATA 0x0213
6219
6220 #define IGU_INT_ENABLE 0
6221 #define IGU_INT_DISABLE 1
6222 #define IGU_INT_NOP 2
6223 #define IGU_INT_NOP2 3
6224
6225 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
6226 #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1
6227 #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2
6228 #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3
6229
6230 #define COMMAND_REG_INT_ACK 0x0
6231 #define COMMAND_REG_PROD_UPD 0x4
6232 #define COMMAND_REG_ATTN_BITS_UPD 0x8
6233 #define COMMAND_REG_ATTN_BITS_SET 0xc
6234 #define COMMAND_REG_ATTN_BITS_CLR 0x10
6235 #define COMMAND_REG_COALESCE_NOW 0x14
6236 #define COMMAND_REG_SIMD_MASK 0x18
6237 #define COMMAND_REG_SIMD_NOMASK 0x1c
6238
6239
6240 #define IGU_MEM_BASE 0x0000
6241
6242 #define IGU_MEM_MSIX_BASE 0x0000
6243 #define IGU_MEM_MSIX_UPPER 0x007f
6244 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
6245
6246 #define IGU_MEM_PBA_MSIX_BASE 0x0200
6247 #define IGU_MEM_PBA_MSIX_UPPER 0x0200
6248
6249 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
6250 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
6251
6252 #define IGU_CMD_INT_ACK_BASE 0x0400
6253 #define IGU_CMD_INT_ACK_UPPER\
6254 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
6255 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
6256
6257 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500
6258 #define IGU_CMD_E2_PROD_UPD_UPPER\
6259 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
6260 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
6261
6262 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
6263 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
6264 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
6265
6266 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
6267 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
6268 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
6269 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
6270
6271 #define IGU_REG_RESERVED_UPPER 0x05ff
6272 /* Fields of IGU PF CONFIGRATION REGISTER */
6273 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
6274 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
6275 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
6276 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
6277 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
6278 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
6279
6280 /* Fields of IGU VF CONFIGRATION REGISTER */
6281 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
6282 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
6283 #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
6284 #define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */
6285 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
6286
6287
6288 #define IGU_BC_DSB_NUM_SEGS 5
6289 #define IGU_BC_NDSB_NUM_SEGS 2
6290 #define IGU_NORM_DSB_NUM_SEGS 2
6291 #define IGU_NORM_NDSB_NUM_SEGS 1
6292 #define IGU_BC_BASE_DSB_PROD 128
6293 #define IGU_NORM_BASE_DSB_PROD 136
6294
6295 #define IGU_CTRL_CMD_TYPE_WR\
6296 1
6297 #define IGU_CTRL_CMD_TYPE_RD\
6298 0
6299
6300 #define IGU_SEG_ACCESS_NORM 0
6301 #define IGU_SEG_ACCESS_DEF 1
6302 #define IGU_SEG_ACCESS_ATTN 2
6303
6304 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
6305 [5:2] = 0; [1:0] = PF number) */
6306 #define IGU_FID_ENCODE_IS_PF (0x1<<6)
6307 #define IGU_FID_ENCODE_IS_PF_SHIFT 6
6308 #define IGU_FID_VF_NUM_MASK (0x3f)
6309 #define IGU_FID_PF_NUM_MASK (0x7)
6310
6311 #define IGU_REG_MAPPING_MEMORY_VALID (1<<0)
6312 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
6313 #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1
6314 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
6315 #define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7
6316
6317
6318 #define CDU_REGION_NUMBER_XCM_AG 2
6319 #define CDU_REGION_NUMBER_UCM_AG 4
6320
6321
6322 /**
6323 * String-to-compress [31:8] = CID (all 24 bits)
6324 * String-to-compress [7:4] = Region
6325 * String-to-compress [3:0] = Type
6326 */
6327 #define CDU_VALID_DATA(_cid, _region, _type)\
6328 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
6329 #define CDU_CRC8(_cid, _region, _type)\
6330 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
6331 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
6332 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
6333 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
6334 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
6335 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
6336
6337 /******************************************************************************
6338 * Description:
6339 * Calculates crc 8 on a word value: polynomial 0-1-2-8
6340 * Code was translated from Verilog.
6341 * Return:
6342 *****************************************************************************/
calc_crc8(u32 data,u8 crc)6343 static inline u8 calc_crc8(u32 data, u8 crc)
6344 {
6345 u8 D[32];
6346 u8 NewCRC[8];
6347 u8 C[8];
6348 u8 crc_res;
6349 u8 i;
6350
6351 /* split the data into 31 bits */
6352 for (i = 0; i < 32; i++) {
6353 D[i] = (u8)(data & 1);
6354 data = data >> 1;
6355 }
6356
6357 /* split the crc into 8 bits */
6358 for (i = 0; i < 8; i++) {
6359 C[i] = crc & 1;
6360 crc = crc >> 1;
6361 }
6362
6363 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
6364 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
6365 C[6] ^ C[7];
6366 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
6367 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
6368 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^
6369 C[6];
6370 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
6371 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
6372 C[0] ^ C[1] ^ C[4] ^ C[5];
6373 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
6374 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
6375 C[1] ^ C[2] ^ C[5] ^ C[6];
6376 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
6377 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
6378 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
6379 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
6380 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
6381 C[3] ^ C[4] ^ C[7];
6382 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
6383 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
6384 C[5];
6385 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
6386 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
6387 C[6];
6388
6389 crc_res = 0;
6390 for (i = 0; i < 8; i++)
6391 crc_res |= (NewCRC[i] << i);
6392
6393 return crc_res;
6394 }
6395
6396
6397 #endif /* BNX2X_REG_H */
6398