1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c)  2018 Intel Corporation */
3 
4 #ifndef _IGC_H_
5 #define _IGC_H_
6 
7 #include <linux/kobject.h>
8 #include <linux/pci.h>
9 #include <linux/netdevice.h>
10 #include <linux/vmalloc.h>
11 #include <linux/ethtool.h>
12 #include <linux/sctp.h>
13 #include <linux/ptp_clock_kernel.h>
14 #include <linux/timecounter.h>
15 #include <linux/net_tstamp.h>
16 
17 #include "igc_hw.h"
18 
19 void igc_ethtool_set_ops(struct net_device *);
20 
21 /* Transmit and receive queues */
22 #define IGC_MAX_RX_QUEUES		4
23 #define IGC_MAX_TX_QUEUES		4
24 
25 #define MAX_Q_VECTORS			8
26 #define MAX_STD_JUMBO_FRAME_SIZE	9216
27 
28 #define MAX_ETYPE_FILTER		8
29 #define IGC_RETA_SIZE			128
30 
31 /* SDP support */
32 #define IGC_N_EXTTS	2
33 #define IGC_N_PEROUT	2
34 #define IGC_N_SDP	4
35 
36 #define MAX_FLEX_FILTER			32
37 
38 enum igc_mac_filter_type {
39 	IGC_MAC_FILTER_TYPE_DST = 0,
40 	IGC_MAC_FILTER_TYPE_SRC
41 };
42 
43 struct igc_tx_queue_stats {
44 	u64 packets;
45 	u64 bytes;
46 	u64 restart_queue;
47 	u64 restart_queue2;
48 };
49 
50 struct igc_rx_queue_stats {
51 	u64 packets;
52 	u64 bytes;
53 	u64 drops;
54 	u64 csum_err;
55 	u64 alloc_failed;
56 };
57 
58 struct igc_rx_packet_stats {
59 	u64 ipv4_packets;      /* IPv4 headers processed */
60 	u64 ipv4e_packets;     /* IPv4E headers with extensions processed */
61 	u64 ipv6_packets;      /* IPv6 headers processed */
62 	u64 ipv6e_packets;     /* IPv6E headers with extensions processed */
63 	u64 tcp_packets;       /* TCP headers processed */
64 	u64 udp_packets;       /* UDP headers processed */
65 	u64 sctp_packets;      /* SCTP headers processed */
66 	u64 nfs_packets;       /* NFS headers processe */
67 	u64 other_packets;
68 };
69 
70 struct igc_ring_container {
71 	struct igc_ring *ring;          /* pointer to linked list of rings */
72 	unsigned int total_bytes;       /* total bytes processed this int */
73 	unsigned int total_packets;     /* total packets processed this int */
74 	u16 work_limit;                 /* total work allowed per interrupt */
75 	u8 count;                       /* total number of rings in vector */
76 	u8 itr;                         /* current ITR setting for ring */
77 };
78 
79 struct igc_ring {
80 	struct igc_q_vector *q_vector;  /* backlink to q_vector */
81 	struct net_device *netdev;      /* back pointer to net_device */
82 	struct device *dev;             /* device for dma mapping */
83 	union {                         /* array of buffer info structs */
84 		struct igc_tx_buffer *tx_buffer_info;
85 		struct igc_rx_buffer *rx_buffer_info;
86 	};
87 	void *desc;                     /* descriptor ring memory */
88 	unsigned long flags;            /* ring specific flags */
89 	void __iomem *tail;             /* pointer to ring tail register */
90 	dma_addr_t dma;                 /* phys address of the ring */
91 	unsigned int size;              /* length of desc. ring in bytes */
92 
93 	u16 count;                      /* number of desc. in the ring */
94 	u8 queue_index;                 /* logical index of the ring*/
95 	u8 reg_idx;                     /* physical index of the ring */
96 	bool launchtime_enable;         /* true if LaunchTime is enabled */
97 	ktime_t last_tx_cycle;          /* end of the cycle with a launchtime transmission */
98 	ktime_t last_ff_cycle;          /* Last cycle with an active first flag */
99 
100 	u32 start_time;
101 	u32 end_time;
102 
103 	/* CBS parameters */
104 	bool cbs_enable;                /* indicates if CBS is enabled */
105 	s32 idleslope;                  /* idleSlope in kbps */
106 	s32 sendslope;                  /* sendSlope in kbps */
107 	s32 hicredit;                   /* hiCredit in bytes */
108 	s32 locredit;                   /* loCredit in bytes */
109 
110 	/* everything past this point are written often */
111 	u16 next_to_clean;
112 	u16 next_to_use;
113 	u16 next_to_alloc;
114 
115 	union {
116 		/* TX */
117 		struct {
118 			struct igc_tx_queue_stats tx_stats;
119 			struct u64_stats_sync tx_syncp;
120 			struct u64_stats_sync tx_syncp2;
121 		};
122 		/* RX */
123 		struct {
124 			struct igc_rx_queue_stats rx_stats;
125 			struct igc_rx_packet_stats pkt_stats;
126 			struct u64_stats_sync rx_syncp;
127 			struct sk_buff *skb;
128 		};
129 	};
130 
131 	struct xdp_rxq_info xdp_rxq;
132 	struct xsk_buff_pool *xsk_pool;
133 } ____cacheline_internodealigned_in_smp;
134 
135 /* Board specific private data structure */
136 struct igc_adapter {
137 	struct net_device *netdev;
138 
139 	struct ethtool_eee eee;
140 	u16 eee_advert;
141 
142 	unsigned long state;
143 	unsigned int flags;
144 	unsigned int num_q_vectors;
145 
146 	struct msix_entry *msix_entries;
147 
148 	/* TX */
149 	u16 tx_work_limit;
150 	u32 tx_timeout_count;
151 	int num_tx_queues;
152 	struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
153 
154 	/* RX */
155 	int num_rx_queues;
156 	struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
157 
158 	struct timer_list watchdog_timer;
159 	struct timer_list dma_err_timer;
160 	struct timer_list phy_info_timer;
161 
162 	u32 wol;
163 	u32 en_mng_pt;
164 	u16 link_speed;
165 	u16 link_duplex;
166 
167 	u8 port_num;
168 
169 	u8 __iomem *io_addr;
170 	/* Interrupt Throttle Rate */
171 	u32 rx_itr_setting;
172 	u32 tx_itr_setting;
173 
174 	struct work_struct reset_task;
175 	struct work_struct watchdog_task;
176 	struct work_struct dma_err_task;
177 	bool fc_autoneg;
178 
179 	u8 tx_timeout_factor;
180 
181 	int msg_enable;
182 	u32 max_frame_size;
183 	u32 min_frame_size;
184 
185 	ktime_t base_time;
186 	ktime_t cycle_time;
187 	bool qbv_enable;
188 
189 	/* OS defined structs */
190 	struct pci_dev *pdev;
191 	/* lock for statistics */
192 	spinlock_t stats64_lock;
193 	struct rtnl_link_stats64 stats64;
194 
195 	/* structs defined in igc_hw.h */
196 	struct igc_hw hw;
197 	struct igc_hw_stats stats;
198 
199 	struct igc_q_vector *q_vector[MAX_Q_VECTORS];
200 	u32 eims_enable_mask;
201 	u32 eims_other;
202 
203 	u16 tx_ring_count;
204 	u16 rx_ring_count;
205 
206 	u32 tx_hwtstamp_timeouts;
207 	u32 tx_hwtstamp_skipped;
208 	u32 rx_hwtstamp_cleared;
209 
210 	u32 rss_queues;
211 	u32 rss_indir_tbl_init;
212 
213 	/* Any access to elements in nfc_rule_list is protected by the
214 	 * nfc_rule_lock.
215 	 */
216 	struct mutex nfc_rule_lock;
217 	struct list_head nfc_rule_list;
218 	unsigned int nfc_rule_count;
219 
220 	u8 rss_indir_tbl[IGC_RETA_SIZE];
221 
222 	unsigned long link_check_timeout;
223 	struct igc_info ei;
224 
225 	u32 test_icr;
226 
227 	struct ptp_clock *ptp_clock;
228 	struct ptp_clock_info ptp_caps;
229 	struct work_struct ptp_tx_work;
230 	struct sk_buff *ptp_tx_skb;
231 	struct hwtstamp_config tstamp_config;
232 	unsigned long ptp_tx_start;
233 	unsigned int ptp_flags;
234 	/* System time value lock */
235 	spinlock_t tmreg_lock;
236 	struct cyclecounter cc;
237 	struct timecounter tc;
238 	struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
239 	ktime_t ptp_reset_start; /* Reset time in clock mono */
240 	struct system_time_snapshot snapshot;
241 
242 	char fw_version[32];
243 
244 	struct bpf_prog *xdp_prog;
245 
246 	bool pps_sys_wrap_on;
247 
248 	struct ptp_pin_desc sdp_config[IGC_N_SDP];
249 	struct {
250 		struct timespec64 start;
251 		struct timespec64 period;
252 	} perout[IGC_N_PEROUT];
253 };
254 
255 void igc_up(struct igc_adapter *adapter);
256 void igc_down(struct igc_adapter *adapter);
257 int igc_open(struct net_device *netdev);
258 int igc_close(struct net_device *netdev);
259 int igc_setup_tx_resources(struct igc_ring *ring);
260 int igc_setup_rx_resources(struct igc_ring *ring);
261 void igc_free_tx_resources(struct igc_ring *ring);
262 void igc_free_rx_resources(struct igc_ring *ring);
263 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
264 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
265 			      const u32 max_rss_queues);
266 int igc_reinit_queues(struct igc_adapter *adapter);
267 void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
268 bool igc_has_link(struct igc_adapter *adapter);
269 void igc_reset(struct igc_adapter *adapter);
270 void igc_update_stats(struct igc_adapter *adapter);
271 void igc_disable_rx_ring(struct igc_ring *ring);
272 void igc_enable_rx_ring(struct igc_ring *ring);
273 void igc_disable_tx_ring(struct igc_ring *ring);
274 void igc_enable_tx_ring(struct igc_ring *ring);
275 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
276 
277 /* igc_dump declarations */
278 void igc_rings_dump(struct igc_adapter *adapter);
279 void igc_regs_dump(struct igc_adapter *adapter);
280 
281 extern char igc_driver_name[];
282 
283 #define IGC_REGS_LEN			740
284 
285 /* flags controlling PTP/1588 function */
286 #define IGC_PTP_ENABLED		BIT(0)
287 
288 /* Flags definitions */
289 #define IGC_FLAG_HAS_MSI		BIT(0)
290 #define IGC_FLAG_QUEUE_PAIRS		BIT(3)
291 #define IGC_FLAG_DMAC			BIT(4)
292 #define IGC_FLAG_PTP			BIT(8)
293 #define IGC_FLAG_WOL_SUPPORTED		BIT(8)
294 #define IGC_FLAG_NEED_LINK_UPDATE	BIT(9)
295 #define IGC_FLAG_MEDIA_RESET		BIT(10)
296 #define IGC_FLAG_MAS_ENABLE		BIT(12)
297 #define IGC_FLAG_HAS_MSIX		BIT(13)
298 #define IGC_FLAG_EEE			BIT(14)
299 #define IGC_FLAG_VLAN_PROMISC		BIT(15)
300 #define IGC_FLAG_RX_LEGACY		BIT(16)
301 #define IGC_FLAG_TSN_QBV_ENABLED	BIT(17)
302 #define IGC_FLAG_TSN_QAV_ENABLED	BIT(18)
303 
304 #define IGC_FLAG_TSN_ANY_ENABLED \
305 	(IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED)
306 
307 #define IGC_FLAG_RSS_FIELD_IPV4_UDP	BIT(6)
308 #define IGC_FLAG_RSS_FIELD_IPV6_UDP	BIT(7)
309 
310 #define IGC_MRQC_ENABLE_RSS_MQ		0x00000002
311 #define IGC_MRQC_RSS_FIELD_IPV4_UDP	0x00400000
312 #define IGC_MRQC_RSS_FIELD_IPV6_UDP	0x00800000
313 
314 /* Interrupt defines */
315 #define IGC_START_ITR			648 /* ~6000 ints/sec */
316 #define IGC_4K_ITR			980
317 #define IGC_20K_ITR			196
318 #define IGC_70K_ITR			56
319 
320 #define IGC_DEFAULT_ITR		3 /* dynamic */
321 #define IGC_MAX_ITR_USECS	10000
322 #define IGC_MIN_ITR_USECS	10
323 #define NON_Q_VECTORS		1
324 #define MAX_MSIX_ENTRIES	10
325 
326 /* TX/RX descriptor defines */
327 #define IGC_DEFAULT_TXD		256
328 #define IGC_DEFAULT_TX_WORK	128
329 #define IGC_MIN_TXD		80
330 #define IGC_MAX_TXD		4096
331 
332 #define IGC_DEFAULT_RXD		256
333 #define IGC_MIN_RXD		80
334 #define IGC_MAX_RXD		4096
335 
336 /* Supported Rx Buffer Sizes */
337 #define IGC_RXBUFFER_256		256
338 #define IGC_RXBUFFER_2048		2048
339 #define IGC_RXBUFFER_3072		3072
340 
341 #define AUTO_ALL_MODES		0
342 #define IGC_RX_HDR_LEN			IGC_RXBUFFER_256
343 
344 /* Transmit and receive latency (for PTP timestamps) */
345 #define IGC_I225_TX_LATENCY_10		240
346 #define IGC_I225_TX_LATENCY_100		58
347 #define IGC_I225_TX_LATENCY_1000	80
348 #define IGC_I225_TX_LATENCY_2500	1325
349 #define IGC_I225_RX_LATENCY_10		6450
350 #define IGC_I225_RX_LATENCY_100		185
351 #define IGC_I225_RX_LATENCY_1000	300
352 #define IGC_I225_RX_LATENCY_2500	1485
353 
354 /* RX and TX descriptor control thresholds.
355  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
356  *           descriptors available in its onboard memory.
357  *           Setting this to 0 disables RX descriptor prefetch.
358  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
359  *           available in host memory.
360  *           If PTHRESH is 0, this should also be 0.
361  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
362  *           descriptors until either it has this many to write back, or the
363  *           ITR timer expires.
364  */
365 #define IGC_RX_PTHRESH			8
366 #define IGC_RX_HTHRESH			8
367 #define IGC_TX_PTHRESH			8
368 #define IGC_TX_HTHRESH			1
369 #define IGC_RX_WTHRESH			4
370 #define IGC_TX_WTHRESH			16
371 
372 #define IGC_RX_DMA_ATTR \
373 	(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
374 
375 #define IGC_TS_HDR_LEN			16
376 
377 #define IGC_SKB_PAD			(NET_SKB_PAD + NET_IP_ALIGN)
378 
379 #if (PAGE_SIZE < 8192)
380 #define IGC_MAX_FRAME_BUILD_SKB \
381 	(SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
382 #else
383 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
384 #endif
385 
386 /* How many Rx Buffers do we bundle into one write to the hardware ? */
387 #define IGC_RX_BUFFER_WRITE	16 /* Must be power of 2 */
388 
389 /* VLAN info */
390 #define IGC_TX_FLAGS_VLAN_MASK	0xffff0000
391 #define IGC_TX_FLAGS_VLAN_SHIFT	16
392 
393 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */
igc_test_staterr(union igc_adv_rx_desc * rx_desc,const u32 stat_err_bits)394 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
395 				      const u32 stat_err_bits)
396 {
397 	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
398 }
399 
400 enum igc_state_t {
401 	__IGC_TESTING,
402 	__IGC_RESETTING,
403 	__IGC_DOWN,
404 	__IGC_PTP_TX_IN_PROGRESS,
405 };
406 
407 enum igc_tx_flags {
408 	/* cmd_type flags */
409 	IGC_TX_FLAGS_VLAN	= 0x01,
410 	IGC_TX_FLAGS_TSO	= 0x02,
411 	IGC_TX_FLAGS_TSTAMP	= 0x04,
412 
413 	/* olinfo flags */
414 	IGC_TX_FLAGS_IPV4	= 0x10,
415 	IGC_TX_FLAGS_CSUM	= 0x20,
416 };
417 
418 enum igc_boards {
419 	board_base,
420 };
421 
422 /* The largest size we can write to the descriptor is 65535.  In order to
423  * maintain a power of two alignment we have to limit ourselves to 32K.
424  */
425 #define IGC_MAX_TXD_PWR		15
426 #define IGC_MAX_DATA_PER_TXD	BIT(IGC_MAX_TXD_PWR)
427 
428 /* Tx Descriptors needed, worst case */
429 #define TXD_USE_COUNT(S)	DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
430 #define DESC_NEEDED	(MAX_SKB_FRAGS + 4)
431 
432 enum igc_tx_buffer_type {
433 	IGC_TX_BUFFER_TYPE_SKB,
434 	IGC_TX_BUFFER_TYPE_XDP,
435 	IGC_TX_BUFFER_TYPE_XSK,
436 };
437 
438 /* wrapper around a pointer to a socket buffer,
439  * so a DMA handle can be stored along with the buffer
440  */
441 struct igc_tx_buffer {
442 	union igc_adv_tx_desc *next_to_watch;
443 	unsigned long time_stamp;
444 	enum igc_tx_buffer_type type;
445 	union {
446 		struct sk_buff *skb;
447 		struct xdp_frame *xdpf;
448 	};
449 	unsigned int bytecount;
450 	u16 gso_segs;
451 	__be16 protocol;
452 
453 	DEFINE_DMA_UNMAP_ADDR(dma);
454 	DEFINE_DMA_UNMAP_LEN(len);
455 	u32 tx_flags;
456 };
457 
458 struct igc_rx_buffer {
459 	union {
460 		struct {
461 			dma_addr_t dma;
462 			struct page *page;
463 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
464 			__u32 page_offset;
465 #else
466 			__u16 page_offset;
467 #endif
468 			__u16 pagecnt_bias;
469 		};
470 		struct xdp_buff *xdp;
471 	};
472 };
473 
474 struct igc_q_vector {
475 	struct igc_adapter *adapter;    /* backlink */
476 	void __iomem *itr_register;
477 	u32 eims_value;                 /* EIMS mask value */
478 
479 	u16 itr_val;
480 	u8 set_itr;
481 
482 	struct igc_ring_container rx, tx;
483 
484 	struct napi_struct napi;
485 
486 	struct rcu_head rcu;    /* to avoid race with update stats on free */
487 	char name[IFNAMSIZ + 9];
488 	struct net_device poll_dev;
489 
490 	/* for dynamic allocation of rings associated with this q_vector */
491 	struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
492 };
493 
494 enum igc_filter_match_flags {
495 	IGC_FILTER_FLAG_ETHER_TYPE =	BIT(0),
496 	IGC_FILTER_FLAG_VLAN_TCI   =	BIT(1),
497 	IGC_FILTER_FLAG_SRC_MAC_ADDR =	BIT(2),
498 	IGC_FILTER_FLAG_DST_MAC_ADDR =	BIT(3),
499 	IGC_FILTER_FLAG_USER_DATA =	BIT(4),
500 	IGC_FILTER_FLAG_VLAN_ETYPE =	BIT(5),
501 };
502 
503 struct igc_nfc_filter {
504 	u8 match_flags;
505 	u16 etype;
506 	__be16 vlan_etype;
507 	u16 vlan_tci;
508 	u8 src_addr[ETH_ALEN];
509 	u8 dst_addr[ETH_ALEN];
510 	u8 user_data[8];
511 	u8 user_mask[8];
512 	u8 flex_index;
513 	u8 rx_queue;
514 	u8 prio;
515 	u8 immediate_irq;
516 	u8 drop;
517 };
518 
519 struct igc_nfc_rule {
520 	struct list_head list;
521 	struct igc_nfc_filter filter;
522 	u32 location;
523 	u16 action;
524 	bool flex;
525 };
526 
527 /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority
528  * based, 8 ethertype based and 32 Flex filter based rules.
529  */
530 #define IGC_MAX_RXNFC_RULES		64
531 
532 struct igc_flex_filter {
533 	u8 index;
534 	u8 data[128];
535 	u8 mask[16];
536 	u8 length;
537 	u8 rx_queue;
538 	u8 prio;
539 	u8 immediate_irq;
540 	u8 drop;
541 };
542 
543 /* igc_desc_unused - calculate if we have unused descriptors */
igc_desc_unused(const struct igc_ring * ring)544 static inline u16 igc_desc_unused(const struct igc_ring *ring)
545 {
546 	u16 ntc = ring->next_to_clean;
547 	u16 ntu = ring->next_to_use;
548 
549 	return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
550 }
551 
igc_get_phy_info(struct igc_hw * hw)552 static inline s32 igc_get_phy_info(struct igc_hw *hw)
553 {
554 	if (hw->phy.ops.get_phy_info)
555 		return hw->phy.ops.get_phy_info(hw);
556 
557 	return 0;
558 }
559 
igc_reset_phy(struct igc_hw * hw)560 static inline s32 igc_reset_phy(struct igc_hw *hw)
561 {
562 	if (hw->phy.ops.reset)
563 		return hw->phy.ops.reset(hw);
564 
565 	return 0;
566 }
567 
txring_txq(const struct igc_ring * tx_ring)568 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
569 {
570 	return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
571 }
572 
573 enum igc_ring_flags_t {
574 	IGC_RING_FLAG_RX_3K_BUFFER,
575 	IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
576 	IGC_RING_FLAG_RX_SCTP_CSUM,
577 	IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
578 	IGC_RING_FLAG_TX_CTX_IDX,
579 	IGC_RING_FLAG_TX_DETECT_HANG,
580 	IGC_RING_FLAG_AF_XDP_ZC,
581 };
582 
583 #define ring_uses_large_buffer(ring) \
584 	test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
585 #define set_ring_uses_large_buffer(ring) \
586 	set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
587 #define clear_ring_uses_large_buffer(ring) \
588 	clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
589 
590 #define ring_uses_build_skb(ring) \
591 	test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
592 
igc_rx_bufsz(struct igc_ring * ring)593 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
594 {
595 #if (PAGE_SIZE < 8192)
596 	if (ring_uses_large_buffer(ring))
597 		return IGC_RXBUFFER_3072;
598 
599 	if (ring_uses_build_skb(ring))
600 		return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
601 #endif
602 	return IGC_RXBUFFER_2048;
603 }
604 
igc_rx_pg_order(struct igc_ring * ring)605 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
606 {
607 #if (PAGE_SIZE < 8192)
608 	if (ring_uses_large_buffer(ring))
609 		return 1;
610 #endif
611 	return 0;
612 }
613 
igc_read_phy_reg(struct igc_hw * hw,u32 offset,u16 * data)614 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
615 {
616 	if (hw->phy.ops.read_reg)
617 		return hw->phy.ops.read_reg(hw, offset, data);
618 
619 	return -EOPNOTSUPP;
620 }
621 
622 void igc_reinit_locked(struct igc_adapter *);
623 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
624 				      u32 location);
625 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
626 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
627 
628 void igc_ptp_init(struct igc_adapter *adapter);
629 void igc_ptp_reset(struct igc_adapter *adapter);
630 void igc_ptp_suspend(struct igc_adapter *adapter);
631 void igc_ptp_stop(struct igc_adapter *adapter);
632 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
633 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
634 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
635 void igc_ptp_tx_hang(struct igc_adapter *adapter);
636 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
637 
638 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
639 
640 #define IGC_TXD_DCMD	(IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
641 
642 #define IGC_RX_DESC(R, i)       \
643 	(&(((union igc_adv_rx_desc *)((R)->desc))[i]))
644 #define IGC_TX_DESC(R, i)       \
645 	(&(((union igc_adv_tx_desc *)((R)->desc))[i]))
646 #define IGC_TX_CTXTDESC(R, i)   \
647 	(&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
648 
649 #endif /* _IGC_H_ */
650