1 /* $Id: irq.h,v 1.20.2.1 2002/03/03 10:31:56 davem Exp $
2 * irq.h: IRQ registers on the 64-bit Sparc.
3 *
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
6 */
7
8 #ifndef _SPARC64_IRQ_H
9 #define _SPARC64_IRQ_H
10
11 #include <linux/config.h>
12 #include <linux/linkage.h>
13 #include <linux/kernel.h>
14 #include <asm/pil.h>
15 #include <asm/ptrace.h>
16
17 /* You should not mess with this directly. That's the job of irq.c.
18 *
19 * If you make changes here, please update hand coded assembler of
20 * SBUS/floppy interrupt handler in entry.S -DaveM
21 *
22 * This is currently one DCACHE line, two buckets per L2 cache
23 * line. Keep this in mind please.
24 */
25 struct ino_bucket {
26 /* Next handler in per-CPU PIL worklist. We know that
27 * bucket pointers have the high 32-bits clear, so to
28 * save space we only store the bits we need.
29 */
30 /*0x00*/unsigned int irq_chain;
31
32 /* PIL to schedule this IVEC at. */
33 /*0x04*/unsigned char pil;
34
35 /* If an IVEC arrives while irq_info is NULL, we
36 * set this to notify request_irq() about the event.
37 */
38 /*0x05*/unsigned char pending;
39
40 /* Miscellaneous flags. */
41 /*0x06*/unsigned char flags;
42
43 /* This is used to deal with IBF_DMA_SYNC on
44 * Sabre systems.
45 */
46 /*0x07*/unsigned char synctab_ent;
47
48 /* Reference to handler for this IRQ. If this is
49 * non-NULL this means it is active and should be
50 * serviced. Else the pending member is set to one
51 * and later registry of the interrupt checks for
52 * this condition.
53 *
54 * Normally this is just an irq_action structure.
55 * But, on PCI, if multiple interrupt sources behind
56 * a bridge have multiple interrupt sources that share
57 * the same INO bucket, this points to an array of
58 * pointers to four IRQ action structures.
59 */
60 /*0x08*/void *irq_info;
61
62 /* Sun5 Interrupt Clear Register. */
63 /*0x10*/unsigned long iclr;
64
65 /* Sun5 Interrupt Mapping Register. */
66 /*0x18*/unsigned long imap;
67
68 };
69
70 #ifdef CONFIG_PCI
71 extern unsigned long pci_dma_wsync;
72 extern unsigned long dma_sync_reg_table[256];
73 extern unsigned char dma_sync_reg_table_entry;
74 #endif
75
76 /* IMAP/ICLR register defines */
77 #define IMAP_VALID 0x80000000 /* IRQ Enabled */
78 #define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */
79 #define IMAP_TID_JBUS 0x7c000000 /* JBUS TargetID */
80 #define IMAP_AID_SAFARI 0x7c000000 /* Safari AgentID */
81 #define IMAP_NID_SAFARI 0x03e00000 /* Safari NodeID */
82 #define IMAP_IGN 0x000007c0 /* IRQ Group Number */
83 #define IMAP_INO 0x0000003f /* IRQ Number */
84 #define IMAP_INR 0x000007ff /* Full interrupt number*/
85
86 #define ICLR_IDLE 0x00000000 /* Idle state */
87 #define ICLR_TRANSMIT 0x00000001 /* Transmit state */
88 #define ICLR_PENDING 0x00000003 /* Pending state */
89
90 /* Only 8-bits are available, be careful. -DaveM */
91 #define IBF_DMA_SYNC 0x01 /* DMA synchronization behind PCI bridge needed. */
92 #define IBF_PCI 0x02 /* Indicates PSYCHO/SABRE/SCHIZO PCI interrupt. */
93 #define IBF_ACTIVE 0x04 /* This interrupt is active and has a handler. */
94 #define IBF_MULTI 0x08 /* On PCI, indicates shared bucket. */
95
96 #define NUM_IVECS 8192
97 extern struct ino_bucket ivector_table[NUM_IVECS];
98
99 #define __irq_ino(irq) \
100 (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
101 #define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
102 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
103 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
104
__irq_itoa(unsigned int irq)105 static __inline__ char *__irq_itoa(unsigned int irq)
106 {
107 static char buff[16];
108
109 sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq));
110 return buff;
111 }
112
113 #define NR_IRQS 16
114
115 extern void disable_irq(unsigned int);
116 #define disable_irq_nosync disable_irq
117 extern void enable_irq(unsigned int);
118 extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
119 extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
120 extern unsigned int psycho_build_irq(void *psycho, int imap_off, int ino, int need_dma_sync);
121
122 #ifdef CONFIG_SMP
123 extern void set_cpu_int(int, int);
124 extern void clear_cpu_int(int, int);
125 extern void set_irq_udt(int);
126 #endif
127
128 extern int request_fast_irq(unsigned int irq,
129 void (*handler)(int, void *, struct pt_regs *),
130 unsigned long flags, __const__ char *devname,
131 void *dev_id);
132
set_softint(unsigned long bits)133 extern __inline__ void set_softint(unsigned long bits)
134 {
135 __asm__ __volatile__("wr %0, 0x0, %%set_softint"
136 : /* No outputs */
137 : "r" (bits));
138 }
139
clear_softint(unsigned long bits)140 extern __inline__ void clear_softint(unsigned long bits)
141 {
142 __asm__ __volatile__("wr %0, 0x0, %%clear_softint"
143 : /* No outputs */
144 : "r" (bits));
145 }
146
get_softint(void)147 extern __inline__ unsigned long get_softint(void)
148 {
149 unsigned long retval;
150
151 __asm__ __volatile__("rd %%softint, %0"
152 : "=r" (retval));
153 return retval;
154 }
155
156 #endif
157