1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3 
4 #ifndef _ICE_TYPE_H_
5 #define _ICE_TYPE_H_
6 
7 #define ICE_BYTES_PER_WORD	2
8 #define ICE_BYTES_PER_DWORD	4
9 #define ICE_CHNL_MAX_TC		16
10 
11 #include "ice_hw_autogen.h"
12 #include "ice_devids.h"
13 #include "ice_osdep.h"
14 #include "ice_controlq.h"
15 #include "ice_lan_tx_rx.h"
16 #include "ice_flex_type.h"
17 #include "ice_protocol_type.h"
18 #include "ice_sbq_cmd.h"
19 #include "ice_vlan_mode.h"
20 
ice_is_tc_ena(unsigned long bitmap,u8 tc)21 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
22 {
23 	return test_bit(tc, &bitmap);
24 }
25 
round_up_64bit(u64 a,u32 b)26 static inline u64 round_up_64bit(u64 a, u32 b)
27 {
28 	return div64_long(((a) + (b) / 2), (b));
29 }
30 
ice_round_to_num(u32 N,u32 R)31 static inline u32 ice_round_to_num(u32 N, u32 R)
32 {
33 	return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
34 		((((N) + (R) - 1) / (R)) * (R)));
35 }
36 
37 /* Driver always calls main vsi_handle first */
38 #define ICE_MAIN_VSI_HANDLE		0
39 
40 /* debug masks - set these bits in hw->debug_mask to control output */
41 #define ICE_DBG_INIT		BIT_ULL(1)
42 #define ICE_DBG_FW_LOG		BIT_ULL(3)
43 #define ICE_DBG_LINK		BIT_ULL(4)
44 #define ICE_DBG_PHY		BIT_ULL(5)
45 #define ICE_DBG_QCTX		BIT_ULL(6)
46 #define ICE_DBG_NVM		BIT_ULL(7)
47 #define ICE_DBG_LAN		BIT_ULL(8)
48 #define ICE_DBG_FLOW		BIT_ULL(9)
49 #define ICE_DBG_SW		BIT_ULL(13)
50 #define ICE_DBG_SCHED		BIT_ULL(14)
51 #define ICE_DBG_RDMA		BIT_ULL(15)
52 #define ICE_DBG_PKG		BIT_ULL(16)
53 #define ICE_DBG_RES		BIT_ULL(17)
54 #define ICE_DBG_PTP		BIT_ULL(19)
55 #define ICE_DBG_AQ_MSG		BIT_ULL(24)
56 #define ICE_DBG_AQ_DESC		BIT_ULL(25)
57 #define ICE_DBG_AQ_DESC_BUF	BIT_ULL(26)
58 #define ICE_DBG_AQ_CMD		BIT_ULL(27)
59 #define ICE_DBG_AQ		(ICE_DBG_AQ_MSG		| \
60 				 ICE_DBG_AQ_DESC	| \
61 				 ICE_DBG_AQ_DESC_BUF	| \
62 				 ICE_DBG_AQ_CMD)
63 
64 #define ICE_DBG_USER		BIT_ULL(31)
65 
66 enum ice_aq_res_ids {
67 	ICE_NVM_RES_ID = 1,
68 	ICE_SPD_RES_ID,
69 	ICE_CHANGE_LOCK_RES_ID,
70 	ICE_GLOBAL_CFG_LOCK_RES_ID
71 };
72 
73 /* FW update timeout definitions are in milliseconds */
74 #define ICE_NVM_TIMEOUT			180000
75 #define ICE_CHANGE_LOCK_TIMEOUT		1000
76 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT	5000
77 
78 enum ice_aq_res_access_type {
79 	ICE_RES_READ = 1,
80 	ICE_RES_WRITE
81 };
82 
83 struct ice_driver_ver {
84 	u8 major_ver;
85 	u8 minor_ver;
86 	u8 build_ver;
87 	u8 subbuild_ver;
88 	u8 driver_string[32];
89 };
90 
91 enum ice_fc_mode {
92 	ICE_FC_NONE = 0,
93 	ICE_FC_RX_PAUSE,
94 	ICE_FC_TX_PAUSE,
95 	ICE_FC_FULL,
96 	ICE_FC_PFC,
97 	ICE_FC_DFLT
98 };
99 
100 enum ice_phy_cache_mode {
101 	ICE_FC_MODE = 0,
102 	ICE_SPEED_MODE,
103 	ICE_FEC_MODE
104 };
105 
106 enum ice_fec_mode {
107 	ICE_FEC_NONE = 0,
108 	ICE_FEC_RS,
109 	ICE_FEC_BASER,
110 	ICE_FEC_AUTO
111 };
112 
113 struct ice_phy_cache_mode_data {
114 	union {
115 		enum ice_fec_mode curr_user_fec_req;
116 		enum ice_fc_mode curr_user_fc_req;
117 		u16 curr_user_speed_req;
118 	} data;
119 };
120 
121 enum ice_set_fc_aq_failures {
122 	ICE_SET_FC_AQ_FAIL_NONE = 0,
123 	ICE_SET_FC_AQ_FAIL_GET,
124 	ICE_SET_FC_AQ_FAIL_SET,
125 	ICE_SET_FC_AQ_FAIL_UPDATE
126 };
127 
128 /* Various MAC types */
129 enum ice_mac_type {
130 	ICE_MAC_UNKNOWN = 0,
131 	ICE_MAC_E810,
132 	ICE_MAC_GENERIC,
133 };
134 
135 /* Media Types */
136 enum ice_media_type {
137 	ICE_MEDIA_UNKNOWN = 0,
138 	ICE_MEDIA_FIBER,
139 	ICE_MEDIA_BASET,
140 	ICE_MEDIA_BACKPLANE,
141 	ICE_MEDIA_DA,
142 };
143 
144 enum ice_vsi_type {
145 	ICE_VSI_PF = 0,
146 	ICE_VSI_VF = 1,
147 	ICE_VSI_CTRL = 3,	/* equates to ICE_VSI_PF with 1 queue pair */
148 	ICE_VSI_CHNL = 4,
149 	ICE_VSI_LB = 6,
150 	ICE_VSI_SWITCHDEV_CTRL = 7,
151 };
152 
153 struct ice_link_status {
154 	/* Refer to ice_aq_phy_type for bits definition */
155 	u64 phy_type_low;
156 	u64 phy_type_high;
157 	u8 topo_media_conflict;
158 	u16 max_frame_size;
159 	u16 link_speed;
160 	u16 req_speeds;
161 	u8 link_cfg_err;
162 	u8 lse_ena;	/* Link Status Event notification */
163 	u8 link_info;
164 	u8 an_info;
165 	u8 ext_info;
166 	u8 fec_info;
167 	u8 pacing;
168 	/* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
169 	 * ice_aqc_get_phy_caps structure
170 	 */
171 	u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
172 };
173 
174 /* Different reset sources for which a disable queue AQ call has to be made in
175  * order to clean the Tx scheduler as a part of the reset
176  */
177 enum ice_disq_rst_src {
178 	ICE_NO_RESET = 0,
179 	ICE_VM_RESET,
180 	ICE_VF_RESET,
181 };
182 
183 /* PHY info such as phy_type, etc... */
184 struct ice_phy_info {
185 	struct ice_link_status link_info;
186 	struct ice_link_status link_info_old;
187 	u64 phy_type_low;
188 	u64 phy_type_high;
189 	enum ice_media_type media_type;
190 	u8 get_link_info;
191 	/* Please refer to struct ice_aqc_get_link_status_data to get
192 	 * detail of enable bit in curr_user_speed_req
193 	 */
194 	u16 curr_user_speed_req;
195 	enum ice_fec_mode curr_user_fec_req;
196 	enum ice_fc_mode curr_user_fc_req;
197 	struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
198 };
199 
200 /* protocol enumeration for filters */
201 enum ice_fltr_ptype {
202 	/* NONE - used for undef/error */
203 	ICE_FLTR_PTYPE_NONF_NONE = 0,
204 	ICE_FLTR_PTYPE_NONF_IPV4_UDP,
205 	ICE_FLTR_PTYPE_NONF_IPV4_TCP,
206 	ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
207 	ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
208 	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
209 	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
210 	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
211 	ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
212 	ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
213 	ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
214 	ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
215 	ICE_FLTR_PTYPE_NONF_IPV4_ESP,
216 	ICE_FLTR_PTYPE_NONF_IPV6_ESP,
217 	ICE_FLTR_PTYPE_NONF_IPV4_AH,
218 	ICE_FLTR_PTYPE_NONF_IPV6_AH,
219 	ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
220 	ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
221 	ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
222 	ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
223 	ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
224 	ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
225 	ICE_FLTR_PTYPE_NON_IP_L2,
226 	ICE_FLTR_PTYPE_FRAG_IPV4,
227 	ICE_FLTR_PTYPE_NONF_IPV6_UDP,
228 	ICE_FLTR_PTYPE_NONF_IPV6_TCP,
229 	ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
230 	ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
231 	ICE_FLTR_PTYPE_MAX,
232 };
233 
234 enum ice_fd_hw_seg {
235 	ICE_FD_HW_SEG_NON_TUN = 0,
236 	ICE_FD_HW_SEG_TUN,
237 	ICE_FD_HW_SEG_MAX,
238 };
239 
240 /* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */
241 #define ICE_MAX_FDIR_VSI_PER_FILTER	(2 + ICE_CHNL_MAX_TC)
242 
243 struct ice_fd_hw_prof {
244 	struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
245 	int cnt;
246 	u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
247 	u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
248 };
249 
250 /* Common HW capabilities for SW use */
251 struct ice_hw_common_caps {
252 	u32 valid_functions;
253 	/* DCB capabilities */
254 	u32 active_tc_bitmap;
255 	u32 maxtc;
256 
257 	/* Tx/Rx queues */
258 	u16 num_rxq;		/* Number/Total Rx queues */
259 	u16 rxq_first_id;	/* First queue ID for Rx queues */
260 	u16 num_txq;		/* Number/Total Tx queues */
261 	u16 txq_first_id;	/* First queue ID for Tx queues */
262 
263 	/* MSI-X vectors */
264 	u16 num_msix_vectors;
265 	u16 msix_vector_first_id;
266 
267 	/* Max MTU for function or device */
268 	u16 max_mtu;
269 
270 	/* Virtualization support */
271 	u8 sr_iov_1_1;			/* SR-IOV enabled */
272 
273 	/* RSS related capabilities */
274 	u16 rss_table_size;		/* 512 for PFs and 64 for VFs */
275 	u8 rss_table_entry_width;	/* RSS Entry width in bits */
276 
277 	u8 dcb;
278 	u8 ieee_1588;
279 	u8 rdma;
280 
281 	bool nvm_update_pending_nvm;
282 	bool nvm_update_pending_orom;
283 	bool nvm_update_pending_netlist;
284 #define ICE_NVM_PENDING_NVM_IMAGE		BIT(0)
285 #define ICE_NVM_PENDING_OROM			BIT(1)
286 #define ICE_NVM_PENDING_NETLIST			BIT(2)
287 	bool nvm_unified_update;
288 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT	BIT(3)
289 	/* PCIe reset avoidance */
290 	bool pcie_reset_avoidance;
291 	/* Post update reset restriction */
292 	bool reset_restrict_support;
293 };
294 
295 /* IEEE 1588 TIME_SYNC specific info */
296 /* Function specific definitions */
297 #define ICE_TS_FUNC_ENA_M		BIT(0)
298 #define ICE_TS_SRC_TMR_OWND_M		BIT(1)
299 #define ICE_TS_TMR_ENA_M		BIT(2)
300 #define ICE_TS_TMR_IDX_OWND_S		4
301 #define ICE_TS_TMR_IDX_OWND_M		BIT(4)
302 #define ICE_TS_CLK_FREQ_S		16
303 #define ICE_TS_CLK_FREQ_M		ICE_M(0x7, ICE_TS_CLK_FREQ_S)
304 #define ICE_TS_CLK_SRC_S		20
305 #define ICE_TS_CLK_SRC_M		BIT(20)
306 #define ICE_TS_TMR_IDX_ASSOC_S		24
307 #define ICE_TS_TMR_IDX_ASSOC_M		BIT(24)
308 
309 /* TIME_REF clock rate specification */
310 enum ice_time_ref_freq {
311 	ICE_TIME_REF_FREQ_25_000	= 0,
312 	ICE_TIME_REF_FREQ_122_880	= 1,
313 	ICE_TIME_REF_FREQ_125_000	= 2,
314 	ICE_TIME_REF_FREQ_153_600	= 3,
315 	ICE_TIME_REF_FREQ_156_250	= 4,
316 	ICE_TIME_REF_FREQ_245_760	= 5,
317 
318 	NUM_ICE_TIME_REF_FREQ
319 };
320 
321 /* Clock source specification */
322 enum ice_clk_src {
323 	ICE_CLK_SRC_TCX0	= 0, /* Temperature compensated oscillator  */
324 	ICE_CLK_SRC_TIME_REF	= 1, /* Use TIME_REF reference clock */
325 
326 	NUM_ICE_CLK_SRC
327 };
328 
329 struct ice_ts_func_info {
330 	/* Function specific info */
331 	enum ice_time_ref_freq time_ref;
332 	u8 clk_freq;
333 	u8 clk_src;
334 	u8 tmr_index_assoc;
335 	u8 ena;
336 	u8 tmr_index_owned;
337 	u8 src_tmr_owned;
338 	u8 tmr_ena;
339 };
340 
341 /* Device specific definitions */
342 #define ICE_TS_TMR0_OWNR_M		0x7
343 #define ICE_TS_TMR0_OWND_M		BIT(3)
344 #define ICE_TS_TMR1_OWNR_S		4
345 #define ICE_TS_TMR1_OWNR_M		ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
346 #define ICE_TS_TMR1_OWND_M		BIT(7)
347 #define ICE_TS_DEV_ENA_M		BIT(24)
348 #define ICE_TS_TMR0_ENA_M		BIT(25)
349 #define ICE_TS_TMR1_ENA_M		BIT(26)
350 
351 struct ice_ts_dev_info {
352 	/* Device specific info */
353 	u32 ena_ports;
354 	u32 tmr_own_map;
355 	u32 tmr0_owner;
356 	u32 tmr1_owner;
357 	u8 tmr0_owned;
358 	u8 tmr1_owned;
359 	u8 ena;
360 	u8 tmr0_ena;
361 	u8 tmr1_ena;
362 };
363 
364 /* Function specific capabilities */
365 struct ice_hw_func_caps {
366 	struct ice_hw_common_caps common_cap;
367 	u32 num_allocd_vfs;		/* Number of allocated VFs */
368 	u32 vf_base_id;			/* Logical ID of the first VF */
369 	u32 guar_num_vsi;
370 	u32 fd_fltr_guar;		/* Number of filters guaranteed */
371 	u32 fd_fltr_best_effort;	/* Number of best effort filters */
372 	struct ice_ts_func_info ts_func_info;
373 };
374 
375 /* Device wide capabilities */
376 struct ice_hw_dev_caps {
377 	struct ice_hw_common_caps common_cap;
378 	u32 num_vfs_exposed;		/* Total number of VFs exposed */
379 	u32 num_vsi_allocd_to_host;	/* Excluding EMP VSI */
380 	u32 num_flow_director_fltr;	/* Number of FD filters available */
381 	struct ice_ts_dev_info ts_dev_info;
382 	u32 num_funcs;
383 };
384 
385 /* MAC info */
386 struct ice_mac_info {
387 	u8 lan_addr[ETH_ALEN];
388 	u8 perm_addr[ETH_ALEN];
389 };
390 
391 /* Reset types used to determine which kind of reset was requested. These
392  * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
393  * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
394  * because its reset source is different than the other types listed.
395  */
396 enum ice_reset_req {
397 	ICE_RESET_POR	= 0,
398 	ICE_RESET_INVAL	= 0,
399 	ICE_RESET_CORER	= 1,
400 	ICE_RESET_GLOBR	= 2,
401 	ICE_RESET_EMPR	= 3,
402 	ICE_RESET_PFR	= 4,
403 };
404 
405 /* Bus parameters */
406 struct ice_bus_info {
407 	u16 device;
408 	u8 func;
409 };
410 
411 /* Flow control (FC) parameters */
412 struct ice_fc_info {
413 	enum ice_fc_mode current_mode;	/* FC mode in effect */
414 	enum ice_fc_mode req_mode;	/* FC mode requested by caller */
415 };
416 
417 /* Option ROM version information */
418 struct ice_orom_info {
419 	u8 major;			/* Major version of OROM */
420 	u8 patch;			/* Patch version of OROM */
421 	u16 build;			/* Build version of OROM */
422 };
423 
424 /* NVM version information */
425 struct ice_nvm_info {
426 	u32 eetrack;
427 	u8 major;
428 	u8 minor;
429 };
430 
431 /* netlist version information */
432 struct ice_netlist_info {
433 	u32 major;			/* major high/low */
434 	u32 minor;			/* minor high/low */
435 	u32 type;			/* type high/low */
436 	u32 rev;			/* revision high/low */
437 	u32 hash;			/* SHA-1 hash word */
438 	u16 cust_ver;			/* customer version */
439 };
440 
441 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
442  * of the flash image.
443  */
444 enum ice_flash_bank {
445 	ICE_INVALID_FLASH_BANK,
446 	ICE_1ST_FLASH_BANK,
447 	ICE_2ND_FLASH_BANK,
448 };
449 
450 /* Enumeration of which flash bank is desired to read from, either the active
451  * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
452  * code which just wants to read the active or inactive flash bank.
453  */
454 enum ice_bank_select {
455 	ICE_ACTIVE_FLASH_BANK,
456 	ICE_INACTIVE_FLASH_BANK,
457 };
458 
459 /* information for accessing NVM, OROM, and Netlist flash banks */
460 struct ice_bank_info {
461 	u32 nvm_ptr;				/* Pointer to 1st NVM bank */
462 	u32 nvm_size;				/* Size of NVM bank */
463 	u32 orom_ptr;				/* Pointer to 1st OROM bank */
464 	u32 orom_size;				/* Size of OROM bank */
465 	u32 netlist_ptr;			/* Pointer to 1st Netlist bank */
466 	u32 netlist_size;			/* Size of Netlist bank */
467 	enum ice_flash_bank nvm_bank;		/* Active NVM bank */
468 	enum ice_flash_bank orom_bank;		/* Active OROM bank */
469 	enum ice_flash_bank netlist_bank;	/* Active Netlist bank */
470 };
471 
472 /* Flash Chip Information */
473 struct ice_flash_info {
474 	struct ice_orom_info orom;	/* Option ROM version info */
475 	struct ice_nvm_info nvm;	/* NVM version information */
476 	struct ice_netlist_info netlist;/* Netlist version info */
477 	struct ice_bank_info banks;	/* Flash Bank information */
478 	u16 sr_words;			/* Shadow RAM size in words */
479 	u32 flash_size;			/* Size of available flash in bytes */
480 	u8 blank_nvm_mode;		/* is NVM empty (no FW present) */
481 };
482 
483 struct ice_link_default_override_tlv {
484 	u8 options;
485 #define ICE_LINK_OVERRIDE_OPT_M		0x3F
486 #define ICE_LINK_OVERRIDE_STRICT_MODE	BIT(0)
487 #define ICE_LINK_OVERRIDE_EPCT_DIS	BIT(1)
488 #define ICE_LINK_OVERRIDE_PORT_DIS	BIT(2)
489 #define ICE_LINK_OVERRIDE_EN		BIT(3)
490 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS	BIT(4)
491 #define ICE_LINK_OVERRIDE_EEE_EN	BIT(5)
492 	u8 phy_config;
493 #define ICE_LINK_OVERRIDE_PHY_CFG_S	8
494 #define ICE_LINK_OVERRIDE_PHY_CFG_M	(0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
495 #define ICE_LINK_OVERRIDE_PAUSE_M	0x3
496 #define ICE_LINK_OVERRIDE_LESM_EN	BIT(6)
497 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN	BIT(7)
498 	u8 fec_options;
499 #define ICE_LINK_OVERRIDE_FEC_OPT_M	0xFF
500 	u8 rsvd1;
501 	u64 phy_type_low;
502 	u64 phy_type_high;
503 };
504 
505 #define ICE_NVM_VER_LEN	32
506 
507 /* Max number of port to queue branches w.r.t topology */
508 #define ICE_MAX_TRAFFIC_CLASS 8
509 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
510 
511 #define ice_for_each_traffic_class(_i)	\
512 	for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
513 
514 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
515  * to driver defined policy for default aggregator
516  */
517 #define ICE_INVAL_TEID 0xFFFFFFFF
518 #define ICE_DFLT_AGG_ID 0
519 
520 struct ice_sched_node {
521 	struct ice_sched_node *parent;
522 	struct ice_sched_node *sibling; /* next sibling in the same layer */
523 	struct ice_sched_node **children;
524 	struct ice_aqc_txsched_elem_data info;
525 	u32 agg_id;			/* aggregator group ID */
526 	u16 vsi_handle;
527 	u8 in_use;			/* suspended or in use */
528 	u8 tx_sched_layer;		/* Logical Layer (1-9) */
529 	u8 num_children;
530 	u8 tc_num;
531 	u8 owner;
532 #define ICE_SCHED_NODE_OWNER_LAN	0
533 #define ICE_SCHED_NODE_OWNER_RDMA	2
534 };
535 
536 /* Access Macros for Tx Sched Elements data */
537 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
538 
539 /* The aggregator type determines if identifier is for a VSI group,
540  * aggregator group, aggregator of queues, or queue group.
541  */
542 enum ice_agg_type {
543 	ICE_AGG_TYPE_UNKNOWN = 0,
544 	ICE_AGG_TYPE_VSI,
545 	ICE_AGG_TYPE_AGG, /* aggregator */
546 	ICE_AGG_TYPE_Q,
547 	ICE_AGG_TYPE_QG
548 };
549 
550 /* Rate limit types */
551 enum ice_rl_type {
552 	ICE_UNKNOWN_BW = 0,
553 	ICE_MIN_BW,		/* for CIR profile */
554 	ICE_MAX_BW,		/* for EIR profile */
555 	ICE_SHARED_BW		/* for shared profile */
556 };
557 
558 #define ICE_SCHED_MIN_BW		500		/* in Kbps */
559 #define ICE_SCHED_MAX_BW		100000000	/* in Kbps */
560 #define ICE_SCHED_DFLT_BW		0xFFFFFFFF	/* unlimited */
561 #define ICE_SCHED_DFLT_RL_PROF_ID	0
562 #define ICE_SCHED_NO_SHARED_RL_PROF_ID	0xFFFF
563 #define ICE_SCHED_DFLT_BW_WT		4
564 #define ICE_SCHED_INVAL_PROF_ID		0xFFFF
565 #define ICE_SCHED_DFLT_BURST_SIZE	(15 * 1024)	/* in bytes (15k) */
566 
567  /* Data structure for saving BW information */
568 enum ice_bw_type {
569 	ICE_BW_TYPE_PRIO,
570 	ICE_BW_TYPE_CIR,
571 	ICE_BW_TYPE_CIR_WT,
572 	ICE_BW_TYPE_EIR,
573 	ICE_BW_TYPE_EIR_WT,
574 	ICE_BW_TYPE_SHARED,
575 	ICE_BW_TYPE_CNT		/* This must be last */
576 };
577 
578 struct ice_bw {
579 	u32 bw;
580 	u16 bw_alloc;
581 };
582 
583 struct ice_bw_type_info {
584 	DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
585 	u8 generic;
586 	struct ice_bw cir_bw;
587 	struct ice_bw eir_bw;
588 	u32 shared_bw;
589 };
590 
591 /* VSI queue context structure for given TC */
592 struct ice_q_ctx {
593 	u16  q_handle;
594 	u32  q_teid;
595 	/* bw_t_info saves queue BW information */
596 	struct ice_bw_type_info bw_t_info;
597 };
598 
599 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
600 struct ice_sched_vsi_info {
601 	struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
602 	struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
603 	struct list_head list_entry;
604 	u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
605 	u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS];
606 	/* bw_t_info saves VSI BW information */
607 	struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
608 };
609 
610 /* driver defines the policy */
611 struct ice_sched_tx_policy {
612 	u16 max_num_vsis;
613 	u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
614 	u8 rdma_ena;
615 };
616 
617 /* CEE or IEEE 802.1Qaz ETS Configuration data */
618 struct ice_dcb_ets_cfg {
619 	u8 willing;
620 	u8 cbs;
621 	u8 maxtcs;
622 	u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
623 	u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
624 	u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
625 };
626 
627 /* CEE or IEEE 802.1Qaz PFC Configuration data */
628 struct ice_dcb_pfc_cfg {
629 	u8 willing;
630 	u8 mbc;
631 	u8 pfccap;
632 	u8 pfcena;
633 };
634 
635 /* CEE or IEEE 802.1Qaz Application Priority data */
636 struct ice_dcb_app_priority_table {
637 	u16 prot_id;
638 	u8 priority;
639 	u8 selector;
640 };
641 
642 #define ICE_MAX_USER_PRIORITY	8
643 #define ICE_DCBX_MAX_APPS	64
644 #define ICE_DSCP_NUM_VAL	64
645 #define ICE_LLDPDU_SIZE		1500
646 #define ICE_TLV_STATUS_OPER	0x1
647 #define ICE_TLV_STATUS_SYNC	0x2
648 #define ICE_TLV_STATUS_ERR	0x4
649 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
650 #define ICE_APP_SEL_ETHTYPE	0x1
651 #define ICE_APP_SEL_TCPIP	0x2
652 #define ICE_CEE_APP_SEL_ETHTYPE	0x0
653 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR	0x134
654 #define ICE_CEE_APP_SEL_TCPIP	0x1
655 
656 struct ice_dcbx_cfg {
657 	u32 numapps;
658 	u32 tlv_status; /* CEE mode TLV status */
659 	struct ice_dcb_ets_cfg etscfg;
660 	struct ice_dcb_ets_cfg etsrec;
661 	struct ice_dcb_pfc_cfg pfc;
662 #define ICE_QOS_MODE_VLAN	0x0
663 #define ICE_QOS_MODE_DSCP	0x1
664 	u8 pfc_mode;
665 	struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
666 	/* when DSCP mapping defined by user set its bit to 1 */
667 	DECLARE_BITMAP(dscp_mapped, ICE_DSCP_NUM_VAL);
668 	/* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
669 	u8 dscp_map[ICE_DSCP_NUM_VAL];
670 	u8 dcbx_mode;
671 #define ICE_DCBX_MODE_CEE	0x1
672 #define ICE_DCBX_MODE_IEEE	0x2
673 	u8 app_mode;
674 #define ICE_DCBX_APPS_NON_WILLING	0x1
675 };
676 
677 struct ice_qos_cfg {
678 	struct ice_dcbx_cfg local_dcbx_cfg;	/* Oper/Local Cfg */
679 	struct ice_dcbx_cfg desired_dcbx_cfg;	/* CEE Desired Cfg */
680 	struct ice_dcbx_cfg remote_dcbx_cfg;	/* Peer Cfg */
681 	u8 dcbx_status : 3;			/* see ICE_DCBX_STATUS_DIS */
682 	u8 is_sw_lldp : 1;
683 };
684 
685 struct ice_port_info {
686 	struct ice_sched_node *root;	/* Root Node per Port */
687 	struct ice_hw *hw;		/* back pointer to HW instance */
688 	u32 last_node_teid;		/* scheduler last node info */
689 	u16 sw_id;			/* Initial switch ID belongs to port */
690 	u16 pf_vf_num;
691 	u8 port_state;
692 #define ICE_SCHED_PORT_STATE_INIT	0x0
693 #define ICE_SCHED_PORT_STATE_READY	0x1
694 	u8 lport;
695 #define ICE_LPORT_MASK			0xff
696 	u16 dflt_tx_vsi_rule_id;
697 	u16 dflt_tx_vsi_num;
698 	u16 dflt_rx_vsi_rule_id;
699 	u16 dflt_rx_vsi_num;
700 	struct ice_fc_info fc;
701 	struct ice_mac_info mac;
702 	struct ice_phy_info phy;
703 	struct mutex sched_lock;	/* protect access to TXSched tree */
704 	struct ice_sched_node *
705 		sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
706 	/* List contain profile ID(s) and other params per layer */
707 	struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
708 	struct ice_qos_cfg qos_cfg;
709 	u8 is_vf:1;
710 };
711 
712 struct ice_switch_info {
713 	struct list_head vsi_list_map_head;
714 	struct ice_sw_recipe *recp_list;
715 	u16 prof_res_bm_init;
716 	u16 max_used_prof_index;
717 
718 	DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
719 };
720 
721 /* FW logging configuration */
722 struct ice_fw_log_evnt {
723 	u8 cfg : 4;	/* New event enables to configure */
724 	u8 cur : 4;	/* Current/active event enables */
725 };
726 
727 struct ice_fw_log_cfg {
728 	u8 cq_en : 1;    /* FW logging is enabled via the control queue */
729 	u8 uart_en : 1;  /* FW logging is enabled via UART for all PFs */
730 	u8 actv_evnts;   /* Cumulation of currently enabled log events */
731 
732 #define ICE_FW_LOG_EVNT_INFO	(ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
733 #define ICE_FW_LOG_EVNT_INIT	(ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
734 #define ICE_FW_LOG_EVNT_FLOW	(ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
735 #define ICE_FW_LOG_EVNT_ERR	(ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
736 	struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
737 };
738 
739 /* Enum defining the different states of the mailbox snapshot in the
740  * PF-VF mailbox overflow detection algorithm. The snapshot can be in
741  * states:
742  * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot
743  * within the mailbox buffer.
744  * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot
745  * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the
746  * mailbox and mark any VFs sending more messages than the threshold limit set.
747  * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF.
748  */
749 enum ice_mbx_snapshot_state {
750 	ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0,
751 	ICE_MAL_VF_DETECT_STATE_TRAVERSE,
752 	ICE_MAL_VF_DETECT_STATE_DETECT,
753 	ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF,
754 };
755 
756 /* Structure to hold information of the static snapshot and the mailbox
757  * buffer data used to generate and track the snapshot.
758  * 1. state: the state of the mailbox snapshot in the malicious VF
759  * detection state handler ice_mbx_vf_state_handler()
760  * 2. head: head of the mailbox snapshot in a circular mailbox buffer
761  * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer
762  * 4. num_iterations: number of messages traversed in circular mailbox buffer
763  * 5. num_msg_proc: number of messages processed in mailbox
764  * 6. num_pending_arq: number of pending asynchronous messages
765  * 7. max_num_msgs_mbx: maximum messages in mailbox for currently
766  * serviced work item or interrupt.
767  */
768 struct ice_mbx_snap_buffer_data {
769 	enum ice_mbx_snapshot_state state;
770 	u32 head;
771 	u32 tail;
772 	u32 num_iterations;
773 	u16 num_msg_proc;
774 	u16 num_pending_arq;
775 	u16 max_num_msgs_mbx;
776 };
777 
778 /* Structure to track messages sent by VFs on mailbox:
779  * 1. vf_cntr: a counter array of VFs to track the number of
780  * asynchronous messages sent by each VF
781  * 2. vfcntr_len: number of entries in VF counter array
782  */
783 struct ice_mbx_vf_counter {
784 	u32 *vf_cntr;
785 	u32 vfcntr_len;
786 };
787 
788 /* Structure to hold data relevant to the captured static snapshot
789  * of the PF-VF mailbox.
790  */
791 struct ice_mbx_snapshot {
792 	struct ice_mbx_snap_buffer_data mbx_buf;
793 	struct ice_mbx_vf_counter mbx_vf;
794 };
795 
796 /* Structure to hold data to be used for capturing or updating a
797  * static snapshot.
798  * 1. num_msg_proc: number of messages processed in mailbox
799  * 2. num_pending_arq: number of pending asynchronous messages
800  * 3. max_num_msgs_mbx: maximum messages in mailbox for currently
801  * serviced work item or interrupt.
802  * 4. async_watermark_val: An upper threshold set by caller to determine
803  * if the pending arq count is large enough to assume that there is
804  * the possibility of a mailicious VF.
805  */
806 struct ice_mbx_data {
807 	u16 num_msg_proc;
808 	u16 num_pending_arq;
809 	u16 max_num_msgs_mbx;
810 	u16 async_watermark_val;
811 };
812 
813 /* Port hardware description */
814 struct ice_hw {
815 	u8 __iomem *hw_addr;
816 	void *back;
817 	struct ice_aqc_layer_props *layer_info;
818 	struct ice_port_info *port_info;
819 	/* PSM clock frequency for calculating RL profile params */
820 	u32 psm_clk_freq;
821 	u64 debug_mask;		/* bitmap for debug mask */
822 	enum ice_mac_type mac_type;
823 
824 	u16 fd_ctr_base;	/* FD counter base index */
825 
826 	/* pci info */
827 	u16 device_id;
828 	u16 vendor_id;
829 	u16 subsystem_device_id;
830 	u16 subsystem_vendor_id;
831 	u8 revision_id;
832 
833 	u8 pf_id;		/* device profile info */
834 
835 	u16 max_burst_size;	/* driver sets this value */
836 
837 	/* Tx Scheduler values */
838 	u8 num_tx_sched_layers;
839 	u8 num_tx_sched_phys_layers;
840 	u8 flattened_layers;
841 	u8 max_cgds;
842 	u8 sw_entry_point_layer;
843 	u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
844 	struct list_head agg_list;	/* lists all aggregator */
845 
846 	struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
847 	u8 evb_veb;		/* true for VEB, false for VEPA */
848 	u8 reset_ongoing;	/* true if HW is in reset, false otherwise */
849 	struct ice_bus_info bus;
850 	struct ice_flash_info flash;
851 	struct ice_hw_dev_caps dev_caps;	/* device capabilities */
852 	struct ice_hw_func_caps func_caps;	/* function capabilities */
853 
854 	struct ice_switch_info *switch_info;	/* switch filter lists */
855 
856 	/* Control Queue info */
857 	struct ice_ctl_q_info adminq;
858 	struct ice_ctl_q_info sbq;
859 	struct ice_ctl_q_info mailboxq;
860 
861 	u8 api_branch;		/* API branch version */
862 	u8 api_maj_ver;		/* API major version */
863 	u8 api_min_ver;		/* API minor version */
864 	u8 api_patch;		/* API patch version */
865 	u8 fw_branch;		/* firmware branch version */
866 	u8 fw_maj_ver;		/* firmware major version */
867 	u8 fw_min_ver;		/* firmware minor version */
868 	u8 fw_patch;		/* firmware patch version */
869 	u32 fw_build;		/* firmware build number */
870 
871 	struct ice_fw_log_cfg fw_log;
872 
873 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
874  * register. Used for determining the ITR/INTRL granularity during
875  * initialization.
876  */
877 #define ICE_MAX_AGG_BW_200G	0x0
878 #define ICE_MAX_AGG_BW_100G	0X1
879 #define ICE_MAX_AGG_BW_50G	0x2
880 #define ICE_MAX_AGG_BW_25G	0x3
881 	/* ITR granularity for different speeds */
882 #define ICE_ITR_GRAN_ABOVE_25	2
883 #define ICE_ITR_GRAN_MAX_25	4
884 	/* ITR granularity in 1 us */
885 	u8 itr_gran;
886 	/* INTRL granularity for different speeds */
887 #define ICE_INTRL_GRAN_ABOVE_25	4
888 #define ICE_INTRL_GRAN_MAX_25	8
889 	/* INTRL granularity in 1 us */
890 	u8 intrl_gran;
891 
892 	u8 ucast_shared;	/* true if VSIs can share unicast addr */
893 
894 #define ICE_PHY_PER_NAC		1
895 #define ICE_MAX_QUAD		2
896 #define ICE_NUM_QUAD_TYPE	2
897 #define ICE_PORTS_PER_QUAD	4
898 #define ICE_PHY_0_LAST_QUAD	1
899 #define ICE_PORTS_PER_PHY	8
900 #define ICE_NUM_EXTERNAL_PORTS		ICE_PORTS_PER_PHY
901 
902 	/* Active package version (currently active) */
903 	struct ice_pkg_ver active_pkg_ver;
904 	u32 active_track_id;
905 	u8 active_pkg_name[ICE_PKG_NAME_SIZE];
906 	u8 active_pkg_in_nvm;
907 
908 	/* Driver's package ver - (from the Ice Metadata section) */
909 	struct ice_pkg_ver pkg_ver;
910 	u8 pkg_name[ICE_PKG_NAME_SIZE];
911 
912 	/* Driver's Ice segment format version and ID (from the Ice seg) */
913 	struct ice_pkg_ver ice_seg_fmt_ver;
914 	u8 ice_seg_id[ICE_SEG_ID_SIZE];
915 
916 	/* Pointer to the ice segment */
917 	struct ice_seg *seg;
918 
919 	/* Pointer to allocated copy of pkg memory */
920 	u8 *pkg_copy;
921 	u32 pkg_size;
922 
923 	/* tunneling info */
924 	struct mutex tnl_lock;
925 	struct ice_tunnel_table tnl;
926 
927 	struct udp_tunnel_nic_shared udp_tunnel_shared;
928 	struct udp_tunnel_nic_info udp_tunnel_nic;
929 
930 	/* dvm boost update information */
931 	struct ice_dvm_table dvm_upd;
932 
933 	/* HW block tables */
934 	struct ice_blk_info blk[ICE_BLK_COUNT];
935 	struct mutex fl_profs_locks[ICE_BLK_COUNT];	/* lock fltr profiles */
936 	struct list_head fl_profs[ICE_BLK_COUNT];
937 
938 	/* Flow Director filter info */
939 	int fdir_active_fltr;
940 
941 	struct mutex fdir_fltr_lock;	/* protect Flow Director */
942 	struct list_head fdir_list_head;
943 
944 	/* Book-keeping of side-band filter count per flow-type.
945 	 * This is used to detect and handle input set changes for
946 	 * respective flow-type.
947 	 */
948 	u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
949 
950 	struct ice_fd_hw_prof **fdir_prof;
951 	DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
952 	struct mutex rss_locks;	/* protect RSS configuration */
953 	struct list_head rss_list_head;
954 	struct ice_mbx_snapshot mbx_snapshot;
955 	DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX);
956 	u8 dvm_ena;
957 	u16 io_expander_handle;
958 };
959 
960 /* Statistics collected by each port, VSI, VEB, and S-channel */
961 struct ice_eth_stats {
962 	u64 rx_bytes;			/* gorc */
963 	u64 rx_unicast;			/* uprc */
964 	u64 rx_multicast;		/* mprc */
965 	u64 rx_broadcast;		/* bprc */
966 	u64 rx_discards;		/* rdpc */
967 	u64 rx_unknown_protocol;	/* rupp */
968 	u64 tx_bytes;			/* gotc */
969 	u64 tx_unicast;			/* uptc */
970 	u64 tx_multicast;		/* mptc */
971 	u64 tx_broadcast;		/* bptc */
972 	u64 tx_discards;		/* tdpc */
973 	u64 tx_errors;			/* tepc */
974 };
975 
976 #define ICE_MAX_UP	8
977 
978 /* Statistics collected by the MAC */
979 struct ice_hw_port_stats {
980 	/* eth stats collected by the port */
981 	struct ice_eth_stats eth;
982 	/* additional port specific stats */
983 	u64 tx_dropped_link_down;	/* tdold */
984 	u64 crc_errors;			/* crcerrs */
985 	u64 illegal_bytes;		/* illerrc */
986 	u64 error_bytes;		/* errbc */
987 	u64 mac_local_faults;		/* mlfc */
988 	u64 mac_remote_faults;		/* mrfc */
989 	u64 rx_len_errors;		/* rlec */
990 	u64 link_xon_rx;		/* lxonrxc */
991 	u64 link_xoff_rx;		/* lxoffrxc */
992 	u64 link_xon_tx;		/* lxontxc */
993 	u64 link_xoff_tx;		/* lxofftxc */
994 	u64 priority_xon_rx[8];		/* pxonrxc[8] */
995 	u64 priority_xoff_rx[8];	/* pxoffrxc[8] */
996 	u64 priority_xon_tx[8];		/* pxontxc[8] */
997 	u64 priority_xoff_tx[8];	/* pxofftxc[8] */
998 	u64 priority_xon_2_xoff[8];	/* pxon2offc[8] */
999 	u64 rx_size_64;			/* prc64 */
1000 	u64 rx_size_127;		/* prc127 */
1001 	u64 rx_size_255;		/* prc255 */
1002 	u64 rx_size_511;		/* prc511 */
1003 	u64 rx_size_1023;		/* prc1023 */
1004 	u64 rx_size_1522;		/* prc1522 */
1005 	u64 rx_size_big;		/* prc9522 */
1006 	u64 rx_undersize;		/* ruc */
1007 	u64 rx_fragments;		/* rfc */
1008 	u64 rx_oversize;		/* roc */
1009 	u64 rx_jabber;			/* rjc */
1010 	u64 tx_size_64;			/* ptc64 */
1011 	u64 tx_size_127;		/* ptc127 */
1012 	u64 tx_size_255;		/* ptc255 */
1013 	u64 tx_size_511;		/* ptc511 */
1014 	u64 tx_size_1023;		/* ptc1023 */
1015 	u64 tx_size_1522;		/* ptc1522 */
1016 	u64 tx_size_big;		/* ptc9522 */
1017 	/* flow director stats */
1018 	u32 fd_sb_status;
1019 	u64 fd_sb_match;
1020 };
1021 
1022 enum ice_sw_fwd_act_type {
1023 	ICE_FWD_TO_VSI = 0,
1024 	ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1025 	ICE_FWD_TO_Q,
1026 	ICE_FWD_TO_QGRP,
1027 	ICE_DROP_PACKET,
1028 	ICE_INVAL_ACT
1029 };
1030 
1031 struct ice_aq_get_set_rss_lut_params {
1032 	u16 vsi_handle;		/* software VSI handle */
1033 	u16 lut_size;		/* size of the LUT buffer */
1034 	u8 lut_type;		/* type of the LUT (i.e. VSI, PF, Global) */
1035 	u8 *lut;		/* input RSS LUT for set and output RSS LUT for get */
1036 	u8 global_lut_id;	/* only valid when lut_type is global */
1037 };
1038 
1039 /* Checksum and Shadow RAM pointers */
1040 #define ICE_SR_NVM_CTRL_WORD		0x00
1041 #define ICE_SR_BOOT_CFG_PTR		0x132
1042 #define ICE_SR_NVM_WOL_CFG		0x19
1043 #define ICE_NVM_OROM_VER_OFF		0x02
1044 #define ICE_SR_PBA_BLOCK_PTR		0x16
1045 #define ICE_SR_NVM_DEV_STARTER_VER	0x18
1046 #define ICE_SR_NVM_EETRACK_LO		0x2D
1047 #define ICE_SR_NVM_EETRACK_HI		0x2E
1048 #define ICE_NVM_VER_LO_SHIFT		0
1049 #define ICE_NVM_VER_LO_MASK		(0xff << ICE_NVM_VER_LO_SHIFT)
1050 #define ICE_NVM_VER_HI_SHIFT		12
1051 #define ICE_NVM_VER_HI_MASK		(0xf << ICE_NVM_VER_HI_SHIFT)
1052 #define ICE_OROM_VER_PATCH_SHIFT	0
1053 #define ICE_OROM_VER_PATCH_MASK		(0xff << ICE_OROM_VER_PATCH_SHIFT)
1054 #define ICE_OROM_VER_BUILD_SHIFT	8
1055 #define ICE_OROM_VER_BUILD_MASK		(0xffff << ICE_OROM_VER_BUILD_SHIFT)
1056 #define ICE_OROM_VER_SHIFT		24
1057 #define ICE_OROM_VER_MASK		(0xff << ICE_OROM_VER_SHIFT)
1058 #define ICE_SR_PFA_PTR			0x40
1059 #define ICE_SR_1ST_NVM_BANK_PTR		0x42
1060 #define ICE_SR_NVM_BANK_SIZE		0x43
1061 #define ICE_SR_1ST_OROM_BANK_PTR	0x44
1062 #define ICE_SR_OROM_BANK_SIZE		0x45
1063 #define ICE_SR_NETLIST_BANK_PTR		0x46
1064 #define ICE_SR_NETLIST_BANK_SIZE	0x47
1065 #define ICE_SR_SECTOR_SIZE_IN_WORDS	0x800
1066 
1067 /* CSS Header words */
1068 #define ICE_NVM_CSS_SREV_L			0x14
1069 #define ICE_NVM_CSS_SREV_H			0x15
1070 
1071 /* Length of CSS header section in words */
1072 #define ICE_CSS_HEADER_LENGTH			330
1073 
1074 /* Offset of Shadow RAM copy in the NVM bank area. */
1075 #define ICE_NVM_SR_COPY_WORD_OFFSET		roundup(ICE_CSS_HEADER_LENGTH, 32)
1076 
1077 /* Size in bytes of Option ROM trailer */
1078 #define ICE_NVM_OROM_TRAILER_LENGTH		(2 * ICE_CSS_HEADER_LENGTH)
1079 
1080 /* The Link Topology Netlist section is stored as a series of words. It is
1081  * stored in the NVM as a TLV, with the first two words containing the type
1082  * and length.
1083  */
1084 #define ICE_NETLIST_LINK_TOPO_MOD_ID		0x011B
1085 #define ICE_NETLIST_TYPE_OFFSET			0x0000
1086 #define ICE_NETLIST_LEN_OFFSET			0x0001
1087 
1088 /* The Link Topology section follows the TLV header. When reading the netlist
1089  * using ice_read_netlist_module, we need to account for the 2-word TLV
1090  * header.
1091  */
1092 #define ICE_NETLIST_LINK_TOPO_OFFSET(n)		((n) + 2)
1093 
1094 #define ICE_LINK_TOPO_MODULE_LEN		ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1095 #define ICE_LINK_TOPO_NODE_COUNT		ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1096 
1097 #define ICE_LINK_TOPO_NODE_COUNT_M		ICE_M(0x3FF, 0)
1098 
1099 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1100 #define ICE_NETLIST_ID_BLK_SIZE			0x30
1101 #define ICE_NETLIST_ID_BLK_OFFSET(n)		ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1102 
1103 /* netlist ID block field offsets (word offsets) */
1104 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW	0x02
1105 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH	0x03
1106 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW	0x04
1107 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH	0x05
1108 #define ICE_NETLIST_ID_BLK_TYPE_LOW		0x06
1109 #define ICE_NETLIST_ID_BLK_TYPE_HIGH		0x07
1110 #define ICE_NETLIST_ID_BLK_REV_LOW		0x08
1111 #define ICE_NETLIST_ID_BLK_REV_HIGH		0x09
1112 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n)	(0x0A + (n))
1113 #define ICE_NETLIST_ID_BLK_CUST_VER		0x2F
1114 
1115 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */
1116 #define ICE_SR_CTRL_WORD_1_S		0x06
1117 #define ICE_SR_CTRL_WORD_1_M		(0x03 << ICE_SR_CTRL_WORD_1_S)
1118 #define ICE_SR_CTRL_WORD_VALID		0x1
1119 #define ICE_SR_CTRL_WORD_OROM_BANK	BIT(3)
1120 #define ICE_SR_CTRL_WORD_NETLIST_BANK	BIT(4)
1121 #define ICE_SR_CTRL_WORD_NVM_BANK	BIT(5)
1122 
1123 #define ICE_SR_NVM_PTR_4KB_UNITS	BIT(15)
1124 
1125 /* Link override related */
1126 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS		10
1127 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS	4
1128 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET		2
1129 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET	1
1130 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET	2
1131 #define ICE_FW_API_LINK_OVERRIDE_MAJ		1
1132 #define ICE_FW_API_LINK_OVERRIDE_MIN		5
1133 #define ICE_FW_API_LINK_OVERRIDE_PATCH		2
1134 
1135 #define ICE_SR_WORDS_IN_1KB		512
1136 
1137 /* Hash redirection LUT for VSI - maximum array size */
1138 #define ICE_VSIQF_HLUT_ARRAY_SIZE	((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1139 
1140 /* AQ API version for LLDP_FILTER_CONTROL */
1141 #define ICE_FW_API_LLDP_FLTR_MAJ	1
1142 #define ICE_FW_API_LLDP_FLTR_MIN	7
1143 #define ICE_FW_API_LLDP_FLTR_PATCH	1
1144 
1145 /* AQ API version for report default configuration */
1146 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ		1
1147 #define ICE_FW_API_REPORT_DFLT_CFG_MIN		7
1148 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH	3
1149 
1150 #endif /* _ICE_TYPE_H_ */
1151