1 /* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27 #ifndef _I915_DRM_H_ 28 #define _I915_DRM_H_ 29 30 #include "drm.h" 31 32 /* Please note that modifications to all structs defined here are 33 * subject to backwards-compatibility constraints. 34 */ 35 36 #ifdef __KERNEL__ 37 /* For use by IPS driver */ 38 extern unsigned long i915_read_mch_val(void); 39 extern bool i915_gpu_raise(void); 40 extern bool i915_gpu_lower(void); 41 extern bool i915_gpu_busy(void); 42 extern bool i915_gpu_turbo_disable(void); 43 #endif 44 45 /* Each region is a minimum of 16k, and there are at most 255 of them. 46 */ 47 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 48 * of chars for next/prev indices */ 49 #define I915_LOG_MIN_TEX_REGION_SIZE 14 50 51 typedef struct _drm_i915_init { 52 enum { 53 I915_INIT_DMA = 0x01, 54 I915_CLEANUP_DMA = 0x02, 55 I915_RESUME_DMA = 0x03 56 } func; 57 unsigned int mmio_offset; 58 int sarea_priv_offset; 59 unsigned int ring_start; 60 unsigned int ring_end; 61 unsigned int ring_size; 62 unsigned int front_offset; 63 unsigned int back_offset; 64 unsigned int depth_offset; 65 unsigned int w; 66 unsigned int h; 67 unsigned int pitch; 68 unsigned int pitch_bits; 69 unsigned int back_pitch; 70 unsigned int depth_pitch; 71 unsigned int cpp; 72 unsigned int chipset; 73 } drm_i915_init_t; 74 75 typedef struct _drm_i915_sarea { 76 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 77 int last_upload; /* last time texture was uploaded */ 78 int last_enqueue; /* last time a buffer was enqueued */ 79 int last_dispatch; /* age of the most recently dispatched buffer */ 80 int ctxOwner; /* last context to upload state */ 81 int texAge; 82 int pf_enabled; /* is pageflipping allowed? */ 83 int pf_active; 84 int pf_current_page; /* which buffer is being displayed? */ 85 int perf_boxes; /* performance boxes to be displayed */ 86 int width, height; /* screen size in pixels */ 87 88 drm_handle_t front_handle; 89 int front_offset; 90 int front_size; 91 92 drm_handle_t back_handle; 93 int back_offset; 94 int back_size; 95 96 drm_handle_t depth_handle; 97 int depth_offset; 98 int depth_size; 99 100 drm_handle_t tex_handle; 101 int tex_offset; 102 int tex_size; 103 int log_tex_granularity; 104 int pitch; 105 int rotation; /* 0, 90, 180 or 270 */ 106 int rotated_offset; 107 int rotated_size; 108 int rotated_pitch; 109 int virtualX, virtualY; 110 111 unsigned int front_tiled; 112 unsigned int back_tiled; 113 unsigned int depth_tiled; 114 unsigned int rotated_tiled; 115 unsigned int rotated2_tiled; 116 117 int pipeA_x; 118 int pipeA_y; 119 int pipeA_w; 120 int pipeA_h; 121 int pipeB_x; 122 int pipeB_y; 123 int pipeB_w; 124 int pipeB_h; 125 126 /* fill out some space for old userspace triple buffer */ 127 drm_handle_t unused_handle; 128 __u32 unused1, unused2, unused3; 129 130 /* buffer object handles for static buffers. May change 131 * over the lifetime of the client. 132 */ 133 __u32 front_bo_handle; 134 __u32 back_bo_handle; 135 __u32 unused_bo_handle; 136 __u32 depth_bo_handle; 137 138 } drm_i915_sarea_t; 139 140 /* due to userspace building against these headers we need some compat here */ 141 #define planeA_x pipeA_x 142 #define planeA_y pipeA_y 143 #define planeA_w pipeA_w 144 #define planeA_h pipeA_h 145 #define planeB_x pipeB_x 146 #define planeB_y pipeB_y 147 #define planeB_w pipeB_w 148 #define planeB_h pipeB_h 149 150 /* Flags for perf_boxes 151 */ 152 #define I915_BOX_RING_EMPTY 0x1 153 #define I915_BOX_FLIP 0x2 154 #define I915_BOX_WAIT 0x4 155 #define I915_BOX_TEXTURE_LOAD 0x8 156 #define I915_BOX_LOST_CONTEXT 0x10 157 158 /* I915 specific ioctls 159 * The device specific ioctl range is 0x40 to 0x79. 160 */ 161 #define DRM_I915_INIT 0x00 162 #define DRM_I915_FLUSH 0x01 163 #define DRM_I915_FLIP 0x02 164 #define DRM_I915_BATCHBUFFER 0x03 165 #define DRM_I915_IRQ_EMIT 0x04 166 #define DRM_I915_IRQ_WAIT 0x05 167 #define DRM_I915_GETPARAM 0x06 168 #define DRM_I915_SETPARAM 0x07 169 #define DRM_I915_ALLOC 0x08 170 #define DRM_I915_FREE 0x09 171 #define DRM_I915_INIT_HEAP 0x0a 172 #define DRM_I915_CMDBUFFER 0x0b 173 #define DRM_I915_DESTROY_HEAP 0x0c 174 #define DRM_I915_SET_VBLANK_PIPE 0x0d 175 #define DRM_I915_GET_VBLANK_PIPE 0x0e 176 #define DRM_I915_VBLANK_SWAP 0x0f 177 #define DRM_I915_HWS_ADDR 0x11 178 #define DRM_I915_GEM_INIT 0x13 179 #define DRM_I915_GEM_EXECBUFFER 0x14 180 #define DRM_I915_GEM_PIN 0x15 181 #define DRM_I915_GEM_UNPIN 0x16 182 #define DRM_I915_GEM_BUSY 0x17 183 #define DRM_I915_GEM_THROTTLE 0x18 184 #define DRM_I915_GEM_ENTERVT 0x19 185 #define DRM_I915_GEM_LEAVEVT 0x1a 186 #define DRM_I915_GEM_CREATE 0x1b 187 #define DRM_I915_GEM_PREAD 0x1c 188 #define DRM_I915_GEM_PWRITE 0x1d 189 #define DRM_I915_GEM_MMAP 0x1e 190 #define DRM_I915_GEM_SET_DOMAIN 0x1f 191 #define DRM_I915_GEM_SW_FINISH 0x20 192 #define DRM_I915_GEM_SET_TILING 0x21 193 #define DRM_I915_GEM_GET_TILING 0x22 194 #define DRM_I915_GEM_GET_APERTURE 0x23 195 #define DRM_I915_GEM_MMAP_GTT 0x24 196 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 197 #define DRM_I915_GEM_MADVISE 0x26 198 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 199 #define DRM_I915_OVERLAY_ATTRS 0x28 200 #define DRM_I915_GEM_EXECBUFFER2 0x29 201 202 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 203 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 204 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 205 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 206 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 207 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 208 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 209 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 210 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 211 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 212 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 213 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 214 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 215 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 216 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 217 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 218 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 219 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 220 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 221 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 222 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 223 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 224 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 225 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 226 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 227 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 228 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 229 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 230 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 231 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 232 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 233 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 234 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 235 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 236 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 237 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 238 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 239 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 240 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image) 241 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 242 243 /* Allow drivers to submit batchbuffers directly to hardware, relying 244 * on the security mechanisms provided by hardware. 245 */ 246 typedef struct drm_i915_batchbuffer { 247 int start; /* agp offset */ 248 int used; /* nr bytes in use */ 249 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 250 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 251 int num_cliprects; /* mulitpass with multiple cliprects? */ 252 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 253 } drm_i915_batchbuffer_t; 254 255 /* As above, but pass a pointer to userspace buffer which can be 256 * validated by the kernel prior to sending to hardware. 257 */ 258 typedef struct _drm_i915_cmdbuffer { 259 char __user *buf; /* pointer to userspace command buffer */ 260 int sz; /* nr bytes in buf */ 261 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 262 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 263 int num_cliprects; /* mulitpass with multiple cliprects? */ 264 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 265 } drm_i915_cmdbuffer_t; 266 267 /* Userspace can request & wait on irq's: 268 */ 269 typedef struct drm_i915_irq_emit { 270 int __user *irq_seq; 271 } drm_i915_irq_emit_t; 272 273 typedef struct drm_i915_irq_wait { 274 int irq_seq; 275 } drm_i915_irq_wait_t; 276 277 /* Ioctl to query kernel params: 278 */ 279 #define I915_PARAM_IRQ_ACTIVE 1 280 #define I915_PARAM_ALLOW_BATCHBUFFER 2 281 #define I915_PARAM_LAST_DISPATCH 3 282 #define I915_PARAM_CHIPSET_ID 4 283 #define I915_PARAM_HAS_GEM 5 284 #define I915_PARAM_NUM_FENCES_AVAIL 6 285 #define I915_PARAM_HAS_OVERLAY 7 286 #define I915_PARAM_HAS_PAGEFLIPPING 8 287 #define I915_PARAM_HAS_EXECBUF2 9 288 #define I915_PARAM_HAS_BSD 10 289 #define I915_PARAM_HAS_BLT 11 290 #define I915_PARAM_HAS_RELAXED_FENCING 12 291 #define I915_PARAM_HAS_COHERENT_RINGS 13 292 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 293 #define I915_PARAM_HAS_RELAXED_DELTA 15 294 295 typedef struct drm_i915_getparam { 296 int param; 297 int __user *value; 298 } drm_i915_getparam_t; 299 300 /* Ioctl to set kernel params: 301 */ 302 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 303 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 304 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 305 #define I915_SETPARAM_NUM_USED_FENCES 4 306 307 typedef struct drm_i915_setparam { 308 int param; 309 int value; 310 } drm_i915_setparam_t; 311 312 /* A memory manager for regions of shared memory: 313 */ 314 #define I915_MEM_REGION_AGP 1 315 316 typedef struct drm_i915_mem_alloc { 317 int region; 318 int alignment; 319 int size; 320 int __user *region_offset; /* offset from start of fb or agp */ 321 } drm_i915_mem_alloc_t; 322 323 typedef struct drm_i915_mem_free { 324 int region; 325 int region_offset; 326 } drm_i915_mem_free_t; 327 328 typedef struct drm_i915_mem_init_heap { 329 int region; 330 int size; 331 int start; 332 } drm_i915_mem_init_heap_t; 333 334 /* Allow memory manager to be torn down and re-initialized (eg on 335 * rotate): 336 */ 337 typedef struct drm_i915_mem_destroy_heap { 338 int region; 339 } drm_i915_mem_destroy_heap_t; 340 341 /* Allow X server to configure which pipes to monitor for vblank signals 342 */ 343 #define DRM_I915_VBLANK_PIPE_A 1 344 #define DRM_I915_VBLANK_PIPE_B 2 345 346 typedef struct drm_i915_vblank_pipe { 347 int pipe; 348 } drm_i915_vblank_pipe_t; 349 350 /* Schedule buffer swap at given vertical blank: 351 */ 352 typedef struct drm_i915_vblank_swap { 353 drm_drawable_t drawable; 354 enum drm_vblank_seq_type seqtype; 355 unsigned int sequence; 356 } drm_i915_vblank_swap_t; 357 358 typedef struct drm_i915_hws_addr { 359 __u64 addr; 360 } drm_i915_hws_addr_t; 361 362 struct drm_i915_gem_init { 363 /** 364 * Beginning offset in the GTT to be managed by the DRM memory 365 * manager. 366 */ 367 __u64 gtt_start; 368 /** 369 * Ending offset in the GTT to be managed by the DRM memory 370 * manager. 371 */ 372 __u64 gtt_end; 373 }; 374 375 struct drm_i915_gem_create { 376 /** 377 * Requested size for the object. 378 * 379 * The (page-aligned) allocated size for the object will be returned. 380 */ 381 __u64 size; 382 /** 383 * Returned handle for the object. 384 * 385 * Object handles are nonzero. 386 */ 387 __u32 handle; 388 __u32 pad; 389 }; 390 391 struct drm_i915_gem_pread { 392 /** Handle for the object being read. */ 393 __u32 handle; 394 __u32 pad; 395 /** Offset into the object to read from */ 396 __u64 offset; 397 /** Length of data to read */ 398 __u64 size; 399 /** 400 * Pointer to write the data into. 401 * 402 * This is a fixed-size type for 32/64 compatibility. 403 */ 404 __u64 data_ptr; 405 }; 406 407 struct drm_i915_gem_pwrite { 408 /** Handle for the object being written to. */ 409 __u32 handle; 410 __u32 pad; 411 /** Offset into the object to write to */ 412 __u64 offset; 413 /** Length of data to write */ 414 __u64 size; 415 /** 416 * Pointer to read the data from. 417 * 418 * This is a fixed-size type for 32/64 compatibility. 419 */ 420 __u64 data_ptr; 421 }; 422 423 struct drm_i915_gem_mmap { 424 /** Handle for the object being mapped. */ 425 __u32 handle; 426 __u32 pad; 427 /** Offset in the object to map. */ 428 __u64 offset; 429 /** 430 * Length of data to map. 431 * 432 * The value will be page-aligned. 433 */ 434 __u64 size; 435 /** 436 * Returned pointer the data was mapped at. 437 * 438 * This is a fixed-size type for 32/64 compatibility. 439 */ 440 __u64 addr_ptr; 441 }; 442 443 struct drm_i915_gem_mmap_gtt { 444 /** Handle for the object being mapped. */ 445 __u32 handle; 446 __u32 pad; 447 /** 448 * Fake offset to use for subsequent mmap call 449 * 450 * This is a fixed-size type for 32/64 compatibility. 451 */ 452 __u64 offset; 453 }; 454 455 struct drm_i915_gem_set_domain { 456 /** Handle for the object */ 457 __u32 handle; 458 459 /** New read domains */ 460 __u32 read_domains; 461 462 /** New write domain */ 463 __u32 write_domain; 464 }; 465 466 struct drm_i915_gem_sw_finish { 467 /** Handle for the object */ 468 __u32 handle; 469 }; 470 471 struct drm_i915_gem_relocation_entry { 472 /** 473 * Handle of the buffer being pointed to by this relocation entry. 474 * 475 * It's appealing to make this be an index into the mm_validate_entry 476 * list to refer to the buffer, but this allows the driver to create 477 * a relocation list for state buffers and not re-write it per 478 * exec using the buffer. 479 */ 480 __u32 target_handle; 481 482 /** 483 * Value to be added to the offset of the target buffer to make up 484 * the relocation entry. 485 */ 486 __u32 delta; 487 488 /** Offset in the buffer the relocation entry will be written into */ 489 __u64 offset; 490 491 /** 492 * Offset value of the target buffer that the relocation entry was last 493 * written as. 494 * 495 * If the buffer has the same offset as last time, we can skip syncing 496 * and writing the relocation. This value is written back out by 497 * the execbuffer ioctl when the relocation is written. 498 */ 499 __u64 presumed_offset; 500 501 /** 502 * Target memory domains read by this operation. 503 */ 504 __u32 read_domains; 505 506 /** 507 * Target memory domains written by this operation. 508 * 509 * Note that only one domain may be written by the whole 510 * execbuffer operation, so that where there are conflicts, 511 * the application will get -EINVAL back. 512 */ 513 __u32 write_domain; 514 }; 515 516 /** @{ 517 * Intel memory domains 518 * 519 * Most of these just align with the various caches in 520 * the system and are used to flush and invalidate as 521 * objects end up cached in different domains. 522 */ 523 /** CPU cache */ 524 #define I915_GEM_DOMAIN_CPU 0x00000001 525 /** Render cache, used by 2D and 3D drawing */ 526 #define I915_GEM_DOMAIN_RENDER 0x00000002 527 /** Sampler cache, used by texture engine */ 528 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 529 /** Command queue, used to load batch buffers */ 530 #define I915_GEM_DOMAIN_COMMAND 0x00000008 531 /** Instruction cache, used by shader programs */ 532 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 533 /** Vertex address cache */ 534 #define I915_GEM_DOMAIN_VERTEX 0x00000020 535 /** GTT domain - aperture and scanout */ 536 #define I915_GEM_DOMAIN_GTT 0x00000040 537 /** @} */ 538 539 struct drm_i915_gem_exec_object { 540 /** 541 * User's handle for a buffer to be bound into the GTT for this 542 * operation. 543 */ 544 __u32 handle; 545 546 /** Number of relocations to be performed on this buffer */ 547 __u32 relocation_count; 548 /** 549 * Pointer to array of struct drm_i915_gem_relocation_entry containing 550 * the relocations to be performed in this buffer. 551 */ 552 __u64 relocs_ptr; 553 554 /** Required alignment in graphics aperture */ 555 __u64 alignment; 556 557 /** 558 * Returned value of the updated offset of the object, for future 559 * presumed_offset writes. 560 */ 561 __u64 offset; 562 }; 563 564 struct drm_i915_gem_execbuffer { 565 /** 566 * List of buffers to be validated with their relocations to be 567 * performend on them. 568 * 569 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 570 * 571 * These buffers must be listed in an order such that all relocations 572 * a buffer is performing refer to buffers that have already appeared 573 * in the validate list. 574 */ 575 __u64 buffers_ptr; 576 __u32 buffer_count; 577 578 /** Offset in the batchbuffer to start execution from. */ 579 __u32 batch_start_offset; 580 /** Bytes used in batchbuffer from batch_start_offset */ 581 __u32 batch_len; 582 __u32 DR1; 583 __u32 DR4; 584 __u32 num_cliprects; 585 /** This is a struct drm_clip_rect *cliprects */ 586 __u64 cliprects_ptr; 587 }; 588 589 struct drm_i915_gem_exec_object2 { 590 /** 591 * User's handle for a buffer to be bound into the GTT for this 592 * operation. 593 */ 594 __u32 handle; 595 596 /** Number of relocations to be performed on this buffer */ 597 __u32 relocation_count; 598 /** 599 * Pointer to array of struct drm_i915_gem_relocation_entry containing 600 * the relocations to be performed in this buffer. 601 */ 602 __u64 relocs_ptr; 603 604 /** Required alignment in graphics aperture */ 605 __u64 alignment; 606 607 /** 608 * Returned value of the updated offset of the object, for future 609 * presumed_offset writes. 610 */ 611 __u64 offset; 612 613 #define EXEC_OBJECT_NEEDS_FENCE (1<<0) 614 __u64 flags; 615 __u64 rsvd1; 616 __u64 rsvd2; 617 }; 618 619 struct drm_i915_gem_execbuffer2 { 620 /** 621 * List of gem_exec_object2 structs 622 */ 623 __u64 buffers_ptr; 624 __u32 buffer_count; 625 626 /** Offset in the batchbuffer to start execution from. */ 627 __u32 batch_start_offset; 628 /** Bytes used in batchbuffer from batch_start_offset */ 629 __u32 batch_len; 630 __u32 DR1; 631 __u32 DR4; 632 __u32 num_cliprects; 633 /** This is a struct drm_clip_rect *cliprects */ 634 __u64 cliprects_ptr; 635 #define I915_EXEC_RING_MASK (7<<0) 636 #define I915_EXEC_DEFAULT (0<<0) 637 #define I915_EXEC_RENDER (1<<0) 638 #define I915_EXEC_BSD (2<<0) 639 #define I915_EXEC_BLT (3<<0) 640 641 /* Used for switching the constants addressing mode on gen4+ RENDER ring. 642 * Gen6+ only supports relative addressing to dynamic state (default) and 643 * absolute addressing. 644 * 645 * These flags are ignored for the BSD and BLT rings. 646 */ 647 #define I915_EXEC_CONSTANTS_MASK (3<<6) 648 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 649 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 650 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 651 __u64 flags; 652 __u64 rsvd1; 653 __u64 rsvd2; 654 }; 655 656 struct drm_i915_gem_pin { 657 /** Handle of the buffer to be pinned. */ 658 __u32 handle; 659 __u32 pad; 660 661 /** alignment required within the aperture */ 662 __u64 alignment; 663 664 /** Returned GTT offset of the buffer. */ 665 __u64 offset; 666 }; 667 668 struct drm_i915_gem_unpin { 669 /** Handle of the buffer to be unpinned. */ 670 __u32 handle; 671 __u32 pad; 672 }; 673 674 struct drm_i915_gem_busy { 675 /** Handle of the buffer to check for busy */ 676 __u32 handle; 677 678 /** Return busy status (1 if busy, 0 if idle) */ 679 __u32 busy; 680 }; 681 682 #define I915_TILING_NONE 0 683 #define I915_TILING_X 1 684 #define I915_TILING_Y 2 685 686 #define I915_BIT_6_SWIZZLE_NONE 0 687 #define I915_BIT_6_SWIZZLE_9 1 688 #define I915_BIT_6_SWIZZLE_9_10 2 689 #define I915_BIT_6_SWIZZLE_9_11 3 690 #define I915_BIT_6_SWIZZLE_9_10_11 4 691 /* Not seen by userland */ 692 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 693 /* Seen by userland. */ 694 #define I915_BIT_6_SWIZZLE_9_17 6 695 #define I915_BIT_6_SWIZZLE_9_10_17 7 696 697 struct drm_i915_gem_set_tiling { 698 /** Handle of the buffer to have its tiling state updated */ 699 __u32 handle; 700 701 /** 702 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 703 * I915_TILING_Y). 704 * 705 * This value is to be set on request, and will be updated by the 706 * kernel on successful return with the actual chosen tiling layout. 707 * 708 * The tiling mode may be demoted to I915_TILING_NONE when the system 709 * has bit 6 swizzling that can't be managed correctly by GEM. 710 * 711 * Buffer contents become undefined when changing tiling_mode. 712 */ 713 __u32 tiling_mode; 714 715 /** 716 * Stride in bytes for the object when in I915_TILING_X or 717 * I915_TILING_Y. 718 */ 719 __u32 stride; 720 721 /** 722 * Returned address bit 6 swizzling required for CPU access through 723 * mmap mapping. 724 */ 725 __u32 swizzle_mode; 726 }; 727 728 struct drm_i915_gem_get_tiling { 729 /** Handle of the buffer to get tiling state for. */ 730 __u32 handle; 731 732 /** 733 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 734 * I915_TILING_Y). 735 */ 736 __u32 tiling_mode; 737 738 /** 739 * Returned address bit 6 swizzling required for CPU access through 740 * mmap mapping. 741 */ 742 __u32 swizzle_mode; 743 }; 744 745 struct drm_i915_gem_get_aperture { 746 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 747 __u64 aper_size; 748 749 /** 750 * Available space in the aperture used by i915_gem_execbuffer, in 751 * bytes 752 */ 753 __u64 aper_available_size; 754 }; 755 756 struct drm_i915_get_pipe_from_crtc_id { 757 /** ID of CRTC being requested **/ 758 __u32 crtc_id; 759 760 /** pipe of requested CRTC **/ 761 __u32 pipe; 762 }; 763 764 #define I915_MADV_WILLNEED 0 765 #define I915_MADV_DONTNEED 1 766 #define __I915_MADV_PURGED 2 /* internal state */ 767 768 struct drm_i915_gem_madvise { 769 /** Handle of the buffer to change the backing store advice */ 770 __u32 handle; 771 772 /* Advice: either the buffer will be needed again in the near future, 773 * or wont be and could be discarded under memory pressure. 774 */ 775 __u32 madv; 776 777 /** Whether the backing store still exists. */ 778 __u32 retained; 779 }; 780 781 /* flags */ 782 #define I915_OVERLAY_TYPE_MASK 0xff 783 #define I915_OVERLAY_YUV_PLANAR 0x01 784 #define I915_OVERLAY_YUV_PACKED 0x02 785 #define I915_OVERLAY_RGB 0x03 786 787 #define I915_OVERLAY_DEPTH_MASK 0xff00 788 #define I915_OVERLAY_RGB24 0x1000 789 #define I915_OVERLAY_RGB16 0x2000 790 #define I915_OVERLAY_RGB15 0x3000 791 #define I915_OVERLAY_YUV422 0x0100 792 #define I915_OVERLAY_YUV411 0x0200 793 #define I915_OVERLAY_YUV420 0x0300 794 #define I915_OVERLAY_YUV410 0x0400 795 796 #define I915_OVERLAY_SWAP_MASK 0xff0000 797 #define I915_OVERLAY_NO_SWAP 0x000000 798 #define I915_OVERLAY_UV_SWAP 0x010000 799 #define I915_OVERLAY_Y_SWAP 0x020000 800 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 801 802 #define I915_OVERLAY_FLAGS_MASK 0xff000000 803 #define I915_OVERLAY_ENABLE 0x01000000 804 805 struct drm_intel_overlay_put_image { 806 /* various flags and src format description */ 807 __u32 flags; 808 /* source picture description */ 809 __u32 bo_handle; 810 /* stride values and offsets are in bytes, buffer relative */ 811 __u16 stride_Y; /* stride for packed formats */ 812 __u16 stride_UV; 813 __u32 offset_Y; /* offset for packet formats */ 814 __u32 offset_U; 815 __u32 offset_V; 816 /* in pixels */ 817 __u16 src_width; 818 __u16 src_height; 819 /* to compensate the scaling factors for partially covered surfaces */ 820 __u16 src_scan_width; 821 __u16 src_scan_height; 822 /* output crtc description */ 823 __u32 crtc_id; 824 __u16 dst_x; 825 __u16 dst_y; 826 __u16 dst_width; 827 __u16 dst_height; 828 }; 829 830 /* flags */ 831 #define I915_OVERLAY_UPDATE_ATTRS (1<<0) 832 #define I915_OVERLAY_UPDATE_GAMMA (1<<1) 833 struct drm_intel_overlay_attrs { 834 __u32 flags; 835 __u32 color_key; 836 __s32 brightness; 837 __u32 contrast; 838 __u32 saturation; 839 __u32 gamma0; 840 __u32 gamma1; 841 __u32 gamma2; 842 __u32 gamma3; 843 __u32 gamma4; 844 __u32 gamma5; 845 }; 846 847 #endif /* _I915_DRM_H_ */ 848