1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
3
4 #ifndef _I40E_H_
5 #define _I40E_H_
6
7 #include <net/tcp.h>
8 #include <net/udp.h>
9 #include <linux/types.h>
10 #include <linux/errno.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/aer.h>
14 #include <linux/netdevice.h>
15 #include <linux/ioport.h>
16 #include <linux/iommu.h>
17 #include <linux/slab.h>
18 #include <linux/list.h>
19 #include <linux/hashtable.h>
20 #include <linux/string.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/sctp.h>
24 #include <linux/pkt_sched.h>
25 #include <linux/ipv6.h>
26 #include <net/checksum.h>
27 #include <net/ip6_checksum.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #include <linux/if_macvlan.h>
31 #include <linux/if_bridge.h>
32 #include <linux/clocksource.h>
33 #include <linux/net_tstamp.h>
34 #include <linux/ptp_clock_kernel.h>
35 #include <net/pkt_cls.h>
36 #include <net/tc_act/tc_gact.h>
37 #include <net/tc_act/tc_mirred.h>
38 #include <net/udp_tunnel.h>
39 #include <net/xdp_sock.h>
40 #include <linux/bitfield.h>
41 #include "i40e_type.h"
42 #include "i40e_prototype.h"
43 #include <linux/net/intel/i40e_client.h>
44 #include <linux/avf/virtchnl.h>
45 #include "i40e_virtchnl_pf.h"
46 #include "i40e_txrx.h"
47 #include "i40e_dcb.h"
48
49 /* Useful i40e defaults */
50 #define I40E_MAX_VEB 16
51
52 #define I40E_MAX_NUM_DESCRIPTORS 4096
53 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
54 #define I40E_DEFAULT_NUM_DESCRIPTORS 512
55 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32
56 #define I40E_MIN_NUM_DESCRIPTORS 64
57 #define I40E_MIN_MSIX 2
58 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
59 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
60 /* max 16 qps */
61 #define i40e_default_queues_per_vmdq(pf) \
62 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
63 #define I40E_DEFAULT_QUEUES_PER_VF 4
64 #define I40E_MAX_VF_QUEUES 16
65 #define i40e_pf_get_max_q_per_tc(pf) \
66 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
67 #define I40E_FDIR_RING_COUNT 32
68 #define I40E_MAX_AQ_BUF_SIZE 4096
69 #define I40E_AQ_LEN 256
70 #define I40E_MIN_ARQ_LEN 1
71 #define I40E_MIN_ASQ_LEN 2
72 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
73 #define I40E_MAX_USER_PRIORITY 8
74 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
75 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10
76 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
77
78 #define I40E_NVM_VERSION_LO_SHIFT 0
79 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
80 #define I40E_NVM_VERSION_HI_SHIFT 12
81 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
82 #define I40E_OEM_VER_BUILD_MASK 0xffff
83 #define I40E_OEM_VER_PATCH_MASK 0xff
84 #define I40E_OEM_VER_BUILD_SHIFT 8
85 #define I40E_OEM_VER_SHIFT 24
86 #define I40E_PHY_DEBUG_ALL \
87 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
88 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
89
90 #define I40E_OEM_EETRACK_ID 0xffffffff
91 #define I40E_OEM_GEN_SHIFT 24
92 #define I40E_OEM_SNAP_MASK 0x00ff0000
93 #define I40E_OEM_SNAP_SHIFT 16
94 #define I40E_OEM_RELEASE_MASK 0x0000ffff
95
96 #define I40E_RX_DESC(R, i) \
97 (&(((union i40e_rx_desc *)((R)->desc))[i]))
98 #define I40E_TX_DESC(R, i) \
99 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
100 #define I40E_TX_CTXTDESC(R, i) \
101 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
102 #define I40E_TX_FDIRDESC(R, i) \
103 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
104
105 /* BW rate limiting */
106 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
107 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
108 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */
109
110 /* driver state flags */
111 enum i40e_state_t {
112 __I40E_TESTING,
113 __I40E_CONFIG_BUSY,
114 __I40E_CONFIG_DONE,
115 __I40E_DOWN,
116 __I40E_SERVICE_SCHED,
117 __I40E_ADMINQ_EVENT_PENDING,
118 __I40E_MDD_EVENT_PENDING,
119 __I40E_VFLR_EVENT_PENDING,
120 __I40E_RESET_RECOVERY_PENDING,
121 __I40E_TIMEOUT_RECOVERY_PENDING,
122 __I40E_MISC_IRQ_REQUESTED,
123 __I40E_RESET_INTR_RECEIVED,
124 __I40E_REINIT_REQUESTED,
125 __I40E_PF_RESET_REQUESTED,
126 __I40E_PF_RESET_AND_REBUILD_REQUESTED,
127 __I40E_CORE_RESET_REQUESTED,
128 __I40E_GLOBAL_RESET_REQUESTED,
129 __I40E_EMP_RESET_INTR_RECEIVED,
130 __I40E_SUSPENDED,
131 __I40E_PTP_TX_IN_PROGRESS,
132 __I40E_BAD_EEPROM,
133 __I40E_DOWN_REQUESTED,
134 __I40E_FD_FLUSH_REQUESTED,
135 __I40E_FD_ATR_AUTO_DISABLED,
136 __I40E_FD_SB_AUTO_DISABLED,
137 __I40E_RESET_FAILED,
138 __I40E_PORT_SUSPENDED,
139 __I40E_VF_DISABLE,
140 __I40E_MACVLAN_SYNC_PENDING,
141 __I40E_TEMP_LINK_POLLING,
142 __I40E_CLIENT_SERVICE_REQUESTED,
143 __I40E_CLIENT_L2_CHANGE,
144 __I40E_CLIENT_RESET,
145 __I40E_VIRTCHNL_OP_PENDING,
146 __I40E_RECOVERY_MODE,
147 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */
148 __I40E_IN_REMOVE,
149 __I40E_VFS_RELEASING,
150 /* This must be last as it determines the size of the BITMAP */
151 __I40E_STATE_SIZE__,
152 };
153
154 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
155 #define I40E_PF_RESET_AND_REBUILD_FLAG \
156 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)
157
158 /* VSI state flags */
159 enum i40e_vsi_state_t {
160 __I40E_VSI_DOWN,
161 __I40E_VSI_NEEDS_RESTART,
162 __I40E_VSI_SYNCING_FILTERS,
163 __I40E_VSI_OVERFLOW_PROMISC,
164 __I40E_VSI_REINIT_REQUESTED,
165 __I40E_VSI_DOWN_REQUESTED,
166 __I40E_VSI_RELEASING,
167 /* This must be last as it determines the size of the BITMAP */
168 __I40E_VSI_STATE_SIZE__,
169 };
170
171 enum i40e_interrupt_policy {
172 I40E_INTERRUPT_BEST_CASE,
173 I40E_INTERRUPT_MEDIUM,
174 I40E_INTERRUPT_LOWEST
175 };
176
177 struct i40e_lump_tracking {
178 u16 num_entries;
179 u16 list[0];
180 #define I40E_PILE_VALID_BIT 0x8000
181 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
182 };
183
184 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20
185 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
186 #define I40E_FDIR_BUFFER_FULL_MARGIN 10
187 #define I40E_FDIR_BUFFER_HEAD_ROOM 32
188 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
189
190 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
191 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
192 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
193
194 enum i40e_fd_stat_idx {
195 I40E_FD_STAT_ATR,
196 I40E_FD_STAT_SB,
197 I40E_FD_STAT_ATR_TUNNEL,
198 I40E_FD_STAT_PF_COUNT
199 };
200 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
201 #define I40E_FD_ATR_STAT_IDX(pf_id) \
202 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
203 #define I40E_FD_SB_STAT_IDX(pf_id) \
204 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
205 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
206 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
207
208 /* The following structure contains the data parsed from the user-defined
209 * field of the ethtool_rx_flow_spec structure.
210 */
211 struct i40e_rx_flow_userdef {
212 bool flex_filter;
213 u16 flex_word;
214 u16 flex_offset;
215 };
216
217 struct i40e_fdir_filter {
218 struct hlist_node fdir_node;
219 /* filter ipnut set */
220 u8 flow_type;
221 u8 ipl4_proto;
222 /* TX packet view of src and dst */
223 __be32 dst_ip;
224 __be32 src_ip;
225 __be32 dst_ip6[4];
226 __be32 src_ip6[4];
227 __be16 src_port;
228 __be16 dst_port;
229 __be32 sctp_v_tag;
230
231 __be16 vlan_etype;
232 __be16 vlan_tag;
233 /* Flexible data to match within the packet payload */
234 __be16 flex_word;
235 u16 flex_offset;
236 bool flex_filter;
237
238 /* filter control */
239 u16 q_index;
240 u8 flex_off;
241 u8 pctype;
242 u16 dest_vsi;
243 u8 dest_ctl;
244 u8 fd_status;
245 u16 cnt_index;
246 u32 fd_id;
247 };
248
249 #define I40E_CLOUD_FIELD_OMAC BIT(0)
250 #define I40E_CLOUD_FIELD_IMAC BIT(1)
251 #define I40E_CLOUD_FIELD_IVLAN BIT(2)
252 #define I40E_CLOUD_FIELD_TEN_ID BIT(3)
253 #define I40E_CLOUD_FIELD_IIP BIT(4)
254
255 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
256 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
257 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
258 I40E_CLOUD_FIELD_IVLAN)
259 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
260 I40E_CLOUD_FIELD_TEN_ID)
261 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
262 I40E_CLOUD_FIELD_IMAC | \
263 I40E_CLOUD_FIELD_TEN_ID)
264 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
265 I40E_CLOUD_FIELD_IVLAN | \
266 I40E_CLOUD_FIELD_TEN_ID)
267 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
268
269 struct i40e_cloud_filter {
270 struct hlist_node cloud_node;
271 unsigned long cookie;
272 /* cloud filter input set follows */
273 u8 dst_mac[ETH_ALEN];
274 u8 src_mac[ETH_ALEN];
275 __be16 vlan_id;
276 u16 seid; /* filter control */
277 __be16 dst_port;
278 __be16 src_port;
279 u32 tenant_id;
280 union {
281 struct {
282 struct in_addr dst_ip;
283 struct in_addr src_ip;
284 } v4;
285 struct {
286 struct in6_addr dst_ip6;
287 struct in6_addr src_ip6;
288 } v6;
289 } ip;
290 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32
291 #define src_ipv6 ip.v6.src_ip6.s6_addr32
292 #define dst_ipv4 ip.v4.dst_ip.s_addr
293 #define src_ipv4 ip.v4.src_ip.s_addr
294 u16 n_proto; /* Ethernet Protocol */
295 u8 ip_proto; /* IPPROTO value */
296 u8 flags;
297 #define I40E_CLOUD_TNL_TYPE_NONE 0xff
298 u8 tunnel_type;
299 };
300
301 #define I40E_DCB_PRIO_TYPE_STRICT 0
302 #define I40E_DCB_PRIO_TYPE_ETS 1
303 #define I40E_DCB_STRICT_PRIO_CREDITS 127
304 /* DCB per TC information data structure */
305 struct i40e_tc_info {
306 u16 qoffset; /* Queue offset from base queue */
307 u16 qcount; /* Total Queues */
308 u8 netdev_tc; /* Netdev TC index if netdev associated */
309 };
310
311 /* TC configuration data structure */
312 struct i40e_tc_configuration {
313 u8 numtc; /* Total number of enabled TCs */
314 u8 enabled_tc; /* TC map */
315 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
316 };
317
318 #define I40E_UDP_PORT_INDEX_UNUSED 255
319 struct i40e_udp_port_config {
320 /* AdminQ command interface expects port number in Host byte order */
321 u16 port;
322 u8 type;
323 u8 filter_index;
324 };
325
326 #define I40_DDP_FLASH_REGION 100
327 #define I40E_PROFILE_INFO_SIZE 48
328 #define I40E_MAX_PROFILE_NUM 16
329 #define I40E_PROFILE_LIST_SIZE \
330 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4)
331 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/"
332 #define I40E_DDP_PROFILE_NAME_MAX 64
333
334 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size,
335 bool is_add);
336 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash);
337
338 struct i40e_ddp_profile_list {
339 u32 p_count;
340 struct i40e_profile_info p_info[];
341 };
342
343 struct i40e_ddp_old_profile_list {
344 struct list_head list;
345 size_t old_ddp_size;
346 u8 old_ddp_buf[];
347 };
348
349 /* macros related to FLX_PIT */
350 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
351 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
352 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
353 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
354 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
355 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
356 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
357 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
358 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
359 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
360 I40E_FLEX_SET_FSIZE(fsize) | \
361 I40E_FLEX_SET_SRC_WORD(src))
362
363
364 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F
365
366 /* macros related to GLQF_ORT */
367 #define I40E_ORT_SET_IDX(idx) (((idx) << \
368 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
369 I40E_GLQF_ORT_PIT_INDX_MASK)
370
371 #define I40E_ORT_SET_COUNT(count) (((count) << \
372 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
373 I40E_GLQF_ORT_FIELD_CNT_MASK)
374
375 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
376 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
377 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
378
379 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
380 I40E_ORT_SET_COUNT(count) | \
381 I40E_ORT_SET_PAYLOAD(payload))
382
383 #define I40E_L3_GLQF_ORT_IDX 34
384 #define I40E_L4_GLQF_ORT_IDX 35
385
386 /* Flex PIT register index */
387 #define I40E_FLEX_PIT_IDX_START_L3 3
388 #define I40E_FLEX_PIT_IDX_START_L4 6
389
390 #define I40E_FLEX_PIT_TABLE_SIZE 3
391
392 #define I40E_FLEX_DEST_UNUSED 63
393
394 #define I40E_FLEX_INDEX_ENTRIES 8
395
396 /* Flex MASK to disable all flexible entries */
397 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
398 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
399 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
400 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
401
402 #define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \
403 (I40E_QINT_TQCTL_CAUSE_ENA_MASK | \
404 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \
405 ((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \
406 ((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \
407 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT))
408
409 #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \
410 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \
411 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
412 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \
413 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \
414 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))
415
416 struct i40e_flex_pit {
417 struct list_head list;
418 u16 src_offset;
419 u8 pit_index;
420 };
421
422 struct i40e_fwd_adapter {
423 struct net_device *netdev;
424 int bit_no;
425 };
426
427 struct i40e_channel {
428 struct list_head list;
429 bool initialized;
430 u8 type;
431 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
432 u16 stat_counter_idx;
433 u16 base_queue;
434 u16 num_queue_pairs; /* Requested by user */
435 u16 seid;
436
437 u8 enabled_tc;
438 struct i40e_aqc_vsi_properties_data info;
439
440 u64 max_tx_rate;
441 struct i40e_fwd_adapter *fwd;
442
443 /* track this channel belongs to which VSI */
444 struct i40e_vsi *parent_vsi;
445 };
446
447 struct i40e_ptp_pins_settings;
448
i40e_is_channel_macvlan(struct i40e_channel * ch)449 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)
450 {
451 return !!ch->fwd;
452 }
453
i40e_channel_mac(struct i40e_channel * ch)454 static inline const u8 *i40e_channel_mac(struct i40e_channel *ch)
455 {
456 if (i40e_is_channel_macvlan(ch))
457 return ch->fwd->netdev->dev_addr;
458 else
459 return NULL;
460 }
461
462 /* struct that defines the Ethernet device */
463 struct i40e_pf {
464 struct pci_dev *pdev;
465 struct i40e_hw hw;
466 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
467 struct msix_entry *msix_entries;
468 bool fc_autoneg_status;
469
470 u16 eeprom_version;
471 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
472 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
473 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
474 u16 num_req_vfs; /* num VFs requested for this PF */
475 u16 num_vf_qps; /* num queue pairs per VF */
476 u16 num_lan_qps; /* num lan queues this PF has set up */
477 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
478 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
479 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
480 int iwarp_base_vector;
481 int queues_left; /* queues left unclaimed */
482 u16 alloc_rss_size; /* allocated RSS queues */
483 u16 rss_size_max; /* HW defined max RSS queues */
484 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
485 u16 num_alloc_vsi; /* num VSIs this driver supports */
486 u8 atr_sample_rate;
487 bool wol_en;
488
489 struct hlist_head fdir_filter_list;
490 u16 fdir_pf_active_filters;
491 unsigned long fd_flush_timestamp;
492 u32 fd_flush_cnt;
493 u32 fd_add_err;
494 u32 fd_atr_cnt;
495
496 /* Book-keeping of side-band filter count per flow-type.
497 * This is used to detect and handle input set changes for
498 * respective flow-type.
499 */
500 u16 fd_tcp4_filter_cnt;
501 u16 fd_udp4_filter_cnt;
502 u16 fd_sctp4_filter_cnt;
503 u16 fd_ip4_filter_cnt;
504
505 u16 fd_tcp6_filter_cnt;
506 u16 fd_udp6_filter_cnt;
507 u16 fd_sctp6_filter_cnt;
508 u16 fd_ip6_filter_cnt;
509
510 /* Flexible filter table values that need to be programmed into
511 * hardware, which expects L3 and L4 to be programmed separately. We
512 * need to ensure that the values are in ascended order and don't have
513 * duplicates, so we track each L3 and L4 values in separate lists.
514 */
515 struct list_head l3_flex_pit_list;
516 struct list_head l4_flex_pit_list;
517
518 struct udp_tunnel_nic_shared udp_tunnel_shared;
519 struct udp_tunnel_nic_info udp_tunnel_nic;
520
521 struct hlist_head cloud_filter_list;
522 u16 num_cloud_filters;
523
524 enum i40e_interrupt_policy int_policy;
525 u16 rx_itr_default;
526 u16 tx_itr_default;
527 u32 msg_enable;
528 char int_name[I40E_INT_NAME_STR_LEN];
529 u16 adminq_work_limit; /* num of admin receive queue desc to process */
530 unsigned long service_timer_period;
531 unsigned long service_timer_previous;
532 struct timer_list service_timer;
533 struct work_struct service_task;
534
535 u32 hw_features;
536 #define I40E_HW_RSS_AQ_CAPABLE BIT(0)
537 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1)
538 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2)
539 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3)
540 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4)
541 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5)
542 #define I40E_HW_100M_SGMII_CAPABLE BIT(6)
543 #define I40E_HW_NO_DCB_SUPPORT BIT(7)
544 #define I40E_HW_USE_SET_LLDP_MIB BIT(8)
545 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9)
546 #define I40E_HW_PTP_L4_CAPABLE BIT(10)
547 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11)
548 #define I40E_HW_HAVE_CRT_RETIMER BIT(13)
549 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14)
550 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15)
551 #define I40E_HW_STOP_FW_LLDP BIT(16)
552 #define I40E_HW_PORT_ID_VALID BIT(17)
553 #define I40E_HW_RESTART_AUTONEG BIT(18)
554
555 u32 flags;
556 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0)
557 #define I40E_FLAG_MSI_ENABLED BIT(1)
558 #define I40E_FLAG_MSIX_ENABLED BIT(2)
559 #define I40E_FLAG_RSS_ENABLED BIT(3)
560 #define I40E_FLAG_VMDQ_ENABLED BIT(4)
561 #define I40E_FLAG_SRIOV_ENABLED BIT(5)
562 #define I40E_FLAG_DCB_CAPABLE BIT(6)
563 #define I40E_FLAG_DCB_ENABLED BIT(7)
564 #define I40E_FLAG_FD_SB_ENABLED BIT(8)
565 #define I40E_FLAG_FD_ATR_ENABLED BIT(9)
566 #define I40E_FLAG_MFP_ENABLED BIT(10)
567 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11)
568 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12)
569 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13)
570 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14)
571 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15)
572 #define I40E_FLAG_LEGACY_RX BIT(16)
573 #define I40E_FLAG_PTP BIT(17)
574 #define I40E_FLAG_IWARP_ENABLED BIT(18)
575 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19)
576 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20)
577 #define I40E_FLAG_TC_MQPRIO BIT(21)
578 #define I40E_FLAG_FD_SB_INACTIVE BIT(22)
579 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23)
580 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24)
581 #define I40E_FLAG_RS_FEC BIT(25)
582 #define I40E_FLAG_BASE_R_FEC BIT(26)
583 #define I40E_FLAG_VF_VLAN_PRUNING BIT(27)
584 /* TOTAL_PORT_SHUTDOWN
585 * Allows to physically disable the link on the NIC's port.
586 * If enabled, (after link down request from the OS)
587 * no link, traffic or led activity is possible on that port.
588 *
589 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the
590 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true
591 * and cannot be disabled by system admin at that time.
592 * The functionalities are exclusive in terms of configuration, but they also
593 * have similar behavior (allowing to disable physical link of the port),
594 * with following differences:
595 * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is
596 * supported by whole family of 7xx Intel Ethernet Controllers
597 * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS)
598 * only if motherboard's BIOS and NIC's FW has support of it
599 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down
600 * by sending phy_type=0 to NIC's FW
601 * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead
602 * the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK)
603 * in abilities field of i40e_aq_set_phy_config structure
604 */
605 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED BIT(27)
606
607 struct i40e_client_instance *cinst;
608 bool stat_offsets_loaded;
609 struct i40e_hw_port_stats stats;
610 struct i40e_hw_port_stats stats_offsets;
611 u32 tx_timeout_count;
612 u32 tx_timeout_recovery_level;
613 unsigned long tx_timeout_last_recovery;
614 u32 tx_sluggish_count;
615 u32 hw_csum_rx_error;
616 u32 led_status;
617 u16 corer_count; /* Core reset count */
618 u16 globr_count; /* Global reset count */
619 u16 empr_count; /* EMP reset count */
620 u16 pfr_count; /* PF reset count */
621 u16 sw_int_count; /* SW interrupt count */
622
623 struct mutex switch_mutex;
624 u16 lan_vsi; /* our default LAN VSI */
625 u16 lan_veb; /* initial relay, if exists */
626 #define I40E_NO_VEB 0xffff
627 #define I40E_NO_VSI 0xffff
628 u16 next_vsi; /* Next unallocated VSI - 0-based! */
629 struct i40e_vsi **vsi;
630 struct i40e_veb *veb[I40E_MAX_VEB];
631
632 struct i40e_lump_tracking *qp_pile;
633 struct i40e_lump_tracking *irq_pile;
634
635 /* switch config info */
636 u16 pf_seid;
637 u16 main_vsi_seid;
638 u16 mac_seid;
639 struct kobject *switch_kobj;
640 #ifdef CONFIG_DEBUG_FS
641 struct dentry *i40e_dbg_pf;
642 #endif /* CONFIG_DEBUG_FS */
643 bool cur_promisc;
644
645 u16 instance; /* A unique number per i40e_pf instance in the system */
646
647 /* sr-iov config info */
648 struct i40e_vf *vf;
649 int num_alloc_vfs; /* actual number of VFs allocated */
650 u32 vf_aq_requests;
651 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
652
653 /* DCBx/DCBNL capability for PF that indicates
654 * whether DCBx is managed by firmware or host
655 * based agent (LLDPAD). Also, indicates what
656 * flavor of DCBx protocol (IEEE/CEE) is supported
657 * by the device. For now we're supporting IEEE
658 * mode only.
659 */
660 u16 dcbx_cap;
661
662 struct i40e_filter_control_settings filter_settings;
663 struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */
664 struct i40e_dcbx_config tmp_cfg;
665
666 /* GPIO defines used by PTP */
667 #define I40E_SDP3_2 18
668 #define I40E_SDP3_3 19
669 #define I40E_GPIO_4 20
670 #define I40E_LED2_0 26
671 #define I40E_LED2_1 27
672 #define I40E_LED3_0 28
673 #define I40E_LED3_1 29
674 #define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \
675 (1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
676 #define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \
677 (1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
678 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \
679 (0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
680 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \
681 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
682 #define I40E_GLGEN_GPIO_CTL_RESERVED BIT(2)
683 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \
684 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
685 #define I40E_GLGEN_GPIO_CTL_DIR_OUT \
686 (1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
687 #define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \
688 (1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
689 #define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \
690 (1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
691 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \
692 (3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
693 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \
694 (4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
695 #define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \
696 (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
697 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \
698 (1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
699 #define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \
700 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
701 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
702 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
703 #define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \
704 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
705 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
706 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
707 #define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \
708 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
709 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
710 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
711 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
712 #define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \
713 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
714 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
715 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
716 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
717 #define I40E_GLGEN_GPIO_CTL_LED_INIT \
718 (I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \
719 I40E_GLGEN_GPIO_CTL_DIR_OUT | \
720 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \
721 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
722 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \
723 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN)
724 #define I40E_PRTTSYN_AUX_1_INSTNT \
725 (1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
726 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE \
727 (1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
728 #define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD (3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
729 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \
730 (I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD)
731 #define I40E_PTP_HALF_SECOND 500000000LL /* nano seconds */
732 #define I40E_PTP_2_SEC_DELAY 2
733
734 struct ptp_clock *ptp_clock;
735 struct ptp_clock_info ptp_caps;
736 struct sk_buff *ptp_tx_skb;
737 unsigned long ptp_tx_start;
738 struct hwtstamp_config tstamp_config;
739 struct timespec64 ptp_prev_hw_time;
740 struct work_struct ptp_pps_work;
741 struct work_struct ptp_extts0_work;
742 struct work_struct ptp_extts1_work;
743 ktime_t ptp_reset_start;
744 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
745 u32 ptp_adj_mult;
746 u32 tx_hwtstamp_timeouts;
747 u32 tx_hwtstamp_skipped;
748 u32 rx_hwtstamp_cleared;
749 u32 latch_event_flags;
750 u64 ptp_pps_start;
751 u32 pps_delay;
752 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
753 struct ptp_pin_desc ptp_pin[3];
754 unsigned long latch_events[4];
755 bool ptp_tx;
756 bool ptp_rx;
757 struct i40e_ptp_pins_settings *ptp_pins;
758 u16 rss_table_size; /* HW RSS table size */
759 u32 max_bw;
760 u32 min_bw;
761
762 u32 ioremap_len;
763 u32 fd_inv;
764 u16 phy_led_val;
765
766 u16 override_q_count;
767 u16 last_sw_conf_flags;
768 u16 last_sw_conf_valid_flags;
769 /* List to keep previous DDP profiles to be rolled back in the future */
770 struct list_head ddp_old_prof;
771 };
772
773 /**
774 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
775 * @macaddr: the MAC Address as the base key
776 *
777 * Simply copies the address and returns it as a u64 for hashing
778 **/
i40e_addr_to_hkey(const u8 * macaddr)779 static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
780 {
781 u64 key = 0;
782
783 ether_addr_copy((u8 *)&key, macaddr);
784 return key;
785 }
786
787 enum i40e_filter_state {
788 I40E_FILTER_INVALID = 0, /* Invalid state */
789 I40E_FILTER_NEW, /* New, not sent to FW yet */
790 I40E_FILTER_ACTIVE, /* Added to switch by FW */
791 I40E_FILTER_FAILED, /* Rejected by FW */
792 I40E_FILTER_REMOVE, /* To be removed */
793 /* There is no 'removed' state; the filter struct is freed */
794 };
795 struct i40e_mac_filter {
796 struct hlist_node hlist;
797 u8 macaddr[ETH_ALEN];
798 #define I40E_VLAN_ANY -1
799 s16 vlan;
800 enum i40e_filter_state state;
801 };
802
803 /* Wrapper structure to keep track of filters while we are preparing to send
804 * firmware commands. We cannot send firmware commands while holding a
805 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
806 * a separate structure, which will track the state change and update the real
807 * filter while under lock. We can't simply hold the filters in a separate
808 * list, as this opens a window for a race condition when adding new MAC
809 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
810 */
811 struct i40e_new_mac_filter {
812 struct hlist_node hlist;
813 struct i40e_mac_filter *f;
814
815 /* Track future changes to state separately */
816 enum i40e_filter_state state;
817 };
818
819 struct i40e_veb {
820 struct i40e_pf *pf;
821 u16 idx;
822 u16 veb_idx; /* index of VEB parent */
823 u16 seid;
824 u16 uplink_seid;
825 u16 stats_idx; /* index of VEB parent */
826 u8 enabled_tc;
827 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
828 u16 flags;
829 u16 bw_limit;
830 u8 bw_max_quanta;
831 bool is_abs_credits;
832 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
833 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
834 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
835 struct kobject *kobj;
836 bool stat_offsets_loaded;
837 struct i40e_eth_stats stats;
838 struct i40e_eth_stats stats_offsets;
839 struct i40e_veb_tc_stats tc_stats;
840 struct i40e_veb_tc_stats tc_stats_offsets;
841 };
842
843 /* struct that defines a VSI, associated with a dev */
844 struct i40e_vsi {
845 struct net_device *netdev;
846 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
847 bool netdev_registered;
848 bool stat_offsets_loaded;
849
850 u32 current_netdev_flags;
851 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
852 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
853 #define I40E_VSI_FLAG_VEB_OWNER BIT(1)
854 unsigned long flags;
855
856 /* Per VSI lock to protect elements/hash (MAC filter) */
857 spinlock_t mac_filter_hash_lock;
858 /* Fixed size hash table with 2^8 buckets for MAC filters */
859 DECLARE_HASHTABLE(mac_filter_hash, 8);
860 bool has_vlan_filter;
861
862 /* VSI stats */
863 struct rtnl_link_stats64 net_stats;
864 struct rtnl_link_stats64 net_stats_offsets;
865 struct i40e_eth_stats eth_stats;
866 struct i40e_eth_stats eth_stats_offsets;
867 u64 tx_restart;
868 u64 tx_busy;
869 u64 tx_linearize;
870 u64 tx_force_wb;
871 u64 tx_stopped;
872 u64 rx_buf_failed;
873 u64 rx_page_failed;
874 u64 rx_page_reuse;
875 u64 rx_page_alloc;
876 u64 rx_page_waive;
877 u64 rx_page_busy;
878
879 /* These are containers of ring pointers, allocated at run-time */
880 struct i40e_ring **rx_rings;
881 struct i40e_ring **tx_rings;
882 struct i40e_ring **xdp_rings; /* XDP Tx rings */
883
884 u32 active_filters;
885 u32 promisc_threshold;
886
887 u16 work_limit;
888 u16 int_rate_limit; /* value in usecs */
889
890 u16 rss_table_size; /* HW RSS table size */
891 u16 rss_size; /* Allocated RSS queues */
892 u8 *rss_hkey_user; /* User configured hash keys */
893 u8 *rss_lut_user; /* User configured lookup table entries */
894
895
896 u16 max_frame;
897 u16 rx_buf_len;
898
899 struct bpf_prog *xdp_prog;
900
901 /* List of q_vectors allocated to this VSI */
902 struct i40e_q_vector **q_vectors;
903 int num_q_vectors;
904 int base_vector;
905 bool irqs_ready;
906
907 u16 seid; /* HW index of this VSI (absolute index) */
908 u16 id; /* VSI number */
909 u16 uplink_seid;
910
911 u16 base_queue; /* vsi's first queue in hw array */
912 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
913 u16 req_queue_pairs; /* User requested queue pairs */
914 u16 num_queue_pairs; /* Used tx and rx pairs */
915 u16 num_tx_desc;
916 u16 num_rx_desc;
917 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
918 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
919
920 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
921 struct i40e_tc_configuration tc_config;
922 struct i40e_aqc_vsi_properties_data info;
923
924 /* VSI BW limit (absolute across all TCs) */
925 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
926 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
927
928 /* Relative TC credits across VSIs */
929 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
930 /* TC BW limit credits within VSI */
931 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
932 /* TC BW limit max quanta within VSI */
933 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
934
935 struct i40e_pf *back; /* Backreference to associated PF */
936 u16 idx; /* index in pf->vsi[] */
937 u16 veb_idx; /* index of VEB parent */
938 struct kobject *kobj; /* sysfs object */
939 bool current_isup; /* Sync 'link up' logging */
940 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
941
942 /* channel specific fields */
943 u16 cnt_q_avail; /* num of queues available for channel usage */
944 u16 orig_rss_size;
945 u16 current_rss_size;
946 bool reconfig_rss;
947
948 u16 next_base_queue; /* next queue to be used for channel setup */
949
950 struct list_head ch_list;
951 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
952
953 /* macvlan fields */
954 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */
955 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */
956 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS);
957 struct list_head macvlan_list;
958 int macvlan_cnt;
959
960 void *priv; /* client driver data reference. */
961
962 /* VSI specific handlers */
963 irqreturn_t (*irq_handler)(int irq, void *data);
964
965 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */
966 } ____cacheline_internodealigned_in_smp;
967
968 struct i40e_netdev_priv {
969 struct i40e_vsi *vsi;
970 };
971
972 extern struct ida i40e_client_ida;
973
974 /* struct that defines an interrupt vector */
975 struct i40e_q_vector {
976 struct i40e_vsi *vsi;
977
978 u16 v_idx; /* index in the vsi->q_vector array. */
979 u16 reg_idx; /* register index of the interrupt */
980
981 struct napi_struct napi;
982
983 struct i40e_ring_container rx;
984 struct i40e_ring_container tx;
985
986 u8 itr_countdown; /* when 0 should adjust adaptive ITR */
987 u8 num_ringpairs; /* total number of ring pairs in vector */
988
989 cpumask_t affinity_mask;
990 struct irq_affinity_notify affinity_notify;
991
992 struct rcu_head rcu; /* to avoid race with update stats on free */
993 char name[I40E_INT_NAME_STR_LEN];
994 bool arm_wb_state;
995 } ____cacheline_internodealigned_in_smp;
996
997 /* lan device */
998 struct i40e_device {
999 struct list_head list;
1000 struct i40e_pf *pf;
1001 };
1002
1003 /**
1004 * i40e_nvm_version_str - format the NVM version strings
1005 * @hw: ptr to the hardware info
1006 **/
i40e_nvm_version_str(struct i40e_hw * hw)1007 static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
1008 {
1009 static char buf[32];
1010 u32 full_ver;
1011
1012 full_ver = hw->nvm.oem_ver;
1013
1014 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
1015 u8 gen, snap;
1016 u16 release;
1017
1018 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
1019 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
1020 I40E_OEM_SNAP_SHIFT);
1021 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
1022
1023 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
1024 } else {
1025 u8 ver, patch;
1026 u16 build;
1027
1028 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
1029 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
1030 I40E_OEM_VER_BUILD_MASK);
1031 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
1032
1033 snprintf(buf, sizeof(buf),
1034 "%x.%02x 0x%x %d.%d.%d",
1035 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
1036 I40E_NVM_VERSION_HI_SHIFT,
1037 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
1038 I40E_NVM_VERSION_LO_SHIFT,
1039 hw->nvm.eetrack, ver, build, patch);
1040 }
1041
1042 return buf;
1043 }
1044
1045 /**
1046 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
1047 * @netdev: the corresponding netdev
1048 *
1049 * Return the PF struct for the given netdev
1050 **/
i40e_netdev_to_pf(struct net_device * netdev)1051 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
1052 {
1053 struct i40e_netdev_priv *np = netdev_priv(netdev);
1054 struct i40e_vsi *vsi = np->vsi;
1055
1056 return vsi->back;
1057 }
1058
i40e_vsi_setup_irqhandler(struct i40e_vsi * vsi,irqreturn_t (* irq_handler)(int,void *))1059 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
1060 irqreturn_t (*irq_handler)(int, void *))
1061 {
1062 vsi->irq_handler = irq_handler;
1063 }
1064
1065 /**
1066 * i40e_get_fd_cnt_all - get the total FD filter space available
1067 * @pf: pointer to the PF struct
1068 **/
i40e_get_fd_cnt_all(struct i40e_pf * pf)1069 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
1070 {
1071 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
1072 }
1073
1074 /**
1075 * i40e_read_fd_input_set - reads value of flow director input set register
1076 * @pf: pointer to the PF struct
1077 * @addr: register addr
1078 *
1079 * This function reads value of flow director input set register
1080 * specified by 'addr' (which is specific to flow-type)
1081 **/
i40e_read_fd_input_set(struct i40e_pf * pf,u16 addr)1082 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
1083 {
1084 u64 val;
1085
1086 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
1087 val <<= 32;
1088 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
1089
1090 return val;
1091 }
1092
1093 /**
1094 * i40e_write_fd_input_set - writes value into flow director input set register
1095 * @pf: pointer to the PF struct
1096 * @addr: register addr
1097 * @val: value to be written
1098 *
1099 * This function writes specified value to the register specified by 'addr'.
1100 * This register is input set register based on flow-type.
1101 **/
i40e_write_fd_input_set(struct i40e_pf * pf,u16 addr,u64 val)1102 static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
1103 u16 addr, u64 val)
1104 {
1105 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
1106 (u32)(val >> 32));
1107 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
1108 (u32)(val & 0xFFFFFFFFULL));
1109 }
1110
1111 /**
1112 * i40e_get_pf_count - get PCI PF count.
1113 * @hw: pointer to a hw.
1114 *
1115 * Reports the function number of the highest PCI physical
1116 * function plus 1 as it is loaded from the NVM.
1117 *
1118 * Return: PCI PF count.
1119 **/
i40e_get_pf_count(struct i40e_hw * hw)1120 static inline u32 i40e_get_pf_count(struct i40e_hw *hw)
1121 {
1122 return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK,
1123 rd32(hw, I40E_GLGEN_PCIFCNCNT));
1124 }
1125
1126 /* needed by i40e_ethtool.c */
1127 int i40e_up(struct i40e_vsi *vsi);
1128 void i40e_down(struct i40e_vsi *vsi);
1129 extern const char i40e_driver_name[];
1130 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
1131 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
1132 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1133 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1134 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
1135 u16 rss_table_size, u16 rss_size);
1136 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
1137 /**
1138 * i40e_find_vsi_by_type - Find and return Flow Director VSI
1139 * @pf: PF to search for VSI
1140 * @type: Value indicating type of VSI we are looking for
1141 **/
1142 static inline struct i40e_vsi *
i40e_find_vsi_by_type(struct i40e_pf * pf,u16 type)1143 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
1144 {
1145 int i;
1146
1147 for (i = 0; i < pf->num_alloc_vsi; i++) {
1148 struct i40e_vsi *vsi = pf->vsi[i];
1149
1150 if (vsi && vsi->type == type)
1151 return vsi;
1152 }
1153
1154 return NULL;
1155 }
1156 void i40e_update_stats(struct i40e_vsi *vsi);
1157 void i40e_update_veb_stats(struct i40e_veb *veb);
1158 void i40e_update_eth_stats(struct i40e_vsi *vsi);
1159 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
1160 int i40e_fetch_switch_configuration(struct i40e_pf *pf,
1161 bool printconfig);
1162
1163 int i40e_add_del_fdir(struct i40e_vsi *vsi,
1164 struct i40e_fdir_filter *input, bool add);
1165 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
1166 u32 i40e_get_current_fd_count(struct i40e_pf *pf);
1167 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1168 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
1169 u32 i40e_get_global_fd_count(struct i40e_pf *pf);
1170 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
1171 void i40e_set_ethtool_ops(struct net_device *netdev);
1172 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1173 const u8 *macaddr, s16 vlan);
1174 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1175 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1176 int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1177 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1178 u16 uplink, u32 param1);
1179 int i40e_vsi_release(struct i40e_vsi *vsi);
1180 void i40e_service_event_schedule(struct i40e_pf *pf);
1181 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1182 u8 *msg, u16 len);
1183
1184 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
1185 bool enable);
1186 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
1187 int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1188 void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1189 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
1190 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1191 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1192 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1193 u16 downlink_seid, u8 enabled_tc);
1194 void i40e_veb_release(struct i40e_veb *veb);
1195
1196 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1197 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1198 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1199 void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1200 void i40e_pf_reset_stats(struct i40e_pf *pf);
1201 #ifdef CONFIG_DEBUG_FS
1202 void i40e_dbg_pf_init(struct i40e_pf *pf);
1203 void i40e_dbg_pf_exit(struct i40e_pf *pf);
1204 void i40e_dbg_init(void);
1205 void i40e_dbg_exit(void);
1206 #else
i40e_dbg_pf_init(struct i40e_pf * pf)1207 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
i40e_dbg_pf_exit(struct i40e_pf * pf)1208 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
i40e_dbg_init(void)1209 static inline void i40e_dbg_init(void) {}
i40e_dbg_exit(void)1210 static inline void i40e_dbg_exit(void) {}
1211 #endif /* CONFIG_DEBUG_FS*/
1212 /* needed by client drivers */
1213 int i40e_lan_add_device(struct i40e_pf *pf);
1214 int i40e_lan_del_device(struct i40e_pf *pf);
1215 void i40e_client_subtask(struct i40e_pf *pf);
1216 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1217 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1218 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1219 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1220 void i40e_client_update_msix_info(struct i40e_pf *pf);
1221 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1222 /**
1223 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1224 * @vsi: pointer to a vsi
1225 * @vector: enable a particular Hw Interrupt vector, without base_vector
1226 **/
i40e_irq_dynamic_enable(struct i40e_vsi * vsi,int vector)1227 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1228 {
1229 struct i40e_pf *pf = vsi->back;
1230 struct i40e_hw *hw = &pf->hw;
1231 u32 val;
1232
1233 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1234 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1235 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1236 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1237 /* skip the flush */
1238 }
1239
1240 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1241 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1242 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1243 int i40e_open(struct net_device *netdev);
1244 int i40e_close(struct net_device *netdev);
1245 int i40e_vsi_open(struct i40e_vsi *vsi);
1246 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1247 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1248 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1249 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1250 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1251 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1252 const u8 *macaddr);
1253 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1254 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1255 int i40e_count_filters(struct i40e_vsi *vsi);
1256 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1257 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
i40e_is_sw_dcb(struct i40e_pf * pf)1258 static inline bool i40e_is_sw_dcb(struct i40e_pf *pf)
1259 {
1260 return !!(pf->flags & I40E_FLAG_DISABLE_FW_LLDP);
1261 }
1262
1263 #ifdef CONFIG_I40E_DCB
1264 void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1265 struct i40e_dcbx_config *old_cfg,
1266 struct i40e_dcbx_config *new_cfg);
1267 void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1268 void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1269 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1270 struct i40e_dcbx_config *old_cfg,
1271 struct i40e_dcbx_config *new_cfg);
1272 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg);
1273 int i40e_dcb_sw_default_config(struct i40e_pf *pf);
1274 #endif /* CONFIG_I40E_DCB */
1275 void i40e_ptp_rx_hang(struct i40e_pf *pf);
1276 void i40e_ptp_tx_hang(struct i40e_pf *pf);
1277 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1278 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1279 void i40e_ptp_set_increment(struct i40e_pf *pf);
1280 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1281 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1282 void i40e_ptp_save_hw_time(struct i40e_pf *pf);
1283 void i40e_ptp_restore_hw_time(struct i40e_pf *pf);
1284 void i40e_ptp_init(struct i40e_pf *pf);
1285 void i40e_ptp_stop(struct i40e_pf *pf);
1286 int i40e_ptp_alloc_pins(struct i40e_pf *pf);
1287 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset);
1288 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1289 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
1290 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
1291 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1292 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1293
1294 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags);
1295
i40e_enabled_xdp_vsi(struct i40e_vsi * vsi)1296 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1297 {
1298 return !!READ_ONCE(vsi->xdp_prog);
1299 }
1300
1301 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1302 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1303 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1304 struct i40e_cloud_filter *filter,
1305 bool add);
1306 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1307 struct i40e_cloud_filter *filter,
1308 bool add);
1309
1310 /**
1311 * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF
1312 * @pf: pointer to a pf.
1313 *
1314 * Check and return value of flag I40E_FLAG_TC_MQPRIO.
1315 *
1316 * Return: I40E_FLAG_TC_MQPRIO set state.
1317 **/
i40e_is_tc_mqprio_enabled(struct i40e_pf * pf)1318 static inline u32 i40e_is_tc_mqprio_enabled(struct i40e_pf *pf)
1319 {
1320 return pf->flags & I40E_FLAG_TC_MQPRIO;
1321 }
1322
1323 #endif /* _I40E_H_ */
1324