1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * ross.h: Ross module specific definitions and defines.
4  *
5  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6  */
7 
8 #ifndef _SPARC_ROSS_H
9 #define _SPARC_ROSS_H
10 
11 #include <asm/asi.h>
12 #include <asm/page.h>
13 
14 /* Ross made Hypersparcs have a %psr 'impl' field of '0001'.  The 'vers'
15  * field has '1111'.
16  */
17 
18 /* The MMU control register fields on the HyperSparc.
19  *
20  * -----------------------------------------------------------------
21  * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
22  * -----------------------------------------------------------------
23  *  31    24 23-22 21  20  19 18-15 14 13 12 11 10  9   8 7-2  1  0
24  *
25  * Phew, lots of fields there ;-)
26  *
27  * CWR: Cache Wrapping Enabled, if one cache wrapping is on.
28  * SE: Snoop Enable, turns on bus snooping for cache activity if one.
29  * WBE: Write Buffer Enable, one turns it on.
30  * MID: The ModuleID of the chip for MBus transactions.
31  * BM: Boot-Mode. One indicates the MMU is in boot mode.
32  * C: Indicates whether accesses are cachable while the MMU is
33  *    disabled.
34  * CS: Cache Size -- 0 = 128k, 1 = 256k
35  * MR: Memory Reflection, one indicates that the memory bus connected
36  *     to the MBus supports memory reflection.
37  * CM: Cache Mode -- 0 = write-through, 1 = copy-back
38  * CE: Cache Enable -- 0 = no caching, 1 = cache is on
39  * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
40  *                 1 = faults from supervisor mode do not generate traps
41  * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
42  */
43 
44 #define HYPERSPARC_CWENABLE   0x00200000
45 #define HYPERSPARC_SBENABLE   0x00100000
46 #define HYPERSPARC_WBENABLE   0x00080000
47 #define HYPERSPARC_MIDMASK    0x00078000
48 #define HYPERSPARC_BMODE      0x00004000
49 #define HYPERSPARC_ACENABLE   0x00002000
50 #define HYPERSPARC_CSIZE      0x00001000
51 #define HYPERSPARC_MRFLCT     0x00000800
52 #define HYPERSPARC_CMODE      0x00000400
53 #define HYPERSPARC_CENABLE    0x00000100
54 #define HYPERSPARC_NFAULT     0x00000002
55 #define HYPERSPARC_MENABLE    0x00000001
56 
57 
58 /* The ICCR instruction cache register on the HyperSparc.
59  *
60  * -----------------------------------------------
61  * |                                 | FTD | ICE |
62  * -----------------------------------------------
63  *  31                                  1     0
64  *
65  * This register is accessed using the V8 'wrasr' and 'rdasr'
66  * opcodes, since not all assemblers understand them and those
67  * that do use different semantics I will just hard code the
68  * instruction with a '.word' statement.
69  *
70  * FTD:  If set to one flush instructions executed during an
71  *       instruction cache hit occurs, the corresponding line
72  *       for said cache-hit is invalidated.  If FTD is zero,
73  *       an unimplemented 'flush' trap will occur when any
74  *       flush is executed by the processor.
75  *
76  * ICE:  If set to one, the instruction cache is enabled.  If
77  *       zero, the cache will not be used for instruction fetches.
78  *
79  * All other bits are read as zeros, and writes to them have no
80  * effect.
81  *
82  * Wheee, not many assemblers understand the %iccr register nor
83  * the generic asr r/w instructions.
84  *
85  *  1000 0011 0100 0111 1100 0000 0000 0000   ! rd %iccr, %g1
86  *
87  * 0x  8    3    4    7    c    0    0    0   ! 0x8347c000
88  *
89  *  1011 1111 1000 0000 0110 0000 0000 0000   ! wr %g1, 0x0, %iccr
90  *
91  * 0x  b    f    8    0    6    0    0    0   ! 0xbf806000
92  *
93  */
94 
95 #define HYPERSPARC_ICCR_FTD     0x00000002
96 #define HYPERSPARC_ICCR_ICE     0x00000001
97 
98 #ifndef __ASSEMBLY__
99 
get_ross_icr(void)100 static inline unsigned int get_ross_icr(void)
101 {
102 	unsigned int icreg;
103 
104 	__asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */
105 			     "mov %%g1, %0\n\t"
106 			     : "=r" (icreg)
107 			     : /* no inputs */
108 			     : "g1", "memory");
109 
110 	return icreg;
111 }
112 
put_ross_icr(unsigned int icreg)113 static inline void put_ross_icr(unsigned int icreg)
114 {
115 	__asm__ __volatile__("or %%g0, %0, %%g1\n\t"
116 			     ".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */
117 			     "nop\n\t"
118 			     "nop\n\t"
119 			     "nop\n\t"
120 			     : /* no outputs */
121 			     : "r" (icreg)
122 			     : "g1", "memory");
123 
124 	return;
125 }
126 
127 /* HyperSparc specific cache flushing. */
128 
129 /* This is for the on-chip instruction cache. */
hyper_flush_whole_icache(void)130 static inline void hyper_flush_whole_icache(void)
131 {
132 	__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
133 			     : /* no outputs */
134 			     : "i" (ASI_M_FLUSH_IWHOLE)
135 			     : "memory");
136 	return;
137 }
138 
139 extern int vac_cache_size;
140 extern int vac_line_size;
141 
hyper_clear_all_tags(void)142 static inline void hyper_clear_all_tags(void)
143 {
144 	unsigned long addr;
145 
146 	for(addr = 0; addr < vac_cache_size; addr += vac_line_size)
147 		__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
148 				     : /* no outputs */
149 				     : "r" (addr), "i" (ASI_M_DATAC_TAG)
150 				     : "memory");
151 }
152 
hyper_flush_unconditional_combined(void)153 static inline void hyper_flush_unconditional_combined(void)
154 {
155 	unsigned long addr;
156 
157 	for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
158 		__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
159 				     : /* no outputs */
160 				     : "r" (addr), "i" (ASI_M_FLUSH_CTX)
161 				     : "memory");
162 }
163 
hyper_flush_cache_user(void)164 static inline void hyper_flush_cache_user(void)
165 {
166 	unsigned long addr;
167 
168 	for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
169 		__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
170 				     : /* no outputs */
171 				     : "r" (addr), "i" (ASI_M_FLUSH_USER)
172 				     : "memory");
173 }
174 
hyper_flush_cache_page(unsigned long page)175 static inline void hyper_flush_cache_page(unsigned long page)
176 {
177 	unsigned long end;
178 
179 	page &= PAGE_MASK;
180 	end = page + PAGE_SIZE;
181 	while (page < end) {
182 		__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
183 				     : /* no outputs */
184 				     : "r" (page), "i" (ASI_M_FLUSH_PAGE)
185 				     : "memory");
186 		page += vac_line_size;
187 	}
188 }
189 
190 #endif /* !(__ASSEMBLY__) */
191 
192 #endif /* !(_SPARC_ROSS_H) */
193