1 /*
2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
3  *
4  *   This program is free software; you can redistribute it and/or
5  *   modify it under the terms of the GNU General Public License
6  *   as published by the Free Software Foundation, version 2.
7  *
8  *   This program is distributed in the hope that it will be useful, but
9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11  *   NON INFRINGEMENT.  See the GNU General Public License for
12  *   more details.
13  */
14 
15 /**
16  * @file hypervisor.h
17  * The hypervisor's public API.
18  */
19 
20 #ifndef _TILE_HV_H
21 #define _TILE_HV_H
22 
23 #include <arch/chip.h>
24 
25 /* Linux builds want unsigned long constants, but assembler wants numbers */
26 #ifdef __ASSEMBLER__
27 /** One, for assembler */
28 #define __HV_SIZE_ONE 1
29 #elif !defined(__tile__) && CHIP_VA_WIDTH() > 32
30 /** One, for 64-bit on host */
31 #define __HV_SIZE_ONE 1ULL
32 #else
33 /** One, for Linux */
34 #define __HV_SIZE_ONE 1UL
35 #endif
36 
37 /** The log2 of the span of a level-1 page table, in bytes.
38  */
39 #define HV_LOG2_L1_SPAN 32
40 
41 /** The span of a level-1 page table, in bytes.
42  */
43 #define HV_L1_SPAN (__HV_SIZE_ONE << HV_LOG2_L1_SPAN)
44 
45 /** The log2 of the size of small pages, in bytes. This value should
46  * be verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
47  */
48 #define HV_LOG2_PAGE_SIZE_SMALL 16
49 
50 /** The size of small pages, in bytes. This value should be verified
51  * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
52  */
53 #define HV_PAGE_SIZE_SMALL (__HV_SIZE_ONE << HV_LOG2_PAGE_SIZE_SMALL)
54 
55 /** The log2 of the size of large pages, in bytes. This value should be
56  * verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
57  */
58 #define HV_LOG2_PAGE_SIZE_LARGE 24
59 
60 /** The size of large pages, in bytes. This value should be verified
61  * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
62  */
63 #define HV_PAGE_SIZE_LARGE (__HV_SIZE_ONE << HV_LOG2_PAGE_SIZE_LARGE)
64 
65 /** The log2 of the granularity at which page tables must be aligned;
66  *  in other words, the CPA for a page table must have this many zero
67  *  bits at the bottom of the address.
68  */
69 #define HV_LOG2_PAGE_TABLE_ALIGN 11
70 
71 /** The granularity at which page tables must be aligned.
72  */
73 #define HV_PAGE_TABLE_ALIGN (__HV_SIZE_ONE << HV_LOG2_PAGE_TABLE_ALIGN)
74 
75 /** Normal start of hypervisor glue in client physical memory. */
76 #define HV_GLUE_START_CPA 0x10000
77 
78 /** This much space is reserved at HV_GLUE_START_CPA
79  * for the hypervisor glue. The client program must start at
80  * some address higher than this, and in particular the address of
81  * its text section should be equal to zero modulo HV_PAGE_SIZE_LARGE
82  * so that relative offsets to the HV glue are correct.
83  */
84 #define HV_GLUE_RESERVED_SIZE 0x10000
85 
86 /** Each entry in the hv dispatch array takes this many bytes. */
87 #define HV_DISPATCH_ENTRY_SIZE 32
88 
89 /** Version of the hypervisor interface defined by this file */
90 #define _HV_VERSION 11
91 
92 /* Index into hypervisor interface dispatch code blocks.
93  *
94  * Hypervisor calls are invoked from user space by calling code
95  * at an address HV_BASE_ADDRESS + (index) * HV_DISPATCH_ENTRY_SIZE,
96  * where index is one of these enum values.
97  *
98  * Normally a supervisor is expected to produce a set of symbols
99  * starting at HV_BASE_ADDRESS that obey this convention, but a user
100  * program could call directly through function pointers if desired.
101  *
102  * These numbers are part of the binary API and will not be changed
103  * without updating HV_VERSION, which should be a rare event.
104  */
105 
106 /** reserved. */
107 #define _HV_DISPATCH_RESERVED                     0
108 
109 /** hv_init  */
110 #define HV_DISPATCH_INIT                          1
111 
112 /** hv_install_context */
113 #define HV_DISPATCH_INSTALL_CONTEXT               2
114 
115 /** hv_sysconf */
116 #define HV_DISPATCH_SYSCONF                       3
117 
118 /** hv_get_rtc */
119 #define HV_DISPATCH_GET_RTC                       4
120 
121 /** hv_set_rtc */
122 #define HV_DISPATCH_SET_RTC                       5
123 
124 /** hv_flush_asid */
125 #define HV_DISPATCH_FLUSH_ASID                    6
126 
127 /** hv_flush_page */
128 #define HV_DISPATCH_FLUSH_PAGE                    7
129 
130 /** hv_flush_pages */
131 #define HV_DISPATCH_FLUSH_PAGES                   8
132 
133 /** hv_restart */
134 #define HV_DISPATCH_RESTART                       9
135 
136 /** hv_halt */
137 #define HV_DISPATCH_HALT                          10
138 
139 /** hv_power_off */
140 #define HV_DISPATCH_POWER_OFF                     11
141 
142 /** hv_inquire_physical */
143 #define HV_DISPATCH_INQUIRE_PHYSICAL              12
144 
145 /** hv_inquire_memory_controller */
146 #define HV_DISPATCH_INQUIRE_MEMORY_CONTROLLER     13
147 
148 /** hv_inquire_virtual */
149 #define HV_DISPATCH_INQUIRE_VIRTUAL               14
150 
151 /** hv_inquire_asid */
152 #define HV_DISPATCH_INQUIRE_ASID                  15
153 
154 /** hv_nanosleep */
155 #define HV_DISPATCH_NANOSLEEP                     16
156 
157 /** hv_console_read_if_ready */
158 #define HV_DISPATCH_CONSOLE_READ_IF_READY         17
159 
160 /** hv_console_write */
161 #define HV_DISPATCH_CONSOLE_WRITE                 18
162 
163 /** hv_downcall_dispatch */
164 #define HV_DISPATCH_DOWNCALL_DISPATCH             19
165 
166 /** hv_inquire_topology */
167 #define HV_DISPATCH_INQUIRE_TOPOLOGY              20
168 
169 /** hv_fs_findfile */
170 #define HV_DISPATCH_FS_FINDFILE                   21
171 
172 /** hv_fs_fstat */
173 #define HV_DISPATCH_FS_FSTAT                      22
174 
175 /** hv_fs_pread */
176 #define HV_DISPATCH_FS_PREAD                      23
177 
178 /** hv_physaddr_read64 */
179 #define HV_DISPATCH_PHYSADDR_READ64               24
180 
181 /** hv_physaddr_write64 */
182 #define HV_DISPATCH_PHYSADDR_WRITE64              25
183 
184 /** hv_get_command_line */
185 #define HV_DISPATCH_GET_COMMAND_LINE              26
186 
187 /** hv_set_caching */
188 #define HV_DISPATCH_SET_CACHING                   27
189 
190 /** hv_bzero_page */
191 #define HV_DISPATCH_BZERO_PAGE                    28
192 
193 /** hv_register_message_state */
194 #define HV_DISPATCH_REGISTER_MESSAGE_STATE        29
195 
196 /** hv_send_message */
197 #define HV_DISPATCH_SEND_MESSAGE                  30
198 
199 /** hv_receive_message */
200 #define HV_DISPATCH_RECEIVE_MESSAGE               31
201 
202 /** hv_inquire_context */
203 #define HV_DISPATCH_INQUIRE_CONTEXT               32
204 
205 /** hv_start_all_tiles */
206 #define HV_DISPATCH_START_ALL_TILES               33
207 
208 /** hv_dev_open */
209 #define HV_DISPATCH_DEV_OPEN                      34
210 
211 /** hv_dev_close */
212 #define HV_DISPATCH_DEV_CLOSE                     35
213 
214 /** hv_dev_pread */
215 #define HV_DISPATCH_DEV_PREAD                     36
216 
217 /** hv_dev_pwrite */
218 #define HV_DISPATCH_DEV_PWRITE                    37
219 
220 /** hv_dev_poll */
221 #define HV_DISPATCH_DEV_POLL                      38
222 
223 /** hv_dev_poll_cancel */
224 #define HV_DISPATCH_DEV_POLL_CANCEL               39
225 
226 /** hv_dev_preada */
227 #define HV_DISPATCH_DEV_PREADA                    40
228 
229 /** hv_dev_pwritea */
230 #define HV_DISPATCH_DEV_PWRITEA                   41
231 
232 /** hv_flush_remote */
233 #define HV_DISPATCH_FLUSH_REMOTE                  42
234 
235 /** hv_console_putc */
236 #define HV_DISPATCH_CONSOLE_PUTC                  43
237 
238 /** hv_inquire_tiles */
239 #define HV_DISPATCH_INQUIRE_TILES                 44
240 
241 /** hv_confstr */
242 #define HV_DISPATCH_CONFSTR                       45
243 
244 /** hv_reexec */
245 #define HV_DISPATCH_REEXEC                        46
246 
247 /** hv_set_command_line */
248 #define HV_DISPATCH_SET_COMMAND_LINE              47
249 
250 #if !CHIP_HAS_IPI()
251 
252 /** hv_clear_intr */
253 #define HV_DISPATCH_CLEAR_INTR                    48
254 
255 /** hv_enable_intr */
256 #define HV_DISPATCH_ENABLE_INTR                   49
257 
258 /** hv_disable_intr */
259 #define HV_DISPATCH_DISABLE_INTR                  50
260 
261 /** hv_raise_intr */
262 #define HV_DISPATCH_RAISE_INTR                    51
263 
264 /** hv_trigger_ipi */
265 #define HV_DISPATCH_TRIGGER_IPI                   52
266 
267 #endif /* !CHIP_HAS_IPI() */
268 
269 /** hv_store_mapping */
270 #define HV_DISPATCH_STORE_MAPPING                 53
271 
272 /** hv_inquire_realpa */
273 #define HV_DISPATCH_INQUIRE_REALPA                54
274 
275 /** hv_flush_all */
276 #define HV_DISPATCH_FLUSH_ALL                     55
277 
278 #if CHIP_HAS_IPI()
279 /** hv_get_ipi_pte */
280 #define HV_DISPATCH_GET_IPI_PTE                   56
281 #endif
282 
283 /** One more than the largest dispatch value */
284 #define _HV_DISPATCH_END                          57
285 
286 
287 #ifndef __ASSEMBLER__
288 
289 #ifdef __KERNEL__
290 #include <asm/types.h>
291 typedef u32 __hv32;        /**< 32-bit value */
292 typedef u64 __hv64;        /**< 64-bit value */
293 #else
294 #include <stdint.h>
295 typedef uint32_t __hv32;   /**< 32-bit value */
296 typedef uint64_t __hv64;   /**< 64-bit value */
297 #endif
298 
299 
300 /** Hypervisor physical address. */
301 typedef __hv64 HV_PhysAddr;
302 
303 #if CHIP_VA_WIDTH() > 32
304 /** Hypervisor virtual address. */
305 typedef __hv64 HV_VirtAddr;
306 #else
307 /** Hypervisor virtual address. */
308 typedef __hv32 HV_VirtAddr;
309 #endif /* CHIP_VA_WIDTH() > 32 */
310 
311 /** Hypervisor ASID. */
312 typedef unsigned int HV_ASID;
313 
314 /** Hypervisor tile location for a memory access
315  * ("location overridden target").
316  */
317 typedef unsigned int HV_LOTAR;
318 
319 /** Hypervisor size of a page. */
320 typedef unsigned long HV_PageSize;
321 
322 /** A page table entry.
323  */
324 typedef struct
325 {
326   __hv64 val;                /**< Value of PTE */
327 } HV_PTE;
328 
329 /** Hypervisor error code. */
330 typedef int HV_Errno;
331 
332 #endif /* !__ASSEMBLER__ */
333 
334 #define HV_OK           0    /**< No error */
335 #define HV_EINVAL      -801  /**< Invalid argument */
336 #define HV_ENODEV      -802  /**< No such device */
337 #define HV_ENOENT      -803  /**< No such file or directory */
338 #define HV_EBADF       -804  /**< Bad file number */
339 #define HV_EFAULT      -805  /**< Bad address */
340 #define HV_ERECIP      -806  /**< Bad recipients */
341 #define HV_E2BIG       -807  /**< Message too big */
342 #define HV_ENOTSUP     -808  /**< Service not supported */
343 #define HV_EBUSY       -809  /**< Device busy */
344 #define HV_ENOSYS      -810  /**< Invalid syscall */
345 #define HV_EPERM       -811  /**< No permission */
346 #define HV_ENOTREADY   -812  /**< Device not ready */
347 #define HV_EIO         -813  /**< I/O error */
348 #define HV_ENOMEM      -814  /**< Out of memory */
349 #define HV_EAGAIN      -815  /**< Try again */
350 
351 #define HV_ERR_MAX     -801  /**< Largest HV error code */
352 #define HV_ERR_MIN     -815  /**< Smallest HV error code */
353 
354 #ifndef __ASSEMBLER__
355 
356 /** Pass HV_VERSION to hv_init to request this version of the interface. */
357 typedef enum { HV_VERSION = _HV_VERSION } HV_VersionNumber;
358 
359 /** Initializes the hypervisor.
360  *
361  * @param interface_version_number The version of the hypervisor interface
362  * that this program expects, typically HV_VERSION.
363  * @param chip_num Architecture number of the chip the client was built for.
364  * @param chip_rev_num Revision number of the chip the client was built for.
365  */
366 void hv_init(HV_VersionNumber interface_version_number,
367              int chip_num, int chip_rev_num);
368 
369 
370 /** Queries we can make for hv_sysconf().
371  *
372  * These numbers are part of the binary API and guaranteed not to change.
373  */
374 typedef enum {
375   /** An invalid value; do not use. */
376   _HV_SYSCONF_RESERVED       = 0,
377 
378   /** The length of the glue section containing the hv_ procs, in bytes. */
379   HV_SYSCONF_GLUE_SIZE       = 1,
380 
381   /** The size of small pages, in bytes. */
382   HV_SYSCONF_PAGE_SIZE_SMALL = 2,
383 
384   /** The size of large pages, in bytes. */
385   HV_SYSCONF_PAGE_SIZE_LARGE = 3,
386 
387   /** Processor clock speed, in hertz. */
388   HV_SYSCONF_CPU_SPEED       = 4,
389 
390   /** Processor temperature, in degrees Kelvin.  The value
391    *  HV_SYSCONF_TEMP_KTOC may be subtracted from this to get degrees
392    *  Celsius.  If that Celsius value is HV_SYSCONF_OVERTEMP, this indicates
393    *  that the temperature has hit an upper limit and is no longer being
394    *  accurately tracked.
395    */
396   HV_SYSCONF_CPU_TEMP        = 5,
397 
398   /** Board temperature, in degrees Kelvin.  The value
399    *  HV_SYSCONF_TEMP_KTOC may be subtracted from this to get degrees
400    *  Celsius.  If that Celsius value is HV_SYSCONF_OVERTEMP, this indicates
401    *  that the temperature has hit an upper limit and is no longer being
402    *  accurately tracked.
403    */
404   HV_SYSCONF_BOARD_TEMP      = 6
405 
406 } HV_SysconfQuery;
407 
408 /** Offset to subtract from returned Kelvin temperature to get degrees
409     Celsius. */
410 #define HV_SYSCONF_TEMP_KTOC 273
411 
412 /** Pseudo-temperature value indicating that the temperature has
413  *  pegged at its upper limit and is no longer accurate; note that this is
414  *  the value after subtracting HV_SYSCONF_TEMP_KTOC. */
415 #define HV_SYSCONF_OVERTEMP 999
416 
417 /** Query a configuration value from the hypervisor.
418  * @param query Which value is requested (HV_SYSCONF_xxx).
419  * @return The requested value, or -1 the requested value is illegal or
420  *         unavailable.
421  */
422 long hv_sysconf(HV_SysconfQuery query);
423 
424 
425 /** Queries we can make for hv_confstr().
426  *
427  * These numbers are part of the binary API and guaranteed not to change.
428  */
429 typedef enum {
430   /** An invalid value; do not use. */
431   _HV_CONFSTR_RESERVED        = 0,
432 
433   /** Board part number. */
434   HV_CONFSTR_BOARD_PART_NUM   = 1,
435 
436   /** Board serial number. */
437   HV_CONFSTR_BOARD_SERIAL_NUM = 2,
438 
439   /** Chip serial number. */
440   HV_CONFSTR_CHIP_SERIAL_NUM  = 3,
441 
442   /** Board revision level. */
443   HV_CONFSTR_BOARD_REV        = 4,
444 
445   /** Hypervisor software version. */
446   HV_CONFSTR_HV_SW_VER        = 5,
447 
448   /** The name for this chip model. */
449   HV_CONFSTR_CHIP_MODEL       = 6,
450 
451   /** Human-readable board description. */
452   HV_CONFSTR_BOARD_DESC       = 7,
453 
454   /** Human-readable description of the hypervisor configuration. */
455   HV_CONFSTR_HV_CONFIG        = 8,
456 
457   /** Human-readable version string for the boot image (for instance,
458    *  who built it and when, what configuration file was used). */
459   HV_CONFSTR_HV_CONFIG_VER    = 9,
460 
461   /** Mezzanine part number. */
462   HV_CONFSTR_MEZZ_PART_NUM   = 10,
463 
464   /** Mezzanine serial number. */
465   HV_CONFSTR_MEZZ_SERIAL_NUM = 11,
466 
467   /** Mezzanine revision level. */
468   HV_CONFSTR_MEZZ_REV        = 12,
469 
470   /** Human-readable mezzanine description. */
471   HV_CONFSTR_MEZZ_DESC       = 13,
472 
473   /** Control path for the onboard network switch. */
474   HV_CONFSTR_SWITCH_CONTROL  = 14,
475 
476   /** Chip revision level. */
477   HV_CONFSTR_CHIP_REV        = 15
478 
479 } HV_ConfstrQuery;
480 
481 /** Query a configuration string from the hypervisor.
482  *
483  * @param query Identifier for the specific string to be retrieved
484  *        (HV_CONFSTR_xxx).
485  * @param buf Buffer in which to place the string.
486  * @param len Length of the buffer.
487  * @return If query is valid, then the length of the corresponding string,
488  *        including the trailing null; if this is greater than len, the string
489  *        was truncated.  If query is invalid, HV_EINVAL.  If the specified
490  *        buffer is not writable by the client, HV_EFAULT.
491  */
492 int hv_confstr(HV_ConfstrQuery query, HV_VirtAddr buf, int len);
493 
494 /** Tile coordinate */
495 typedef struct
496 {
497   /** X coordinate, relative to supervisor's top-left coordinate */
498   int x;
499 
500   /** Y coordinate, relative to supervisor's top-left coordinate */
501   int y;
502 } HV_Coord;
503 
504 
505 #if CHIP_HAS_IPI()
506 
507 /** Get the PTE for sending an IPI to a particular tile.
508  *
509  * @param tile Tile which will receive the IPI.
510  * @param pl Indicates which IPI registers: 0 = IPI_0, 1 = IPI_1.
511  * @param pte Filled with resulting PTE.
512  * @result Zero if no error, non-zero for invalid parameters.
513  */
514 int hv_get_ipi_pte(HV_Coord tile, int pl, HV_PTE* pte);
515 
516 #else /* !CHIP_HAS_IPI() */
517 
518 /** A set of interrupts. */
519 typedef __hv32 HV_IntrMask;
520 
521 /** The low interrupt numbers are reserved for use by the client in
522  *  delivering IPIs.  Any interrupt numbers higher than this value are
523  *  reserved for use by HV device drivers. */
524 #define HV_MAX_IPI_INTERRUPT 7
525 
526 /** Enable a set of device interrupts.
527  *
528  * @param enab_mask Bitmap of interrupts to enable.
529  */
530 void hv_enable_intr(HV_IntrMask enab_mask);
531 
532 /** Disable a set of device interrupts.
533  *
534  * @param disab_mask Bitmap of interrupts to disable.
535  */
536 void hv_disable_intr(HV_IntrMask disab_mask);
537 
538 /** Clear a set of device interrupts.
539  *
540  * @param clear_mask Bitmap of interrupts to clear.
541  */
542 void hv_clear_intr(HV_IntrMask clear_mask);
543 
544 /** Raise a set of device interrupts.
545  *
546  * @param raise_mask Bitmap of interrupts to raise.
547  */
548 void hv_raise_intr(HV_IntrMask raise_mask);
549 
550 /** Trigger a one-shot interrupt on some tile
551  *
552  * @param tile Which tile to interrupt.
553  * @param interrupt Interrupt number to trigger; must be between 0 and
554  *        HV_MAX_IPI_INTERRUPT.
555  * @return HV_OK on success, or a hypervisor error code.
556  */
557 HV_Errno hv_trigger_ipi(HV_Coord tile, int interrupt);
558 
559 #endif /* !CHIP_HAS_IPI() */
560 
561 /** Store memory mapping in debug memory so that external debugger can read it.
562  * A maximum of 16 entries can be stored.
563  *
564  * @param va VA of memory that is mapped.
565  * @param len Length of mapped memory.
566  * @param pa PA of memory that is mapped.
567  * @return 0 on success, -1 if the maximum number of mappings is exceeded.
568  */
569 int hv_store_mapping(HV_VirtAddr va, unsigned int len, HV_PhysAddr pa);
570 
571 /** Given a client PA and a length, return its real (HV) PA.
572  *
573  * @param cpa Client physical address.
574  * @param len Length of mapped memory.
575  * @return physical address, or -1 if cpa or len is not valid.
576  */
577 HV_PhysAddr hv_inquire_realpa(HV_PhysAddr cpa, unsigned int len);
578 
579 /** RTC return flag for no RTC chip present.
580  */
581 #define HV_RTC_NO_CHIP     0x1
582 
583 /** RTC return flag for low-voltage condition, indicating that battery had
584  * died and time read is unreliable.
585  */
586 #define HV_RTC_LOW_VOLTAGE 0x2
587 
588 /** Date/Time of day */
589 typedef struct {
590 #if CHIP_WORD_SIZE() > 32
591   __hv64 tm_sec;   /**< Seconds, 0-59 */
592   __hv64 tm_min;   /**< Minutes, 0-59 */
593   __hv64 tm_hour;  /**< Hours, 0-23 */
594   __hv64 tm_mday;  /**< Day of month, 0-30 */
595   __hv64 tm_mon;   /**< Month, 0-11 */
596   __hv64 tm_year;  /**< Years since 1900, 0-199 */
597   __hv64 flags;    /**< Return flags, 0 if no error */
598 #else
599   __hv32 tm_sec;   /**< Seconds, 0-59 */
600   __hv32 tm_min;   /**< Minutes, 0-59 */
601   __hv32 tm_hour;  /**< Hours, 0-23 */
602   __hv32 tm_mday;  /**< Day of month, 0-30 */
603   __hv32 tm_mon;   /**< Month, 0-11 */
604   __hv32 tm_year;  /**< Years since 1900, 0-199 */
605   __hv32 flags;    /**< Return flags, 0 if no error */
606 #endif
607 } HV_RTCTime;
608 
609 /** Read the current time-of-day clock.
610  * @return HV_RTCTime of current time (GMT).
611  */
612 HV_RTCTime hv_get_rtc(void);
613 
614 
615 /** Set the current time-of-day clock.
616  * @param time time to reset time-of-day to (GMT).
617  */
618 void hv_set_rtc(HV_RTCTime time);
619 
620 /** Installs a context, comprising a page table and other attributes.
621  *
622  *  Once this service completes, page_table will be used to translate
623  *  subsequent virtual address references to physical memory.
624  *
625  *  Installing a context does not cause an implicit TLB flush.  Before
626  *  reusing an ASID value for a different address space, the client is
627  *  expected to flush old references from the TLB with hv_flush_asid().
628  *  (Alternately, hv_flush_all() may be used to flush many ASIDs at once.)
629  *  After invalidating a page table entry, changing its attributes, or
630  *  changing its target CPA, the client is expected to flush old references
631  *  from the TLB with hv_flush_page() or hv_flush_pages(). Making a
632  *  previously invalid page valid does not require a flush.
633  *
634  *  Specifying an invalid ASID, or an invalid CPA (client physical address)
635  *  (either as page_table_pointer, or within the referenced table),
636  *  or another page table data item documented as above as illegal may
637  *  lead to client termination; since the validation of the table is
638  *  done as needed, this may happen before the service returns, or at
639  *  some later time, or never, depending upon the client's pattern of
640  *  memory references.  Page table entries which supply translations for
641  *  invalid virtual addresses may result in client termination, or may
642  *  be silently ignored.  "Invalid" in this context means a value which
643  *  was not provided to the client via the appropriate hv_inquire_* routine.
644  *
645  *  To support changing the instruction VAs at the same time as
646  *  installing the new page table, this call explicitly supports
647  *  setting the "lr" register to a different address and then jumping
648  *  directly to the hv_install_context() routine.  In this case, the
649  *  new page table does not need to contain any mapping for the
650  *  hv_install_context address itself.
651  *
652  * @param page_table Root of the page table.
653  * @param access PTE providing info on how to read the page table.  This
654  *   value must be consistent between multiple tiles sharing a page table,
655  *   and must also be consistent with any virtual mappings the client
656  *   may be using to access the page table.
657  * @param asid HV_ASID the page table is to be used for.
658  * @param flags Context flags, denoting attributes or privileges of the
659  *   current context (HV_CTX_xxx).
660  * @return Zero on success, or a hypervisor error code on failure.
661  */
662 int hv_install_context(HV_PhysAddr page_table, HV_PTE access, HV_ASID asid,
663                        __hv32 flags);
664 
665 #endif /* !__ASSEMBLER__ */
666 
667 #define HV_CTX_DIRECTIO     0x1   /**< Direct I/O requests are accepted from
668                                        PL0. */
669 
670 #ifndef __ASSEMBLER__
671 
672 /** Value returned from hv_inquire_context(). */
673 typedef struct
674 {
675   /** Physical address of page table */
676   HV_PhysAddr page_table;
677 
678   /** PTE which defines access method for top of page table */
679   HV_PTE access;
680 
681   /** ASID associated with this page table */
682   HV_ASID asid;
683 
684   /** Context flags */
685   __hv32 flags;
686 } HV_Context;
687 
688 /** Retrieve information about the currently installed context.
689  * @return The data passed to the last successful hv_install_context call.
690  */
691 HV_Context hv_inquire_context(void);
692 
693 
694 /** Flushes all translations associated with the named address space
695  *  identifier from the TLB and any other hypervisor data structures.
696  *  Translations installed with the "global" bit are not flushed.
697  *
698  *  Specifying an invalid ASID may lead to client termination.  "Invalid"
699  *  in this context means a value which was not provided to the client
700  *  via <tt>hv_inquire_asid()</tt>.
701  *
702  * @param asid HV_ASID whose entries are to be flushed.
703  * @return Zero on success, or a hypervisor error code on failure.
704 */
705 int hv_flush_asid(HV_ASID asid);
706 
707 
708 /** Flushes all translations associated with the named virtual address
709  *  and page size from the TLB and other hypervisor data structures. Only
710  *  pages visible to the current ASID are affected; note that this includes
711  *  global pages in addition to pages specific to the current ASID.
712  *
713  *  The supplied VA need not be aligned; it may be anywhere in the
714  *  subject page.
715  *
716  *  Specifying an invalid virtual address may lead to client termination,
717  *  or may silently succeed.  "Invalid" in this context means a value
718  *  which was not provided to the client via hv_inquire_virtual.
719  *
720  * @param address Address of the page to flush.
721  * @param page_size Size of pages to assume.
722  * @return Zero on success, or a hypervisor error code on failure.
723  */
724 int hv_flush_page(HV_VirtAddr address, HV_PageSize page_size);
725 
726 
727 /** Flushes all translations associated with the named virtual address range
728  *  and page size from the TLB and other hypervisor data structures. Only
729  *  pages visible to the current ASID are affected; note that this includes
730  *  global pages in addition to pages specific to the current ASID.
731  *
732  *  The supplied VA need not be aligned; it may be anywhere in the
733  *  subject page.
734  *
735  *  Specifying an invalid virtual address may lead to client termination,
736  *  or may silently succeed.  "Invalid" in this context means a value
737  *  which was not provided to the client via hv_inquire_virtual.
738  *
739  * @param start Address to flush.
740  * @param page_size Size of pages to assume.
741  * @param size The number of bytes to flush. Any page in the range
742  *        [start, start + size) will be flushed from the TLB.
743  * @return Zero on success, or a hypervisor error code on failure.
744  */
745 int hv_flush_pages(HV_VirtAddr start, HV_PageSize page_size,
746                    unsigned long size);
747 
748 
749 /** Flushes all non-global translations (if preserve_global is true),
750  *  or absolutely all translations (if preserve_global is false).
751  *
752  * @param preserve_global Non-zero if we want to preserve "global" mappings.
753  * @return Zero on success, or a hypervisor error code on failure.
754 */
755 int hv_flush_all(int preserve_global);
756 
757 
758 /** Restart machine with optional restart command and optional args.
759  * @param cmd Const pointer to command to restart with, or NULL
760  * @param args Const pointer to argument string to restart with, or NULL
761  */
762 void hv_restart(HV_VirtAddr cmd, HV_VirtAddr args);
763 
764 
765 /** Halt machine. */
766 void hv_halt(void);
767 
768 
769 /** Power off machine. */
770 void hv_power_off(void);
771 
772 
773 /** Re-enter virtual-is-physical memory translation mode and restart
774  *  execution at a given address.
775  * @param entry Client physical address at which to begin execution.
776  * @return A hypervisor error code on failure; if the operation is
777  *         successful the call does not return.
778  */
779 int hv_reexec(HV_PhysAddr entry);
780 
781 
782 /** Chip topology */
783 typedef struct
784 {
785   /** Relative coordinates of the querying tile */
786   HV_Coord coord;
787 
788   /** Width of the querying supervisor's tile rectangle. */
789   int width;
790 
791   /** Height of the querying supervisor's tile rectangle. */
792   int height;
793 
794 } HV_Topology;
795 
796 /** Returns information about the tile coordinate system.
797  *
798  * Each supervisor is given a rectangle of tiles it potentially controls.
799  * These tiles are labeled using a relative coordinate system with (0,0) as
800  * the upper left tile regardless of their physical location on the chip.
801  *
802  * This call returns both the size of that rectangle and the position
803  * within that rectangle of the querying tile.
804  *
805  * Not all tiles within that rectangle may be available to the supervisor;
806  * to get the precise set of available tiles, you must also call
807  * hv_inquire_tiles(HV_INQ_TILES_AVAIL, ...).
808  **/
809 HV_Topology hv_inquire_topology(void);
810 
811 /** Sets of tiles we can retrieve with hv_inquire_tiles().
812  *
813  * These numbers are part of the binary API and guaranteed not to change.
814  */
815 typedef enum {
816   /** An invalid value; do not use. */
817   _HV_INQ_TILES_RESERVED       = 0,
818 
819   /** All available tiles within the supervisor's tile rectangle. */
820   HV_INQ_TILES_AVAIL           = 1,
821 
822   /** The set of tiles used for hash-for-home caching. */
823   HV_INQ_TILES_HFH_CACHE       = 2,
824 
825   /** The set of tiles that can be legally used as a LOTAR for a PTE. */
826   HV_INQ_TILES_LOTAR           = 3
827 } HV_InqTileSet;
828 
829 /** Returns specific information about various sets of tiles within the
830  *  supervisor's tile rectangle.
831  *
832  * @param set Which set of tiles to retrieve.
833  * @param cpumask Pointer to a returned bitmask (in row-major order,
834  *        supervisor-relative) of tiles.  The low bit of the first word
835  *        corresponds to the tile at the upper left-hand corner of the
836  *        supervisor's rectangle.  In order for the supervisor to know the
837  *        buffer length to supply, it should first call hv_inquire_topology.
838  * @param length Number of bytes available for the returned bitmask.
839  **/
840 HV_Errno hv_inquire_tiles(HV_InqTileSet set, HV_VirtAddr cpumask, int length);
841 
842 
843 /** An identifier for a memory controller. Multiple memory controllers
844  * may be connected to one chip, and this uniquely identifies each one.
845  */
846 typedef int HV_MemoryController;
847 
848 /** A range of physical memory. */
849 typedef struct
850 {
851   HV_PhysAddr start;   /**< Starting address. */
852   __hv64 size;         /**< Size in bytes. */
853   HV_MemoryController controller;  /**< Which memory controller owns this. */
854 } HV_PhysAddrRange;
855 
856 /** Returns information about a range of physical memory.
857  *
858  * hv_inquire_physical() returns one of the ranges of client
859  * physical addresses which are available to this client.
860  *
861  * The first range is retrieved by specifying an idx of 0, and
862  * successive ranges are returned with subsequent idx values.  Ranges
863  * are ordered by increasing start address (i.e., as idx increases,
864  * so does start), do not overlap, and do not touch (i.e., the
865  * available memory is described with the fewest possible ranges).
866  *
867  * If an out-of-range idx value is specified, the returned size will be zero.
868  * A client can count the number of ranges by increasing idx until the
869  * returned size is zero. There will always be at least one valid range.
870  *
871  * Some clients might not be prepared to deal with more than one
872  * physical address range; they still ought to call this routine and
873  * issue a warning message if they're given more than one range, on the
874  * theory that whoever configured the hypervisor to provide that memory
875  * should know that it's being wasted.
876  */
877 HV_PhysAddrRange hv_inquire_physical(int idx);
878 
879 /** Possible DIMM types. */
880 typedef enum
881 {
882   NO_DIMM                    = 0,  /**< No DIMM */
883   DDR2                       = 1,  /**< DDR2 */
884   DDR3                       = 2   /**< DDR3 */
885 } HV_DIMM_Type;
886 
887 #ifdef __tilegx__
888 
889 /** Log2 of minimum DIMM bytes supported by the memory controller. */
890 #define HV_MSH_MIN_DIMM_SIZE_SHIFT 29
891 
892 /** Max number of DIMMs contained by one memory controller. */
893 #define HV_MSH_MAX_DIMMS 8
894 
895 #else
896 
897 /** Log2 of minimum DIMM bytes supported by the memory controller. */
898 #define HV_MSH_MIN_DIMM_SIZE_SHIFT 26
899 
900 /** Max number of DIMMs contained by one memory controller. */
901 #define HV_MSH_MAX_DIMMS 2
902 
903 #endif
904 
905 /** Number of bits to right-shift to get the DIMM type. */
906 #define HV_DIMM_TYPE_SHIFT 0
907 
908 /** Bits to mask to get the DIMM type. */
909 #define HV_DIMM_TYPE_MASK 0xf
910 
911 /** Number of bits to right-shift to get the DIMM size. */
912 #define HV_DIMM_SIZE_SHIFT 4
913 
914 /** Bits to mask to get the DIMM size. */
915 #define HV_DIMM_SIZE_MASK 0xf
916 
917 /** Memory controller information. */
918 typedef struct
919 {
920   HV_Coord coord;   /**< Relative tile coordinates of the port used by a
921                          specified tile to communicate with this controller. */
922   __hv64 speed;     /**< Speed of this controller in bytes per second. */
923 } HV_MemoryControllerInfo;
924 
925 /** Returns information about a particular memory controller.
926  *
927  *  hv_inquire_memory_controller(coord,idx) returns information about a
928  *  particular controller.  Two pieces of information are returned:
929  *  - The relative coordinates of the port on the controller that the specified
930  *    tile would use to contact it.  The relative coordinates may lie
931  *    outside the supervisor's rectangle, i.e. the controller may not
932  *    be attached to a node managed by the querying node's supervisor.
933  *    In particular note that x or y may be negative.
934  *  - The speed of the memory controller.  (This is a not-to-exceed value
935  *    based on the raw hardware data rate, and may not be achievable in
936  *    practice; it is provided to give clients information on the relative
937  *    performance of the available controllers.)
938  *
939  *  Clients should avoid calling this interface with invalid values.
940  *  A client who does may be terminated.
941  * @param coord Tile for which to calculate the relative port position.
942  * @param controller Index of the controller; identical to value returned
943  *        from other routines like hv_inquire_physical.
944  * @return Information about the controller.
945  */
946 HV_MemoryControllerInfo hv_inquire_memory_controller(HV_Coord coord,
947                                                      int controller);
948 
949 
950 /** A range of virtual memory. */
951 typedef struct
952 {
953   HV_VirtAddr start;   /**< Starting address. */
954   __hv64 size;         /**< Size in bytes. */
955 } HV_VirtAddrRange;
956 
957 /** Returns information about a range of virtual memory.
958  *
959  * hv_inquire_virtual() returns one of the ranges of client
960  * virtual addresses which are available to this client.
961  *
962  * The first range is retrieved by specifying an idx of 0, and
963  * successive ranges are returned with subsequent idx values.  Ranges
964  * are ordered by increasing start address (i.e., as idx increases,
965  * so does start), do not overlap, and do not touch (i.e., the
966  * available memory is described with the fewest possible ranges).
967  *
968  * If an out-of-range idx value is specified, the returned size will be zero.
969  * A client can count the number of ranges by increasing idx until the
970  * returned size is zero. There will always be at least one valid range.
971  *
972  * Some clients may well have various virtual addresses hardwired
973  * into themselves; for instance, their instruction stream may
974  * have been compiled expecting to live at a particular address.
975  * Such clients should use this interface to verify they've been
976  * given the virtual address space they expect, and issue a (potentially
977  * fatal) warning message otherwise.
978  *
979  * Note that the returned size is a __hv64, not a __hv32, so it is
980  * possible to express a single range spanning the entire 32-bit
981  * address space.
982  */
983 HV_VirtAddrRange hv_inquire_virtual(int idx);
984 
985 
986 /** A range of ASID values. */
987 typedef struct
988 {
989   HV_ASID start;        /**< First ASID in the range. */
990   unsigned int size;    /**< Number of ASIDs. Zero for an invalid range. */
991 } HV_ASIDRange;
992 
993 /** Returns information about a range of ASIDs.
994  *
995  * hv_inquire_asid() returns one of the ranges of address
996  * space identifiers which are available to this client.
997  *
998  * The first range is retrieved by specifying an idx of 0, and
999  * successive ranges are returned with subsequent idx values.  Ranges
1000  * are ordered by increasing start value (i.e., as idx increases,
1001  * so does start), do not overlap, and do not touch (i.e., the
1002  * available ASIDs are described with the fewest possible ranges).
1003  *
1004  * If an out-of-range idx value is specified, the returned size will be zero.
1005  * A client can count the number of ranges by increasing idx until the
1006  * returned size is zero. There will always be at least one valid range.
1007  */
1008 HV_ASIDRange hv_inquire_asid(int idx);
1009 
1010 
1011 /** Waits for at least the specified number of nanoseconds then returns.
1012  *
1013  * NOTE: this deprecated function currently assumes a 750 MHz clock,
1014  * and is thus not generally suitable for use.  New code should call
1015  * hv_sysconf(HV_SYSCONF_CPU_SPEED), compute a cycle count to wait for,
1016  * and delay by looping while checking the cycle counter SPR.
1017  *
1018  * @param nanosecs The number of nanoseconds to sleep.
1019  */
1020 void hv_nanosleep(int nanosecs);
1021 
1022 
1023 /** Reads a character from the console without blocking.
1024  *
1025  * @return A value from 0-255 indicates the value successfully read.
1026  * A negative value means no value was ready.
1027  */
1028 int hv_console_read_if_ready(void);
1029 
1030 
1031 /** Writes a character to the console, blocking if the console is busy.
1032  *
1033  *  This call cannot fail. If the console is broken for some reason,
1034  *  output will simply vanish.
1035  * @param byte Character to write.
1036  */
1037 void hv_console_putc(int byte);
1038 
1039 
1040 /** Writes a string to the console, blocking if the console is busy.
1041  * @param bytes Pointer to characters to write.
1042  * @param len Number of characters to write.
1043  * @return Number of characters written, or HV_EFAULT if the buffer is invalid.
1044  */
1045 int hv_console_write(HV_VirtAddr bytes, int len);
1046 
1047 
1048 /** Dispatch the next interrupt from the client downcall mechanism.
1049  *
1050  *  The hypervisor uses downcalls to notify the client of asynchronous
1051  *  events.  Some of these events are hypervisor-created (like incoming
1052  *  messages).  Some are regular interrupts which initially occur in
1053  *  the hypervisor, and are normally handled directly by the client;
1054  *  when these occur in a client's interrupt critical section, they must
1055  *  be delivered through the downcall mechanism.
1056  *
1057  *  A downcall is initially delivered to the client as an INTCTRL_CL
1058  *  interrupt, where CL is the client's PL.  Upon entry to the INTCTRL_CL
1059  *  vector, the client must immediately invoke the hv_downcall_dispatch
1060  *  service.  This service will not return; instead it will cause one of
1061  *  the client's actual downcall-handling interrupt vectors to be entered.
1062  *  The EX_CONTEXT registers in the client will be set so that when the
1063  *  client irets, it will return to the code which was interrupted by the
1064  *  INTCTRL_CL interrupt.
1065  *
1066  *  Under some circumstances, the firing of INTCTRL_CL can race with
1067  *  the lowering of a device interrupt.  In such a case, the
1068  *  hv_downcall_dispatch service may issue an iret instruction instead
1069  *  of entering one of the client's actual downcall-handling interrupt
1070  *  vectors.  This will return execution to the location that was
1071  *  interrupted by INTCTRL_CL.
1072  *
1073  *  Any saving of registers should be done by the actual handling
1074  *  vectors; no registers should be changed by the INTCTRL_CL handler.
1075  *  In particular, the client should not use a jal instruction to invoke
1076  *  the hv_downcall_dispatch service, as that would overwrite the client's
1077  *  lr register.  Note that the hv_downcall_dispatch service may overwrite
1078  *  one or more of the client's system save registers.
1079  *
1080  *  The client must not modify the INTCTRL_CL_STATUS SPR.  The hypervisor
1081  *  will set this register to cause a downcall to happen, and will clear
1082  *  it when no further downcalls are pending.
1083  *
1084  *  When a downcall vector is entered, the INTCTRL_CL interrupt will be
1085  *  masked.  When the client is done processing a downcall, and is ready
1086  *  to accept another, it must unmask this interrupt; if more downcalls
1087  *  are pending, this will cause the INTCTRL_CL vector to be reentered.
1088  *  Currently the following interrupt vectors can be entered through a
1089  *  downcall:
1090  *
1091  *  INT_MESSAGE_RCV_DWNCL   (hypervisor message available)
1092  *  INT_DEV_INTR_DWNCL      (device interrupt)
1093  *  INT_DMATLB_MISS_DWNCL   (DMA TLB miss)
1094  *  INT_SNITLB_MISS_DWNCL   (SNI TLB miss)
1095  *  INT_DMATLB_ACCESS_DWNCL (DMA TLB access violation)
1096  */
1097 void hv_downcall_dispatch(void);
1098 
1099 #endif /* !__ASSEMBLER__ */
1100 
1101 /** We use actual interrupt vectors which never occur (they're only there
1102  *  to allow setting MPLs for related SPRs) for our downcall vectors.
1103  */
1104 /** Message receive downcall interrupt vector */
1105 #define INT_MESSAGE_RCV_DWNCL    INT_BOOT_ACCESS
1106 /** DMA TLB miss downcall interrupt vector */
1107 #define INT_DMATLB_MISS_DWNCL    INT_DMA_ASID
1108 /** Static nework processor instruction TLB miss interrupt vector */
1109 #define INT_SNITLB_MISS_DWNCL    INT_SNI_ASID
1110 /** DMA TLB access violation downcall interrupt vector */
1111 #define INT_DMATLB_ACCESS_DWNCL  INT_DMA_CPL
1112 /** Device interrupt downcall interrupt vector */
1113 #define INT_DEV_INTR_DWNCL       INT_WORLD_ACCESS
1114 
1115 #ifndef __ASSEMBLER__
1116 
1117 /** Requests the inode for a specific full pathname.
1118  *
1119  * Performs a lookup in the hypervisor filesystem for a given filename.
1120  * Multiple calls with the same filename will always return the same inode.
1121  * If there is no such filename, HV_ENOENT is returned.
1122  * A bad filename pointer may result in HV_EFAULT instead.
1123  *
1124  * @param filename Constant pointer to name of requested file
1125  * @return Inode of requested file
1126  */
1127 int hv_fs_findfile(HV_VirtAddr filename);
1128 
1129 
1130 /** Data returned from an fstat request.
1131  * Note that this structure should be no more than 40 bytes in size so
1132  * that it can always be returned completely in registers.
1133  */
1134 typedef struct
1135 {
1136   int size;             /**< Size of file (or HV_Errno on error) */
1137   unsigned int flags;   /**< Flags (see HV_FS_FSTAT_FLAGS) */
1138 } HV_FS_StatInfo;
1139 
1140 /** Bitmask flags for fstat request */
1141 typedef enum
1142 {
1143   HV_FS_ISDIR    = 0x0001   /**< Is the entry a directory? */
1144 } HV_FS_FSTAT_FLAGS;
1145 
1146 /** Get stat information on a given file inode.
1147  *
1148  * Return information on the file with the given inode.
1149  *
1150  * IF the HV_FS_ISDIR bit is set, the "file" is a directory.  Reading
1151  * it will return NUL-separated filenames (no directory part) relative
1152  * to the path to the inode of the directory "file".  These can be
1153  * appended to the path to the directory "file" after a forward slash
1154  * to create additional filenames.  Note that it is not required
1155  * that all valid paths be decomposable into valid parent directories;
1156  * a filesystem may validly have just a few files, none of which have
1157  * HV_FS_ISDIR set.  However, if clients may wish to enumerate the
1158  * files in the filesystem, it is recommended to include all the
1159  * appropriate parent directory "files" to give a consistent view.
1160  *
1161  * An invalid file inode will cause an HV_EBADF error to be returned.
1162  *
1163  * @param inode The inode number of the query
1164  * @return An HV_FS_StatInfo structure
1165  */
1166 HV_FS_StatInfo hv_fs_fstat(int inode);
1167 
1168 
1169 /** Read data from a specific hypervisor file.
1170  * On error, may return HV_EBADF for a bad inode or HV_EFAULT for a bad buf.
1171  * Reads near the end of the file will return fewer bytes than requested.
1172  * Reads at or beyond the end of a file will return zero.
1173  *
1174  * @param inode the hypervisor file to read
1175  * @param buf the buffer to read data into
1176  * @param length the number of bytes of data to read
1177  * @param offset the offset into the file to read the data from
1178  * @return number of bytes successfully read, or an HV_Errno code
1179  */
1180 int hv_fs_pread(int inode, HV_VirtAddr buf, int length, int offset);
1181 
1182 
1183 /** Read a 64-bit word from the specified physical address.
1184  * The address must be 8-byte aligned.
1185  * Specifying an invalid physical address will lead to client termination.
1186  * @param addr The physical address to read
1187  * @param access The PTE describing how to read the memory
1188  * @return The 64-bit value read from the given address
1189  */
1190 unsigned long long hv_physaddr_read64(HV_PhysAddr addr, HV_PTE access);
1191 
1192 
1193 /** Write a 64-bit word to the specified physical address.
1194  * The address must be 8-byte aligned.
1195  * Specifying an invalid physical address will lead to client termination.
1196  * @param addr The physical address to write
1197  * @param access The PTE that says how to write the memory
1198  * @param val The 64-bit value to write to the given address
1199  */
1200 void hv_physaddr_write64(HV_PhysAddr addr, HV_PTE access,
1201                          unsigned long long val);
1202 
1203 
1204 /** Get the value of the command-line for the supervisor, if any.
1205  * This will not include the filename of the booted supervisor, but may
1206  * include configured-in boot arguments or the hv_restart() arguments.
1207  * If the buffer is not long enough the hypervisor will NUL the first
1208  * character of the buffer but not write any other data.
1209  * @param buf The virtual address to write the command-line string to.
1210  * @param length The length of buf, in characters.
1211  * @return The actual length of the command line, including the trailing NUL
1212  *         (may be larger than "length").
1213  */
1214 int hv_get_command_line(HV_VirtAddr buf, int length);
1215 
1216 
1217 /** Set a new value for the command-line for the supervisor, which will
1218  *  be returned from subsequent invocations of hv_get_command_line() on
1219  *  this tile.
1220  * @param buf The virtual address to read the command-line string from.
1221  * @param length The length of buf, in characters; must be no more than
1222  *        HV_COMMAND_LINE_LEN.
1223  * @return Zero if successful, or a hypervisor error code.
1224  */
1225 HV_Errno hv_set_command_line(HV_VirtAddr buf, int length);
1226 
1227 /** Maximum size of a command line passed to hv_set_command_line(); note
1228  *  that a line returned from hv_get_command_line() could be larger than
1229  *  this.*/
1230 #define HV_COMMAND_LINE_LEN  256
1231 
1232 /** Tell the hypervisor how to cache non-priority pages
1233  * (its own as well as pages explicitly represented in page tables).
1234  * Normally these will be represented as red/black pages, but
1235  * when the supervisor starts to allocate "priority" pages in the PTE
1236  * the hypervisor will need to start marking those pages as (e.g.) "red"
1237  * and non-priority pages as either "black" (if they cache-alias
1238  * with the existing priority pages) or "red/black" (if they don't).
1239  * The bitmask provides information on which parts of the cache
1240  * have been used for pinned pages so far on this tile; if (1 << N)
1241  * appears in the bitmask, that indicates that a page has been marked
1242  * "priority" whose PFN equals N, mod 8.
1243  * @param bitmask A bitmap of priority page set values
1244  */
1245 void hv_set_caching(unsigned int bitmask);
1246 
1247 
1248 /** Zero out a specified number of pages.
1249  * The va and size must both be multiples of 4096.
1250  * Caches are bypassed and memory is directly set to zero.
1251  * This API is implemented only in the magic hypervisor and is intended
1252  * to provide a performance boost to the minimal supervisor by
1253  * giving it a fast way to zero memory pages when allocating them.
1254  * @param va Virtual address where the page has been mapped
1255  * @param size Number of bytes (must be a page size multiple)
1256  */
1257 void hv_bzero_page(HV_VirtAddr va, unsigned int size);
1258 
1259 
1260 /** State object for the hypervisor messaging subsystem. */
1261 typedef struct
1262 {
1263 #if CHIP_VA_WIDTH() > 32
1264   __hv64 opaque[2]; /**< No user-serviceable parts inside */
1265 #else
1266   __hv32 opaque[2]; /**< No user-serviceable parts inside */
1267 #endif
1268 }
1269 HV_MsgState;
1270 
1271 /** Register to receive incoming messages.
1272  *
1273  *  This routine configures the current tile so that it can receive
1274  *  incoming messages.  It must be called before the client can receive
1275  *  messages with the hv_receive_message routine, and must be called on
1276  *  each tile which will receive messages.
1277  *
1278  *  msgstate is the virtual address of a state object of type HV_MsgState.
1279  *  Once the state is registered, the client must not read or write the
1280  *  state object; doing so will cause undefined results.
1281  *
1282  *  If this routine is called with msgstate set to 0, the client's message
1283  *  state will be freed and it will no longer be able to receive messages.
1284  *  Note that this may cause the loss of any as-yet-undelivered messages
1285  *  for the client.
1286  *
1287  *  If another client attempts to send a message to a client which has
1288  *  not yet called hv_register_message_state, or which has freed its
1289  *  message state, the message will not be delivered, as if the client
1290  *  had insufficient buffering.
1291  *
1292  *  This routine returns HV_OK if the registration was successful, and
1293  *  HV_EINVAL if the supplied state object is unsuitable.  Note that some
1294  *  errors may not be detected during this routine, but might be detected
1295  *  during a subsequent message delivery.
1296  * @param msgstate State object.
1297  **/
1298 HV_Errno hv_register_message_state(HV_MsgState* msgstate);
1299 
1300 /** Possible message recipient states. */
1301 typedef enum
1302 {
1303   HV_TO_BE_SENT,    /**< Not sent (not attempted, or recipient not ready) */
1304   HV_SENT,          /**< Successfully sent */
1305   HV_BAD_RECIP      /**< Bad recipient coordinates (permanent error) */
1306 } HV_Recip_State;
1307 
1308 /** Message recipient. */
1309 typedef struct
1310 {
1311   /** X coordinate, relative to supervisor's top-left coordinate */
1312   unsigned int x:11;
1313 
1314   /** Y coordinate, relative to supervisor's top-left coordinate */
1315   unsigned int y:11;
1316 
1317   /** Status of this recipient */
1318   HV_Recip_State state:10;
1319 } HV_Recipient;
1320 
1321 /** Send a message to a set of recipients.
1322  *
1323  *  This routine sends a message to a set of recipients.
1324  *
1325  *  recips is an array of HV_Recipient structures.  Each specifies a tile,
1326  *  and a message state; initially, it is expected that the state will
1327  *  be set to HV_TO_BE_SENT.  nrecip specifies the number of recipients
1328  *  in the recips array.
1329  *
1330  *  For each recipient whose state is HV_TO_BE_SENT, the hypervisor attempts
1331  *  to send that tile the specified message.  In order to successfully
1332  *  receive the message, the receiver must be a valid tile to which the
1333  *  sender has access, must not be the sending tile itself, and must have
1334  *  sufficient free buffer space.  (The hypervisor guarantees that each
1335  *  tile which has called hv_register_message_state() will be able to
1336  *  buffer one message from every other tile which can legally send to it;
1337  *  more space may be provided but is not guaranteed.)  If an invalid tile
1338  *  is specified, the recipient's state is set to HV_BAD_RECIP; this is a
1339  *  permanent delivery error.  If the message is successfully delivered
1340  *  to the recipient's buffer, the recipient's state is set to HV_SENT.
1341  *  Otherwise, the recipient's state is unchanged.  Message delivery is
1342  *  synchronous; all attempts to send messages are completed before this
1343  *  routine returns.
1344  *
1345  *  If no permanent delivery errors were encountered, the routine returns
1346  *  the number of messages successfully sent: that is, the number of
1347  *  recipients whose states changed from HV_TO_BE_SENT to HV_SENT during
1348  *  this operation.  If any permanent delivery errors were encountered,
1349  *  the routine returns HV_ERECIP.  In the event of permanent delivery
1350  *  errors, it may be the case that delivery was not attempted to all
1351  *  recipients; if any messages were successfully delivered, however,
1352  *  recipients' state values will be updated appropriately.
1353  *
1354  *  It is explicitly legal to specify a recipient structure whose state
1355  *  is not HV_TO_BE_SENT; such a recipient is ignored.  One suggested way
1356  *  of using hv_send_message to send a message to multiple tiles is to set
1357  *  up a list of recipients, and then call the routine repeatedly with the
1358  *  same list, each time accumulating the number of messages successfully
1359  *  sent, until all messages are sent, a permanent error is encountered,
1360  *  or the desired number of attempts have been made.  When used in this
1361  *  way, the routine will deliver each message no more than once to each
1362  *  recipient.
1363  *
1364  *  Note that a message being successfully delivered to the recipient's
1365  *  buffer space does not guarantee that it is received by the recipient,
1366  *  either immediately or at any time in the future; the recipient might
1367  *  never call hv_receive_message, or could register a different state
1368  *  buffer, losing the message.
1369  *
1370  *  Specifying the same recipient more than once in the recipient list
1371  *  is an error, which will not result in an error return but which may
1372  *  or may not result in more than one message being delivered to the
1373  *  recipient tile.
1374  *
1375  *  buf and buflen specify the message to be sent.  buf is a virtual address
1376  *  which must be currently mapped in the client's page table; if not, the
1377  *  routine returns HV_EFAULT.  buflen must be greater than zero and less
1378  *  than or equal to HV_MAX_MESSAGE_SIZE, and nrecip must be less than the
1379  *  number of tiles to which the sender has access; if not, the routine
1380  *  returns HV_EINVAL.
1381  * @param recips List of recipients.
1382  * @param nrecip Number of recipients.
1383  * @param buf Address of message data.
1384  * @param buflen Length of message data.
1385  **/
1386 int hv_send_message(HV_Recipient *recips, int nrecip,
1387                     HV_VirtAddr buf, int buflen);
1388 
1389 /** Maximum hypervisor message size, in bytes */
1390 #define HV_MAX_MESSAGE_SIZE 28
1391 
1392 
1393 /** Return value from hv_receive_message() */
1394 typedef struct
1395 {
1396   int msglen;     /**< Message length in bytes, or an error code */
1397   __hv32 source;  /**< Code identifying message sender (HV_MSG_xxx) */
1398 } HV_RcvMsgInfo;
1399 
1400 #define HV_MSG_TILE 0x0         /**< Message source is another tile */
1401 #define HV_MSG_INTR 0x1         /**< Message source is a driver interrupt */
1402 
1403 /** Receive a message.
1404  *
1405  * This routine retrieves a message from the client's incoming message
1406  * buffer.
1407  *
1408  * Multiple messages sent from a particular sending tile to a particular
1409  * receiving tile are received in the order that they were sent; however,
1410  * no ordering is guaranteed between messages sent by different tiles.
1411  *
1412  * Whenever the a client's message buffer is empty, the first message
1413  * subsequently received will cause the client's MESSAGE_RCV_DWNCL
1414  * interrupt vector to be invoked through the interrupt downcall mechanism
1415  * (see the description of the hv_downcall_dispatch() routine for details
1416  * on downcalls).
1417  *
1418  * Another message-available downcall will not occur until a call to
1419  * this routine is made when the message buffer is empty, and a message
1420  * subsequently arrives.  Note that such a downcall could occur while
1421  * this routine is executing.  If the calling code does not wish this
1422  * to happen, it is recommended that this routine be called with the
1423  * INTCTRL_1 interrupt masked, or inside an interrupt critical section.
1424  *
1425  * msgstate is the value previously passed to hv_register_message_state().
1426  * buf is the virtual address of the buffer into which the message will
1427  * be written; buflen is the length of the buffer.
1428  *
1429  * This routine returns an HV_RcvMsgInfo structure.  The msglen member
1430  * of that structure is the length of the message received, zero if no
1431  * message is available, or HV_E2BIG if the message is too large for the
1432  * specified buffer.  If the message is too large, it is not consumed,
1433  * and may be retrieved by a subsequent call to this routine specifying
1434  * a sufficiently large buffer.  A buffer which is HV_MAX_MESSAGE_SIZE
1435  * bytes long is guaranteed to be able to receive any possible message.
1436  *
1437  * The source member of the HV_RcvMsgInfo structure describes the sender
1438  * of the message.  For messages sent by another client tile via an
1439  * hv_send_message() call, this value is HV_MSG_TILE; for messages sent
1440  * as a result of a device interrupt, this value is HV_MSG_INTR.
1441  */
1442 
1443 HV_RcvMsgInfo hv_receive_message(HV_MsgState msgstate, HV_VirtAddr buf,
1444                                  int buflen);
1445 
1446 
1447 /** Start remaining tiles owned by this supervisor.  Initially, only one tile
1448  *  executes the client program; after it calls this service, the other tiles
1449  *  are started.  This allows the initial tile to do one-time configuration
1450  *  of shared data structures without having to lock them against simultaneous
1451  *  access.
1452  */
1453 void hv_start_all_tiles(void);
1454 
1455 
1456 /** Open a hypervisor device.
1457  *
1458  *  This service initializes an I/O device and its hypervisor driver software,
1459  *  and makes it available for use.  The open operation is per-device per-chip;
1460  *  once it has been performed, the device handle returned may be used in other
1461  *  device services calls made by any tile.
1462  *
1463  * @param name Name of the device.  A base device name is just a text string
1464  *        (say, "pcie").  If there is more than one instance of a device, the
1465  *        base name is followed by a slash and a device number (say, "pcie/0").
1466  *        Some devices may support further structure beneath those components;
1467  *        most notably, devices which require control operations do so by
1468  *        supporting reads and/or writes to a control device whose name
1469  *        includes a trailing "/ctl" (say, "pcie/0/ctl").
1470  * @param flags Flags (HV_DEV_xxx).
1471  * @return A positive integer device handle, or a negative error code.
1472  */
1473 int hv_dev_open(HV_VirtAddr name, __hv32 flags);
1474 
1475 
1476 /** Close a hypervisor device.
1477  *
1478  *  This service uninitializes an I/O device and its hypervisor driver
1479  *  software, and makes it unavailable for use.  The close operation is
1480  *  per-device per-chip; once it has been performed, the device is no longer
1481  *  available.  Normally there is no need to ever call the close service.
1482  *
1483  * @param devhdl Device handle of the device to be closed.
1484  * @return Zero if the close is successful, otherwise, a negative error code.
1485  */
1486 int hv_dev_close(int devhdl);
1487 
1488 
1489 /** Read data from a hypervisor device synchronously.
1490  *
1491  *  This service transfers data from a hypervisor device to a memory buffer.
1492  *  When the service returns, the data has been written from the memory buffer,
1493  *  and the buffer will not be further modified by the driver.
1494  *
1495  *  No ordering is guaranteed between requests issued from different tiles.
1496  *
1497  *  Devices may choose to support both the synchronous and asynchronous read
1498  *  operations, only one of them, or neither of them.
1499  *
1500  * @param devhdl Device handle of the device to be read from.
1501  * @param flags Flags (HV_DEV_xxx).
1502  * @param va Virtual address of the target data buffer.  This buffer must
1503  *        be mapped in the currently installed page table; if not, HV_EFAULT
1504  *        may be returned.
1505  * @param len Number of bytes to be transferred.
1506  * @param offset Driver-dependent offset.  For a random-access device, this is
1507  *        often a byte offset from the beginning of the device; in other cases,
1508  *        like on a control device, it may have a different meaning.
1509  * @return A non-negative value if the read was at least partially successful;
1510  *         otherwise, a negative error code.  The precise interpretation of
1511  *         the return value is driver-dependent, but many drivers will return
1512  *         the number of bytes successfully transferred.
1513  */
1514 int hv_dev_pread(int devhdl, __hv32 flags, HV_VirtAddr va, __hv32 len,
1515                  __hv64 offset);
1516 
1517 #define HV_DEV_NB_EMPTY     0x1   /**< Don't block when no bytes of data can
1518                                        be transferred. */
1519 #define HV_DEV_NB_PARTIAL   0x2   /**< Don't block when some bytes, but not all
1520                                        of the requested bytes, can be
1521                                        transferred. */
1522 #define HV_DEV_NOCACHE      0x4   /**< The caller warrants that none of the
1523                                        cache lines which might contain data
1524                                        from the requested buffer are valid.
1525                                        Useful with asynchronous operations
1526                                        only. */
1527 
1528 #define HV_DEV_ALLFLAGS     (HV_DEV_NB_EMPTY | HV_DEV_NB_PARTIAL | \
1529                              HV_DEV_NOCACHE)   /**< All HV_DEV_xxx flags */
1530 
1531 /** Write data to a hypervisor device synchronously.
1532  *
1533  *  This service transfers data from a memory buffer to a hypervisor device.
1534  *  When the service returns, the data has been read from the memory buffer,
1535  *  and the buffer may be overwritten by the client; the data may not
1536  *  necessarily have been conveyed to the actual hardware I/O interface.
1537  *
1538  *  No ordering is guaranteed between requests issued from different tiles.
1539  *
1540  *  Devices may choose to support both the synchronous and asynchronous write
1541  *  operations, only one of them, or neither of them.
1542  *
1543  * @param devhdl Device handle of the device to be written to.
1544  * @param flags Flags (HV_DEV_xxx).
1545  * @param va Virtual address of the source data buffer.  This buffer must
1546  *        be mapped in the currently installed page table; if not, HV_EFAULT
1547  *        may be returned.
1548  * @param len Number of bytes to be transferred.
1549  * @param offset Driver-dependent offset.  For a random-access device, this is
1550  *        often a byte offset from the beginning of the device; in other cases,
1551  *        like on a control device, it may have a different meaning.
1552  * @return A non-negative value if the write was at least partially successful;
1553  *         otherwise, a negative error code.  The precise interpretation of
1554  *         the return value is driver-dependent, but many drivers will return
1555  *         the number of bytes successfully transferred.
1556  */
1557 int hv_dev_pwrite(int devhdl, __hv32 flags, HV_VirtAddr va, __hv32 len,
1558                   __hv64 offset);
1559 
1560 
1561 /** Interrupt arguments, used in the asynchronous I/O interfaces. */
1562 #if CHIP_VA_WIDTH() > 32
1563 typedef __hv64 HV_IntArg;
1564 #else
1565 typedef __hv32 HV_IntArg;
1566 #endif
1567 
1568 /** Interrupt messages are delivered via the mechanism as normal messages,
1569  *  but have a message source of HV_DEV_INTR.  The message is formatted
1570  *  as an HV_IntrMsg structure.
1571  */
1572 
1573 typedef struct
1574 {
1575   HV_IntArg intarg;  /**< Interrupt argument, passed to the poll/preada/pwritea
1576                           services */
1577   HV_IntArg intdata; /**< Interrupt-specific interrupt data */
1578 } HV_IntrMsg;
1579 
1580 /** Request an interrupt message when a device condition is satisfied.
1581  *
1582  *  This service requests that an interrupt message be delivered to the
1583  *  requesting tile when a device becomes readable or writable, or when any
1584  *  data queued to the device via previous write operations from this tile
1585  *  has been actually sent out on the hardware I/O interface.  Devices may
1586  *  choose to support any, all, or none of the available conditions.
1587  *
1588  *  If multiple conditions are specified, only one message will be
1589  *  delivered.  If the event mask delivered to that interrupt handler
1590  *  indicates that some of the conditions have not yet occurred, the
1591  *  client must issue another poll() call if it wishes to wait for those
1592  *  conditions.
1593  *
1594  *  Only one poll may be outstanding per device handle per tile.  If more than
1595  *  one tile is polling on the same device and condition, they will all be
1596  *  notified when it happens.  Because of this, clients may not assume that
1597  *  the condition signaled is necessarily still true when they request a
1598  *  subsequent service; for instance, the readable data which caused the
1599  *  poll call to interrupt may have been read by another tile in the interim.
1600  *
1601  *  The notification interrupt message could come directly, or via the
1602  *  downcall (intctrl1) method, depending on what the tile is doing
1603  *  when the condition is satisfied.  Note that it is possible for the
1604  *  requested interrupt to be delivered after this service is called but
1605  *  before it returns.
1606  *
1607  * @param devhdl Device handle of the device to be polled.
1608  * @param events Flags denoting the events which will cause the interrupt to
1609  *        be delivered (HV_DEVPOLL_xxx).
1610  * @param intarg Value which will be delivered as the intarg member of the
1611  *        eventual interrupt message; the intdata member will be set to a
1612  *        mask of HV_DEVPOLL_xxx values indicating which conditions have been
1613  *        satisifed.
1614  * @return Zero if the interrupt was successfully scheduled; otherwise, a
1615  *         negative error code.
1616  */
1617 int hv_dev_poll(int devhdl, __hv32 events, HV_IntArg intarg);
1618 
1619 #define HV_DEVPOLL_READ     0x1   /**< Test device for readability */
1620 #define HV_DEVPOLL_WRITE    0x2   /**< Test device for writability */
1621 #define HV_DEVPOLL_FLUSH    0x4   /**< Test device for output drained */
1622 
1623 
1624 /** Cancel a request for an interrupt when a device event occurs.
1625  *
1626  *  This service requests that no interrupt be delivered when the events
1627  *  noted in the last-issued poll() call happen.  Once this service returns,
1628  *  the interrupt has been canceled; however, it is possible for the interrupt
1629  *  to be delivered after this service is called but before it returns.
1630  *
1631  * @param devhdl Device handle of the device on which to cancel polling.
1632  * @return Zero if the poll was successfully canceled; otherwise, a negative
1633  *         error code.
1634  */
1635 int hv_dev_poll_cancel(int devhdl);
1636 
1637 
1638 /** Scatter-gather list for preada/pwritea calls. */
1639 typedef struct
1640 #if CHIP_VA_WIDTH() <= 32
1641 __attribute__ ((packed, aligned(4)))
1642 #endif
1643 {
1644   HV_PhysAddr pa;  /**< Client physical address of the buffer segment. */
1645   HV_PTE pte;      /**< Page table entry describing the caching and location
1646                         override characteristics of the buffer segment.  Some
1647                         drivers ignore this element and will require that
1648                         the NOCACHE flag be set on their requests. */
1649   __hv32 len;      /**< Length of the buffer segment. */
1650 } HV_SGL;
1651 
1652 #define HV_SGL_MAXLEN 16  /**< Maximum number of entries in a scatter-gather
1653                                list */
1654 
1655 /** Read data from a hypervisor device asynchronously.
1656  *
1657  *  This service transfers data from a hypervisor device to a memory buffer.
1658  *  When the service returns, the read has been scheduled.  When the read
1659  *  completes, an interrupt message will be delivered, and the buffer will
1660  *  not be further modified by the driver.
1661  *
1662  *  The number of possible outstanding asynchronous requests is defined by
1663  *  each driver, but it is recommended that it be at least two requests
1664  *  per tile per device.
1665  *
1666  *  No ordering is guaranteed between synchronous and asynchronous requests,
1667  *  even those issued on the same tile.
1668  *
1669  *  The completion interrupt message could come directly, or via the downcall
1670  *  (intctrl1) method, depending on what the tile is doing when the read
1671  *  completes.  Interrupts do not coalesce; one is delivered for each
1672  *  asynchronous I/O request.  Note that it is possible for the requested
1673  *  interrupt to be delivered after this service is called but before it
1674  *  returns.
1675  *
1676  *  Devices may choose to support both the synchronous and asynchronous read
1677  *  operations, only one of them, or neither of them.
1678  *
1679  * @param devhdl Device handle of the device to be read from.
1680  * @param flags Flags (HV_DEV_xxx).
1681  * @param sgl_len Number of elements in the scatter-gather list.
1682  * @param sgl Scatter-gather list describing the memory to which data will be
1683  *        written.
1684  * @param offset Driver-dependent offset.  For a random-access device, this is
1685  *        often a byte offset from the beginning of the device; in other cases,
1686  *        like on a control device, it may have a different meaning.
1687  * @param intarg Value which will be delivered as the intarg member of the
1688  *        eventual interrupt message; the intdata member will be set to the
1689  *        normal return value from the read request.
1690  * @return Zero if the read was successfully scheduled; otherwise, a negative
1691  *         error code.  Note that some drivers may choose to pre-validate
1692  *         their arguments, and may thus detect certain device error
1693  *         conditions at this time rather than when the completion notification
1694  *         occurs, but this is not required.
1695  */
1696 int hv_dev_preada(int devhdl, __hv32 flags, __hv32 sgl_len,
1697                   HV_SGL sgl[/* sgl_len */], __hv64 offset, HV_IntArg intarg);
1698 
1699 
1700 /** Write data to a hypervisor device asynchronously.
1701  *
1702  *  This service transfers data from a memory buffer to a hypervisor
1703  *  device.  When the service returns, the write has been scheduled.
1704  *  When the write completes, an interrupt message will be delivered,
1705  *  and the buffer may be overwritten by the client; the data may not
1706  *  necessarily have been conveyed to the actual hardware I/O interface.
1707  *
1708  *  The number of possible outstanding asynchronous requests is defined by
1709  *  each driver, but it is recommended that it be at least two requests
1710  *  per tile per device.
1711  *
1712  *  No ordering is guaranteed between synchronous and asynchronous requests,
1713  *  even those issued on the same tile.
1714  *
1715  *  The completion interrupt message could come directly, or via the downcall
1716  *  (intctrl1) method, depending on what the tile is doing when the read
1717  *  completes.  Interrupts do not coalesce; one is delivered for each
1718  *  asynchronous I/O request.  Note that it is possible for the requested
1719  *  interrupt to be delivered after this service is called but before it
1720  *  returns.
1721  *
1722  *  Devices may choose to support both the synchronous and asynchronous write
1723  *  operations, only one of them, or neither of them.
1724  *
1725  * @param devhdl Device handle of the device to be read from.
1726  * @param flags Flags (HV_DEV_xxx).
1727  * @param sgl_len Number of elements in the scatter-gather list.
1728  * @param sgl Scatter-gather list describing the memory from which data will be
1729  *        read.
1730  * @param offset Driver-dependent offset.  For a random-access device, this is
1731  *        often a byte offset from the beginning of the device; in other cases,
1732  *        like on a control device, it may have a different meaning.
1733  * @param intarg Value which will be delivered as the intarg member of the
1734  *        eventual interrupt message; the intdata member will be set to the
1735  *        normal return value from the write request.
1736  * @return Zero if the write was successfully scheduled; otherwise, a negative
1737  *         error code.  Note that some drivers may choose to pre-validate
1738  *         their arguments, and may thus detect certain device error
1739  *         conditions at this time rather than when the completion notification
1740  *         occurs, but this is not required.
1741  */
1742 int hv_dev_pwritea(int devhdl, __hv32 flags, __hv32 sgl_len,
1743                    HV_SGL sgl[/* sgl_len */], __hv64 offset, HV_IntArg intarg);
1744 
1745 
1746 /** Define a pair of tile and ASID to identify a user process context. */
1747 typedef struct
1748 {
1749   /** X coordinate, relative to supervisor's top-left coordinate */
1750   unsigned int x:11;
1751 
1752   /** Y coordinate, relative to supervisor's top-left coordinate */
1753   unsigned int y:11;
1754 
1755   /** ASID of the process on this x,y tile */
1756   HV_ASID asid:10;
1757 } HV_Remote_ASID;
1758 
1759 /** Flush cache and/or TLB state on remote tiles.
1760  *
1761  * @param cache_pa Client physical address to flush from cache (ignored if
1762  *        the length encoded in cache_control is zero, or if
1763  *        HV_FLUSH_EVICT_L2 is set, or if cache_cpumask is NULL).
1764  * @param cache_control This argument allows you to specify a length of
1765  *        physical address space to flush (maximum HV_FLUSH_MAX_CACHE_LEN).
1766  *        You can "or" in HV_FLUSH_EVICT_L2 to flush the whole L2 cache.
1767  *        You can "or" in HV_FLUSH_EVICT_L1I to flush the whole L1I cache.
1768  *        HV_FLUSH_ALL flushes all caches.
1769  * @param cache_cpumask Bitmask (in row-major order, supervisor-relative) of
1770  *        tile indices to perform cache flush on.  The low bit of the first
1771  *        word corresponds to the tile at the upper left-hand corner of the
1772  *        supervisor's rectangle.  If passed as a NULL pointer, equivalent
1773  *        to an empty bitmask.  On chips which support hash-for-home caching,
1774  *        if passed as -1, equivalent to a mask containing tiles which could
1775  *        be doing hash-for-home caching.
1776  * @param tlb_va Virtual address to flush from TLB (ignored if
1777  *        tlb_length is zero or tlb_cpumask is NULL).
1778  * @param tlb_length Number of bytes of data to flush from the TLB.
1779  * @param tlb_pgsize Page size to use for TLB flushes.
1780  *        tlb_va and tlb_length need not be aligned to this size.
1781  * @param tlb_cpumask Bitmask for tlb flush, like cache_cpumask.
1782  *        If passed as a NULL pointer, equivalent to an empty bitmask.
1783  * @param asids Pointer to an HV_Remote_ASID array of tile/ASID pairs to flush.
1784  * @param asidcount Number of HV_Remote_ASID entries in asids[].
1785  * @return Zero for success, or else HV_EINVAL or HV_EFAULT for errors that
1786  *        are detected while parsing the arguments.
1787  */
1788 int hv_flush_remote(HV_PhysAddr cache_pa, unsigned long cache_control,
1789                     unsigned long* cache_cpumask,
1790                     HV_VirtAddr tlb_va, unsigned long tlb_length,
1791                     unsigned long tlb_pgsize, unsigned long* tlb_cpumask,
1792                     HV_Remote_ASID* asids, int asidcount);
1793 
1794 /** Include in cache_control to ensure a flush of the entire L2. */
1795 #define HV_FLUSH_EVICT_L2 (1UL << 31)
1796 
1797 /** Include in cache_control to ensure a flush of the entire L1I. */
1798 #define HV_FLUSH_EVICT_L1I (1UL << 30)
1799 
1800 /** Maximum legal size to use for the "length" component of cache_control. */
1801 #define HV_FLUSH_MAX_CACHE_LEN ((1UL << 30) - 1)
1802 
1803 /** Use for cache_control to ensure a flush of all caches. */
1804 #define HV_FLUSH_ALL -1UL
1805 
1806 #else   /* __ASSEMBLER__ */
1807 
1808 /** Include in cache_control to ensure a flush of the entire L2. */
1809 #define HV_FLUSH_EVICT_L2 (1 << 31)
1810 
1811 /** Include in cache_control to ensure a flush of the entire L1I. */
1812 #define HV_FLUSH_EVICT_L1I (1 << 30)
1813 
1814 /** Maximum legal size to use for the "length" component of cache_control. */
1815 #define HV_FLUSH_MAX_CACHE_LEN ((1 << 30) - 1)
1816 
1817 /** Use for cache_control to ensure a flush of all caches. */
1818 #define HV_FLUSH_ALL -1
1819 
1820 #endif  /* __ASSEMBLER__ */
1821 
1822 #ifndef __ASSEMBLER__
1823 
1824 /** Return a 64-bit value corresponding to the PTE if needed */
1825 #define hv_pte_val(pte) ((pte).val)
1826 
1827 /** Cast a 64-bit value to an HV_PTE */
1828 #define hv_pte(val) ((HV_PTE) { val })
1829 
1830 #endif  /* !__ASSEMBLER__ */
1831 
1832 
1833 /** Bits in the size of an HV_PTE */
1834 #define HV_LOG2_PTE_SIZE 3
1835 
1836 /** Size of an HV_PTE */
1837 #define HV_PTE_SIZE (1 << HV_LOG2_PTE_SIZE)
1838 
1839 
1840 /* Bits in HV_PTE's low word. */
1841 #define HV_PTE_INDEX_PRESENT          0  /**< PTE is valid */
1842 #define HV_PTE_INDEX_MIGRATING        1  /**< Page is migrating */
1843 #define HV_PTE_INDEX_CLIENT0          2  /**< Page client state 0 */
1844 #define HV_PTE_INDEX_CLIENT1          3  /**< Page client state 1 */
1845 #define HV_PTE_INDEX_NC               4  /**< L1$/L2$ incoherent with L3$ */
1846 #define HV_PTE_INDEX_NO_ALLOC_L1      5  /**< Page is uncached in local L1$ */
1847 #define HV_PTE_INDEX_NO_ALLOC_L2      6  /**< Page is uncached in local L2$ */
1848 #define HV_PTE_INDEX_CACHED_PRIORITY  7  /**< Page is priority cached */
1849 #define HV_PTE_INDEX_PAGE             8  /**< PTE describes a page */
1850 #define HV_PTE_INDEX_GLOBAL           9  /**< Page is global */
1851 #define HV_PTE_INDEX_USER            10  /**< Page is user-accessible */
1852 #define HV_PTE_INDEX_ACCESSED        11  /**< Page has been accessed */
1853 #define HV_PTE_INDEX_DIRTY           12  /**< Page has been written */
1854                                          /*   Bits 13-15 are reserved for
1855                                               future use. */
1856 #define HV_PTE_INDEX_MODE            16  /**< Page mode; see HV_PTE_MODE_xxx */
1857 #define HV_PTE_MODE_BITS              3  /**< Number of bits in mode */
1858                                          /*   Bit 19 is reserved for
1859                                               future use. */
1860 #define HV_PTE_INDEX_LOTAR           20  /**< Page's LOTAR; must be high bits
1861                                               of word */
1862 #define HV_PTE_LOTAR_BITS            12  /**< Number of bits in a LOTAR */
1863 
1864 /* Bits in HV_PTE's high word. */
1865 #define HV_PTE_INDEX_READABLE        32  /**< Page is readable */
1866 #define HV_PTE_INDEX_WRITABLE        33  /**< Page is writable */
1867 #define HV_PTE_INDEX_EXECUTABLE      34  /**< Page is executable */
1868 #define HV_PTE_INDEX_PTFN            35  /**< Page's PTFN; must be high bits
1869                                               of word */
1870 #define HV_PTE_PTFN_BITS             29  /**< Number of bits in a PTFN */
1871 
1872 /** Position of the PFN field within the PTE (subset of the PTFN). */
1873 #define HV_PTE_INDEX_PFN (HV_PTE_INDEX_PTFN + (HV_LOG2_PAGE_SIZE_SMALL - \
1874                                                HV_LOG2_PAGE_TABLE_ALIGN))
1875 
1876 /** Length of the PFN field within the PTE (subset of the PTFN). */
1877 #define HV_PTE_INDEX_PFN_BITS (HV_PTE_INDEX_PTFN_BITS - \
1878                                (HV_LOG2_PAGE_SIZE_SMALL - \
1879                                 HV_LOG2_PAGE_TABLE_ALIGN))
1880 
1881 /*
1882  * Legal values for the PTE's mode field
1883  */
1884 /** Data is not resident in any caches; loads and stores access memory
1885  *  directly.
1886  */
1887 #define HV_PTE_MODE_UNCACHED          1
1888 
1889 /** Data is resident in the tile's local L1 and/or L2 caches; if a load
1890  *  or store misses there, it goes to memory.
1891  *
1892  *  The copy in the local L1$/L2$ is not invalidated when the copy in
1893  *  memory is changed.
1894  */
1895 #define HV_PTE_MODE_CACHE_NO_L3       2
1896 
1897 /** Data is resident in the tile's local L1 and/or L2 caches.  If a load
1898  *  or store misses there, it goes to an L3 cache in a designated tile;
1899  *  if it misses there, it goes to memory.
1900  *
1901  *  If the NC bit is not set, the copy in the local L1$/L2$ is invalidated
1902  *  when the copy in the remote L3$ is changed.  Otherwise, such
1903  *  invalidation will not occur.
1904  *
1905  *  Chips for which CHIP_HAS_COHERENT_LOCAL_CACHE() is 0 do not support
1906  *  invalidation from an L3$ to another tile's L1$/L2$.  If the NC bit is
1907  *  clear on such a chip, no copy is kept in the local L1$/L2$ in this mode.
1908  */
1909 #define HV_PTE_MODE_CACHE_TILE_L3     3
1910 
1911 /** Data is resident in the tile's local L1 and/or L2 caches.  If a load
1912  *  or store misses there, it goes to an L3 cache in one of a set of
1913  *  designated tiles; if it misses there, it goes to memory.  Which tile
1914  *  is chosen from the set depends upon a hash function applied to the
1915  *  physical address.  This mode is not supported on chips for which
1916  *  CHIP_HAS_CBOX_HOME_MAP() is 0.
1917  *
1918  *  If the NC bit is not set, the copy in the local L1$/L2$ is invalidated
1919  *  when the copy in the remote L3$ is changed.  Otherwise, such
1920  *  invalidation will not occur.
1921  *
1922  *  Chips for which CHIP_HAS_COHERENT_LOCAL_CACHE() is 0 do not support
1923  *  invalidation from an L3$ to another tile's L1$/L2$.  If the NC bit is
1924  *  clear on such a chip, no copy is kept in the local L1$/L2$ in this mode.
1925  */
1926 #define HV_PTE_MODE_CACHE_HASH_L3     4
1927 
1928 /** Data is not resident in memory; accesses are instead made to an I/O
1929  *  device, whose tile coordinates are given by the PTE's LOTAR field.
1930  *  This mode is only supported on chips for which CHIP_HAS_MMIO() is 1.
1931  *  The EXECUTABLE bit may not be set in an MMIO PTE.
1932  */
1933 #define HV_PTE_MODE_MMIO              5
1934 
1935 
1936 /* C wants 1ULL so it is typed as __hv64, but the assembler needs just numbers.
1937  * The assembler can't handle shifts greater than 31, but treats them
1938  * as shifts mod 32, so assembler code must be aware of which word
1939  * the bit belongs in when using these macros.
1940  */
1941 #ifdef __ASSEMBLER__
1942 #define __HV_PTE_ONE 1        /**< One, for assembler */
1943 #else
1944 #define __HV_PTE_ONE 1ULL     /**< One, for C */
1945 #endif
1946 
1947 /** Is this PTE present?
1948  *
1949  * If this bit is set, this PTE represents a valid translation or level-2
1950  * page table pointer.  Otherwise, the page table does not contain a
1951  * translation for the subject virtual pages.
1952  *
1953  * If this bit is not set, the other bits in the PTE are not
1954  * interpreted by the hypervisor, and may contain any value.
1955  */
1956 #define HV_PTE_PRESENT               (__HV_PTE_ONE << HV_PTE_INDEX_PRESENT)
1957 
1958 /** Does this PTE map a page?
1959  *
1960  * If this bit is set in the level-1 page table, the entry should be
1961  * interpreted as a level-2 page table entry mapping a large page.
1962  *
1963  * This bit should not be modified by the client while PRESENT is set, as
1964  * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits.
1965  *
1966  * In a level-2 page table, this bit is ignored and must be zero.
1967  */
1968 #define HV_PTE_PAGE                  (__HV_PTE_ONE << HV_PTE_INDEX_PAGE)
1969 
1970 /** Is this a global (non-ASID) mapping?
1971  *
1972  * If this bit is set, the translations established by this PTE will
1973  * not be flushed from the TLB by the hv_flush_asid() service; they
1974  * will be flushed by the hv_flush_page() or hv_flush_pages() services.
1975  *
1976  * Setting this bit for translations which are identical in all page
1977  * tables (for instance, code and data belonging to a client OS) can
1978  * be very beneficial, as it will reduce the number of TLB misses.
1979  * Note that, while it is not an error which will be detected by the
1980  * hypervisor, it is an extremely bad idea to set this bit for
1981  * translations which are _not_ identical in all page tables.
1982  *
1983  * This bit should not be modified by the client while PRESENT is set, as
1984  * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits.
1985  *
1986  * This bit is ignored in level-1 PTEs unless the Page bit is set.
1987  */
1988 #define HV_PTE_GLOBAL                (__HV_PTE_ONE << HV_PTE_INDEX_GLOBAL)
1989 
1990 /** Is this mapping accessible to users?
1991  *
1992  * If this bit is set, code running at any PL will be permitted to
1993  * access the virtual addresses mapped by this PTE.  Otherwise, only
1994  * code running at PL 1 or above will be allowed to do so.
1995  *
1996  * This bit should not be modified by the client while PRESENT is set, as
1997  * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits.
1998  *
1999  * This bit is ignored in level-1 PTEs unless the Page bit is set.
2000  */
2001 #define HV_PTE_USER                  (__HV_PTE_ONE << HV_PTE_INDEX_USER)
2002 
2003 /** Has this mapping been accessed?
2004  *
2005  * This bit is set by the hypervisor when the memory described by the
2006  * translation is accessed for the first time.  It is never cleared by
2007  * the hypervisor, but may be cleared by the client.  After the bit
2008  * has been cleared, subsequent references are not guaranteed to set
2009  * it again until the translation has been flushed from the TLB.
2010  *
2011  * This bit is ignored in level-1 PTEs unless the Page bit is set.
2012  */
2013 #define HV_PTE_ACCESSED              (__HV_PTE_ONE << HV_PTE_INDEX_ACCESSED)
2014 
2015 /** Is this mapping dirty?
2016  *
2017  * This bit is set by the hypervisor when the memory described by the
2018  * translation is written for the first time.  It is never cleared by
2019  * the hypervisor, but may be cleared by the client.  After the bit
2020  * has been cleared, subsequent references are not guaranteed to set
2021  * it again until the translation has been flushed from the TLB.
2022  *
2023  * This bit is ignored in level-1 PTEs unless the Page bit is set.
2024  */
2025 #define HV_PTE_DIRTY                 (__HV_PTE_ONE << HV_PTE_INDEX_DIRTY)
2026 
2027 /** Migrating bit in PTE.
2028  *
2029  * This bit is guaranteed not to be inspected or modified by the
2030  * hypervisor.  The name is indicative of the suggested use by the client
2031  * to tag pages whose L3 cache is being migrated from one cpu to another.
2032  */
2033 #define HV_PTE_MIGRATING             (__HV_PTE_ONE << HV_PTE_INDEX_MIGRATING)
2034 
2035 /** Client-private bit in PTE.
2036  *
2037  * This bit is guaranteed not to be inspected or modified by the
2038  * hypervisor.
2039  */
2040 #define HV_PTE_CLIENT0               (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT0)
2041 
2042 /** Client-private bit in PTE.
2043  *
2044  * This bit is guaranteed not to be inspected or modified by the
2045  * hypervisor.
2046  */
2047 #define HV_PTE_CLIENT1               (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT1)
2048 
2049 /** Non-coherent (NC) bit in PTE.
2050  *
2051  * If this bit is set, the mapping that is set up will be non-coherent
2052  * (also known as non-inclusive).  This means that changes to the L3
2053  * cache will not cause a local copy to be invalidated.  It is generally
2054  * recommended only for read-only mappings.
2055  *
2056  * In level-1 PTEs, if the Page bit is clear, this bit determines how the
2057  * level-2 page table is accessed.
2058  */
2059 #define HV_PTE_NC                    (__HV_PTE_ONE << HV_PTE_INDEX_NC)
2060 
2061 /** Is this page prevented from filling the L1$?
2062  *
2063  * If this bit is set, the page described by the PTE will not be cached
2064  * the local cpu's L1 cache.
2065  *
2066  * If CHIP_HAS_NC_AND_NOALLOC_BITS() is not true in <chip.h> for this chip,
2067  * it is illegal to use this attribute, and may cause client termination.
2068  *
2069  * In level-1 PTEs, if the Page bit is clear, this bit
2070  * determines how the level-2 page table is accessed.
2071  */
2072 #define HV_PTE_NO_ALLOC_L1           (__HV_PTE_ONE << HV_PTE_INDEX_NO_ALLOC_L1)
2073 
2074 /** Is this page prevented from filling the L2$?
2075  *
2076  * If this bit is set, the page described by the PTE will not be cached
2077  * the local cpu's L2 cache.
2078  *
2079  * If CHIP_HAS_NC_AND_NOALLOC_BITS() is not true in <chip.h> for this chip,
2080  * it is illegal to use this attribute, and may cause client termination.
2081  *
2082  * In level-1 PTEs, if the Page bit is clear, this bit determines how the
2083  * level-2 page table is accessed.
2084  */
2085 #define HV_PTE_NO_ALLOC_L2           (__HV_PTE_ONE << HV_PTE_INDEX_NO_ALLOC_L2)
2086 
2087 /** Is this a priority page?
2088  *
2089  * If this bit is set, the page described by the PTE will be given
2090  * priority in the cache.  Normally this translates into allowing the
2091  * page to use only the "red" half of the cache.  The client may wish to
2092  * then use the hv_set_caching service to specify that other pages which
2093  * alias this page will use only the "black" half of the cache.
2094  *
2095  * If the Cached Priority bit is clear, the hypervisor uses the
2096  * current hv_set_caching() value to choose how to cache the page.
2097  *
2098  * It is illegal to set the Cached Priority bit if the Non-Cached bit
2099  * is set and the Cached Remotely bit is clear, i.e. if requests to
2100  * the page map directly to memory.
2101  *
2102  * This bit is ignored in level-1 PTEs unless the Page bit is set.
2103  */
2104 #define HV_PTE_CACHED_PRIORITY       (__HV_PTE_ONE << \
2105                                       HV_PTE_INDEX_CACHED_PRIORITY)
2106 
2107 /** Is this a readable mapping?
2108  *
2109  * If this bit is set, code will be permitted to read from (e.g.,
2110  * issue load instructions against) the virtual addresses mapped by
2111  * this PTE.
2112  *
2113  * It is illegal for this bit to be clear if the Writable bit is set.
2114  *
2115  * This bit is ignored in level-1 PTEs unless the Page bit is set.
2116  */
2117 #define HV_PTE_READABLE              (__HV_PTE_ONE << HV_PTE_INDEX_READABLE)
2118 
2119 /** Is this a writable mapping?
2120  *
2121  * If this bit is set, code will be permitted to write to (e.g., issue
2122  * store instructions against) the virtual addresses mapped by this
2123  * PTE.
2124  *
2125  * This bit is ignored in level-1 PTEs unless the Page bit is set.
2126  */
2127 #define HV_PTE_WRITABLE              (__HV_PTE_ONE << HV_PTE_INDEX_WRITABLE)
2128 
2129 /** Is this an executable mapping?
2130  *
2131  * If this bit is set, code will be permitted to execute from
2132  * (e.g., jump to) the virtual addresses mapped by this PTE.
2133  *
2134  * This bit applies to any processor on the tile, if there are more
2135  * than one.
2136  *
2137  * This bit is ignored in level-1 PTEs unless the Page bit is set.
2138  */
2139 #define HV_PTE_EXECUTABLE            (__HV_PTE_ONE << HV_PTE_INDEX_EXECUTABLE)
2140 
2141 /** The width of a LOTAR's x or y bitfield. */
2142 #define HV_LOTAR_WIDTH 11
2143 
2144 /** Converts an x,y pair to a LOTAR value. */
2145 #define HV_XY_TO_LOTAR(x, y) ((HV_LOTAR)(((x) << HV_LOTAR_WIDTH) | (y)))
2146 
2147 /** Extracts the X component of a lotar. */
2148 #define HV_LOTAR_X(lotar) ((lotar) >> HV_LOTAR_WIDTH)
2149 
2150 /** Extracts the Y component of a lotar. */
2151 #define HV_LOTAR_Y(lotar) ((lotar) & ((1 << HV_LOTAR_WIDTH) - 1))
2152 
2153 #ifndef __ASSEMBLER__
2154 
2155 /** Define accessor functions for a PTE bit. */
2156 #define _HV_BIT(name, bit)                                      \
2157 static __inline int                                             \
2158 hv_pte_get_##name(HV_PTE pte)                                   \
2159 {                                                               \
2160   return (pte.val >> HV_PTE_INDEX_##bit) & 1;                   \
2161 }                                                               \
2162                                                                 \
2163 static __inline HV_PTE                                          \
2164 hv_pte_set_##name(HV_PTE pte)                                   \
2165 {                                                               \
2166   pte.val |= 1ULL << HV_PTE_INDEX_##bit;                        \
2167   return pte;                                                   \
2168 }                                                               \
2169                                                                 \
2170 static __inline HV_PTE                                          \
2171 hv_pte_clear_##name(HV_PTE pte)                                 \
2172 {                                                               \
2173   pte.val &= ~(1ULL << HV_PTE_INDEX_##bit);                     \
2174   return pte;                                                   \
2175 }
2176 
2177 /* Generate accessors to get, set, and clear various PTE flags.
2178  */
_HV_BIT(present,PRESENT)2179 _HV_BIT(present,         PRESENT)
2180 _HV_BIT(page,            PAGE)
2181 _HV_BIT(client0,         CLIENT0)
2182 _HV_BIT(client1,         CLIENT1)
2183 _HV_BIT(migrating,       MIGRATING)
2184 _HV_BIT(nc,              NC)
2185 _HV_BIT(readable,        READABLE)
2186 _HV_BIT(writable,        WRITABLE)
2187 _HV_BIT(executable,      EXECUTABLE)
2188 _HV_BIT(accessed,        ACCESSED)
2189 _HV_BIT(dirty,           DIRTY)
2190 _HV_BIT(no_alloc_l1,     NO_ALLOC_L1)
2191 _HV_BIT(no_alloc_l2,     NO_ALLOC_L2)
2192 _HV_BIT(cached_priority, CACHED_PRIORITY)
2193 _HV_BIT(global,          GLOBAL)
2194 _HV_BIT(user,            USER)
2195 
2196 #undef _HV_BIT
2197 
2198 /** Get the page mode from the PTE.
2199  *
2200  * This field generally determines whether and how accesses to the page
2201  * are cached; the HV_PTE_MODE_xxx symbols define the legal values for the
2202  * page mode.  The NC, NO_ALLOC_L1, and NO_ALLOC_L2 bits modify this
2203  * general policy.
2204  */
2205 static __inline unsigned int
2206 hv_pte_get_mode(const HV_PTE pte)
2207 {
2208   return (((__hv32) pte.val) >> HV_PTE_INDEX_MODE) &
2209          ((1 << HV_PTE_MODE_BITS) - 1);
2210 }
2211 
2212 /** Set the page mode into a PTE.  See hv_pte_get_mode. */
2213 static __inline HV_PTE
hv_pte_set_mode(HV_PTE pte,unsigned int val)2214 hv_pte_set_mode(HV_PTE pte, unsigned int val)
2215 {
2216   pte.val &= ~(((1ULL << HV_PTE_MODE_BITS) - 1) << HV_PTE_INDEX_MODE);
2217   pte.val |= val << HV_PTE_INDEX_MODE;
2218   return pte;
2219 }
2220 
2221 /** Get the page frame number from the PTE.
2222  *
2223  * This field contains the upper bits of the CPA (client physical
2224  * address) of the target page; the complete CPA is this field with
2225  * HV_LOG2_PAGE_SIZE_SMALL zero bits appended to it.
2226  *
2227  * For PTEs in a level-1 page table where the Page bit is set, the
2228  * CPA must be aligned modulo the large page size.
2229  */
2230 static __inline unsigned int
hv_pte_get_pfn(const HV_PTE pte)2231 hv_pte_get_pfn(const HV_PTE pte)
2232 {
2233   return pte.val >> HV_PTE_INDEX_PFN;
2234 }
2235 
2236 
2237 /** Set the page frame number into a PTE.  See hv_pte_get_pfn. */
2238 static __inline HV_PTE
hv_pte_set_pfn(HV_PTE pte,unsigned int val)2239 hv_pte_set_pfn(HV_PTE pte, unsigned int val)
2240 {
2241   /*
2242    * Note that the use of "PTFN" in the next line is intentional; we
2243    * don't want any garbage lower bits left in that field.
2244    */
2245   pte.val &= ~(((1ULL << HV_PTE_PTFN_BITS) - 1) << HV_PTE_INDEX_PTFN);
2246   pte.val |= (__hv64) val << HV_PTE_INDEX_PFN;
2247   return pte;
2248 }
2249 
2250 /** Get the page table frame number from the PTE.
2251  *
2252  * This field contains the upper bits of the CPA (client physical
2253  * address) of the target page table; the complete CPA is this field with
2254  * with HV_PAGE_TABLE_ALIGN zero bits appended to it.
2255  *
2256  * For PTEs in a level-1 page table when the Page bit is not set, the
2257  * CPA must be aligned modulo the sticter of HV_PAGE_TABLE_ALIGN and
2258  * the level-2 page table size.
2259  */
2260 static __inline unsigned long
hv_pte_get_ptfn(const HV_PTE pte)2261 hv_pte_get_ptfn(const HV_PTE pte)
2262 {
2263   return pte.val >> HV_PTE_INDEX_PTFN;
2264 }
2265 
2266 
2267 /** Set the page table frame number into a PTE.  See hv_pte_get_ptfn. */
2268 static __inline HV_PTE
hv_pte_set_ptfn(HV_PTE pte,unsigned long val)2269 hv_pte_set_ptfn(HV_PTE pte, unsigned long val)
2270 {
2271   pte.val &= ~(((1ULL << HV_PTE_PTFN_BITS)-1) << HV_PTE_INDEX_PTFN);
2272   pte.val |= (__hv64) val << HV_PTE_INDEX_PTFN;
2273   return pte;
2274 }
2275 
2276 
2277 /** Get the remote tile caching this page.
2278  *
2279  * Specifies the remote tile which is providing the L3 cache for this page.
2280  *
2281  * This field is ignored unless the page mode is HV_PTE_MODE_CACHE_TILE_L3.
2282  *
2283  * In level-1 PTEs, if the Page bit is clear, this field determines how the
2284  * level-2 page table is accessed.
2285  */
2286 static __inline unsigned int
hv_pte_get_lotar(const HV_PTE pte)2287 hv_pte_get_lotar(const HV_PTE pte)
2288 {
2289   unsigned int lotar = ((__hv32) pte.val) >> HV_PTE_INDEX_LOTAR;
2290 
2291   return HV_XY_TO_LOTAR( (lotar >> (HV_PTE_LOTAR_BITS / 2)),
2292                          (lotar & ((1 << (HV_PTE_LOTAR_BITS / 2)) - 1)) );
2293 }
2294 
2295 
2296 /** Set the remote tile caching a page into a PTE.  See hv_pte_get_lotar. */
2297 static __inline HV_PTE
hv_pte_set_lotar(HV_PTE pte,unsigned int val)2298 hv_pte_set_lotar(HV_PTE pte, unsigned int val)
2299 {
2300   unsigned int x = HV_LOTAR_X(val);
2301   unsigned int y = HV_LOTAR_Y(val);
2302 
2303   pte.val &= ~(((1ULL << HV_PTE_LOTAR_BITS)-1) << HV_PTE_INDEX_LOTAR);
2304   pte.val |= (x << (HV_PTE_INDEX_LOTAR + HV_PTE_LOTAR_BITS / 2)) |
2305              (y << HV_PTE_INDEX_LOTAR);
2306   return pte;
2307 }
2308 
2309 #endif  /* !__ASSEMBLER__ */
2310 
2311 /** Converts a client physical address to a pfn. */
2312 #define HV_CPA_TO_PFN(p) ((p) >> HV_LOG2_PAGE_SIZE_SMALL)
2313 
2314 /** Converts a pfn to a client physical address. */
2315 #define HV_PFN_TO_CPA(p) (((HV_PhysAddr)(p)) << HV_LOG2_PAGE_SIZE_SMALL)
2316 
2317 /** Converts a client physical address to a ptfn. */
2318 #define HV_CPA_TO_PTFN(p) ((p) >> HV_LOG2_PAGE_TABLE_ALIGN)
2319 
2320 /** Converts a ptfn to a client physical address. */
2321 #define HV_PTFN_TO_CPA(p) (((HV_PhysAddr)(p)) << HV_LOG2_PAGE_TABLE_ALIGN)
2322 
2323 /** Converts a ptfn to a pfn. */
2324 #define HV_PTFN_TO_PFN(p) \
2325   ((p) >> (HV_LOG2_PAGE_SIZE_SMALL - HV_LOG2_PAGE_TABLE_ALIGN))
2326 
2327 /** Converts a pfn to a ptfn. */
2328 #define HV_PFN_TO_PTFN(p) \
2329   ((p) << (HV_LOG2_PAGE_SIZE_SMALL - HV_LOG2_PAGE_TABLE_ALIGN))
2330 
2331 #if CHIP_VA_WIDTH() > 32
2332 
2333 /** Log number of HV_PTE entries in L0 page table */
2334 #define HV_LOG2_L0_ENTRIES (CHIP_VA_WIDTH() - HV_LOG2_L1_SPAN)
2335 
2336 /** Number of HV_PTE entries in L0 page table */
2337 #define HV_L0_ENTRIES (1 << HV_LOG2_L0_ENTRIES)
2338 
2339 /** Log size of L0 page table in bytes */
2340 #define HV_LOG2_L0_SIZE (HV_LOG2_PTE_SIZE + HV_LOG2_L0_ENTRIES)
2341 
2342 /** Size of L0 page table in bytes */
2343 #define HV_L0_SIZE (1 << HV_LOG2_L0_SIZE)
2344 
2345 #ifdef __ASSEMBLER__
2346 
2347 /** Index in L0 for a specific VA */
2348 #define HV_L0_INDEX(va) \
2349   (((va) >> HV_LOG2_L1_SPAN) & (HV_L0_ENTRIES - 1))
2350 
2351 #else
2352 
2353 /** Index in L1 for a specific VA */
2354 #define HV_L0_INDEX(va) \
2355   (((HV_VirtAddr)(va) >> HV_LOG2_L1_SPAN) & (HV_L0_ENTRIES - 1))
2356 
2357 #endif
2358 
2359 #endif /* CHIP_VA_WIDTH() > 32 */
2360 
2361 /** Log number of HV_PTE entries in L1 page table */
2362 #define HV_LOG2_L1_ENTRIES (HV_LOG2_L1_SPAN - HV_LOG2_PAGE_SIZE_LARGE)
2363 
2364 /** Number of HV_PTE entries in L1 page table */
2365 #define HV_L1_ENTRIES (1 << HV_LOG2_L1_ENTRIES)
2366 
2367 /** Log size of L1 page table in bytes */
2368 #define HV_LOG2_L1_SIZE (HV_LOG2_PTE_SIZE + HV_LOG2_L1_ENTRIES)
2369 
2370 /** Size of L1 page table in bytes */
2371 #define HV_L1_SIZE (1 << HV_LOG2_L1_SIZE)
2372 
2373 /** Log number of HV_PTE entries in level-2 page table */
2374 #define HV_LOG2_L2_ENTRIES (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL)
2375 
2376 /** Number of HV_PTE entries in level-2 page table */
2377 #define HV_L2_ENTRIES (1 << HV_LOG2_L2_ENTRIES)
2378 
2379 /** Log size of level-2 page table in bytes */
2380 #define HV_LOG2_L2_SIZE (HV_LOG2_PTE_SIZE + HV_LOG2_L2_ENTRIES)
2381 
2382 /** Size of level-2 page table in bytes */
2383 #define HV_L2_SIZE (1 << HV_LOG2_L2_SIZE)
2384 
2385 #ifdef __ASSEMBLER__
2386 
2387 #if CHIP_VA_WIDTH() > 32
2388 
2389 /** Index in L1 for a specific VA */
2390 #define HV_L1_INDEX(va) \
2391   (((va) >> HV_LOG2_PAGE_SIZE_LARGE) & (HV_L1_ENTRIES - 1))
2392 
2393 #else /* CHIP_VA_WIDTH() > 32 */
2394 
2395 /** Index in L1 for a specific VA */
2396 #define HV_L1_INDEX(va) \
2397   (((va) >> HV_LOG2_PAGE_SIZE_LARGE))
2398 
2399 #endif /* CHIP_VA_WIDTH() > 32 */
2400 
2401 /** Index in level-2 page table for a specific VA */
2402 #define HV_L2_INDEX(va) \
2403   (((va) >> HV_LOG2_PAGE_SIZE_SMALL) & (HV_L2_ENTRIES - 1))
2404 
2405 #else /* __ASSEMBLER __ */
2406 
2407 #if CHIP_VA_WIDTH() > 32
2408 
2409 /** Index in L1 for a specific VA */
2410 #define HV_L1_INDEX(va) \
2411   (((HV_VirtAddr)(va) >> HV_LOG2_PAGE_SIZE_LARGE) & (HV_L1_ENTRIES - 1))
2412 
2413 #else /* CHIP_VA_WIDTH() > 32 */
2414 
2415 /** Index in L1 for a specific VA */
2416 #define HV_L1_INDEX(va) \
2417   (((HV_VirtAddr)(va) >> HV_LOG2_PAGE_SIZE_LARGE))
2418 
2419 #endif /* CHIP_VA_WIDTH() > 32 */
2420 
2421 /** Index in level-2 page table for a specific VA */
2422 #define HV_L2_INDEX(va) \
2423   (((HV_VirtAddr)(va) >> HV_LOG2_PAGE_SIZE_SMALL) & (HV_L2_ENTRIES - 1))
2424 
2425 #endif /* __ASSEMBLER __ */
2426 
2427 #endif /* _TILE_HV_H */
2428