1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef ATH11K_DP_H
7 #define ATH11K_DP_H
8 
9 #include "hal_rx.h"
10 
11 #define MAX_RXDMA_PER_PDEV     2
12 
13 struct ath11k_base;
14 struct ath11k_peer;
15 struct ath11k_dp;
16 struct ath11k_vif;
17 struct hal_tcl_status_ring;
18 struct ath11k_ext_irq_grp;
19 
20 struct dp_rx_tid {
21 	u8 tid;
22 	u32 *vaddr;
23 	dma_addr_t paddr;
24 	u32 size;
25 	u32 ba_win_sz;
26 	bool active;
27 
28 	/* Info related to rx fragments */
29 	u32 cur_sn;
30 	u16 last_frag_no;
31 	u16 rx_frag_bitmap;
32 
33 	struct sk_buff_head rx_frags;
34 	struct hal_reo_dest_ring *dst_ring_desc;
35 
36 	/* Timer info related to fragments */
37 	struct timer_list frag_timer;
38 	struct ath11k_base *ab;
39 };
40 
41 #define DP_REO_DESC_FREE_THRESHOLD  64
42 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000
43 #define DP_MON_PURGE_TIMEOUT_MS     100
44 #define DP_MON_SERVICE_BUDGET       128
45 
46 struct dp_reo_cache_flush_elem {
47 	struct list_head list;
48 	struct dp_rx_tid data;
49 	unsigned long ts;
50 };
51 
52 struct dp_reo_cmd {
53 	struct list_head list;
54 	struct dp_rx_tid data;
55 	int cmd_num;
56 	void (*handler)(struct ath11k_dp *, void *,
57 			enum hal_reo_cmd_status status);
58 };
59 
60 struct dp_srng {
61 	u32 *vaddr_unaligned;
62 	u32 *vaddr;
63 	dma_addr_t paddr_unaligned;
64 	dma_addr_t paddr;
65 	int size;
66 	u32 ring_id;
67 	u8 cached;
68 };
69 
70 struct dp_rxdma_ring {
71 	struct dp_srng refill_buf_ring;
72 	struct idr bufs_idr;
73 	/* Protects bufs_idr */
74 	spinlock_t idr_lock;
75 	int bufs_max;
76 };
77 
78 #define ATH11K_TX_COMPL_NEXT(x)	(((x) + 1) % DP_TX_COMP_RING_SIZE)
79 
80 struct dp_tx_ring {
81 	u8 tcl_data_ring_id;
82 	struct dp_srng tcl_data_ring;
83 	struct dp_srng tcl_comp_ring;
84 	struct idr txbuf_idr;
85 	/* Protects txbuf_idr and num_pending */
86 	spinlock_t tx_idr_lock;
87 	struct hal_wbm_release_ring *tx_status;
88 	int tx_status_head;
89 	int tx_status_tail;
90 };
91 
92 enum dp_mon_status_buf_state {
93 	/* PPDU id matches in dst ring and status ring */
94 	DP_MON_STATUS_MATCH,
95 	/* status ring dma is not done */
96 	DP_MON_STATUS_NO_DMA,
97 	/* status ring is lagging, reap status ring */
98 	DP_MON_STATUS_LAG,
99 	/* status ring is leading, reap dst ring and drop */
100 	DP_MON_STATUS_LEAD,
101 	/* replinish monitor status ring */
102 	DP_MON_STATUS_REPLINISH,
103 };
104 
105 struct ath11k_pdev_mon_stats {
106 	u32 status_ppdu_state;
107 	u32 status_ppdu_start;
108 	u32 status_ppdu_end;
109 	u32 status_ppdu_compl;
110 	u32 status_ppdu_start_mis;
111 	u32 status_ppdu_end_mis;
112 	u32 status_ppdu_done;
113 	u32 dest_ppdu_done;
114 	u32 dest_mpdu_done;
115 	u32 dest_mpdu_drop;
116 	u32 dup_mon_linkdesc_cnt;
117 	u32 dup_mon_buf_cnt;
118 	u32 dest_mon_stuck;
119 	u32 dest_mon_not_reaped;
120 };
121 
122 struct dp_full_mon_mpdu {
123 	struct list_head list;
124 	struct sk_buff *head;
125 	struct sk_buff *tail;
126 };
127 
128 struct dp_link_desc_bank {
129 	void *vaddr_unaligned;
130 	void *vaddr;
131 	dma_addr_t paddr_unaligned;
132 	dma_addr_t paddr;
133 	u32 size;
134 };
135 
136 /* Size to enforce scatter idle list mode */
137 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
138 #define DP_LINK_DESC_BANKS_MAX 8
139 
140 #define DP_RX_DESC_COOKIE_INDEX_MAX		0x3ffff
141 #define DP_RX_DESC_COOKIE_POOL_ID_MAX		0x1c0000
142 #define DP_RX_DESC_COOKIE_MAX	\
143 	(DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX)
144 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000
145 
146 enum ath11k_dp_ppdu_state {
147 	DP_PPDU_STATUS_START,
148 	DP_PPDU_STATUS_DONE,
149 };
150 
151 struct ath11k_mon_data {
152 	struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
153 	struct hal_rx_mon_ppdu_info mon_ppdu_info;
154 
155 	u32 mon_ppdu_status;
156 	u32 mon_last_buf_cookie;
157 	u64 mon_last_linkdesc_paddr;
158 	u16 chan_noise_floor;
159 	bool hold_mon_dst_ring;
160 	enum dp_mon_status_buf_state buf_state;
161 	dma_addr_t mon_status_paddr;
162 	struct dp_full_mon_mpdu *mon_mpdu;
163 	struct hal_sw_mon_ring_entries sw_mon_entries;
164 	struct ath11k_pdev_mon_stats rx_mon_stats;
165 	/* lock for monitor data */
166 	spinlock_t mon_lock;
167 	struct sk_buff_head rx_status_q;
168 };
169 
170 struct ath11k_pdev_dp {
171 	u32 mac_id;
172 	u32 mon_dest_ring_stuck_cnt;
173 	atomic_t num_tx_pending;
174 	wait_queue_head_t tx_empty_waitq;
175 	struct dp_rxdma_ring rx_refill_buf_ring;
176 	struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];
177 	struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];
178 	struct dp_srng rxdma_mon_dst_ring;
179 	struct dp_srng rxdma_mon_desc_ring;
180 
181 	struct dp_rxdma_ring rxdma_mon_buf_ring;
182 	struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV];
183 	struct ieee80211_rx_status rx_status;
184 	struct ath11k_mon_data mon_data;
185 };
186 
187 #define DP_NUM_CLIENTS_MAX 64
188 #define DP_AVG_TIDS_PER_CLIENT 2
189 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT)
190 #define DP_AVG_MSDUS_PER_FLOW 128
191 #define DP_AVG_FLOWS_PER_TID 2
192 #define DP_AVG_MPDUS_PER_TID_MAX 128
193 #define DP_AVG_MSDUS_PER_MPDU 4
194 
195 #define DP_RX_HASH_ENABLE	1 /* Enable hash based Rx steering */
196 
197 #define DP_BA_WIN_SZ_MAX	256
198 
199 #define DP_TCL_NUM_RING_MAX	3
200 #define DP_TCL_NUM_RING_MAX_QCA6390	1
201 
202 #define DP_IDLE_SCATTER_BUFS_MAX 16
203 
204 #define DP_WBM_RELEASE_RING_SIZE	64
205 #define DP_TCL_DATA_RING_SIZE		512
206 #define DP_TX_COMP_RING_SIZE		32768
207 #define DP_TX_IDR_SIZE			DP_TX_COMP_RING_SIZE
208 #define DP_TCL_CMD_RING_SIZE		32
209 #define DP_TCL_STATUS_RING_SIZE		32
210 #define DP_REO_DST_RING_MAX		4
211 #define DP_REO_DST_RING_SIZE		2048
212 #define DP_REO_REINJECT_RING_SIZE	32
213 #define DP_RX_RELEASE_RING_SIZE		1024
214 #define DP_REO_EXCEPTION_RING_SIZE	128
215 #define DP_REO_CMD_RING_SIZE		128
216 #define DP_REO_STATUS_RING_SIZE		2048
217 #define DP_RXDMA_BUF_RING_SIZE		4096
218 #define DP_RXDMA_REFILL_RING_SIZE	2048
219 #define DP_RXDMA_ERR_DST_RING_SIZE	1024
220 #define DP_RXDMA_MON_STATUS_RING_SIZE	1024
221 #define DP_RXDMA_MONITOR_BUF_RING_SIZE	4096
222 #define DP_RXDMA_MONITOR_DST_RING_SIZE	2048
223 #define DP_RXDMA_MONITOR_DESC_RING_SIZE	4096
224 
225 #define DP_RX_BUFFER_SIZE	2048
226 #define	DP_RX_BUFFER_SIZE_LITE  1024
227 #define DP_RX_BUFFER_ALIGN_SIZE	128
228 
229 #define DP_RXDMA_BUF_COOKIE_BUF_ID	GENMASK(17, 0)
230 #define DP_RXDMA_BUF_COOKIE_PDEV_ID	GENMASK(20, 18)
231 
232 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0)
233 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1)
234 
235 #define DP_TX_DESC_ID_MAC_ID  GENMASK(1, 0)
236 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
237 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
238 
239 #define ATH11K_SHADOW_DP_TIMER_INTERVAL 20
240 #define ATH11K_SHADOW_CTRL_TIMER_INTERVAL 10
241 
242 struct ath11k_hp_update_timer {
243 	struct timer_list timer;
244 	bool started;
245 	bool init;
246 	u32 tx_num;
247 	u32 timer_tx_num;
248 	u32 ring_id;
249 	u32 interval;
250 	struct ath11k_base *ab;
251 };
252 
253 struct ath11k_dp {
254 	struct ath11k_base *ab;
255 	enum ath11k_htc_ep_id eid;
256 	struct completion htt_tgt_version_received;
257 	u8 htt_tgt_ver_major;
258 	u8 htt_tgt_ver_minor;
259 	struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX];
260 	struct dp_srng wbm_idle_ring;
261 	struct dp_srng wbm_desc_rel_ring;
262 	struct dp_srng tcl_cmd_ring;
263 	struct dp_srng tcl_status_ring;
264 	struct dp_srng reo_reinject_ring;
265 	struct dp_srng rx_rel_ring;
266 	struct dp_srng reo_except_ring;
267 	struct dp_srng reo_cmd_ring;
268 	struct dp_srng reo_status_ring;
269 	struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX];
270 	struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
271 	struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX];
272 	struct list_head reo_cmd_list;
273 	struct list_head reo_cmd_cache_flush_list;
274 	struct list_head dp_full_mon_mpdu_list;
275 	u32 reo_cmd_cache_flush_count;
276 	/**
277 	 * protects access to below fields,
278 	 * - reo_cmd_list
279 	 * - reo_cmd_cache_flush_list
280 	 * - reo_cmd_cache_flush_count
281 	 */
282 	spinlock_t reo_cmd_lock;
283 	struct ath11k_hp_update_timer reo_cmd_timer;
284 	struct ath11k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
285 };
286 
287 /* HTT definitions */
288 
289 #define HTT_TCL_META_DATA_TYPE			BIT(0)
290 #define HTT_TCL_META_DATA_VALID_HTT		BIT(1)
291 
292 /* vdev meta data */
293 #define HTT_TCL_META_DATA_VDEV_ID		GENMASK(9, 2)
294 #define HTT_TCL_META_DATA_PDEV_ID		GENMASK(11, 10)
295 #define HTT_TCL_META_DATA_HOST_INSPECTED	BIT(12)
296 
297 /* peer meta data */
298 #define HTT_TCL_META_DATA_PEER_ID		GENMASK(15, 2)
299 
300 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8
301 
302 /* HTT tx completion is overlayed in wbm_release_ring */
303 #define HTT_TX_WBM_COMP_INFO0_STATUS		GENMASK(12, 9)
304 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON	GENMASK(16, 13)
305 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON	GENMASK(16, 13)
306 
307 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI		GENMASK(31, 24)
308 
309 struct htt_tx_wbm_completion {
310 	u32 info0;
311 	u32 info1;
312 	u32 info2;
313 	u32 info3;
314 } __packed;
315 
316 enum htt_h2t_msg_type {
317 	HTT_H2T_MSG_TYPE_VERSION_REQ		= 0,
318 	HTT_H2T_MSG_TYPE_SRING_SETUP		= 0xb,
319 	HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG	= 0xc,
320 	HTT_H2T_MSG_TYPE_EXT_STATS_CFG		= 0x10,
321 	HTT_H2T_MSG_TYPE_PPDU_STATS_CFG		= 0x11,
322 	HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE	= 0x17,
323 };
324 
325 #define HTT_VER_REQ_INFO_MSG_ID		GENMASK(7, 0)
326 
327 struct htt_ver_req_cmd {
328 	u32 ver_reg_info;
329 } __packed;
330 
331 enum htt_srng_ring_type {
332 	HTT_HW_TO_SW_RING,
333 	HTT_SW_TO_HW_RING,
334 	HTT_SW_TO_SW_RING,
335 };
336 
337 enum htt_srng_ring_id {
338 	HTT_RXDMA_HOST_BUF_RING,
339 	HTT_RXDMA_MONITOR_STATUS_RING,
340 	HTT_RXDMA_MONITOR_BUF_RING,
341 	HTT_RXDMA_MONITOR_DESC_RING,
342 	HTT_RXDMA_MONITOR_DEST_RING,
343 	HTT_HOST1_TO_FW_RXBUF_RING,
344 	HTT_HOST2_TO_FW_RXBUF_RING,
345 	HTT_RXDMA_NON_MONITOR_DEST_RING,
346 };
347 
348 /* host -> target  HTT_SRING_SETUP message
349  *
350  * After target is booted up, Host can send SRING setup message for
351  * each host facing LMAC SRING. Target setups up HW registers based
352  * on setup message and confirms back to Host if response_required is set.
353  * Host should wait for confirmation message before sending new SRING
354  * setup message
355  *
356  * The message would appear as follows:
357  *
358  * |31            24|23    20|19|18 16|15|14          8|7                0|
359  * |--------------- +-----------------+----------------+------------------|
360  * |    ring_type   |      ring_id    |    pdev_id     |     msg_type     |
361  * |----------------------------------------------------------------------|
362  * |                          ring_base_addr_lo                           |
363  * |----------------------------------------------------------------------|
364  * |                         ring_base_addr_hi                            |
365  * |----------------------------------------------------------------------|
366  * |ring_misc_cfg_flag|ring_entry_size|            ring_size              |
367  * |----------------------------------------------------------------------|
368  * |                         ring_head_offset32_remote_addr_lo            |
369  * |----------------------------------------------------------------------|
370  * |                         ring_head_offset32_remote_addr_hi            |
371  * |----------------------------------------------------------------------|
372  * |                         ring_tail_offset32_remote_addr_lo            |
373  * |----------------------------------------------------------------------|
374  * |                         ring_tail_offset32_remote_addr_hi            |
375  * |----------------------------------------------------------------------|
376  * |                          ring_msi_addr_lo                            |
377  * |----------------------------------------------------------------------|
378  * |                          ring_msi_addr_hi                            |
379  * |----------------------------------------------------------------------|
380  * |                          ring_msi_data                               |
381  * |----------------------------------------------------------------------|
382  * |         intr_timer_th            |IM|      intr_batch_counter_th     |
383  * |----------------------------------------------------------------------|
384  * |          reserved        |RR|PTCF|        intr_low_threshold         |
385  * |----------------------------------------------------------------------|
386  * Where
387  *     IM = sw_intr_mode
388  *     RR = response_required
389  *     PTCF = prefetch_timer_cfg
390  *
391  * The message is interpreted as follows:
392  * dword0  - b'0:7   - msg_type: This will be set to
393  *                     HTT_H2T_MSG_TYPE_SRING_SETUP
394  *           b'8:15  - pdev_id:
395  *                     0 (for rings at SOC/UMAC level),
396  *                     1/2/3 mac id (for rings at LMAC level)
397  *           b'16:23 - ring_id: identify which ring is to setup,
398  *                     more details can be got from enum htt_srng_ring_id
399  *           b'24:31 - ring_type: identify type of host rings,
400  *                     more details can be got from enum htt_srng_ring_type
401  * dword1  - b'0:31  - ring_base_addr_lo: Lower 32bits of ring base address
402  * dword2  - b'0:31  - ring_base_addr_hi: Upper 32bits of ring base address
403  * dword3  - b'0:15  - ring_size: size of the ring in unit of 4-bytes words
404  *           b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
405  *           b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
406  *                     SW_TO_HW_RING.
407  *                     Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
408  * dword4  - b'0:31  - ring_head_off32_remote_addr_lo:
409  *                     Lower 32 bits of memory address of the remote variable
410  *                     storing the 4-byte word offset that identifies the head
411  *                     element within the ring.
412  *                     (The head offset variable has type u32.)
413  *                     Valid for HW_TO_SW and SW_TO_SW rings.
414  * dword5  - b'0:31  - ring_head_off32_remote_addr_hi:
415  *                     Upper 32 bits of memory address of the remote variable
416  *                     storing the 4-byte word offset that identifies the head
417  *                     element within the ring.
418  *                     (The head offset variable has type u32.)
419  *                     Valid for HW_TO_SW and SW_TO_SW rings.
420  * dword6  - b'0:31  - ring_tail_off32_remote_addr_lo:
421  *                     Lower 32 bits of memory address of the remote variable
422  *                     storing the 4-byte word offset that identifies the tail
423  *                     element within the ring.
424  *                     (The tail offset variable has type u32.)
425  *                     Valid for HW_TO_SW and SW_TO_SW rings.
426  * dword7  - b'0:31  - ring_tail_off32_remote_addr_hi:
427  *                     Upper 32 bits of memory address of the remote variable
428  *                     storing the 4-byte word offset that identifies the tail
429  *                     element within the ring.
430  *                     (The tail offset variable has type u32.)
431  *                     Valid for HW_TO_SW and SW_TO_SW rings.
432  * dword8  - b'0:31  - ring_msi_addr_lo: Lower 32bits of MSI cfg address
433  *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
434  * dword9  - b'0:31  - ring_msi_addr_hi: Upper 32bits of MSI cfg address
435  *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
436  * dword10 - b'0:31  - ring_msi_data: MSI data
437  *                     Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
438  *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
439  * dword11 - b'0:14  - intr_batch_counter_th:
440  *                     batch counter threshold is in units of 4-byte words.
441  *                     HW internally maintains and increments batch count.
442  *                     (see SRING spec for detail description).
443  *                     When batch count reaches threshold value, an interrupt
444  *                     is generated by HW.
445  *           b'15    - sw_intr_mode:
446  *                     This configuration shall be static.
447  *                     Only programmed at power up.
448  *                     0: generate pulse style sw interrupts
449  *                     1: generate level style sw interrupts
450  *           b'16:31 - intr_timer_th:
451  *                     The timer init value when timer is idle or is
452  *                     initialized to start downcounting.
453  *                     In 8us units (to cover a range of 0 to 524 ms)
454  * dword12 - b'0:15  - intr_low_threshold:
455  *                     Used only by Consumer ring to generate ring_sw_int_p.
456  *                     Ring entries low threshold water mark, that is used
457  *                     in combination with the interrupt timer as well as
458  *                     the clearing of the level interrupt.
459  *           b'16:18 - prefetch_timer_cfg:
460  *                     Used only by Consumer ring to set timer mode to
461  *                     support Application prefetch handling.
462  *                     The external tail offset/pointer will be updated
463  *                     at following intervals:
464  *                     3'b000: (Prefetch feature disabled; used only for debug)
465  *                     3'b001: 1 usec
466  *                     3'b010: 4 usec
467  *                     3'b011: 8 usec (default)
468  *                     3'b100: 16 usec
469  *                     Others: Reserverd
470  *           b'19    - response_required:
471  *                     Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
472  *           b'20:31 - reserved:  reserved for future use
473  */
474 
475 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE	GENMASK(7, 0)
476 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID	GENMASK(15, 8)
477 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID	GENMASK(23, 16)
478 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE	GENMASK(31, 24)
479 
480 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE			GENMASK(15, 0)
481 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE		GENMASK(23, 16)
482 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS		BIT(25)
483 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP		BIT(27)
484 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP	BIT(28)
485 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP		BIT(29)
486 
487 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH	GENMASK(14, 0)
488 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE		BIT(15)
489 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH		GENMASK(31, 16)
490 
491 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH	GENMASK(15, 0)
492 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG	BIT(16)
493 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED	BIT(19)
494 
495 struct htt_srng_setup_cmd {
496 	u32 info0;
497 	u32 ring_base_addr_lo;
498 	u32 ring_base_addr_hi;
499 	u32 info1;
500 	u32 ring_head_off32_remote_addr_lo;
501 	u32 ring_head_off32_remote_addr_hi;
502 	u32 ring_tail_off32_remote_addr_lo;
503 	u32 ring_tail_off32_remote_addr_hi;
504 	u32 ring_msi_addr_lo;
505 	u32 ring_msi_addr_hi;
506 	u32 msi_data;
507 	u32 intr_info;
508 	u32 info2;
509 } __packed;
510 
511 /* host -> target FW  PPDU_STATS config message
512  *
513  * @details
514  * The following field definitions describe the format of the HTT host
515  * to target FW for PPDU_STATS_CFG msg.
516  * The message allows the host to configure the PPDU_STATS_IND messages
517  * produced by the target.
518  *
519  * |31          24|23          16|15           8|7            0|
520  * |-----------------------------------------------------------|
521  * |    REQ bit mask             |   pdev_mask  |   msg type   |
522  * |-----------------------------------------------------------|
523  * Header fields:
524  *  - MSG_TYPE
525  *    Bits 7:0
526  *    Purpose: identifies this is a req to configure ppdu_stats_ind from target
527  *    Value: 0x11
528  *  - PDEV_MASK
529  *    Bits 8:15
530  *    Purpose: identifies which pdevs this PPDU stats configuration applies to
531  *    Value: This is a overloaded field, refer to usage and interpretation of
532  *           PDEV in interface document.
533  *           Bit   8    :  Reserved for SOC stats
534  *           Bit 9 - 15 :  Indicates PDEV_MASK in DBDC
535  *                         Indicates MACID_MASK in DBS
536  *  - REQ_TLV_BIT_MASK
537  *    Bits 16:31
538  *    Purpose: each set bit indicates the corresponding PPDU stats TLV type
539  *        needs to be included in the target's PPDU_STATS_IND messages.
540  *    Value: refer htt_ppdu_stats_tlv_tag_t <<<???
541  *
542  */
543 
544 struct htt_ppdu_stats_cfg_cmd {
545 	u32 msg;
546 } __packed;
547 
548 #define HTT_PPDU_STATS_CFG_MSG_TYPE		GENMASK(7, 0)
549 #define HTT_PPDU_STATS_CFG_SOC_STATS		BIT(8)
550 #define HTT_PPDU_STATS_CFG_PDEV_ID		GENMASK(15, 9)
551 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK	GENMASK(31, 16)
552 
553 enum htt_ppdu_stats_tag_type {
554 	HTT_PPDU_STATS_TAG_COMMON,
555 	HTT_PPDU_STATS_TAG_USR_COMMON,
556 	HTT_PPDU_STATS_TAG_USR_RATE,
557 	HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,
558 	HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,
559 	HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,
560 	HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,
561 	HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,
562 	HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,
563 	HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,
564 	HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,
565 	HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,
566 	HTT_PPDU_STATS_TAG_INFO,
567 	HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,
568 
569 	/* New TLV's are added above to this line */
570 	HTT_PPDU_STATS_TAG_MAX,
571 };
572 
573 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
574 				   | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
575 				   | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
576 				   | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
577 				   | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
578 				   | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
579 				   | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
580 				   | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
581 
582 #define HTT_PPDU_STATS_TAG_PKTLOG  (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
583 				    BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
584 				    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
585 				    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
586 				    BIT(HTT_PPDU_STATS_TAG_INFO) | \
587 				    BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
588 				    HTT_PPDU_STATS_TAG_DEFAULT)
589 
590 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message
591  *
592  * details:
593  *    HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
594  *    configure RXDMA rings.
595  *    The configuration is per ring based and includes both packet subtypes
596  *    and PPDU/MPDU TLVs.
597  *
598  *    The message would appear as follows:
599  *
600  *    |31       26|25|24|23            16|15             8|7             0|
601  *    |-----------------+----------------+----------------+---------------|
602  *    |   rsvd1   |PS|SS|     ring_id    |     pdev_id    |    msg_type   |
603  *    |-------------------------------------------------------------------|
604  *    |              rsvd2               |           ring_buffer_size     |
605  *    |-------------------------------------------------------------------|
606  *    |                        packet_type_enable_flags_0                 |
607  *    |-------------------------------------------------------------------|
608  *    |                        packet_type_enable_flags_1                 |
609  *    |-------------------------------------------------------------------|
610  *    |                        packet_type_enable_flags_2                 |
611  *    |-------------------------------------------------------------------|
612  *    |                        packet_type_enable_flags_3                 |
613  *    |-------------------------------------------------------------------|
614  *    |                         tlv_filter_in_flags                       |
615  *    |-------------------------------------------------------------------|
616  * Where:
617  *     PS = pkt_swap
618  *     SS = status_swap
619  * The message is interpreted as follows:
620  * dword0 - b'0:7   - msg_type: This will be set to
621  *                    HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
622  *          b'8:15  - pdev_id:
623  *                    0 (for rings at SOC/UMAC level),
624  *                    1/2/3 mac id (for rings at LMAC level)
625  *          b'16:23 - ring_id : Identify the ring to configure.
626  *                    More details can be got from enum htt_srng_ring_id
627  *          b'24    - status_swap: 1 is to swap status TLV
628  *          b'25    - pkt_swap:  1 is to swap packet TLV
629  *          b'26:31 - rsvd1:  reserved for future use
630  * dword1 - b'0:16  - ring_buffer_size: size of bufferes referenced by rx ring,
631  *                    in byte units.
632  *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
633  *        - b'16:31 - rsvd2: Reserved for future use
634  * dword2 - b'0:31  - packet_type_enable_flags_0:
635  *                    Enable MGMT packet from 0b0000 to 0b1001
636  *                    bits from low to high: FP, MD, MO - 3 bits
637  *                        FP: Filter_Pass
638  *                        MD: Monitor_Direct
639  *                        MO: Monitor_Other
640  *                    10 mgmt subtypes * 3 bits -> 30 bits
641  *                    Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
642  * dword3 - b'0:31  - packet_type_enable_flags_1:
643  *                    Enable MGMT packet from 0b1010 to 0b1111
644  *                    bits from low to high: FP, MD, MO - 3 bits
645  *                    Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
646  * dword4 - b'0:31 -  packet_type_enable_flags_2:
647  *                    Enable CTRL packet from 0b0000 to 0b1001
648  *                    bits from low to high: FP, MD, MO - 3 bits
649  *                    Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
650  * dword5 - b'0:31  - packet_type_enable_flags_3:
651  *                    Enable CTRL packet from 0b1010 to 0b1111,
652  *                    MCAST_DATA, UCAST_DATA, NULL_DATA
653  *                    bits from low to high: FP, MD, MO - 3 bits
654  *                    Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
655  * dword6 - b'0:31 -  tlv_filter_in_flags:
656  *                    Filter in Attention/MPDU/PPDU/Header/User tlvs
657  *                    Refer to CFG_TLV_FILTER_IN_FLAG defs
658  */
659 
660 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE	GENMASK(7, 0)
661 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID	GENMASK(15, 8)
662 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID	GENMASK(23, 16)
663 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS		BIT(24)
664 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS		BIT(25)
665 
666 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE	GENMASK(15, 0)
667 
668 enum htt_rx_filter_tlv_flags {
669 	HTT_RX_FILTER_TLV_FLAGS_MPDU_START		= BIT(0),
670 	HTT_RX_FILTER_TLV_FLAGS_MSDU_START		= BIT(1),
671 	HTT_RX_FILTER_TLV_FLAGS_RX_PACKET		= BIT(2),
672 	HTT_RX_FILTER_TLV_FLAGS_MSDU_END		= BIT(3),
673 	HTT_RX_FILTER_TLV_FLAGS_MPDU_END		= BIT(4),
674 	HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER		= BIT(5),
675 	HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER		= BIT(6),
676 	HTT_RX_FILTER_TLV_FLAGS_ATTENTION		= BIT(7),
677 	HTT_RX_FILTER_TLV_FLAGS_PPDU_START		= BIT(8),
678 	HTT_RX_FILTER_TLV_FLAGS_PPDU_END		= BIT(9),
679 	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS	= BIT(10),
680 	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT	= BIT(11),
681 	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE	= BIT(12),
682 };
683 
684 enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
685 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ		= BIT(0),
686 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ		= BIT(1),
687 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ		= BIT(2),
688 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP		= BIT(3),
689 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP		= BIT(4),
690 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP		= BIT(5),
691 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ	= BIT(6),
692 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ	= BIT(7),
693 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ	= BIT(8),
694 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP	= BIT(9),
695 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP	= BIT(10),
696 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP	= BIT(11),
697 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ		= BIT(12),
698 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ		= BIT(13),
699 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ		= BIT(14),
700 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP		= BIT(15),
701 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP		= BIT(16),
702 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP		= BIT(17),
703 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV	= BIT(18),
704 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV	= BIT(19),
705 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV	= BIT(20),
706 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7		= BIT(21),
707 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7		= BIT(22),
708 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7		= BIT(23),
709 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON		= BIT(24),
710 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON		= BIT(25),
711 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON		= BIT(26),
712 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM		= BIT(27),
713 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM		= BIT(28),
714 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM		= BIT(29),
715 };
716 
717 enum htt_rx_mgmt_pkt_filter_tlv_flags1 {
718 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC		= BIT(0),
719 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC		= BIT(1),
720 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC		= BIT(2),
721 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH		= BIT(3),
722 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH		= BIT(4),
723 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH		= BIT(5),
724 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH		= BIT(6),
725 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH		= BIT(7),
726 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH		= BIT(8),
727 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION		= BIT(9),
728 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION		= BIT(10),
729 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION		= BIT(11),
730 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK	= BIT(12),
731 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK	= BIT(13),
732 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK	= BIT(14),
733 	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15	= BIT(15),
734 	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15	= BIT(16),
735 	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15	= BIT(17),
736 };
737 
738 enum htt_rx_ctrl_pkt_filter_tlv_flags2 {
739 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1	= BIT(0),
740 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1	= BIT(1),
741 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1	= BIT(2),
742 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2	= BIT(3),
743 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2	= BIT(4),
744 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2	= BIT(5),
745 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER	= BIT(6),
746 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER	= BIT(7),
747 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER	= BIT(8),
748 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4	= BIT(9),
749 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4	= BIT(10),
750 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4	= BIT(11),
751 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL	= BIT(12),
752 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL	= BIT(13),
753 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL	= BIT(14),
754 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP	= BIT(15),
755 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP	= BIT(16),
756 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP	= BIT(17),
757 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT	= BIT(18),
758 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT	= BIT(19),
759 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT	= BIT(20),
760 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER	= BIT(21),
761 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER	= BIT(22),
762 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER	= BIT(23),
763 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR		= BIT(24),
764 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR		= BIT(25),
765 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR		= BIT(26),
766 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA			= BIT(27),
767 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA			= BIT(28),
768 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA			= BIT(29),
769 };
770 
771 enum htt_rx_ctrl_pkt_filter_tlv_flags3 {
772 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL		= BIT(0),
773 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL		= BIT(1),
774 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL		= BIT(2),
775 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS		= BIT(3),
776 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS		= BIT(4),
777 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS		= BIT(5),
778 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS		= BIT(6),
779 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS		= BIT(7),
780 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS		= BIT(8),
781 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK		= BIT(9),
782 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK		= BIT(10),
783 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK		= BIT(11),
784 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND		= BIT(12),
785 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND		= BIT(13),
786 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND		= BIT(14),
787 	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK		= BIT(15),
788 	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK		= BIT(16),
789 	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK		= BIT(17),
790 };
791 
792 enum htt_rx_data_pkt_filter_tlv_flasg3 {
793 	HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST	= BIT(18),
794 	HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST	= BIT(19),
795 	HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST	= BIT(20),
796 	HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST	= BIT(21),
797 	HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST	= BIT(22),
798 	HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST	= BIT(23),
799 	HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA	= BIT(24),
800 	HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA	= BIT(25),
801 	HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA	= BIT(26),
802 };
803 
804 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \
805 	(HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
806 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
807 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
808 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
809 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
810 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
811 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
812 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
813 	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
814 
815 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \
816 	(HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
817 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
818 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
819 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
820 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
821 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
822 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
823 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
824 	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
825 
826 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \
827 	(HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
828 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
829 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
830 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
831 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
832 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
833 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
834 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
835 	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
836 
837 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
838 				     | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
839 				     | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
840 				     | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
841 				     | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
842 
843 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
844 				     | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
845 				     | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
846 				     | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
847 				     | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
848 
849 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
850 				     | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
851 				     | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
852 				     | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
853 				     | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
854 
855 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
856 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
857 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
858 
859 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
860 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
861 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
862 
863 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
864 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
865 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
866 
867 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
868 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
869 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
870 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
871 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
872 				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
873 
874 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
875 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
876 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
877 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
878 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
879 				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
880 
881 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
882 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
883 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
884 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
885 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
886 				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
887 
888 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
889 				     | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
890 				     | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
891 
892 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
893 				     | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
894 				     | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
895 
896 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
897 				     | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
898 				     | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
899 
900 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \
901 		(HTT_RX_FP_MGMT_FILTER_FLAGS0 | \
902 		HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
903 
904 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \
905 		(HTT_RX_MO_MGMT_FILTER_FLAGS0 | \
906 		HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
907 
908 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \
909 		(HTT_RX_FP_MGMT_FILTER_FLAGS1 | \
910 		HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
911 
912 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \
913 		(HTT_RX_MO_MGMT_FILTER_FLAGS1 | \
914 		HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
915 
916 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \
917 		(HTT_RX_FP_CTRL_FILTER_FLASG2 | \
918 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
919 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
920 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
921 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
922 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
923 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
924 		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
925 
926 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \
927 		(HTT_RX_MO_CTRL_FILTER_FLASG2 | \
928 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
929 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
930 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
931 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
932 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
933 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
934 		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
935 
936 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3
937 
938 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3
939 
940 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3
941 
942 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3
943 
944 #define HTT_RX_MON_FILTER_TLV_FLAGS \
945 		(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
946 		HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
947 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
948 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
949 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
950 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
951 
952 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \
953 		(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
954 		HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
955 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
956 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
957 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
958 		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
959 
960 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \
961 		(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
962 		HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
963 		HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
964 		HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
965 		HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
966 		HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
967 		HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
968 		HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
969 
970 struct htt_rx_ring_selection_cfg_cmd {
971 	u32 info0;
972 	u32 info1;
973 	u32 pkt_type_en_flags0;
974 	u32 pkt_type_en_flags1;
975 	u32 pkt_type_en_flags2;
976 	u32 pkt_type_en_flags3;
977 	u32 rx_filter_tlv;
978 } __packed;
979 
980 struct htt_rx_ring_tlv_filter {
981 	u32 rx_filter; /* see htt_rx_filter_tlv_flags */
982 	u32 pkt_filter_flags0; /* MGMT */
983 	u32 pkt_filter_flags1; /* MGMT */
984 	u32 pkt_filter_flags2; /* CTRL */
985 	u32 pkt_filter_flags3; /* DATA */
986 };
987 
988 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE	GENMASK(7, 0)
989 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID	GENMASK(15, 8)
990 
991 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE			BIT(0)
992 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END		BIT(1)
993 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END	BIT(2)
994 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING		GENMASK(10, 3)
995 
996 /**
997  * Enumeration for full monitor mode destination ring select
998  * 0 - REO destination ring select
999  * 1 - FW destination ring select
1000  * 2 - SW destination ring select
1001  * 3 - Release destination ring select
1002  */
1003 enum htt_rx_full_mon_release_ring {
1004 	HTT_RX_MON_RING_REO,
1005 	HTT_RX_MON_RING_FW,
1006 	HTT_RX_MON_RING_SW,
1007 	HTT_RX_MON_RING_RELEASE,
1008 };
1009 
1010 struct htt_rx_full_monitor_mode_cfg_cmd {
1011 	u32 info0;
1012 	u32 cfg;
1013 } __packed;
1014 
1015 /* HTT message target->host */
1016 
1017 enum htt_t2h_msg_type {
1018 	HTT_T2H_MSG_TYPE_VERSION_CONF,
1019 	HTT_T2H_MSG_TYPE_PEER_MAP	= 0x3,
1020 	HTT_T2H_MSG_TYPE_PEER_UNMAP	= 0x4,
1021 	HTT_T2H_MSG_TYPE_RX_ADDBA	= 0x5,
1022 	HTT_T2H_MSG_TYPE_PKTLOG		= 0x8,
1023 	HTT_T2H_MSG_TYPE_SEC_IND	= 0xb,
1024 	HTT_T2H_MSG_TYPE_PEER_MAP2	= 0x1e,
1025 	HTT_T2H_MSG_TYPE_PEER_UNMAP2	= 0x1f,
1026 	HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
1027 	HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
1028 	HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
1029 };
1030 
1031 #define HTT_TARGET_VERSION_MAJOR 3
1032 
1033 #define HTT_T2H_MSG_TYPE		GENMASK(7, 0)
1034 #define HTT_T2H_VERSION_CONF_MINOR	GENMASK(15, 8)
1035 #define HTT_T2H_VERSION_CONF_MAJOR	GENMASK(23, 16)
1036 
1037 struct htt_t2h_version_conf_msg {
1038 	u32 version;
1039 } __packed;
1040 
1041 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID	GENMASK(15, 8)
1042 #define HTT_T2H_PEER_MAP_INFO_PEER_ID	GENMASK(31, 16)
1043 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16	GENMASK(15, 0)
1044 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID	GENMASK(31, 16)
1045 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL	GENMASK(15, 0)
1046 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M	BIT(16)
1047 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S	16
1048 
1049 struct htt_t2h_peer_map_event {
1050 	u32 info;
1051 	u32 mac_addr_l32;
1052 	u32 info1;
1053 	u32 info2;
1054 } __packed;
1055 
1056 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID	HTT_T2H_PEER_MAP_INFO_VDEV_ID
1057 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID	HTT_T2H_PEER_MAP_INFO_PEER_ID
1058 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \
1059 					HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16
1060 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M
1061 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S
1062 
1063 struct htt_t2h_peer_unmap_event {
1064 	u32 info;
1065 	u32 mac_addr_l32;
1066 	u32 info1;
1067 } __packed;
1068 
1069 struct htt_resp_msg {
1070 	union {
1071 		struct htt_t2h_version_conf_msg version_msg;
1072 		struct htt_t2h_peer_map_event peer_map_ev;
1073 		struct htt_t2h_peer_unmap_event peer_unmap_ev;
1074 	};
1075 } __packed;
1076 
1077 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8)
1078 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16)
1079 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24)
1080 
1081 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0)
1082 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16)
1083 
1084 #define HTT_BACKPRESSURE_UMAC_RING_TYPE	0
1085 #define HTT_BACKPRESSURE_LMAC_RING_TYPE	1
1086 
1087 enum htt_backpressure_umac_ringid {
1088 	HTT_SW_RING_IDX_REO_REO2SW1_RING,
1089 	HTT_SW_RING_IDX_REO_REO2SW2_RING,
1090 	HTT_SW_RING_IDX_REO_REO2SW3_RING,
1091 	HTT_SW_RING_IDX_REO_REO2SW4_RING,
1092 	HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING,
1093 	HTT_SW_RING_IDX_REO_REO2TCL_RING,
1094 	HTT_SW_RING_IDX_REO_REO2FW_RING,
1095 	HTT_SW_RING_IDX_REO_REO_RELEASE_RING,
1096 	HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING,
1097 	HTT_SW_RING_IDX_TCL_TCL2TQM_RING,
1098 	HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING,
1099 	HTT_SW_RING_IDX_WBM_REO_RELEASE_RING,
1100 	HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING,
1101 	HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING,
1102 	HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING,
1103 	HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING,
1104 	HTT_SW_RING_IDX_REO_REO_CMD_RING,
1105 	HTT_SW_RING_IDX_REO_REO_STATUS_RING,
1106 	HTT_SW_UMAC_RING_IDX_MAX,
1107 };
1108 
1109 enum htt_backpressure_lmac_ringid {
1110 	HTT_SW_RING_IDX_FW2RXDMA_BUF_RING,
1111 	HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING,
1112 	HTT_SW_RING_IDX_FW2RXDMA_LINK_RING,
1113 	HTT_SW_RING_IDX_SW2RXDMA_BUF_RING,
1114 	HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING,
1115 	HTT_SW_RING_IDX_RXDMA2FW_RING,
1116 	HTT_SW_RING_IDX_RXDMA2SW_RING,
1117 	HTT_SW_RING_IDX_RXDMA2RELEASE_RING,
1118 	HTT_SW_RING_IDX_RXDMA2REO_RING,
1119 	HTT_SW_RING_IDX_MONITOR_STATUS_RING,
1120 	HTT_SW_RING_IDX_MONITOR_BUF_RING,
1121 	HTT_SW_RING_IDX_MONITOR_DESC_RING,
1122 	HTT_SW_RING_IDX_MONITOR_DEST_RING,
1123 	HTT_SW_LMAC_RING_IDX_MAX,
1124 };
1125 
1126 /* ppdu stats
1127  *
1128  * @details
1129  * The following field definitions describe the format of the HTT target
1130  * to host ppdu stats indication message.
1131  *
1132  *
1133  * |31                         16|15   12|11   10|9      8|7            0 |
1134  * |----------------------------------------------------------------------|
1135  * |    payload_size             | rsvd  |pdev_id|mac_id  |    msg type   |
1136  * |----------------------------------------------------------------------|
1137  * |                          ppdu_id                                     |
1138  * |----------------------------------------------------------------------|
1139  * |                        Timestamp in us                               |
1140  * |----------------------------------------------------------------------|
1141  * |                          reserved                                    |
1142  * |----------------------------------------------------------------------|
1143  * |                    type-specific stats info                          |
1144  * |                     (see htt_ppdu_stats.h)                           |
1145  * |----------------------------------------------------------------------|
1146  * Header fields:
1147  *  - MSG_TYPE
1148  *    Bits 7:0
1149  *    Purpose: Identifies this is a PPDU STATS indication
1150  *             message.
1151  *    Value: 0x1d
1152  *  - mac_id
1153  *    Bits 9:8
1154  *    Purpose: mac_id of this ppdu_id
1155  *    Value: 0-3
1156  *  - pdev_id
1157  *    Bits 11:10
1158  *    Purpose: pdev_id of this ppdu_id
1159  *    Value: 0-3
1160  *     0 (for rings at SOC level),
1161  *     1/2/3 PDEV -> 0/1/2
1162  *  - payload_size
1163  *    Bits 31:16
1164  *    Purpose: total tlv size
1165  *    Value: payload_size in bytes
1166  */
1167 
1168 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
1169 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
1170 
1171 struct ath11k_htt_ppdu_stats_msg {
1172 	u32 info;
1173 	u32 ppdu_id;
1174 	u32 timestamp;
1175 	u32 rsvd;
1176 	u8 data[];
1177 } __packed;
1178 
1179 struct htt_tlv {
1180 	u32 header;
1181 	u8 value[];
1182 } __packed;
1183 
1184 #define HTT_TLV_TAG			GENMASK(11, 0)
1185 #define HTT_TLV_LEN			GENMASK(23, 12)
1186 
1187 enum HTT_PPDU_STATS_BW {
1188 	HTT_PPDU_STATS_BANDWIDTH_5MHZ   = 0,
1189 	HTT_PPDU_STATS_BANDWIDTH_10MHZ  = 1,
1190 	HTT_PPDU_STATS_BANDWIDTH_20MHZ  = 2,
1191 	HTT_PPDU_STATS_BANDWIDTH_40MHZ  = 3,
1192 	HTT_PPDU_STATS_BANDWIDTH_80MHZ  = 4,
1193 	HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
1194 	HTT_PPDU_STATS_BANDWIDTH_DYN    = 6,
1195 };
1196 
1197 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M	GENMASK(7, 0)
1198 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M	GENMASK(15, 8)
1199 /* bw - HTT_PPDU_STATS_BW */
1200 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M		GENMASK(19, 16)
1201 
1202 struct htt_ppdu_stats_common {
1203 	u32 ppdu_id;
1204 	u16 sched_cmdid;
1205 	u8 ring_id;
1206 	u8 num_users;
1207 	u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/
1208 	u32 chain_mask;
1209 	u32 fes_duration_us; /* frame exchange sequence */
1210 	u32 ppdu_sch_eval_start_tstmp_us;
1211 	u32 ppdu_sch_end_tstmp_us;
1212 	u32 ppdu_start_tstmp_us;
1213 	/* BIT [15 :  0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
1214 	 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
1215 	 */
1216 	u16 phy_mode;
1217 	u16 bw_mhz;
1218 } __packed;
1219 
1220 enum htt_ppdu_stats_gi {
1221 	HTT_PPDU_STATS_SGI_0_8_US,
1222 	HTT_PPDU_STATS_SGI_0_4_US,
1223 	HTT_PPDU_STATS_SGI_1_6_US,
1224 	HTT_PPDU_STATS_SGI_3_2_US,
1225 };
1226 
1227 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M	GENMASK(3, 0)
1228 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M	GENMASK(11, 4)
1229 
1230 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M	BIT(0)
1231 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M	GENMASK(5, 1)
1232 
1233 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M	GENMASK(1, 0)
1234 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M		BIT(2)
1235 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M		BIT(3)
1236 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M		GENMASK(7, 4)
1237 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M		GENMASK(11, 8)
1238 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M		GENMASK(15, 12)
1239 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M		GENMASK(19, 16)
1240 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M	GENMASK(23, 20)
1241 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M		GENMASK(27, 24)
1242 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M		BIT(28)
1243 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M		BIT(29)
1244 
1245 #define HTT_USR_RATE_PREAMBLE(_val) \
1246 		FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val)
1247 #define HTT_USR_RATE_BW(_val) \
1248 		FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val)
1249 #define HTT_USR_RATE_NSS(_val) \
1250 		FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val)
1251 #define HTT_USR_RATE_MCS(_val) \
1252 		FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val)
1253 #define HTT_USR_RATE_GI(_val) \
1254 		FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val)
1255 #define HTT_USR_RATE_DCM(_val) \
1256 		FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val)
1257 
1258 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M		GENMASK(1, 0)
1259 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M		BIT(2)
1260 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M		BIT(3)
1261 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M		GENMASK(7, 4)
1262 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M		GENMASK(11, 8)
1263 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M		GENMASK(15, 12)
1264 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M		GENMASK(19, 16)
1265 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M		GENMASK(23, 20)
1266 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M		GENMASK(27, 24)
1267 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M		BIT(28)
1268 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M		BIT(29)
1269 
1270 struct htt_ppdu_stats_user_rate {
1271 	u8 tid_num;
1272 	u8 reserved0;
1273 	u16 sw_peer_id;
1274 	u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/
1275 	u16 ru_end;
1276 	u16 ru_start;
1277 	u16 resp_ru_end;
1278 	u16 resp_ru_start;
1279 	u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */
1280 	u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */
1281 	/* Note: resp_rate_info is only valid for if resp_type is UL */
1282 	u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */
1283 } __packed;
1284 
1285 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M		GENMASK(7, 0)
1286 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M		BIT(8)
1287 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M	GENMASK(10, 9)
1288 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M		GENMASK(13, 11)
1289 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M		BIT(14)
1290 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M		GENMASK(31, 16)
1291 
1292 #define HTT_TX_INFO_IS_AMSDU(_flags) \
1293 			FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags)
1294 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \
1295 			FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags)
1296 #define HTT_TX_INFO_RATECODE(_flags) \
1297 			FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags)
1298 #define HTT_TX_INFO_PEERID(_flags) \
1299 			FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags)
1300 
1301 struct htt_tx_ppdu_stats_info {
1302 	struct htt_tlv tlv_hdr;
1303 	u32 tx_success_bytes;
1304 	u32 tx_retry_bytes;
1305 	u32 tx_failed_bytes;
1306 	u32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */
1307 	u16 tx_success_msdus;
1308 	u16 tx_retry_msdus;
1309 	u16 tx_failed_msdus;
1310 	u16 tx_duration; /* united in us */
1311 } __packed;
1312 
1313 enum  htt_ppdu_stats_usr_compln_status {
1314 	HTT_PPDU_STATS_USER_STATUS_OK,
1315 	HTT_PPDU_STATS_USER_STATUS_FILTERED,
1316 	HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,
1317 	HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,
1318 	HTT_PPDU_STATS_USER_STATUS_ABORT,
1319 };
1320 
1321 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M	GENMASK(3, 0)
1322 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M	GENMASK(7, 4)
1323 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M		BIT(8)
1324 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M		GENMASK(12, 9)
1325 
1326 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \
1327 	    FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val)
1328 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \
1329 	    FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val)
1330 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \
1331 	    FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val)
1332 
1333 struct htt_ppdu_stats_usr_cmpltn_cmn {
1334 	u8 status;
1335 	u8 tid_num;
1336 	u16 sw_peer_id;
1337 	/* RSSI value of last ack packet (units = dB above noise floor) */
1338 	u32 ack_rssi;
1339 	u16 mpdu_tried;
1340 	u16 mpdu_success;
1341 	u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/
1342 } __packed;
1343 
1344 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M	GENMASK(8, 0)
1345 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M	GENMASK(24, 9)
1346 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM	GENMASK(31, 25)
1347 
1348 #define HTT_PPDU_STATS_NON_QOS_TID	16
1349 
1350 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {
1351 	u32 ppdu_id;
1352 	u16 sw_peer_id;
1353 	u16 reserved0;
1354 	u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */
1355 	u16 current_seq;
1356 	u16 start_seq;
1357 	u32 success_bytes;
1358 } __packed;
1359 
1360 struct htt_ppdu_stats_usr_cmn_array {
1361 	struct htt_tlv tlv_hdr;
1362 	u32 num_ppdu_stats;
1363 	/* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info
1364 	 * elements.
1365 	 * tx_ppdu_stats_info is variable length, with length =
1366 	 *     number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info)
1367 	 */
1368 	struct htt_tx_ppdu_stats_info tx_ppdu_info[];
1369 } __packed;
1370 
1371 struct htt_ppdu_user_stats {
1372 	u16 peer_id;
1373 	u32 tlv_flags;
1374 	bool is_valid_peer_id;
1375 	struct htt_ppdu_stats_user_rate rate;
1376 	struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;
1377 	struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;
1378 };
1379 
1380 #define HTT_PPDU_STATS_MAX_USERS	8
1381 #define HTT_PPDU_DESC_MAX_DEPTH	16
1382 
1383 struct htt_ppdu_stats {
1384 	struct htt_ppdu_stats_common common;
1385 	struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];
1386 };
1387 
1388 struct htt_ppdu_stats_info {
1389 	u32 ppdu_id;
1390 	struct htt_ppdu_stats ppdu_stats;
1391 	struct list_head list;
1392 };
1393 
1394 /**
1395  * @brief target -> host packet log message
1396  *
1397  * @details
1398  * The following field definitions describe the format of the packet log
1399  * message sent from the target to the host.
1400  * The message consists of a 4-octet header,followed by a variable number
1401  * of 32-bit character values.
1402  *
1403  * |31                         16|15  12|11   10|9    8|7            0|
1404  * |------------------------------------------------------------------|
1405  * |        payload_size         | rsvd |pdev_id|mac_id|   msg type   |
1406  * |------------------------------------------------------------------|
1407  * |                              payload                             |
1408  * |------------------------------------------------------------------|
1409  *   - MSG_TYPE
1410  *     Bits 7:0
1411  *     Purpose: identifies this as a pktlog message
1412  *     Value: HTT_T2H_MSG_TYPE_PKTLOG
1413  *   - mac_id
1414  *     Bits 9:8
1415  *     Purpose: identifies which MAC/PHY instance generated this pktlog info
1416  *     Value: 0-3
1417  *   - pdev_id
1418  *     Bits 11:10
1419  *     Purpose: pdev_id
1420  *     Value: 0-3
1421  *     0 (for rings at SOC level),
1422  *     1/2/3 PDEV -> 0/1/2
1423  *   - payload_size
1424  *     Bits 31:16
1425  *     Purpose: explicitly specify the payload size
1426  *     Value: payload size in bytes (payload size is a multiple of 4 bytes)
1427  */
1428 struct htt_pktlog_msg {
1429 	u32 hdr;
1430 	u8 payload[];
1431 };
1432 
1433 /**
1434  * @brief host -> target FW extended statistics retrieve
1435  *
1436  * @details
1437  * The following field definitions describe the format of the HTT host
1438  * to target FW extended stats retrieve message.
1439  * The message specifies the type of stats the host wants to retrieve.
1440  *
1441  * |31          24|23          16|15           8|7            0|
1442  * |-----------------------------------------------------------|
1443  * |   reserved   | stats type   |   pdev_mask  |   msg type   |
1444  * |-----------------------------------------------------------|
1445  * |                   config param [0]                        |
1446  * |-----------------------------------------------------------|
1447  * |                   config param [1]                        |
1448  * |-----------------------------------------------------------|
1449  * |                   config param [2]                        |
1450  * |-----------------------------------------------------------|
1451  * |                   config param [3]                        |
1452  * |-----------------------------------------------------------|
1453  * |                         reserved                          |
1454  * |-----------------------------------------------------------|
1455  * |                        cookie LSBs                        |
1456  * |-----------------------------------------------------------|
1457  * |                        cookie MSBs                        |
1458  * |-----------------------------------------------------------|
1459  * Header fields:
1460  *  - MSG_TYPE
1461  *    Bits 7:0
1462  *    Purpose: identifies this is a extended stats upload request message
1463  *    Value: 0x10
1464  *  - PDEV_MASK
1465  *    Bits 8:15
1466  *    Purpose: identifies the mask of PDEVs to retrieve stats from
1467  *    Value: This is a overloaded field, refer to usage and interpretation of
1468  *           PDEV in interface document.
1469  *           Bit   8    :  Reserved for SOC stats
1470  *           Bit 9 - 15 :  Indicates PDEV_MASK in DBDC
1471  *                         Indicates MACID_MASK in DBS
1472  *  - STATS_TYPE
1473  *    Bits 23:16
1474  *    Purpose: identifies which FW statistics to upload
1475  *    Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
1476  *  - Reserved
1477  *    Bits 31:24
1478  *  - CONFIG_PARAM [0]
1479  *    Bits 31:0
1480  *    Purpose: give an opaque configuration value to the specified stats type
1481  *    Value: stats-type specific configuration value
1482  *           Refer to htt_stats.h for interpretation for each stats sub_type
1483  *  - CONFIG_PARAM [1]
1484  *    Bits 31:0
1485  *    Purpose: give an opaque configuration value to the specified stats type
1486  *    Value: stats-type specific configuration value
1487  *           Refer to htt_stats.h for interpretation for each stats sub_type
1488  *  - CONFIG_PARAM [2]
1489  *    Bits 31:0
1490  *    Purpose: give an opaque configuration value to the specified stats type
1491  *    Value: stats-type specific configuration value
1492  *           Refer to htt_stats.h for interpretation for each stats sub_type
1493  *  - CONFIG_PARAM [3]
1494  *    Bits 31:0
1495  *    Purpose: give an opaque configuration value to the specified stats type
1496  *    Value: stats-type specific configuration value
1497  *           Refer to htt_stats.h for interpretation for each stats sub_type
1498  *  - Reserved [31:0] for future use.
1499  *  - COOKIE_LSBS
1500  *    Bits 31:0
1501  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1502  *        message with its preceding host->target stats request message.
1503  *    Value: LSBs of the opaque cookie specified by the host-side requestor
1504  *  - COOKIE_MSBS
1505  *    Bits 31:0
1506  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1507  *        message with its preceding host->target stats request message.
1508  *    Value: MSBs of the opaque cookie specified by the host-side requestor
1509  */
1510 
1511 struct htt_ext_stats_cfg_hdr {
1512 	u8 msg_type;
1513 	u8 pdev_mask;
1514 	u8 stats_type;
1515 	u8 reserved;
1516 } __packed;
1517 
1518 struct htt_ext_stats_cfg_cmd {
1519 	struct htt_ext_stats_cfg_hdr hdr;
1520 	u32 cfg_param0;
1521 	u32 cfg_param1;
1522 	u32 cfg_param2;
1523 	u32 cfg_param3;
1524 	u32 reserved;
1525 	u32 cookie_lsb;
1526 	u32 cookie_msb;
1527 } __packed;
1528 
1529 /* htt stats config default params */
1530 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0
1531 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff
1532 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff
1533 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff
1534 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff
1535 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff
1536 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00
1537 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00
1538 
1539 /* HTT_DBG_EXT_STATS_PEER_INFO
1540  * PARAMS:
1541  * @config_param0:
1542  *  [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
1543  *  [Bit15 : Bit 1] htt_peer_stats_req_mode_t
1544  *  [Bit31 : Bit16] sw_peer_id
1545  * @config_param1:
1546  *  peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)
1547  *   0 bit htt_peer_stats_cmn_tlv
1548  *   1 bit htt_peer_details_tlv
1549  *   2 bit htt_tx_peer_rate_stats_tlv
1550  *   3 bit htt_rx_peer_rate_stats_tlv
1551  *   4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
1552  *   5 bit htt_rx_tid_stats_tlv
1553  *   6 bit htt_msdu_flow_stats_tlv
1554  * @config_param2: [Bit31 : Bit0] mac_addr31to0
1555  * @config_param3: [Bit15 : Bit0] mac_addr47to32
1556  *                [Bit31 : Bit16] reserved
1557  */
1558 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
1559 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f
1560 
1561 /* Used to set different configs to the specified stats type.*/
1562 struct htt_ext_stats_cfg_params {
1563 	u32 cfg0;
1564 	u32 cfg1;
1565 	u32 cfg2;
1566 	u32 cfg3;
1567 };
1568 
1569 /**
1570  * @brief target -> host extended statistics upload
1571  *
1572  * @details
1573  * The following field definitions describe the format of the HTT target
1574  * to host stats upload confirmation message.
1575  * The message contains a cookie echoed from the HTT host->target stats
1576  * upload request, which identifies which request the confirmation is
1577  * for, and a single stats can span over multiple HTT stats indication
1578  * due to the HTT message size limitation so every HTT ext stats indication
1579  * will have tag-length-value stats information elements.
1580  * The tag-length header for each HTT stats IND message also includes a
1581  * status field, to indicate whether the request for the stat type in
1582  * question was fully met, partially met, unable to be met, or invalid
1583  * (if the stat type in question is disabled in the target).
1584  * A Done bit 1's indicate the end of the of stats info elements.
1585  *
1586  *
1587  * |31                         16|15    12|11|10 8|7   5|4       0|
1588  * |--------------------------------------------------------------|
1589  * |                   reserved                   |    msg type   |
1590  * |--------------------------------------------------------------|
1591  * |                         cookie LSBs                          |
1592  * |--------------------------------------------------------------|
1593  * |                         cookie MSBs                          |
1594  * |--------------------------------------------------------------|
1595  * |      stats entry length     | rsvd   | D|  S |   stat type   |
1596  * |--------------------------------------------------------------|
1597  * |                   type-specific stats info                   |
1598  * |                      (see htt_stats.h)                       |
1599  * |--------------------------------------------------------------|
1600  * Header fields:
1601  *  - MSG_TYPE
1602  *    Bits 7:0
1603  *    Purpose: Identifies this is a extended statistics upload confirmation
1604  *             message.
1605  *    Value: 0x1c
1606  *  - COOKIE_LSBS
1607  *    Bits 31:0
1608  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1609  *        message with its preceding host->target stats request message.
1610  *    Value: LSBs of the opaque cookie specified by the host-side requestor
1611  *  - COOKIE_MSBS
1612  *    Bits 31:0
1613  *    Purpose: Provide a mechanism to match a target->host stats confirmation
1614  *        message with its preceding host->target stats request message.
1615  *    Value: MSBs of the opaque cookie specified by the host-side requestor
1616  *
1617  * Stats Information Element tag-length header fields:
1618  *  - STAT_TYPE
1619  *    Bits 7:0
1620  *    Purpose: identifies the type of statistics info held in the
1621  *        following information element
1622  *    Value: htt_dbg_ext_stats_type
1623  *  - STATUS
1624  *    Bits 10:8
1625  *    Purpose: indicate whether the requested stats are present
1626  *    Value: htt_dbg_ext_stats_status
1627  *  - DONE
1628  *    Bits 11
1629  *    Purpose:
1630  *        Indicates the completion of the stats entry, this will be the last
1631  *        stats conf HTT segment for the requested stats type.
1632  *    Value:
1633  *        0 -> the stats retrieval is ongoing
1634  *        1 -> the stats retrieval is complete
1635  *  - LENGTH
1636  *    Bits 31:16
1637  *    Purpose: indicate the stats information size
1638  *    Value: This field specifies the number of bytes of stats information
1639  *       that follows the element tag-length header.
1640  *       It is expected but not required that this length is a multiple of
1641  *       4 bytes.
1642  */
1643 
1644 #define HTT_T2H_EXT_STATS_INFO1_DONE	BIT(11)
1645 #define HTT_T2H_EXT_STATS_INFO1_LENGTH   GENMASK(31, 16)
1646 
1647 struct ath11k_htt_extd_stats_msg {
1648 	u32 info0;
1649 	u64 cookie;
1650 	u32 info1;
1651 	u8 data[];
1652 } __packed;
1653 
1654 #define	HTT_MAC_ADDR_L32_0	GENMASK(7, 0)
1655 #define	HTT_MAC_ADDR_L32_1	GENMASK(15, 8)
1656 #define	HTT_MAC_ADDR_L32_2	GENMASK(23, 16)
1657 #define	HTT_MAC_ADDR_L32_3	GENMASK(31, 24)
1658 #define	HTT_MAC_ADDR_H16_0	GENMASK(7, 0)
1659 #define	HTT_MAC_ADDR_H16_1	GENMASK(15, 8)
1660 
1661 struct htt_mac_addr {
1662 	u32 mac_addr_l32;
1663 	u32 mac_addr_h16;
1664 };
1665 
ath11k_dp_get_mac_addr(u32 addr_l32,u16 addr_h16,u8 * addr)1666 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr)
1667 {
1668 	if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
1669 		addr_l32 = swab32(addr_l32);
1670 		addr_h16 = swab16(addr_h16);
1671 	}
1672 
1673 	memcpy(addr, &addr_l32, 4);
1674 	memcpy(addr + 4, &addr_h16, ETH_ALEN - 4);
1675 }
1676 
1677 int ath11k_dp_service_srng(struct ath11k_base *ab,
1678 			   struct ath11k_ext_irq_grp *irq_grp,
1679 			   int budget);
1680 int ath11k_dp_htt_connect(struct ath11k_dp *dp);
1681 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif);
1682 void ath11k_dp_free(struct ath11k_base *ab);
1683 int ath11k_dp_alloc(struct ath11k_base *ab);
1684 int ath11k_dp_pdev_alloc(struct ath11k_base *ab);
1685 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab);
1686 void ath11k_dp_pdev_free(struct ath11k_base *ab);
1687 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
1688 				int mac_id, enum hal_ring_type ring_type);
1689 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr);
1690 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr);
1691 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring);
1692 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring,
1693 			 enum hal_ring_type type, int ring_num,
1694 			 int mac_id, int num_entries);
1695 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab,
1696 				 struct dp_link_desc_bank *desc_bank,
1697 				 u32 ring_type, struct dp_srng *ring);
1698 int ath11k_dp_link_desc_setup(struct ath11k_base *ab,
1699 			      struct dp_link_desc_bank *link_desc_banks,
1700 			      u32 ring_type, struct hal_srng *srng,
1701 			      u32 n_link_desc);
1702 void ath11k_dp_shadow_start_timer(struct ath11k_base *ab,
1703 				  struct hal_srng	*srng,
1704 				  struct ath11k_hp_update_timer *update_timer);
1705 void ath11k_dp_shadow_stop_timer(struct ath11k_base *ab,
1706 				 struct ath11k_hp_update_timer *update_timer);
1707 void ath11k_dp_shadow_init_timer(struct ath11k_base *ab,
1708 				 struct ath11k_hp_update_timer *update_timer,
1709 				 u32 interval, u32 ring_id);
1710 void ath11k_dp_stop_shadow_timers(struct ath11k_base *ab);
1711 
1712 #endif
1713