1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3  *
4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5  *
6  ******************************************************************************/
7 #ifndef __HAL_COMMON_REG_H__
8 #define __HAL_COMMON_REG_H__
9 
10 
11 #define MAC_ADDR_LEN				6
12 
13 #define HAL_NAV_UPPER_UNIT		128		/*  micro-second */
14 
15 /*  8188E PKT_BUFF_ACCESS_CTRL value */
16 #define TXPKT_BUF_SELECT				0x69
17 #define RXPKT_BUF_SELECT				0xA5
18 #define DISABLE_TRXPKT_BUF_ACCESS		0x0
19 
20 /*  */
21 /*  */
22 /*  */
23 
24 /*  */
25 /*  */
26 /* 	0x0000h ~ 0x00FFh	System Configuration */
27 /*  */
28 /*  */
29 #define REG_SYS_ISO_CTRL				0x0000
30 #define REG_SYS_FUNC_EN				0x0002
31 #define REG_APS_FSMCO					0x0004
32 #define REG_SYS_CLKR					0x0008
33 #define REG_9346CR						0x000A
34 #define REG_SYS_EEPROM_CTRL			0x000A
35 #define REG_EE_VPD						0x000C
36 #define REG_AFE_MISC					0x0010
37 #define REG_SPS0_CTRL					0x0011
38 #define REG_SPS0_CTRL_6					0x0016
39 #define REG_POWER_OFF_IN_PROCESS		0x0017
40 #define REG_SPS_OCP_CFG				0x0018
41 #define REG_RSV_CTRL					0x001C
42 #define REG_RF_CTRL						0x001F
43 #define REG_LDOA15_CTRL				0x0020
44 #define REG_LDOV12D_CTRL				0x0021
45 #define REG_LDOHCI12_CTRL				0x0022
46 #define REG_LPLDO_CTRL					0x0023
47 #define REG_AFE_XTAL_CTRL				0x0024
48 #define REG_AFE_LDO_CTRL				0x0027 /*  1.5v for 8188EE test chip, 1.4v for MP chip */
49 #define REG_AFE_PLL_CTRL				0x0028
50 #define REG_MAC_PHY_CTRL				0x002c /* for 92d, DMDP, SMSP, DMSP contrl */
51 #define REG_APE_PLL_CTRL_EXT			0x002c
52 #define REG_EFUSE_CTRL					0x0030
53 #define REG_EFUSE_TEST					0x0034
54 #define REG_PWR_DATA					0x0038
55 #define REG_CAL_TIMER					0x003C
56 #define REG_ACLK_MON					0x003E
57 #define REG_GPIO_MUXCFG				0x0040
58 #define REG_GPIO_IO_SEL					0x0042
59 #define REG_MAC_PINMUX_CFG			0x0043
60 #define REG_GPIO_PIN_CTRL				0x0044
61 #define REG_GPIO_INTM					0x0048
62 #define REG_LEDCFG0						0x004C
63 #define REG_LEDCFG1						0x004D
64 #define REG_LEDCFG2						0x004E
65 #define REG_LEDCFG3						0x004F
66 #define REG_FSIMR						0x0050
67 #define REG_FSISR						0x0054
68 #define REG_HSIMR						0x0058
69 #define REG_HSISR						0x005c
70 #define REG_GPIO_PIN_CTRL_2			0x0060 /*  RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
71 #define REG_GPIO_IO_SEL_2				0x0062 /*  RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
72 #define REG_MULTI_FUNC_CTRL			0x0068 /*  RTL8723 WIFI/BT/GPS Multi-Function control source. */
73 #define REG_GSSR						0x006c
74 #define REG_AFE_XTAL_CTRL_EXT			0x0078 /* RTL8188E */
75 #define REG_MCUFWDL					0x0080
76 #define REG_MCUTSTCFG					0x0084
77 #define REG_FDHM0						0x0088
78 #define REG_EFUSE_ACCESS				0x00CF	/*  Efuse access protection for RTL8723 */
79 #define REG_BIST_SCAN					0x00D0
80 #define REG_BIST_RPT					0x00D4
81 #define REG_BIST_ROM_RPT				0x00D8
82 #define REG_USB_SIE_INTF				0x00E0
83 #define REG_PCIE_MIO_INTF				0x00E4
84 #define REG_PCIE_MIO_INTD				0x00E8
85 #define REG_HPON_FSM					0x00EC
86 #define REG_SYS_CFG						0x00F0
87 #define REG_GPIO_OUTSTS				0x00F4	/*  For RTL8723 only. */
88 #define REG_TYPE_ID						0x00FC
89 
90 /*  */
91 /*  2010/12/29 MH Add for 92D */
92 /*  */
93 #define REG_MAC_PHY_CTRL_NORMAL		0x00f8
94 
95 
96 /*  */
97 /*  */
98 /* 	0x0100h ~ 0x01FFh	MACTOP General Configuration */
99 /*  */
100 /*  */
101 #define REG_CR							0x0100
102 #define REG_PBP							0x0104
103 #define REG_PKT_BUFF_ACCESS_CTRL		0x0106
104 #define REG_TRXDMA_CTRL				0x010C
105 #define REG_TRXFF_BNDY					0x0114
106 #define REG_TRXFF_STATUS				0x0118
107 #define REG_RXFF_PTR					0x011C
108 #define REG_HIMR						0x0120
109 #define REG_HISR						0x0124
110 #define REG_HIMRE						0x0128
111 #define REG_HISRE						0x012C
112 #define REG_CPWM						0x012F
113 #define REG_FWIMR						0x0130
114 #define REG_FWISR						0x0134
115 #define REG_FTIMR						0x0138
116 #define REG_PKTBUF_DBG_CTRL			0x0140
117 #define REG_RXPKTBUF_CTRL				(REG_PKTBUF_DBG_CTRL+2)
118 #define REG_PKTBUF_DBG_DATA_L			0x0144
119 #define REG_PKTBUF_DBG_DATA_H		0x0148
120 
121 #define REG_TC0_CTRL					0x0150
122 #define REG_TC1_CTRL					0x0154
123 #define REG_TC2_CTRL					0x0158
124 #define REG_TC3_CTRL					0x015C
125 #define REG_TC4_CTRL					0x0160
126 #define REG_TCUNIT_BASE				0x0164
127 #define REG_MBIST_START				0x0174
128 #define REG_MBIST_DONE					0x0178
129 #define REG_MBIST_FAIL					0x017C
130 #define REG_C2HEVT_MSG_NORMAL		0x01A0
131 #define REG_C2HEVT_CLEAR				0x01AF
132 #define REG_MCUTST_1					0x01c0
133 #define REG_FMETHR						0x01C8
134 #define REG_HMETFR						0x01CC
135 #define REG_HMEBOX_0					0x01D0
136 #define REG_HMEBOX_1					0x01D4
137 #define REG_HMEBOX_2					0x01D8
138 #define REG_HMEBOX_3					0x01DC
139 #define REG_LLT_INIT					0x01E0
140 
141 
142 /*  */
143 /*  */
144 /* 	0x0200h ~ 0x027Fh	TXDMA Configuration */
145 /*  */
146 /*  */
147 #define REG_RQPN						0x0200
148 #define REG_FIFOPAGE					0x0204
149 #define REG_TDECTRL						0x0208
150 #define REG_TXDMA_OFFSET_CHK			0x020C
151 #define REG_TXDMA_STATUS				0x0210
152 #define REG_RQPN_NPQ					0x0214
153 #define REG_AUTO_LLT					0x0224
154 
155 
156 /*  */
157 /*  */
158 /* 	0x0280h ~ 0x02FFh	RXDMA Configuration */
159 /*  */
160 /*  */
161 #define REG_RXDMA_AGG_PG_TH			0x0280
162 #define REG_RXPKT_NUM					0x0284
163 #define REG_RXDMA_STATUS				0x0288
164 
165 /*  */
166 /*  */
167 /* 	0x0300h ~ 0x03FFh	PCIe */
168 /*  */
169 /*  */
170 #define REG_PCIE_CTRL_REG				0x0300
171 #define REG_INT_MIG						0x0304	/*  Interrupt Migration */
172 #define REG_BCNQ_DESA					0x0308	/*  TX Beacon Descriptor Address */
173 #define REG_HQ_DESA					0x0310	/*  TX High Queue Descriptor Address */
174 #define REG_MGQ_DESA					0x0318	/*  TX Manage Queue Descriptor Address */
175 #define REG_VOQ_DESA					0x0320	/*  TX VO Queue Descriptor Address */
176 #define REG_VIQ_DESA					0x0328	/*  TX VI Queue Descriptor Address */
177 #define REG_BEQ_DESA					0x0330	/*  TX BE Queue Descriptor Address */
178 #define REG_BKQ_DESA					0x0338	/*  TX BK Queue Descriptor Address */
179 #define REG_RX_DESA						0x0340	/*  RX Queue	Descriptor Address */
180 /* sherry added for DBI Read/Write  20091126 */
181 #define REG_DBI_WDATA					0x0348	/*  Backdoor REG for Access Configuration */
182 #define REG_DBI_RDATA				0x034C	/* Backdoor REG for Access Configuration */
183 #define REG_DBI_CTRL					0x0350	/* Backdoor REG for Access Configuration */
184 #define REG_DBI_FLAG					0x0352	/* Backdoor REG for Access Configuration */
185 #define REG_MDIO						0x0354	/*  MDIO for Access PCIE PHY */
186 #define REG_DBG_SEL						0x0360	/*  Debug Selection Register */
187 #define REG_PCIE_HRPWM					0x0361	/* PCIe RPWM */
188 #define REG_PCIE_HCPWM					0x0363	/* PCIe CPWM */
189 #define REG_WATCH_DOG					0x0368
190 
191 /*  RTL8723 series ------------------------------- */
192 #define REG_PCIE_HISR_EN				0x0394	/* PCIE Local Interrupt Enable Register */
193 #define REG_PCIE_HISR					0x03A0
194 #define REG_PCIE_HISRE					0x03A4
195 #define REG_PCIE_HIMR					0x03A8
196 #define REG_PCIE_HIMRE					0x03AC
197 
198 #define REG_USB_HIMR					0xFE38
199 #define REG_USB_HIMRE					0xFE3C
200 #define REG_USB_HISR					0xFE78
201 #define REG_USB_HISRE					0xFE7C
202 
203 
204 /*  */
205 /*  */
206 /* 	0x0400h ~ 0x047Fh	Protocol Configuration */
207 /*  */
208 /*  */
209 #define REG_VOQ_INFORMATION			0x0400
210 #define REG_VIQ_INFORMATION			0x0404
211 #define REG_BEQ_INFORMATION			0x0408
212 #define REG_BKQ_INFORMATION			0x040C
213 #define REG_MGQ_INFORMATION			0x0410
214 #define REG_HGQ_INFORMATION			0x0414
215 #define REG_BCNQ_INFORMATION			0x0418
216 #define REG_TXPKT_EMPTY				0x041A
217 #define REG_CPU_MGQ_INFORMATION		0x041C
218 #define REG_FWHW_TXQ_CTRL				0x0420
219 #define REG_HWSEQ_CTRL					0x0423
220 #define REG_BCNQ_BDNY					0x0424
221 #define REG_MGQ_BDNY					0x0425
222 #define REG_LIFETIME_CTRL				0x0426
223 #define REG_MULTI_BCNQ_OFFSET			0x0427
224 #define REG_SPEC_SIFS					0x0428
225 #define REG_RL							0x042A
226 #define REG_DARFRC						0x0430
227 #define REG_RARFRC						0x0438
228 #define REG_RRSR						0x0440
229 #define REG_ARFR0						0x0444
230 #define REG_ARFR1						0x0448
231 #define REG_ARFR2						0x044C
232 #define REG_ARFR3						0x0450
233 #define REG_BCNQ1_BDNY					0x0457
234 
235 #define REG_AGGLEN_LMT					0x0458
236 #define REG_AMPDU_MIN_SPACE			0x045C
237 #define REG_WMAC_LBK_BF_HD			0x045D
238 #define REG_FAST_EDCA_CTRL				0x0460
239 #define REG_RD_RESP_PKT_TH				0x0463
240 
241 #define REG_INIRTS_RATE_SEL				0x0480
242 #define REG_INIDATA_RATE_SEL			0x0484
243 
244 #define REG_POWER_STAGE1				0x04B4
245 #define REG_POWER_STAGE2				0x04B8
246 #define REG_PKT_VO_VI_LIFE_TIME		0x04C0
247 #define REG_PKT_BE_BK_LIFE_TIME		0x04C2
248 #define REG_STBC_SETTING				0x04C4
249 #define REG_QUEUE_CTRL					0x04C6
250 #define REG_SINGLE_AMPDU_CTRL			0x04c7
251 #define REG_PROT_MODE_CTRL			0x04C8
252 #define REG_MAX_AGGR_NUM				0x04CA
253 #define REG_RTS_MAX_AGGR_NUM			0x04CB
254 #define REG_BAR_MODE_CTRL				0x04CC
255 #define REG_RA_TRY_RATE_AGG_LMT		0x04CF
256 #define REG_EARLY_MODE_CONTROL		0x04D0
257 #define REG_MACID_SLEEP				0x04D4
258 #define REG_NQOS_SEQ					0x04DC
259 #define REG_QOS_SEQ					0x04DE
260 #define REG_NEED_CPU_HANDLE			0x04E0
261 #define REG_PKT_LOSE_RPT				0x04E1
262 #define REG_PTCL_ERR_STATUS			0x04E2
263 #define REG_TX_RPT_CTRL					0x04EC
264 #define REG_TX_RPT_TIME					0x04F0	/*  2 byte */
265 #define REG_DUMMY						0x04FC
266 
267 /*  */
268 /*  */
269 /* 	0x0500h ~ 0x05FFh	EDCA Configuration */
270 /*  */
271 /*  */
272 #define REG_EDCA_VO_PARAM				0x0500
273 #define REG_EDCA_VI_PARAM				0x0504
274 #define REG_EDCA_BE_PARAM				0x0508
275 #define REG_EDCA_BK_PARAM				0x050C
276 #define REG_BCNTCFG						0x0510
277 #define REG_PIFS							0x0512
278 #define REG_RDG_PIFS					0x0513
279 #define REG_SIFS_CTX					0x0514
280 #define REG_SIFS_TRX					0x0516
281 #define REG_TSFTR_SYN_OFFSET			0x0518
282 #define REG_AGGR_BREAK_TIME			0x051A
283 #define REG_SLOT						0x051B
284 #define REG_TX_PTCL_CTRL				0x0520
285 #define REG_TXPAUSE						0x0522
286 #define REG_DIS_TXREQ_CLR				0x0523
287 #define REG_RD_CTRL						0x0524
288 /*  */
289 /*  Format for offset 540h-542h: */
290 /* 	[3:0]:   TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. */
291 /* 	[7:4]:   Reserved. */
292 /* 	[19:8]:  TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. */
293 /* 	[23:20]: Reserved */
294 /*  Description: */
295 /* 	              | */
296 /*      |<--Setup--|--Hold------------>| */
297 /* 	--------------|---------------------- */
298 /*                 | */
299 /*                TBTT */
300 /*  Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. */
301 /*  Described by Designer Tim and Bruce, 2011-01-14. */
302 /*  */
303 #define REG_TBTT_PROHIBIT				0x0540
304 #define REG_RD_NAV_NXT					0x0544
305 #define REG_NAV_PROT_LEN				0x0546
306 #define REG_BCN_CTRL					0x0550
307 #define REG_BCN_CTRL_1					0x0551
308 #define REG_MBID_NUM					0x0552
309 #define REG_DUAL_TSF_RST				0x0553
310 #define REG_BCN_INTERVAL				0x0554	/*  The same as REG_MBSSID_BCN_SPACE */
311 #define REG_DRVERLYINT					0x0558
312 #define REG_BCNDMATIM					0x0559
313 #define REG_ATIMWND					0x055A
314 #define REG_USTIME_TSF					0x055C
315 #define REG_BCN_MAX_ERR				0x055D
316 #define REG_RXTSF_OFFSET_CCK			0x055E
317 #define REG_RXTSF_OFFSET_OFDM			0x055F
318 #define REG_TSFTR						0x0560
319 #define REG_TSFTR1						0x0568	/*  HW Port 1 TSF Register */
320 #define REG_ATIMWND_1					0x0570
321 #define REG_P2P_CTWIN					0x0572 /*  1 Byte long (in unit of TU) */
322 #define REG_PSTIMER						0x0580
323 #define REG_TIMER0						0x0584
324 #define REG_TIMER1						0x0588
325 #define REG_ACMHWCTRL					0x05C0
326 #define REG_NOA_DESC_SEL				0x05CF
327 #define REG_NOA_DESC_DURATION		0x05E0
328 #define REG_NOA_DESC_INTERVAL			0x05E4
329 #define REG_NOA_DESC_START			0x05E8
330 #define REG_NOA_DESC_COUNT			0x05EC
331 
332 #define REG_DMC							0x05F0	/* Dual MAC Co-Existence Register */
333 #define REG_SCH_TX_CMD					0x05F8
334 
335 #define REG_FW_RESET_TSF_CNT_1		0x05FC
336 #define REG_FW_RESET_TSF_CNT_0		0x05FD
337 #define REG_FW_BCN_DIS_CNT			0x05FE
338 
339 /*  */
340 /*  */
341 /* 	0x0600h ~ 0x07FFh	WMAC Configuration */
342 /*  */
343 /*  */
344 #define REG_APSD_CTRL					0x0600
345 #define REG_BWOPMODE					0x0603
346 #define REG_TCR							0x0604
347 #define REG_RCR							0x0608
348 #define REG_RX_PKT_LIMIT				0x060C
349 #define REG_RX_DLK_TIME				0x060D
350 #define REG_RX_DRVINFO_SZ				0x060F
351 
352 #define REG_MACID						0x0610
353 #define REG_BSSID						0x0618
354 #define REG_MAR							0x0620
355 #define REG_MBIDCAMCFG					0x0628
356 
357 #define REG_PNO_STATUS					0x0631
358 #define REG_USTIME_EDCA				0x0638
359 #define REG_MAC_SPEC_SIFS				0x063A
360 /*  20100719 Joseph: Hardware register definition change. (HW datasheet v54) */
361 #define REG_RESP_SIFS_CCK				0x063C	/*  [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
362 #define REG_RESP_SIFS_OFDM                    0x063E	/*  [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
363 
364 #define REG_ACKTO						0x0640
365 #define REG_CTS2TO						0x0641
366 #define REG_EIFS							0x0642
367 
368 
369 /* RXERR_RPT */
370 #define RXERR_TYPE_OFDM_PPDU			0
371 #define RXERR_TYPE_OFDMfalse_ALARM	1
372 #define RXERR_TYPE_OFDM_MPDU_OK			2
373 #define RXERR_TYPE_OFDM_MPDU_FAIL	3
374 #define RXERR_TYPE_CCK_PPDU			4
375 #define RXERR_TYPE_CCKfalse_ALARM	5
376 #define RXERR_TYPE_CCK_MPDU_OK		6
377 #define RXERR_TYPE_CCK_MPDU_FAIL		7
378 #define RXERR_TYPE_HT_PPDU				8
379 #define RXERR_TYPE_HTfalse_ALARM	9
380 #define RXERR_TYPE_HT_MPDU_TOTAL		10
381 #define RXERR_TYPE_HT_MPDU_OK			11
382 #define RXERR_TYPE_HT_MPDU_FAIL			12
383 #define RXERR_TYPE_RX_FULL_DROP			15
384 
385 #define RXERR_COUNTER_MASK			0xFFFFF
386 #define RXERR_RPT_RST					BIT(27)
387 #define _RXERR_RPT_SEL(type)			((type) << 28)
388 
389 /*  */
390 /*  Note: */
391 /* 	The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is */
392 /* 	always too small, but the WiFi TestPlan test by 25, 000 microseconds of NAV through sending */
393 /* 	CTS in the air. We must update this value greater than 25, 000 microseconds to pass the item. */
394 /* 	The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented */
395 /* 	by SD1 Scott. */
396 /*  By Bruce, 2011-07-18. */
397 /*  */
398 #define REG_NAV_UPPER					0x0652	/*  unit of 128 */
399 
400 /* WMA, BA, CCX */
401 #define REG_NAV_CTRL					0x0650
402 #define REG_BACAMCMD					0x0654
403 #define REG_BACAMCONTENT				0x0658
404 #define REG_LBDLY						0x0660
405 #define REG_FWDLY						0x0661
406 #define REG_RXERR_RPT					0x0664
407 #define REG_WMAC_TRXPTCL_CTL			0x0668
408 
409 /*  Security */
410 #define REG_CAMCMD						0x0670
411 #define REG_CAMWRITE					0x0674
412 #define REG_CAMREAD					0x0678
413 #define REG_CAMDBG						0x067C
414 #define REG_SECCFG						0x0680
415 
416 /*  Power */
417 #define REG_WOW_CTRL					0x0690
418 #define REG_PS_RX_INFO					0x0692
419 #define REG_UAPSD_TID					0x0693
420 #define REG_WKFMCAM_CMD				0x0698
421 #define REG_WKFMCAM_NUM				REG_WKFMCAM_CMD
422 #define REG_WKFMCAM_RWD				0x069C
423 #define REG_RXFLTMAP0					0x06A0
424 #define REG_RXFLTMAP1					0x06A2
425 #define REG_RXFLTMAP2					0x06A4
426 #define REG_BCN_PSR_RPT				0x06A8
427 #define REG_BT_COEX_TABLE				0x06C0
428 
429 /*  Hardware Port 2 */
430 #define REG_MACID1						0x0700
431 #define REG_BSSID1						0x0708
432 
433 
434 /*  */
435 /*  */
436 /* 	0xFE00h ~ 0xFE55h	USB Configuration */
437 /*  */
438 /*  */
439 #define REG_USB_INFO					0xFE17
440 #define REG_USB_SPECIAL_OPTION		0xFE55
441 #define REG_USB_DMA_AGG_TO			0xFE5B
442 #define REG_USB_AGG_TO					0xFE5C
443 #define REG_USB_AGG_TH					0xFE5D
444 
445 #define REG_USB_HRPWM					0xFE58
446 #define REG_USB_HCPWM					0xFE57
447 
448 /*  for 92DU high_Queue low_Queue Normal_Queue select */
449 #define REG_USB_High_NORMAL_Queue_Select_MAC0	0xFE44
450 /* define REG_USB_LOW_Queue_Select_MAC0		0xFE45 */
451 #define REG_USB_High_NORMAL_Queue_Select_MAC1	0xFE47
452 /* define REG_USB_LOW_Queue_Select_MAC1		0xFE48 */
453 
454 /*  For test chip */
455 #define REG_TEST_USB_TXQS				0xFE48
456 #define REG_TEST_SIE_VID				0xFE60		/*  0xFE60~0xFE61 */
457 #define REG_TEST_SIE_PID				0xFE62		/*  0xFE62~0xFE63 */
458 #define REG_TEST_SIE_OPTIONAL			0xFE64
459 #define REG_TEST_SIE_CHIRP_K			0xFE65
460 #define REG_TEST_SIE_PHY				0xFE66		/*  0xFE66~0xFE6B */
461 #define REG_TEST_SIE_MAC_ADDR			0xFE70		/*  0xFE70~0xFE75 */
462 #define REG_TEST_SIE_STRING			0xFE80		/*  0xFE80~0xFEB9 */
463 
464 
465 /*  For normal chip */
466 #define REG_NORMAL_SIE_VID				0xFE60		/*  0xFE60~0xFE61 */
467 #define REG_NORMAL_SIE_PID				0xFE62		/*  0xFE62~0xFE63 */
468 #define REG_NORMAL_SIE_OPTIONAL		0xFE64
469 #define REG_NORMAL_SIE_EP				0xFE65		/*  0xFE65~0xFE67 */
470 #define REG_NORMAL_SIE_PHY			0xFE68		/*  0xFE68~0xFE6B */
471 #define REG_NORMAL_SIE_OPTIONAL2		0xFE6C
472 #define REG_NORMAL_SIE_GPS_EP			0xFE6D		/*  0xFE6D, for RTL8723 only. */
473 #define REG_NORMAL_SIE_MAC_ADDR		0xFE70		/*  0xFE70~0xFE75 */
474 #define REG_NORMAL_SIE_STRING			0xFE80		/*  0xFE80~0xFEDF */
475 
476 
477 /*  */
478 /*  */
479 /* 	Redifine 8192C register definition for compatibility */
480 /*  */
481 /*  */
482 
483 /*  TODO: use these definition when using REG_xxx naming rule. */
484 /*  NOTE: DO NOT Remove these definition. Use later. */
485 
486 #define EFUSE_CTRL				REG_EFUSE_CTRL		/*  E-Fuse Control. */
487 #define EFUSE_TEST				REG_EFUSE_TEST		/*  E-Fuse Test. */
488 #define MSR						(REG_CR + 2)		/*  Media Status register */
489 /* define ISR						REG_HISR */
490 
491 #define TSFR						REG_TSFTR			/*  Timing Sync Function Timer Register. */
492 #define TSFR1					REG_TSFTR1			/*  HW Port 1 TSF Register */
493 
494 #define PBP						REG_PBP
495 
496 /*  Redifine MACID register, to compatible prior ICs. */
497 #define IDR0						REG_MACID			/*  MAC ID Register, Offset 0x0050-0x0053 */
498 #define IDR4						(REG_MACID + 4)		/*  MAC ID Register, Offset 0x0054-0x0055 */
499 
500 
501 /*  */
502 /*  9. Security Control Registers	(Offset:) */
503 /*  */
504 #define RWCAM					REG_CAMCMD		/* IN 8190 Data Sheet is called CAMcmd */
505 #define WCAMI					REG_CAMWRITE	/*  Software write CAM input content */
506 #define RCAMO					REG_CAMREAD		/*  Software read/write CAM config */
507 #define CAMDBG					REG_CAMDBG
508 #define SECR						REG_SECCFG		/* Security Configuration Register */
509 
510 /*  Unused register */
511 #define UnusedRegister			0x1BF
512 #define DCAM					UnusedRegister
513 #define PSR						UnusedRegister
514 #define BBAddr					UnusedRegister
515 #define PhyDataR					UnusedRegister
516 
517 /*  Min Spacing related settings. */
518 #define MAX_MSS_DENSITY_2T			0x13
519 #define MAX_MSS_DENSITY_1T			0x0A
520 
521 /*  */
522 /*        8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
523 /*  */
524 #define HSISR_GPIO12_0_INT				BIT0
525 #define HSISR_SPS_OCP_INT				BIT5
526 #define HSISR_RON_INT					BIT6
527 #define HSISR_PDNINT					BIT7
528 #define HSISR_GPIO9_INT					BIT25
529 
530 /*  */
531 /*        USB INTR CONTENT */
532 /*  */
533 #define USB_C2H_CMDID_OFFSET					0
534 #define USB_C2H_SEQ_OFFSET					1
535 #define USB_C2H_EVENT_OFFSET					2
536 #define USB_INTR_CPWM_OFFSET					16
537 #define USB_INTR_CONTENT_C2H_OFFSET			0
538 #define USB_INTR_CONTENT_CPWM1_OFFSET		16
539 #define USB_INTR_CONTENT_CPWM2_OFFSET		20
540 #define USB_INTR_CONTENT_HISR_OFFSET			48
541 #define USB_INTR_CONTENT_HISRE_OFFSET		52
542 #define USB_INTR_CONTENT_LENGTH				56
543 
544 /*  */
545 /*        Response Rate Set Register	(offset 0x440, 24bits) */
546 /*  */
547 #define RRSR_1M					BIT0
548 #define RRSR_2M					BIT1
549 #define RRSR_5_5M				BIT2
550 #define RRSR_11M				BIT3
551 #define RRSR_6M					BIT4
552 #define RRSR_9M					BIT5
553 #define RRSR_12M				BIT6
554 #define RRSR_18M				BIT7
555 #define RRSR_24M				BIT8
556 #define RRSR_36M				BIT9
557 #define RRSR_48M				BIT10
558 #define RRSR_54M				BIT11
559 #define RRSR_MCS0				BIT12
560 #define RRSR_MCS1				BIT13
561 #define RRSR_MCS2				BIT14
562 #define RRSR_MCS3				BIT15
563 #define RRSR_MCS4				BIT16
564 #define RRSR_MCS5				BIT17
565 #define RRSR_MCS6				BIT18
566 #define RRSR_MCS7				BIT19
567 
568 #define RRSR_CCK_RATES (RRSR_11M|RRSR_5_5M|RRSR_2M|RRSR_1M)
569 #define RRSR_OFDM_RATES (RRSR_54M|RRSR_48M|RRSR_36M|RRSR_24M|RRSR_18M|RRSR_12M|RRSR_9M|RRSR_6M)
570 
571 /*  WOL bit information */
572 #define HAL92C_WOL_PTK_UPDATE_EVENT		BIT0
573 #define HAL92C_WOL_GTK_UPDATE_EVENT		BIT1
574 #define HAL92C_WOL_DISASSOC_EVENT		BIT2
575 #define HAL92C_WOL_DEAUTH_EVENT			BIT3
576 #define HAL92C_WOL_FW_DISCONNECT_EVENT	BIT4
577 
578 /*  */
579 /*        Rate Definition */
580 /*  */
581 /* CCK */
582 #define	RATR_1M					0x00000001
583 #define	RATR_2M					0x00000002
584 #define	RATR_55M					0x00000004
585 #define	RATR_11M					0x00000008
586 /* OFDM */
587 #define	RATR_6M					0x00000010
588 #define	RATR_9M					0x00000020
589 #define	RATR_12M					0x00000040
590 #define	RATR_18M					0x00000080
591 #define	RATR_24M					0x00000100
592 #define	RATR_36M					0x00000200
593 #define	RATR_48M					0x00000400
594 #define	RATR_54M					0x00000800
595 /* MCS 1 Spatial Stream */
596 #define	RATR_MCS0					0x00001000
597 #define	RATR_MCS1					0x00002000
598 #define	RATR_MCS2					0x00004000
599 #define	RATR_MCS3					0x00008000
600 #define	RATR_MCS4					0x00010000
601 #define	RATR_MCS5					0x00020000
602 #define	RATR_MCS6					0x00040000
603 #define	RATR_MCS7					0x00080000
604 
605 /* CCK */
606 #define RATE_1M					BIT(0)
607 #define RATE_2M					BIT(1)
608 #define RATE_5_5M				BIT(2)
609 #define RATE_11M				BIT(3)
610 /* OFDM */
611 #define RATE_6M					BIT(4)
612 #define RATE_9M					BIT(5)
613 #define RATE_12M				BIT(6)
614 #define RATE_18M				BIT(7)
615 #define RATE_24M				BIT(8)
616 #define RATE_36M				BIT(9)
617 #define RATE_48M				BIT(10)
618 #define RATE_54M				BIT(11)
619 /* MCS 1 Spatial Stream */
620 #define RATE_MCS0				BIT(12)
621 #define RATE_MCS1				BIT(13)
622 #define RATE_MCS2				BIT(14)
623 #define RATE_MCS3				BIT(15)
624 #define RATE_MCS4				BIT(16)
625 #define RATE_MCS5				BIT(17)
626 #define RATE_MCS6				BIT(18)
627 #define RATE_MCS7				BIT(19)
628 
629 /*  ALL CCK Rate */
630 #define RATE_BITMAP_ALL			0xFFFFF
631 
632 /*  Only use CCK 1M rate for ACK */
633 #define RATE_RRSR_CCK_ONLY_1M		0xFFFF1
634 #define RATE_RRSR_WITHOUT_CCK		0xFFFF0
635 
636 /*  */
637 /*        BW_OPMODE bits				(Offset 0x603, 8bit) */
638 /*  */
639 #define BW_OPMODE_20MHZ			BIT2
640 
641 /*  */
642 /*        CAM Config Setting (offset 0x680, 1 byte) */
643 /*  */
644 #define CAM_VALID				BIT15
645 #define CAM_NOTVALID			0x0000
646 #define CAM_USEDK				BIT5
647 
648 #define CAM_CONTENT_COUNT	8
649 
650 #define CAM_NONE				0x0
651 #define CAM_WEP40				0x01
652 #define CAM_TKIP				0x02
653 #define CAM_AES					0x04
654 #define CAM_WEP104				0x05
655 #define CAM_SMS4				0x6
656 
657 #define TOTAL_CAM_ENTRY		32
658 #define HALF_CAM_ENTRY			16
659 
660 #define CAM_CONFIG_USEDK		true
661 #define CAM_CONFIG_NO_USEDK	false
662 
663 #define CAM_WRITE				BIT16
664 #define CAM_READ				0x00000000
665 #define CAM_POLLINIG			BIT31
666 
667 /*  */
668 /*  10. Power Save Control Registers */
669 /*  */
670 #define WOW_PMEN				BIT0 /*  Power management Enable. */
671 #define WOW_WOMEN				BIT1 /*  WoW function on or off. */
672 #define WOW_MAGIC				BIT2 /*  Magic packet */
673 #define WOW_UWF				BIT3 /*  Unicast Wakeup frame. */
674 
675 /*  */
676 /*  12. Host Interrupt Status Registers */
677 /*  */
678 /*  */
679 /*       8190 IMR/ISR bits */
680 /*  */
681 #define IMR8190_DISABLED		0x0
682 #define IMR_DISABLED			0x0
683 /*  IMR DW0 Bit 0-31 */
684 #define IMR_BCNDMAINT6			BIT31		/*  Beacon DMA Interrupt 6 */
685 #define IMR_BCNDMAINT5			BIT30		/*  Beacon DMA Interrupt 5 */
686 #define IMR_BCNDMAINT4			BIT29		/*  Beacon DMA Interrupt 4 */
687 #define IMR_BCNDMAINT3			BIT28		/*  Beacon DMA Interrupt 3 */
688 #define IMR_BCNDMAINT2			BIT27		/*  Beacon DMA Interrupt 2 */
689 #define IMR_BCNDMAINT1			BIT26		/*  Beacon DMA Interrupt 1 */
690 #define IMR_BCNDOK8				BIT25		/*  Beacon Queue DMA OK Interrupt 8 */
691 #define IMR_BCNDOK7				BIT24		/*  Beacon Queue DMA OK Interrupt 7 */
692 #define IMR_BCNDOK6				BIT23		/*  Beacon Queue DMA OK Interrupt 6 */
693 #define IMR_BCNDOK5				BIT22		/*  Beacon Queue DMA OK Interrupt 5 */
694 #define IMR_BCNDOK4				BIT21		/*  Beacon Queue DMA OK Interrupt 4 */
695 #define IMR_BCNDOK3				BIT20		/*  Beacon Queue DMA OK Interrupt 3 */
696 #define IMR_BCNDOK2				BIT19		/*  Beacon Queue DMA OK Interrupt 2 */
697 #define IMR_BCNDOK1				BIT18		/*  Beacon Queue DMA OK Interrupt 1 */
698 #define IMR_TIMEOUT2			BIT17		/*  Timeout interrupt 2 */
699 #define IMR_TIMEOUT1			BIT16		/*  Timeout interrupt 1 */
700 #define IMR_TXFOVW				BIT15		/*  Transmit FIFO Overflow */
701 #define IMR_PSTIMEOUT			BIT14		/*  Power save time out interrupt */
702 #define IMR_BcnInt				BIT13		/*  Beacon DMA Interrupt 0 */
703 #define IMR_RXFOVW				BIT12		/*  Receive FIFO Overflow */
704 #define IMR_RDU					BIT11		/*  Receive Descriptor Unavailable */
705 #define IMR_ATIMEND				BIT10		/*  For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */
706 #define IMR_BDOK				BIT9		/*  Beacon Queue DMA OK Interrupt */
707 #define IMR_HIGHDOK				BIT8		/*  High Queue DMA OK Interrupt */
708 #define IMR_TBDOK				BIT7		/*  Transmit Beacon OK interrupt */
709 #define IMR_MGNTDOK			BIT6		/*  Management Queue DMA OK Interrupt */
710 #define IMR_TBDER				BIT5		/*  For 92C, Transmit Beacon Error Interrupt */
711 #define IMR_BKDOK				BIT4		/*  AC_BK DMA OK Interrupt */
712 #define IMR_BEDOK				BIT3		/*  AC_BE DMA OK Interrupt */
713 #define IMR_VIDOK				BIT2		/*  AC_VI DMA OK Interrupt */
714 #define IMR_VODOK				BIT1		/*  AC_VO DMA Interrupt */
715 #define IMR_ROK					BIT0		/*  Receive DMA OK Interrupt */
716 
717 /*  13. Host Interrupt Status Extension Register	 (Offset: 0x012C-012Eh) */
718 #define IMR_TSF_BIT32_TOGGLE	BIT15
719 #define IMR_BcnInt_E				BIT12
720 #define IMR_TXERR				BIT11
721 #define IMR_RXERR				BIT10
722 #define IMR_C2HCMD				BIT9
723 #define IMR_CPWM				BIT8
724 /* RSVD [2-7] */
725 #define IMR_OCPINT				BIT1
726 #define IMR_WLANOFF			BIT0
727 
728 /*  */
729 /*        8192C (RCR) Receive Configuration Register	(Offset 0x608, 32 bits) */
730 /*  */
731 #define RCR_APPFCS				BIT31	/*  WMAC append FCS after pauload */
732 #define RCR_APP_MIC				BIT30	/*  MACRX will retain the MIC at the bottom of the packet. */
733 #define RCR_APP_ICV				BIT29	/*  MACRX will retain the ICV at the bottom of the packet. */
734 #define RCR_APP_PHYST_RXFF		BIT28	/*  PHY Status is appended before RX packet in RXFF */
735 #define RCR_APP_BA_SSN			BIT27	/*  SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */
736 #define RCR_NONQOS_VHT			BIT26	/*  Reserved */
737 #define RCR_RSVD_BIT25			BIT25	/*  Reserved */
738 #define RCR_ENMBID				BIT24	/*  Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */
739 #define RCR_LSIGEN				BIT23	/*  Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */
740 #define RCR_MFBEN				BIT22	/*  Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */
741 #define RCR_RSVD_BIT21			BIT21	/*  Reserved */
742 #define RCR_RSVD_BIT20			BIT20	/*  Reserved */
743 #define RCR_RSVD_BIT19			BIT19	/*  Reserved */
744 #define RCR_TIM_PARSER_EN		BIT18	/*  RX Beacon TIM Parser. */
745 #define RCR_BM_DATA_EN			BIT17	/*  Broadcast data packet interrupt enable. */
746 #define RCR_UC_DATA_EN			BIT16	/*  Unicast data packet interrupt enable. */
747 #define RCR_RSVD_BIT15			BIT15	/*  Reserved */
748 #define RCR_HTC_LOC_CTRL		BIT14	/*  MFC<--HTC = 1 MFC-->HTC = 0 */
749 #define RCR_AMF					BIT13	/*  Accept management type frame */
750 #define RCR_ACF					BIT12	/*  Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */
751 #define RCR_ADF					BIT11	/*  Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */
752 #define RCR_RSVD_BIT10			BIT10	/*  Reserved */
753 #define RCR_AICV					BIT9		/*  Accept ICV error packet */
754 #define RCR_ACRC32				BIT8		/*  Accept CRC32 error packet */
755 #define RCR_CBSSID_BCN			BIT7		/*  Accept BSSID match packet (Rx beacon, probe rsp) */
756 #define RCR_CBSSID_DATA		BIT6		/*  Accept BSSID match packet (Data) */
757 #define RCR_CBSSID				RCR_CBSSID_DATA	/*  Accept BSSID match packet */
758 #define RCR_APWRMGT			BIT5		/*  Accept power management packet */
759 #define RCR_ADD3				BIT4		/*  Accept address 3 match packet */
760 #define RCR_AB					BIT3		/*  Accept broadcast packet */
761 #define RCR_AM					BIT2		/*  Accept multicast packet */
762 #define RCR_APM					BIT1		/*  Accept physical match packet */
763 #define RCR_AAP					BIT0		/*  Accept all unicast packet */
764 
765 
766 /*  */
767 /*  */
768 /* 	0x0000h ~ 0x00FFh	System Configuration */
769 /*  */
770 /*  */
771 
772 /* 2 SYS_ISO_CTRL */
773 #define ISO_MD2PP				BIT(0)
774 #define ISO_UA2USB				BIT(1)
775 #define ISO_UD2CORE				BIT(2)
776 #define ISO_PA2PCIE				BIT(3)
777 #define ISO_PD2CORE				BIT(4)
778 #define ISO_IP2MAC				BIT(5)
779 #define ISO_DIOP					BIT(6)
780 #define ISO_DIOE					BIT(7)
781 #define ISO_EB2CORE				BIT(8)
782 #define ISO_DIOR					BIT(9)
783 #define PWC_EV12V				BIT(15)
784 
785 
786 /* 2 SYS_FUNC_EN */
787 #define FEN_BBRSTB				BIT(0)
788 #define FEN_BB_GLB_RSTn		BIT(1)
789 #define FEN_USBA				BIT(2)
790 #define FEN_UPLL				BIT(3)
791 #define FEN_USBD				BIT(4)
792 #define FEN_DIO_PCIE			BIT(5)
793 #define FEN_PCIEA				BIT(6)
794 #define FEN_PPLL					BIT(7)
795 #define FEN_PCIED				BIT(8)
796 #define FEN_DIOE				BIT(9)
797 #define FEN_CPUEN				BIT(10)
798 #define FEN_DCORE				BIT(11)
799 #define FEN_ELDR				BIT(12)
800 #define FEN_EN_25_1				BIT(13)
801 #define FEN_HWPDN				BIT(14)
802 #define FEN_MREGEN				BIT(15)
803 
804 /* 2 APS_FSMCO */
805 #define PFM_LDALL				BIT(0)
806 #define PFM_ALDN				BIT(1)
807 #define PFM_LDKP				BIT(2)
808 #define PFM_WOWL				BIT(3)
809 #define EnPDN					BIT(4)
810 #define PDN_PL					BIT(5)
811 #define APFM_ONMAC				BIT(8)
812 #define APFM_OFF				BIT(9)
813 #define APFM_RSM				BIT(10)
814 #define AFSM_HSUS				BIT(11)
815 #define AFSM_PCIE				BIT(12)
816 #define APDM_MAC				BIT(13)
817 #define APDM_HOST				BIT(14)
818 #define APDM_HPDN				BIT(15)
819 #define RDY_MACON				BIT(16)
820 #define SUS_HOST				BIT(17)
821 #define ROP_ALD					BIT(20)
822 #define ROP_PWR					BIT(21)
823 #define ROP_SPS					BIT(22)
824 #define SOP_MRST				BIT(25)
825 #define SOP_FUSE				BIT(26)
826 #define SOP_ABG					BIT(27)
827 #define SOP_AMB					BIT(28)
828 #define SOP_RCK					BIT(29)
829 #define SOP_A8M					BIT(30)
830 #define XOP_BTCK				BIT(31)
831 
832 /* 2 SYS_CLKR */
833 #define ANAD16V_EN				BIT(0)
834 #define ANA8M					BIT(1)
835 #define MACSLP					BIT(4)
836 #define LOADER_CLK_EN			BIT(5)
837 
838 
839 /* 2 9346CR /REG_SYS_EEPROM_CTRL */
840 #define BOOT_FROM_EEPROM		BIT(4)
841 #define EEPROMSEL				BIT(4)
842 #define EEPROM_EN				BIT(5)
843 
844 
845 /* 2 RF_CTRL */
846 #define RF_EN					BIT(0)
847 #define RF_RSTB					BIT(1)
848 #define RF_SDMRSTB				BIT(2)
849 
850 
851 /* 2 LDOV12D_CTRL */
852 #define LDV12_EN				BIT(0)
853 #define LDV12_SDBY				BIT(1)
854 #define LPLDO_HSM				BIT(2)
855 #define LPLDO_LSM_DIS			BIT(3)
856 #define _LDV12_VADJ(x)			(((x) & 0xF) << 4)
857 
858 
859 
860 /* 2 EFUSE_TEST (For RTL8723 partially) */
861 #define EF_TRPT					BIT(7)
862 #define EF_CELL_SEL				(BIT(8)|BIT(9)) /*  00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
863 #define LDOE25_EN				BIT(31)
864 #define EFUSE_SEL(x)				(((x) & 0x3) << 8)
865 #define EFUSE_SEL_MASK			0x300
866 #define EFUSE_WIFI_SEL_0		0x0
867 #define EFUSE_BT_SEL_0			0x1
868 #define EFUSE_BT_SEL_1			0x2
869 #define EFUSE_BT_SEL_2			0x3
870 
871 
872 /* 2 8051FWDL */
873 /* 2 MCUFWDL */
874 #define MCUFWDL_EN				BIT(0)
875 #define MCUFWDL_RDY			BIT(1)
876 #define FWDL_ChkSum_rpt		BIT(2)
877 #define MACINI_RDY				BIT(3)
878 #define BBINI_RDY				BIT(4)
879 #define RFINI_RDY				BIT(5)
880 #define WINTINI_RDY				BIT(6)
881 #define RAM_DL_SEL				BIT(7)
882 #define ROM_DLEN				BIT(19)
883 #define CPRST					BIT(23)
884 
885 
886 /* 2 REG_SYS_CFG */
887 #define XCLK_VLD				BIT(0)
888 #define ACLK_VLD				BIT(1)
889 #define UCLK_VLD				BIT(2)
890 #define PCLK_VLD				BIT(3)
891 #define PCIRSTB					BIT(4)
892 #define V15_VLD					BIT(5)
893 #define SW_OFFLOAD_EN			BIT(7)
894 #define SIC_IDLE					BIT(8)
895 #define BD_MAC2					BIT(9)
896 #define BD_MAC1					BIT(10)
897 #define IC_MACPHY_MODE		BIT(11)
898 #define CHIP_VER				(BIT(12)|BIT(13)|BIT(14)|BIT(15))
899 #define BT_FUNC					BIT(16)
900 #define VENDOR_ID				BIT(19)
901 #define EXT_VENDOR_ID			(BIT(18)|BIT(19)) /* Currently only for RTL8723B */
902 #define PAD_HWPD_IDN			BIT(22)
903 #define TRP_VAUX_EN				BIT(23)	/*  RTL ID */
904 #define TRP_BT_EN				BIT(24)
905 #define BD_PKG_SEL				BIT(25)
906 #define BD_HCI_SEL				BIT(26)
907 #define TYPE_ID					BIT(27)
908 #define RF_TYPE_ID				BIT(27)
909 
910 #define RTL_ID					BIT(23) /*  TestChip ID, 1:Test(RLE); 0:MP(RL) */
911 #define SPS_SEL					BIT(24) /*  1:LDO regulator mode; 0:Switching regulator mode */
912 
913 
914 #define CHIP_VER_RTL_MASK		0xF000	/* Bit 12 ~ 15 */
915 #define CHIP_VER_RTL_SHIFT		12
916 #define EXT_VENDOR_ID_SHIFT	18
917 
918 /* 2 REG_GPIO_OUTSTS (For RTL8723 only) */
919 #define EFS_HCI_SEL				(BIT(0)|BIT(1))
920 #define PAD_HCI_SEL				(BIT(2)|BIT(3))
921 #define HCI_SEL					(BIT(4)|BIT(5))
922 #define PKG_SEL_HCI				BIT(6)
923 #define FEN_GPS					BIT(7)
924 #define FEN_BT					BIT(8)
925 #define FEN_WL					BIT(9)
926 #define FEN_PCI					BIT(10)
927 #define FEN_USB					BIT(11)
928 #define BTRF_HWPDN_N			BIT(12)
929 #define WLRF_HWPDN_N			BIT(13)
930 #define PDN_BT_N				BIT(14)
931 #define PDN_GPS_N				BIT(15)
932 #define BT_CTL_HWPDN			BIT(16)
933 #define GPS_CTL_HWPDN			BIT(17)
934 #define PPHY_SUSB				BIT(20)
935 #define UPHY_SUSB				BIT(21)
936 #define PCI_SUSEN				BIT(22)
937 #define USB_SUSEN				BIT(23)
938 #define RF_RL_ID					(BIT(31)|BIT(30)|BIT(29)|BIT(28))
939 
940 
941 /*  */
942 /*  */
943 /* 	0x0100h ~ 0x01FFh	MACTOP General Configuration */
944 /*  */
945 /*  */
946 
947 /* 2 Function Enable Registers */
948 /* 2 CR */
949 #define HCI_TXDMA_EN			BIT(0)
950 #define HCI_RXDMA_EN			BIT(1)
951 #define TXDMA_EN				BIT(2)
952 #define RXDMA_EN				BIT(3)
953 #define PROTOCOL_EN				BIT(4)
954 #define SCHEDULE_EN				BIT(5)
955 #define MACTXEN					BIT(6)
956 #define MACRXEN					BIT(7)
957 #define ENSWBCN					BIT(8)
958 #define ENSEC					BIT(9)
959 #define CALTMR_EN				BIT(10)	/*  32k CAL TMR enable */
960 
961 /*  Network type */
962 #define _NETTYPE(x)				(((x) & 0x3) << 16)
963 #define MASK_NETTYPE			0x30000
964 #define NT_NO_LINK				0x0
965 #define NT_LINK_AD_HOC			0x1
966 #define NT_LINK_AP				0x2
967 #define NT_AS_AP				0x3
968 
969 /* 2 PBP - Page Size Register */
970 #define GET_RX_PAGE_SIZE(value)			((value) & 0xF)
971 #define GET_TX_PAGE_SIZE(value)			(((value) & 0xF0) >> 4)
972 #define _PSRX_MASK				0xF
973 #define _PSTX_MASK				0xF0
974 #define _PSRX(x)				(x)
975 #define _PSTX(x)				((x) << 4)
976 
977 #define PBP_64					0x0
978 #define PBP_128					0x1
979 #define PBP_256					0x2
980 #define PBP_512					0x3
981 #define PBP_1024				0x4
982 
983 
984 /* 2 TX/RXDMA */
985 #define RXDMA_ARBBW_EN		BIT(0)
986 #define RXSHFT_EN				BIT(1)
987 #define RXDMA_AGG_EN			BIT(2)
988 #define QS_VO_QUEUE			BIT(8)
989 #define QS_VI_QUEUE				BIT(9)
990 #define QS_BE_QUEUE			BIT(10)
991 #define QS_BK_QUEUE			BIT(11)
992 #define QS_MANAGER_QUEUE		BIT(12)
993 #define QS_HIGH_QUEUE			BIT(13)
994 
995 #define HQSEL_VOQ				BIT(0)
996 #define HQSEL_VIQ				BIT(1)
997 #define HQSEL_BEQ				BIT(2)
998 #define HQSEL_BKQ				BIT(3)
999 #define HQSEL_MGTQ				BIT(4)
1000 #define HQSEL_HIQ				BIT(5)
1001 
1002 /*  For normal driver, 0x10C */
1003 #define _TXDMA_CMQ_MAP(x)			(((x)&0x3) << 16)
1004 #define _TXDMA_HIQ_MAP(x)			(((x)&0x3) << 14)
1005 #define _TXDMA_MGQ_MAP(x)			(((x)&0x3) << 12)
1006 #define _TXDMA_BKQ_MAP(x)			(((x)&0x3) << 10)
1007 #define _TXDMA_BEQ_MAP(x)			(((x)&0x3) << 8)
1008 #define _TXDMA_VIQ_MAP(x)			(((x)&0x3) << 6)
1009 #define _TXDMA_VOQ_MAP(x)			(((x)&0x3) << 4)
1010 
1011 #define QUEUE_EXTRA				0
1012 #define QUEUE_LOW				1
1013 #define QUEUE_NORMAL			2
1014 #define QUEUE_HIGH				3
1015 
1016 
1017 /* 2 TRXFF_BNDY */
1018 
1019 
1020 /* 2 LLT_INIT */
1021 #define _LLT_NO_ACTIVE				0x0
1022 #define _LLT_WRITE_ACCESS			0x1
1023 #define _LLT_READ_ACCESS			0x2
1024 
1025 #define _LLT_INIT_DATA(x)			((x) & 0xFF)
1026 #define _LLT_INIT_ADDR(x)			(((x) & 0xFF) << 8)
1027 #define _LLT_OP(x)					(((x) & 0x3) << 30)
1028 #define _LLT_OP_VALUE(x)			(((x) >> 30) & 0x3)
1029 
1030 
1031 /*  */
1032 /*  */
1033 /* 	0x0200h ~ 0x027Fh	TXDMA Configuration */
1034 /*  */
1035 /*  */
1036 /* 2 RQPN */
1037 #define _HPQ(x)					((x) & 0xFF)
1038 #define _LPQ(x)					(((x) & 0xFF) << 8)
1039 #define _PUBQ(x)					(((x) & 0xFF) << 16)
1040 #define _NPQ(x)					((x) & 0xFF)			/*  NOTE: in RQPN_NPQ register */
1041 #define _EPQ(x)					(((x) & 0xFF) << 16)	/*  NOTE: in RQPN_EPQ register */
1042 
1043 
1044 #define HPQ_PUBLIC_DIS			BIT(24)
1045 #define LPQ_PUBLIC_DIS			BIT(25)
1046 #define LD_RQPN					BIT(31)
1047 
1048 
1049 /* 2 TDECTL */
1050 #define BLK_DESC_NUM_SHIFT			4
1051 #define BLK_DESC_NUM_MASK			0xF
1052 
1053 
1054 /* 2 TXDMA_OFFSET_CHK */
1055 #define DROP_DATA_EN				BIT(9)
1056 
1057 /* 2 AUTO_LLT */
1058 #define BIT_SHIFT_TXPKTNUM 24
1059 #define BIT_MASK_TXPKTNUM 0xff
1060 #define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)
1061 
1062 #define BIT_TDE_DBG_SEL BIT(23)
1063 #define BIT_AUTO_INIT_LLT BIT(16)
1064 
1065 #define BIT_SHIFT_Tx_OQT_free_space 8
1066 #define BIT_MASK_Tx_OQT_free_space 0xff
1067 #define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space)
1068 
1069 
1070 /*  */
1071 /*  */
1072 /* 	0x0280h ~ 0x028Bh	RX DMA Configuration */
1073 /*  */
1074 /*  */
1075 
1076 /* 2 REG_RXDMA_CONTROL, 0x0286h */
1077 /*  Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before */
1078 /*  this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. */
1079 /* define RXPKT_RELEASE_POLL			BIT(0) */
1080 /*  Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in */
1081 /*  this bit. FW can start releasing packets after RXDMA entering idle mode. */
1082 /* define RXDMA_IDLE					BIT(1) */
1083 /*  When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host */
1084 /*  completed, and stop DMA packet to host. RXDMA will then report Default: 0; */
1085 /* define RW_RELEASE_EN				BIT(2) */
1086 
1087 /* 2 REG_RXPKT_NUM, 0x0284 */
1088 #define		RXPKT_RELEASE_POLL	BIT(16)
1089 #define	RXDMA_IDLE				BIT(17)
1090 #define	RW_RELEASE_EN			BIT(18)
1091 
1092 /*  */
1093 /*  */
1094 /* 	0x0400h ~ 0x047Fh	Protocol Configuration */
1095 /*  */
1096 /*  */
1097 /* 2 FWHW_TXQ_CTRL */
1098 #define EN_AMPDU_RTY_NEW			BIT(7)
1099 
1100 
1101 /* 2 SPEC SIFS */
1102 #define _SPEC_SIFS_CCK(x)			((x) & 0xFF)
1103 #define _SPEC_SIFS_OFDM(x)			(((x) & 0xFF) << 8)
1104 
1105 /* 2 RL */
1106 #define	RETRY_LIMIT_SHORT_SHIFT			8
1107 #define	RETRY_LIMIT_LONG_SHIFT			0
1108 
1109 /*  */
1110 /*  */
1111 /* 	0x0500h ~ 0x05FFh	EDCA Configuration */
1112 /*  */
1113 /*  */
1114 
1115 /* 2 EDCA setting */
1116 #define AC_PARAM_TXOP_LIMIT_OFFSET		16
1117 #define AC_PARAM_ECW_MAX_OFFSET			12
1118 #define AC_PARAM_ECW_MIN_OFFSET			8
1119 #define AC_PARAM_AIFS_OFFSET				0
1120 
1121 
1122 #define _LRL(x)					((x) & 0x3F)
1123 #define _SRL(x)					(((x) & 0x3F) << 8)
1124 
1125 
1126 /* 2 BCN_CTRL */
1127 #define EN_TXBCN_RPT			BIT(2)
1128 #define EN_BCN_FUNCTION		BIT(3)
1129 #define STOP_BCNQ				BIT(6)
1130 #define DIS_RX_BSSID_FIT		BIT(6)
1131 
1132 #define DIS_ATIM					BIT(0)
1133 #define DIS_BCNQ_SUB			BIT(1)
1134 #define DIS_TSF_UDT				BIT(4)
1135 
1136 /*  The same function but different bit field. */
1137 #define DIS_TSF_UDT0_NORMAL_CHIP	BIT(4)
1138 #define DIS_TSF_UDT0_TEST_CHIP	BIT(5)
1139 
1140 
1141 /* 2 ACMHWCTRL */
1142 #define AcmHw_HwEn				BIT(0)
1143 #define AcmHw_BeqEn			BIT(1)
1144 #define AcmHw_ViqEn				BIT(2)
1145 #define AcmHw_VoqEn			BIT(3)
1146 #define AcmHw_BeqStatus		BIT(4)
1147 #define AcmHw_ViqStatus			BIT(5)
1148 #define AcmHw_VoqStatus		BIT(6)
1149 
1150 /* 2 REG_DUAL_TSF_RST (0x553) */
1151 #define DUAL_TSF_RST_P2P		BIT(4)
1152 
1153 /* 2  REG_NOA_DESC_SEL (0x5CF) */
1154 #define NOA_DESC_SEL_0			0
1155 #define NOA_DESC_SEL_1			BIT(4)
1156 
1157 /*  */
1158 /*  */
1159 /* 	0x0600h ~ 0x07FFh	WMAC Configuration */
1160 /*  */
1161 /*  */
1162 
1163 /* 2 APSD_CTRL */
1164 #define APSDOFF					BIT(6)
1165 
1166 /* 2 TCR */
1167 #define TSFRST					BIT(0)
1168 #define DIS_GCLK					BIT(1)
1169 #define PAD_SEL					BIT(2)
1170 #define PWR_ST					BIT(6)
1171 #define PWRBIT_OW_EN			BIT(7)
1172 #define ACRC						BIT(8)
1173 #define CFENDFORM				BIT(9)
1174 #define ICV						BIT(10)
1175 
1176 
1177 /* 2 RCR */
1178 #define AAP						BIT(0)
1179 #define APM						BIT(1)
1180 #define AM						BIT(2)
1181 #define AB						BIT(3)
1182 #define ADD3						BIT(4)
1183 #define APWRMGT				BIT(5)
1184 #define CBSSID					BIT(6)
1185 #define CBSSID_DATA				BIT(6)
1186 #define CBSSID_BCN				BIT(7)
1187 #define ACRC32					BIT(8)
1188 #define AICV						BIT(9)
1189 #define ADF						BIT(11)
1190 #define ACF						BIT(12)
1191 #define AMF						BIT(13)
1192 #define HTC_LOC_CTRL			BIT(14)
1193 #define UC_DATA_EN				BIT(16)
1194 #define BM_DATA_EN				BIT(17)
1195 #define MFBEN					BIT(22)
1196 #define LSIGEN					BIT(23)
1197 #define EnMBID					BIT(24)
1198 #define FORCEACK				BIT(26)
1199 #define APP_BASSN				BIT(27)
1200 #define APP_PHYSTS				BIT(28)
1201 #define APP_ICV					BIT(29)
1202 #define APP_MIC					BIT(30)
1203 #define APP_FCS					BIT(31)
1204 
1205 
1206 /* 2 SECCFG */
1207 #define SCR_TxUseDK				BIT(0)			/* Force Tx Use Default Key */
1208 #define SCR_RxUseDK				BIT(1)			/* Force Rx Use Default Key */
1209 #define SCR_TxEncEnable			BIT(2)			/* Enable Tx Encryption */
1210 #define SCR_RxDecEnable			BIT(3)			/* Enable Rx Decryption */
1211 #define SCR_SKByA2				BIT(4)			/* Search kEY BY A2 */
1212 #define SCR_NoSKMC				BIT(5)			/* No Key Search Multicast */
1213 #define SCR_TXBCUSEDK			BIT(6)			/*  Force Tx Broadcast packets Use Default Key */
1214 #define SCR_RXBCUSEDK			BIT(7)			/*  Force Rx Broadcast packets Use Default Key */
1215 #define SCR_CHK_KEYID			BIT(8)
1216 
1217 /*  */
1218 /*  */
1219 /* 	SDIO Bus Specification */
1220 /*  */
1221 /*  */
1222 
1223 /*  I/O bus domain address mapping */
1224 #define SDIO_LOCAL_BASE		0x10250000
1225 #define WLAN_IOREG_BASE		0x10260000
1226 #define FIRMWARE_FIFO_BASE	0x10270000
1227 #define TX_HIQ_BASE				0x10310000
1228 #define TX_MIQ_BASE				0x10320000
1229 #define TX_LOQ_BASE				0x10330000
1230 #define TX_EPQ_BASE				0x10350000
1231 #define RX_RX0FF_BASE			0x10340000
1232 
1233 /* SDIO host local register space mapping. */
1234 #define SDIO_LOCAL_MSK				0x0FFF
1235 #define WLAN_IOREG_MSK			0x7FFF
1236 #define WLAN_FIFO_MSK				0x1FFF	/*  Aggregation Length[12:0] */
1237 #define WLAN_RX0FF_MSK				0x0003
1238 
1239 #define SDIO_WITHOUT_REF_DEVICE_ID	0	/*  Without reference to the SDIO Device ID */
1240 #define SDIO_LOCAL_DEVICE_ID			0	/*  0b[16], 000b[15:13] */
1241 #define WLAN_TX_HIQ_DEVICE_ID			4	/*  0b[16], 100b[15:13] */
1242 #define WLAN_TX_MIQ_DEVICE_ID		5	/*  0b[16], 101b[15:13] */
1243 #define WLAN_TX_LOQ_DEVICE_ID		6	/*  0b[16], 110b[15:13] */
1244 #define WLAN_TX_EXQ_DEVICE_ID		3	/*  0b[16], 011b[15:13] */
1245 #define WLAN_RX0FF_DEVICE_ID			7	/*  0b[16], 111b[15:13] */
1246 #define WLAN_IOREG_DEVICE_ID			8	/*  1b[16] */
1247 
1248 /* SDIO Tx Free Page Index */
1249 #define HI_QUEUE_IDX				0
1250 #define MID_QUEUE_IDX				1
1251 #define LOW_QUEUE_IDX				2
1252 #define PUBLIC_QUEUE_IDX			3
1253 
1254 #define SDIO_MAX_TX_QUEUE			3		/*  HIQ, MIQ and LOQ */
1255 #define SDIO_MAX_RX_QUEUE			1
1256 
1257 #define SDIO_REG_TX_CTRL			0x0000 /*  SDIO Tx Control */
1258 #define SDIO_REG_HIMR				0x0014 /*  SDIO Host Interrupt Mask */
1259 #define SDIO_REG_HISR				0x0018 /*  SDIO Host Interrupt Service Routine */
1260 #define SDIO_REG_HCPWM			0x0019 /*  HCI Current Power Mode */
1261 #define SDIO_REG_RX0_REQ_LEN		0x001C /*  RXDMA Request Length */
1262 #define SDIO_REG_OQT_FREE_PG		0x001E /*  OQT Free Page */
1263 #define SDIO_REG_FREE_TXPG			0x0020 /*  Free Tx Buffer Page */
1264 #define SDIO_REG_HCPWM1			0x0024 /*  HCI Current Power Mode 1 */
1265 #define SDIO_REG_HCPWM2			0x0026 /*  HCI Current Power Mode 2 */
1266 #define SDIO_REG_FREE_TXPG_SEQ	0x0028 /*  Free Tx Page Sequence */
1267 #define SDIO_REG_HTSFR_INFO		0x0030 /*  HTSF Informaion */
1268 #define SDIO_REG_HRPWM1			0x0080 /*  HCI Request Power Mode 1 */
1269 #define SDIO_REG_HRPWM2			0x0082 /*  HCI Request Power Mode 2 */
1270 #define SDIO_REG_HPS_CLKR			0x0084 /*  HCI Power Save Clock */
1271 #define SDIO_REG_HSUS_CTRL			0x0086 /*  SDIO HCI Suspend Control */
1272 #define SDIO_REG_HIMR_ON			0x0090 /* SDIO Host Extension Interrupt Mask Always */
1273 #define SDIO_REG_HISR_ON			0x0091 /* SDIO Host Extension Interrupt Status Always */
1274 
1275 #define SDIO_HIMR_DISABLED			0
1276 
1277 /*  RTL8723/RTL8188E SDIO Host Interrupt Mask Register */
1278 #define SDIO_HIMR_RX_REQUEST_MSK		BIT0
1279 #define SDIO_HIMR_AVAL_MSK			BIT1
1280 #define SDIO_HIMR_TXERR_MSK			BIT2
1281 #define SDIO_HIMR_RXERR_MSK			BIT3
1282 #define SDIO_HIMR_TXFOVW_MSK			BIT4
1283 #define SDIO_HIMR_RXFOVW_MSK			BIT5
1284 #define SDIO_HIMR_TXBCNOK_MSK			BIT6
1285 #define SDIO_HIMR_TXBCNERR_MSK		BIT7
1286 #define SDIO_HIMR_BCNERLY_INT_MSK		BIT16
1287 #define SDIO_HIMR_C2HCMD_MSK			BIT17
1288 #define SDIO_HIMR_CPWM1_MSK			BIT18
1289 #define SDIO_HIMR_CPWM2_MSK			BIT19
1290 #define SDIO_HIMR_HSISR_IND_MSK		BIT20
1291 #define SDIO_HIMR_GTINT3_IND_MSK		BIT21
1292 #define SDIO_HIMR_GTINT4_IND_MSK		BIT22
1293 #define SDIO_HIMR_PSTIMEOUT_MSK		BIT23
1294 #define SDIO_HIMR_OCPINT_MSK			BIT24
1295 #define SDIO_HIMR_ATIMEND_MSK			BIT25
1296 #define SDIO_HIMR_ATIMEND_E_MSK		BIT26
1297 #define SDIO_HIMR_CTWEND_MSK			BIT27
1298 
1299 /*  SDIO Host Interrupt Service Routine */
1300 #define SDIO_HISR_RX_REQUEST			BIT0
1301 #define SDIO_HISR_AVAL					BIT1
1302 #define SDIO_HISR_TXERR					BIT2
1303 #define SDIO_HISR_RXERR					BIT3
1304 #define SDIO_HISR_TXFOVW				BIT4
1305 #define SDIO_HISR_RXFOVW				BIT5
1306 #define SDIO_HISR_TXBCNOK				BIT6
1307 #define SDIO_HISR_TXBCNERR				BIT7
1308 #define SDIO_HISR_BCNERLY_INT			BIT16
1309 #define SDIO_HISR_C2HCMD				BIT17
1310 #define SDIO_HISR_CPWM1				BIT18
1311 #define SDIO_HISR_CPWM2				BIT19
1312 #define SDIO_HISR_HSISR_IND			BIT20
1313 #define SDIO_HISR_GTINT3_IND			BIT21
1314 #define SDIO_HISR_GTINT4_IND			BIT22
1315 #define SDIO_HISR_PSTIMEOUT			BIT23
1316 #define SDIO_HISR_OCPINT				BIT24
1317 #define SDIO_HISR_ATIMEND				BIT25
1318 #define SDIO_HISR_ATIMEND_E			BIT26
1319 #define SDIO_HISR_CTWEND				BIT27
1320 
1321 #define MASK_SDIO_HISR_CLEAR		(SDIO_HISR_TXERR |\
1322 									SDIO_HISR_RXERR |\
1323 									SDIO_HISR_TXFOVW |\
1324 									SDIO_HISR_RXFOVW |\
1325 									SDIO_HISR_TXBCNOK |\
1326 									SDIO_HISR_TXBCNERR |\
1327 									SDIO_HISR_C2HCMD |\
1328 									SDIO_HISR_CPWM1 |\
1329 									SDIO_HISR_CPWM2 |\
1330 									SDIO_HISR_HSISR_IND |\
1331 									SDIO_HISR_GTINT3_IND |\
1332 									SDIO_HISR_GTINT4_IND |\
1333 									SDIO_HISR_PSTIMEOUT |\
1334 									SDIO_HISR_OCPINT)
1335 
1336 /*  SDIO HCI Suspend Control Register */
1337 #define HCI_RESUME_PWR_RDY			BIT1
1338 #define HCI_SUS_CTRL					BIT0
1339 
1340 /*  SDIO Tx FIFO related */
1341 #define SDIO_TX_FREE_PG_QUEUE			4	/*  The number of Tx FIFO free page */
1342 #define SDIO_TX_FIFO_PAGE_SZ			128
1343 
1344 #define MAX_TX_AGG_PACKET_NUMBER	0x8
1345 
1346 /*  */
1347 /*  */
1348 /* 	0xFE00h ~ 0xFE55h	USB Configuration */
1349 /*  */
1350 /*  */
1351 
1352 /* 2 USB Information (0xFE17) */
1353 #define USB_IS_HIGH_SPEED			0
1354 #define USB_IS_FULL_SPEED			1
1355 #define USB_SPEED_MASK				BIT(5)
1356 
1357 #define USB_NORMAL_SIE_EP_MASK	0xF
1358 #define USB_NORMAL_SIE_EP_SHIFT	4
1359 
1360 /* 2 Special Option */
1361 #define USB_AGG_EN				BIT(3)
1362 
1363 /*  0; Use interrupt endpoint to upload interrupt pkt */
1364 /*  1; Use bulk endpoint to upload interrupt pkt, */
1365 #define INT_BULK_SEL			BIT(4)
1366 
1367 /* 2REG_C2HEVT_CLEAR */
1368 #define C2H_EVT_HOST_CLOSE		0x00	/*  Set by driver and notify FW that the driver has read the C2H command message */
1369 #define C2H_EVT_FW_CLOSE		0xFF	/*  Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */
1370 
1371 
1372 /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
1373 #define WL_HWPDN_EN			BIT0	/*  Enable GPIO[9] as WiFi HW PDn source */
1374 #define WL_HWPDN_SL			BIT1	/*  WiFi HW PDn polarity control */
1375 #define WL_FUNC_EN				BIT2	/*  WiFi function enable */
1376 #define WL_HWROF_EN			BIT3	/*  Enable GPIO[9] as WiFi RF HW PDn source */
1377 #define BT_HWPDN_EN			BIT16	/*  Enable GPIO[11] as BT HW PDn source */
1378 #define BT_HWPDN_SL			BIT17	/*  BT HW PDn polarity control */
1379 #define BT_FUNC_EN				BIT18	/*  BT function enable */
1380 #define BT_HWROF_EN			BIT19	/*  Enable GPIO[11] as BT/GPS RF HW PDn source */
1381 #define GPS_HWPDN_EN			BIT20	/*  Enable GPIO[10] as GPS HW PDn source */
1382 #define GPS_HWPDN_SL			BIT21	/*  GPS HW PDn polarity control */
1383 #define GPS_FUNC_EN			BIT22	/*  GPS function enable */
1384 
1385 /*  */
1386 /*  General definitions */
1387 /*  */
1388 
1389 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B		255
1390 
1391 #define POLLING_LLT_THRESHOLD				20
1392 #define POLLING_READY_TIMEOUT_COUNT		1000
1393 
1394 #endif /* __HAL_COMMON_H__ */
1395