1 /* 2 * HP i8042 System Device Controller -- header 3 * 4 * Copyright (c) 2001 Brian S. Julin 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * 29 * References: 30 * 31 * HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A 32 * 33 * System Device Controller Microprocessor Firmware Theory of Operation 34 * for Part Number 1820-4784 Revision B. Dwg No. A-1820-4784-2 35 * 36 */ 37 38 #ifndef _LINUX_HP_SDC_H 39 #define _LINUX_HP_SDC_H 40 41 #include <linux/interrupt.h> 42 #include <linux/types.h> 43 #include <linux/time.h> 44 #include <linux/timer.h> 45 #include <asm/hardware.h> 46 47 48 /* No 4X status reads take longer than this (in usec). 49 */ 50 #define HP_SDC_MAX_REG_DELAY 20000 51 52 typedef void (hp_sdc_irqhook) (int irq, void *dev_id, 53 uint8_t status, uint8_t data); 54 55 int hp_sdc_request_timer_irq(hp_sdc_irqhook *callback); 56 int hp_sdc_request_hil_irq(hp_sdc_irqhook *callback); 57 int hp_sdc_request_cooked_irq(hp_sdc_irqhook *callback); 58 int hp_sdc_release_timer_irq(hp_sdc_irqhook *callback); 59 int hp_sdc_release_hil_irq(hp_sdc_irqhook *callback); 60 int hp_sdc_release_cooked_irq(hp_sdc_irqhook *callback); 61 62 typedef struct { 63 int actidx; /* Start of act. Acts are atomic WRT I/O to SDC */ 64 int idx; /* Index within the act */ 65 int endidx; /* transaction is over and done if idx == endidx */ 66 uint8_t *seq; /* commands/data for the transaction */ 67 union { 68 hp_sdc_irqhook *irqhook; /* Callback, isr or tasklet context */ 69 struct semaphore *semaphore; /* Semaphore to sleep on. */ 70 } act; 71 } hp_sdc_transaction; 72 int hp_sdc_enqueue_transaction(hp_sdc_transaction *this); 73 int hp_sdc_dequeue_transaction(hp_sdc_transaction *this); 74 75 /* The HP_SDC_ACT* values are peculiar to this driver. 76 * Nuance: never HP_SDC_ACT_DATAIN | HP_SDC_ACT_DEALLOC, use another 77 * act to perform the dealloc. 78 */ 79 #define HP_SDC_ACT_PRECMD 0x01 /* Send a command first */ 80 #define HP_SDC_ACT_DATAREG 0x02 /* Set data registers */ 81 #define HP_SDC_ACT_DATAOUT 0x04 /* Send data bytes */ 82 #define HP_SDC_ACT_POSTCMD 0x08 /* Send command after */ 83 #define HP_SDC_ACT_DATAIN 0x10 /* Collect data after */ 84 #define HP_SDC_ACT_DURING 0x1f 85 #define HP_SDC_ACT_SEMAPHORE 0x20 /* Raise semaphore after */ 86 #define HP_SDC_ACT_CALLBACK 0x40 /* Pass data to IRQ handler */ 87 #define HP_SDC_ACT_DEALLOC 0x80 /* Destroy transaction after */ 88 #define HP_SDC_ACT_AFTER 0xe0 89 #define HP_SDC_ACT_DEAD 0x60 /* Act timed out. */ 90 91 /* Rest of the flags are straightforward representation of the SDC interface */ 92 #define HP_SDC_STATUS_IBF 0x02 /* Input buffer full */ 93 94 #define HP_SDC_STATUS_IRQMASK 0xf0 /* Bits containing "level 1" irq */ 95 #define HP_SDC_STATUS_PERIODIC 0x10 /* Periodic 10ms timer */ 96 #define HP_SDC_STATUS_USERTIMER 0x20 /* "Special purpose" timer */ 97 #define HP_SDC_STATUS_TIMER 0x30 /* Both PERIODIC and USERTIMER */ 98 #define HP_SDC_STATUS_REG 0x40 /* Data from an i8042 register */ 99 #define HP_SDC_STATUS_HILCMD 0x50 /* Command from HIL MLC */ 100 #define HP_SDC_STATUS_HILDATA 0x60 /* Data from HIL MLC */ 101 #define HP_SDC_STATUS_PUP 0x70 /* Sucessful power-up self test */ 102 #define HP_SDC_STATUS_KCOOKED 0x80 /* Key from cooked kbd */ 103 #define HP_SDC_STATUS_KRPG 0xc0 /* Key from Repeat Gen */ 104 #define HP_SDC_STATUS_KMOD_SUP 0x10 /* Shift key is up */ 105 #define HP_SDC_STATUS_KMOD_CUP 0x20 /* Control key is up */ 106 107 #define HP_SDC_NMISTATUS_FHS 0x40 /* NMI is a fast handshake irq */ 108 109 /* Internal i8042 registers (there are more, but they are not too useful). */ 110 111 #define HP_SDC_USE 0x02 /* Resource usage (including OB bit) */ 112 #define HP_SDC_IM 0x04 /* Interrupt mask */ 113 #define HP_SDC_CFG 0x11 /* Configuration register */ 114 #define HP_SDC_KBLANGUAGE 0x12 /* Keyboard language */ 115 116 #define HP_SDC_D0 0x70 /* General purpose data buffer 0 */ 117 #define HP_SDC_D1 0x71 /* General purpose data buffer 1 */ 118 #define HP_SDC_D2 0x72 /* General purpose data buffer 2 */ 119 #define HP_SDC_D3 0x73 /* General purpose data buffer 3 */ 120 #define HP_SDC_VT1 0x74 /* Timer for voice 1 */ 121 #define HP_SDC_VT2 0x75 /* Timer for voice 2 */ 122 #define HP_SDC_VT3 0x76 /* Timer for voice 3 */ 123 #define HP_SDC_VT4 0x77 /* Timer for voice 4 */ 124 #define HP_SDC_KBN 0x78 /* Which HIL devs are Nimitz */ 125 #define HP_SDC_KBC 0x79 /* Which HIL devs are cooked kbds */ 126 #define HP_SDC_LPS 0x7a /* i8042's view of HIL status */ 127 #define HP_SDC_LPC 0x7b /* i8042's view of HIL "control" */ 128 #define HP_SDC_RSV 0x7c /* Reserved "for testing" */ 129 #define HP_SDC_LPR 0x7d /* i8042 count of HIL reconfigs */ 130 #define HP_SDC_XTD 0x7e /* "Extended Configuration" register */ 131 #define HP_SDC_STR 0x7f /* i8042 self-test result */ 132 133 /* Bitfields for above registers */ 134 #define HP_SDC_USE_LOOP 0x04 /* Command is currently on the loop. */ 135 136 #define HP_SDC_IM_MASK 0x1f /* these bits not part of cmd/status */ 137 #define HP_SDC_IM_FH 0x10 /* Mask the fast handshake irq */ 138 #define HP_SDC_IM_PT 0x08 /* Mask the periodic timer irq */ 139 #define HP_SDC_IM_TIMERS 0x04 /* Mask the MT/DT/CT irq */ 140 #define HP_SDC_IM_RESET 0x02 /* Mask the reset key irq */ 141 #define HP_SDC_IM_HIL 0x01 /* Mask the HIL MLC irq */ 142 143 #define HP_SDC_CFG_ROLLOVER 0x08 /* WTF is "N-key rollover"? */ 144 #define HP_SDC_CFG_KBD 0x10 /* There is a keyboard */ 145 #define HP_SDC_CFG_NEW 0x20 /* Supports/uses HIL MLC */ 146 #define HP_SDC_CFG_KBD_OLD 0x03 /* keyboard code for non-HIL */ 147 #define HP_SDC_CFG_KBD_NEW 0x07 /* keyboard code from HIL autoconfig */ 148 #define HP_SDC_CFG_REV 0x40 /* Code revision bit */ 149 #define HP_SDC_CFG_IDPROM 0x80 /* IDPROM present in kbd (not HIL) */ 150 151 #define HP_SDC_LPS_NDEV 0x07 /* # devices autoconfigured on HIL */ 152 #define HP_SDC_LPS_ACSUCC 0x08 /* loop autoconfigured successfully */ 153 #define HP_SDC_LPS_ACFAIL 0x80 /* last loop autoconfigure failed */ 154 155 #define HP_SDC_LPC_APE_IPF 0x01 /* HIL MLC APE/IPF (autopoll) set */ 156 #define HP_SDC_LPC_ARCONERR 0x02 /* i8042 autoreconfigs loop on err */ 157 #define HP_SDC_LPC_ARCQUIET 0x03 /* i8042 doesn't report autoreconfigs*/ 158 #define HP_SDC_LPC_COOK 0x10 /* i8042 cooks devices in _KBN */ 159 #define HP_SDC_LPC_RC 0x80 /* causes autoreconfig */ 160 161 #define HP_SDC_XTD_REV 0x07 /* contains revision code */ 162 #define HP_SDC_XTD_REV_STRINGS(val, str) \ 163 switch (val) { \ 164 case 0x1: str = "1820-3712"; break; \ 165 case 0x2: str = "1820-4379"; break; \ 166 case 0x3: str = "1820-4784"; break; \ 167 default: str = "unknown"; \ 168 }; 169 #define HP_SDC_XTD_BEEPER 0x08 /* TI SN76494 beeper available */ 170 #define HP_SDC_XTD_BBRTC 0x20 /* OKI MSM-58321 BBRTC present */ 171 172 #define HP_SDC_CMD_LOAD_RT 0x31 /* Load real time (from 8042) */ 173 #define HP_SDC_CMD_LOAD_FHS 0x36 /* Load the fast handshake timer */ 174 #define HP_SDC_CMD_LOAD_MT 0x38 /* Load the match timer */ 175 #define HP_SDC_CMD_LOAD_DT 0x3B /* Load the delay timer */ 176 #define HP_SDC_CMD_LOAD_CT 0x3E /* Load the cycle timer */ 177 178 #define HP_SDC_CMD_SET_IM 0x40 /* 010xxxxx == set irq mask */ 179 180 /* The documents provided do not explicitly state that all registers betweem 181 * 0x01 and 0x1f inclusive can be read by sending their register index as a 182 * command, but this is implied and appears to be the case. 183 */ 184 #define HP_SDC_CMD_READ_RAM 0x00 /* Load from i8042 RAM (autoinc) */ 185 #define HP_SDC_CMD_READ_USE 0x02 /* Undocumented! Load from usage reg */ 186 #define HP_SDC_CMD_READ_IM 0x04 /* Load current interrupt mask */ 187 #define HP_SDC_CMD_READ_KCC 0x11 /* Load primary kbd config code */ 188 #define HP_SDC_CMD_READ_KLC 0x12 /* Load primary kbd language code */ 189 #define HP_SDC_CMD_READ_T1 0x13 /* Load timer output buffer byte 1 */ 190 #define HP_SDC_CMD_READ_T2 0x14 /* Load timer output buffer byte 1 */ 191 #define HP_SDC_CMD_READ_T3 0x15 /* Load timer output buffer byte 1 */ 192 #define HP_SDC_CMD_READ_T4 0x16 /* Load timer output buffer byte 1 */ 193 #define HP_SDC_CMD_READ_T5 0x17 /* Load timer output buffer byte 1 */ 194 #define HP_SDC_CMD_READ_D0 0xf0 /* Load from i8042 RAM location 0x70 */ 195 #define HP_SDC_CMD_READ_D1 0xf1 /* Load from i8042 RAM location 0x71 */ 196 #define HP_SDC_CMD_READ_D2 0xf2 /* Load from i8042 RAM location 0x72 */ 197 #define HP_SDC_CMD_READ_D3 0xf3 /* Load from i8042 RAM location 0x73 */ 198 #define HP_SDC_CMD_READ_VT1 0xf4 /* Load from i8042 RAM location 0x74 */ 199 #define HP_SDC_CMD_READ_VT2 0xf5 /* Load from i8042 RAM location 0x75 */ 200 #define HP_SDC_CMD_READ_VT3 0xf6 /* Load from i8042 RAM location 0x76 */ 201 #define HP_SDC_CMD_READ_VT4 0xf7 /* Load from i8042 RAM location 0x77 */ 202 #define HP_SDC_CMD_READ_KBN 0xf8 /* Load from i8042 RAM location 0x78 */ 203 #define HP_SDC_CMD_READ_KBC 0xf9 /* Load from i8042 RAM location 0x79 */ 204 #define HP_SDC_CMD_READ_LPS 0xfa /* Load from i8042 RAM location 0x7a */ 205 #define HP_SDC_CMD_READ_LPC 0xfb /* Load from i8042 RAM location 0x7b */ 206 #define HP_SDC_CMD_READ_RSV 0xfc /* Load from i8042 RAM location 0x7c */ 207 #define HP_SDC_CMD_READ_LPR 0xfd /* Load from i8042 RAM location 0x7d */ 208 #define HP_SDC_CMD_READ_XTD 0xfe /* Load from i8042 RAM location 0x7e */ 209 #define HP_SDC_CMD_READ_STR 0xff /* Load from i8042 RAM location 0x7f */ 210 211 #define HP_SDC_CMD_SET_ARD 0xA0 /* Set emulated autorepeat delay */ 212 #define HP_SDC_CMD_SET_ARR 0xA2 /* Set emulated autorepeat rate */ 213 #define HP_SDC_CMD_SET_BELL 0xA3 /* Set voice 3 params for "beep" cmd */ 214 #define HP_SDC_CMD_SET_RPGR 0xA6 /* Set "RPG" irq rate (doesn't work) */ 215 #define HP_SDC_CMD_SET_RTMS 0xAD /* Set the RTC time (milliseconds) */ 216 #define HP_SDC_CMD_SET_RTD 0xAF /* Set the RTC time (days) */ 217 #define HP_SDC_CMD_SET_FHS 0xB2 /* Set fast handshake timer */ 218 #define HP_SDC_CMD_SET_MT 0xB4 /* Set match timer */ 219 #define HP_SDC_CMD_SET_DT 0xB7 /* Set delay timer */ 220 #define HP_SDC_CMD_SET_CT 0xBA /* Set cycle timer */ 221 #define HP_SDC_CMD_SET_RAMP 0xC1 /* Reset READ_RAM autoinc counter */ 222 #define HP_SDC_CMD_SET_D0 0xe0 /* Load to i8042 RAM location 0x70 */ 223 #define HP_SDC_CMD_SET_D1 0xe1 /* Load to i8042 RAM location 0x71 */ 224 #define HP_SDC_CMD_SET_D2 0xe2 /* Load to i8042 RAM location 0x72 */ 225 #define HP_SDC_CMD_SET_D3 0xe3 /* Load to i8042 RAM location 0x73 */ 226 #define HP_SDC_CMD_SET_VT1 0xe4 /* Load to i8042 RAM location 0x74 */ 227 #define HP_SDC_CMD_SET_VT2 0xe5 /* Load to i8042 RAM location 0x75 */ 228 #define HP_SDC_CMD_SET_VT3 0xe6 /* Load to i8042 RAM location 0x76 */ 229 #define HP_SDC_CMD_SET_VT4 0xe7 /* Load to i8042 RAM location 0x77 */ 230 #define HP_SDC_CMD_SET_KBN 0xe8 /* Load to i8042 RAM location 0x78 */ 231 #define HP_SDC_CMD_SET_KBC 0xe9 /* Load to i8042 RAM location 0x79 */ 232 #define HP_SDC_CMD_SET_LPS 0xea /* Load to i8042 RAM location 0x7a */ 233 #define HP_SDC_CMD_SET_LPC 0xeb /* Load to i8042 RAM location 0x7b */ 234 #define HP_SDC_CMD_SET_RSV 0xec /* Load to i8042 RAM location 0x7c */ 235 #define HP_SDC_CMD_SET_LPR 0xed /* Load to i8042 RAM location 0x7d */ 236 #define HP_SDC_CMD_SET_XTD 0xee /* Load to i8042 RAM location 0x7e */ 237 #define HP_SDC_CMD_SET_STR 0xef /* Load to i8042 RAM location 0x7f */ 238 239 #define HP_SDC_CMD_DO_RTCW 0xc2 /* i8042 RAM 0x70 --> RTC */ 240 #define HP_SDC_CMD_DO_RTCR 0xc3 /* RTC[0x70 0:3] --> irq/status/data */ 241 #define HP_SDC_CMD_DO_BEEP 0xc4 /* i8042 RAM 0x70-74 --> beeper,VT3 */ 242 #define HP_SDC_CMD_DO_HIL 0xc5 /* i8042 RAM 0x70-73 --> 243 HIL MLC R0,R1 i8042 HIL watchdog */ 244 245 /* Values used to (de)mangle input/output to/from the HIL MLC */ 246 #define HP_SDC_DATA 0x40 /* Data from an 8042 register */ 247 #define HP_SDC_HIL_CMD 0x50 /* Data from HIL MLC R1/8042 */ 248 #define HP_SDC_HIL_R1MASK 0x0f /* Contents of HIL MLC R1 0:3 */ 249 #define HP_SDC_HIL_AUTO 0x10 /* Set if POL results from i8042 */ 250 #define HP_SDC_HIL_ISERR 0x80 /* Has meaning as in next 4 values */ 251 #define HP_SDC_HIL_RC_DONE 0x80 /* i8042 auto-configured loop */ 252 #define HP_SDC_HIL_ERR 0x81 /* HIL MLC R2 had a bit set */ 253 #define HP_SDC_HIL_TO 0x82 /* i8042 HIL watchdog expired */ 254 #define HP_SDC_HIL_RC 0x84 /* i8042 is auto-configuring loop */ 255 #define HP_SDC_HIL_DAT 0x60 /* Data from HIL MLC R0 */ 256 257 258 typedef struct { 259 rwlock_t ibf_lock; 260 rwlock_t lock; /* user/tasklet lock */ 261 rwlock_t rtq_lock; /* isr/tasklet lock */ 262 rwlock_t hook_lock; /* isr/user lock for handler add/del */ 263 264 unsigned int irq, nmi; /* Our IRQ lines */ 265 unsigned long base_io, status_io, data_io; /* Our IO ports */ 266 267 uint8_t im; /* Interrupt mask */ 268 int set_im; /* Interrupt mask needs to be set. */ 269 270 int ibf; /* Last known status of IBF flag */ 271 uint8_t wi; /* current i8042 write index */ 272 uint8_t r7[4]; /* current i8042[0x70 - 0x74] values */ 273 uint8_t r11, r7e; /* Values from version/revision regs */ 274 275 hp_sdc_irqhook *timer, *reg, *hil, *pup, *cooked; 276 277 #define HP_SDC_QUEUE_LEN 16 278 hp_sdc_transaction *tq[HP_SDC_QUEUE_LEN]; /* All pending read/writes */ 279 280 int rcurr, rqty; /* Current read transact in process */ 281 struct timeval rtv; /* Time when current read started */ 282 int wcurr; /* Current write transact in process */ 283 284 #ifdef __hppa__ 285 struct parisc_device *dev; 286 int dev_err; /* carries status from registration */ 287 #else 288 #error No support for device registration on this arch yet. 289 #endif 290 291 struct timer_list kicker; /* Keeps below task alive */ 292 struct tasklet_struct task; 293 294 } hp_i8042_sdc; 295 296 #endif /* _LINUX_HP_SDC_H */ 297