1 #ifndef __IBMPHP_H
2 #define __IBMPHP_H
3
4 /*
5 * IBM Hot Plug Controller Driver
6 *
7 * Written By: Jyoti Shah, Tong Yu, Irene Zubarev, IBM Corporation
8 *
9 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
10 * Copyright (C) 2001,2002 IBM Corp.
11 *
12 * All rights reserved.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or (at
17 * your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful, but
20 * WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
22 * NON INFRINGEMENT. See the GNU General Public License for more
23 * details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 * Send feedback to <gregkh@us.ibm.com>
30 *
31 */
32
33 #include "pci_hotplug.h"
34
35 extern int ibmphp_debug;
36
37 #if !defined(CONFIG_HOTPLUG_PCI_IBM_MODULE)
38 #define MY_NAME "ibmphpd"
39 #else
40 #define MY_NAME THIS_MODULE->name
41 #endif
42 #define debug(fmt, arg...) do { if (ibmphp_debug == 1) printk(KERN_DEBUG "%s: " fmt , MY_NAME , ## arg); } while (0)
43 #define debug_pci(fmt, arg...) do { if (ibmphp_debug) printk(KERN_DEBUG "%s: " fmt , MY_NAME , ## arg); } while (0)
44 #define err(format, arg...) printk(KERN_ERR "%s: " format , MY_NAME , ## arg)
45 #define info(format, arg...) printk(KERN_INFO "%s: " format , MY_NAME , ## arg)
46 #define warn(format, arg...) printk(KERN_WARNING "%s: " format , MY_NAME , ## arg)
47
48
49 /* EBDA stuff */
50
51 /***********************************************************
52 * SLOT CAPABILITY *
53 ***********************************************************/
54
55 #define EBDA_SLOT_133_MAX 0x20
56 #define EBDA_SLOT_100_MAX 0x10
57 #define EBDA_SLOT_66_MAX 0x02
58 #define EBDA_SLOT_PCIX_CAP 0x08
59
60
61 /************************************************************
62 * RESOURE TYPE *
63 ************************************************************/
64
65 #define EBDA_RSRC_TYPE_MASK 0x03
66 #define EBDA_IO_RSRC_TYPE 0x00
67 #define EBDA_MEM_RSRC_TYPE 0x01
68 #define EBDA_PFM_RSRC_TYPE 0x03
69 #define EBDA_RES_RSRC_TYPE 0x02
70
71
72 /*************************************************************
73 * IO RESTRICTION TYPE *
74 *************************************************************/
75
76 #define EBDA_IO_RESTRI_MASK 0x0c
77 #define EBDA_NO_RESTRI 0x00
78 #define EBDA_AVO_VGA_ADDR 0x04
79 #define EBDA_AVO_VGA_ADDR_AND_ALIA 0x08
80 #define EBDA_AVO_ISA_ADDR 0x0c
81
82
83 /**************************************************************
84 * DEVICE TYPE DEF *
85 **************************************************************/
86
87 #define EBDA_DEV_TYPE_MASK 0x10
88 #define EBDA_PCI_DEV 0x10
89 #define EBDA_NON_PCI_DEV 0x00
90
91
92 /***************************************************************
93 * PRIMARY DEF DEFINITION *
94 ***************************************************************/
95
96 #define EBDA_PRI_DEF_MASK 0x20
97 #define EBDA_PRI_PCI_BUS_INFO 0x20
98 #define EBDA_NORM_DEV_RSRC_INFO 0x00
99
100
101 //--------------------------------------------------------------
102 // RIO TABLE DATA STRUCTURE
103 //--------------------------------------------------------------
104
105 struct rio_table_hdr {
106 u8 ver_num;
107 u8 scal_count;
108 u8 riodev_count;
109 u16 offset;
110 };
111
112 //-------------------------------------------------------------
113 // SCALABILITY DETAIL
114 //-------------------------------------------------------------
115
116 struct scal_detail {
117 u8 node_id;
118 u32 cbar;
119 u8 port0_node_connect;
120 u8 port0_port_connect;
121 u8 port1_node_connect;
122 u8 port1_port_connect;
123 u8 port2_node_connect;
124 u8 port2_port_connect;
125 u8 chassis_num;
126 // struct list_head scal_detail_list;
127 };
128
129 //--------------------------------------------------------------
130 // RIO DETAIL
131 //--------------------------------------------------------------
132
133 struct rio_detail {
134 u8 rio_node_id;
135 u32 bbar;
136 u8 rio_type;
137 u8 owner_id;
138 u8 port0_node_connect;
139 u8 port0_port_connect;
140 u8 port1_node_connect;
141 u8 port1_port_connect;
142 u8 first_slot_num;
143 u8 status;
144 u8 wpindex;
145 u8 chassis_num;
146 struct list_head rio_detail_list;
147 };
148
149 struct opt_rio {
150 u8 rio_type;
151 u8 chassis_num;
152 u8 first_slot_num;
153 u8 middle_num;
154 struct list_head opt_rio_list;
155 };
156
157 struct opt_rio_lo {
158 u8 rio_type;
159 u8 chassis_num;
160 u8 first_slot_num;
161 u8 middle_num;
162 u8 pack_count;
163 struct list_head opt_rio_lo_list;
164 };
165
166 /****************************************************************
167 * HPC DESCRIPTOR NODE *
168 ****************************************************************/
169
170 struct ebda_hpc_list {
171 u8 format;
172 u16 num_ctlrs;
173 short phys_addr;
174 // struct list_head ebda_hpc_list;
175 };
176 /*****************************************************************
177 * IN HPC DATA STRUCTURE, THE ASSOCIATED SLOT AND BUS *
178 * STRUCTURE *
179 *****************************************************************/
180
181 struct ebda_hpc_slot {
182 u8 slot_num;
183 u32 slot_bus_num;
184 u8 ctl_index;
185 u8 slot_cap;
186 };
187
188 struct ebda_hpc_bus {
189 u32 bus_num;
190 u8 slots_at_33_conv;
191 u8 slots_at_66_conv;
192 u8 slots_at_66_pcix;
193 u8 slots_at_100_pcix;
194 u8 slots_at_133_pcix;
195 };
196
197
198 /********************************************************************
199 * THREE TYPE OF HOT PLUG CONTROLER *
200 ********************************************************************/
201
202 struct isa_ctlr_access {
203 u16 io_start;
204 u16 io_end;
205 };
206
207 struct pci_ctlr_access {
208 u8 bus;
209 u8 dev_fun;
210 };
211
212 struct wpeg_i2c_ctlr_access {
213 ulong wpegbbar;
214 u8 i2c_addr;
215 };
216
217 #define HPC_DEVICE_ID 0x0246
218 #define HPC_SUBSYSTEM_ID 0x0247
219 #define HPC_PCI_OFFSET 0x40
220 /*************************************************************************
221 * RSTC DESCRIPTOR NODE *
222 *************************************************************************/
223
224 struct ebda_rsrc_list {
225 u8 format;
226 u16 num_entries;
227 u16 phys_addr;
228 struct ebda_rsrc_list *next;
229 };
230
231
232 /***************************************************************************
233 * PCI RSRC NODE *
234 ***************************************************************************/
235
236 struct ebda_pci_rsrc {
237 u8 rsrc_type;
238 u8 bus_num;
239 u8 dev_fun;
240 u32 start_addr;
241 u32 end_addr;
242 u8 marked; /* for NVRAM */
243 struct list_head ebda_pci_rsrc_list;
244 };
245
246
247 /***********************************************************
248 * BUS_INFO DATE STRUCTURE *
249 ***********************************************************/
250
251 struct bus_info {
252 u8 slot_min;
253 u8 slot_max;
254 u8 slot_count;
255 u8 busno;
256 u8 controller_id;
257 u8 current_speed;
258 u8 current_bus_mode;
259 u8 index;
260 u8 slots_at_33_conv;
261 u8 slots_at_66_conv;
262 u8 slots_at_66_pcix;
263 u8 slots_at_100_pcix;
264 u8 slots_at_133_pcix;
265 struct list_head bus_info_list;
266 };
267
268
269 /***********************************************************
270 * GLOBAL VARIABLES *
271 ***********************************************************/
272 extern struct list_head ibmphp_ebda_pci_rsrc_head;
273 extern struct list_head ibmphp_slot_head;
274 extern struct list_head ibmphp_res_head;
275 /***********************************************************
276 * FUNCTION PROTOTYPES *
277 ***********************************************************/
278
279 extern void ibmphp_free_ebda_hpc_queue (void);
280 extern int ibmphp_access_ebda (void);
281 extern struct slot *ibmphp_get_slot_from_physical_num (u8);
282 extern int ibmphp_get_total_hp_slots (void);
283 extern void ibmphp_free_ibm_slot (struct slot *);
284 extern void ibmphp_free_bus_info_queue (void);
285 extern void ibmphp_free_ebda_pci_rsrc_queue (void);
286 extern struct bus_info *ibmphp_find_same_bus_num (u32);
287 extern int ibmphp_get_bus_index (u8);
288 extern u16 ibmphp_get_total_controllers (void);
289 extern int ibmphp_register_pci (void);
290
291 /* passed parameters */
292 #define MEM 0
293 #define IO 1
294 #define PFMEM 2
295
296 /* bit masks */
297 #define RESTYPE 0x03
298 #define IOMASK 0x00 /* will need to take its complement */
299 #define MMASK 0x01
300 #define PFMASK 0x03
301 #define PCIDEVMASK 0x10 /* we should always have PCI devices */
302 #define PRIMARYBUSMASK 0x20
303
304 /* pci specific defines */
305 #define PCI_VENDOR_ID_NOTVALID 0xFFFF
306 #define PCI_HEADER_TYPE_MULTIDEVICE 0x80
307 #define PCI_HEADER_TYPE_MULTIBRIDGE 0x81
308
309 #define LATENCY 0x64
310 #define CACHE 64
311 #define DEVICEENABLE 0x015F /* CPQ has 0x0157 */
312
313 #define IOBRIDGE 0x1000 /* 4k */
314 #define MEMBRIDGE 0x100000 /* 1M */
315
316 /* irqs */
317 #define SCSI_IRQ 0x09
318 #define LAN_IRQ 0x0A
319 #define OTHER_IRQ 0x0B
320
321 /* Data Structures */
322
323 /* type is of the form x x xx xx
324 * | | | |_ 00 - I/O, 01 - Memory, 11 - PFMemory
325 * | | - 00 - No Restrictions, 01 - Avoid VGA, 10 - Avoid
326 * | | VGA and their aliases, 11 - Avoid ISA
327 * | - 1 - PCI device, 0 - non pci device
328 * - 1 - Primary PCI Bus Information (0 if Normal device)
329 * the IO restrictions [2:3] are only for primary buses
330 */
331
332
333 /* we need this struct because there could be several resource blocks
334 * allocated per primary bus in the EBDA
335 */
336 struct range_node {
337 int rangeno;
338 u32 start;
339 u32 end;
340 struct range_node *next;
341 };
342
343 struct bus_node {
344 u8 busno;
345 int noIORanges;
346 struct range_node *rangeIO;
347 int noMemRanges;
348 struct range_node *rangeMem;
349 int noPFMemRanges;
350 struct range_node *rangePFMem;
351 int needIOUpdate;
352 int needMemUpdate;
353 int needPFMemUpdate;
354 struct resource_node *firstIO; /* first IO resource on the Bus */
355 struct resource_node *firstMem; /* first memory resource on the Bus */
356 struct resource_node *firstPFMem; /* first prefetchable memory resource on the Bus */
357 struct resource_node *firstPFMemFromMem; /* when run out of pfmem available, taking from Mem */
358 struct list_head bus_list;
359 };
360
361 struct resource_node {
362 int rangeno;
363 u8 busno;
364 u8 devfunc;
365 u32 start;
366 u32 end;
367 u32 len;
368 int type; /* MEM, IO, PFMEM */
369 u8 fromMem; /* this is to indicate that the range is from
370 * from the Memory bucket rather than from PFMem */
371 struct resource_node *next;
372 struct resource_node *nextRange; /* for the other mem range on bus */
373 };
374
375 struct res_needed {
376 u32 mem;
377 u32 pfmem;
378 u32 io;
379 u8 not_correct; /* needed for return */
380 int devices[32]; /* for device numbers behind this bridge */
381 };
382
383 /* functions */
384
385 extern int ibmphp_rsrc_init (void);
386 extern int ibmphp_add_resource (struct resource_node *);
387 extern int ibmphp_remove_resource (struct resource_node *);
388 extern int ibmphp_find_resource (struct bus_node *, u32, struct resource_node **, int);
389 extern int ibmphp_check_resource (struct resource_node *, u8);
390 extern int ibmphp_remove_bus (struct bus_node *, u8);
391 extern void ibmphp_free_resources (void);
392 extern int ibmphp_add_pfmem_from_mem (struct resource_node *);
393 extern struct bus_node *ibmphp_find_res_bus (u8);
394 extern void ibmphp_print_test (void); /* for debugging purposes */
395
396 extern void ibmphp_hpc_initvars (void);
397 extern int ibmphp_hpc_readslot (struct slot *, u8, u8 *);
398 extern int ibmphp_hpc_writeslot (struct slot *, u8);
399 extern void ibmphp_lock_operations (void);
400 extern void ibmphp_unlock_operations (void);
401 extern int ibmphp_hpc_fillhpslotinfo (struct hotplug_slot *);
402 extern int ibmphp_hpc_start_poll_thread (void);
403 extern void ibmphp_hpc_stop_poll_thread (void);
404
405 //----------------------------------------------------------------------------
406
407
408 //----------------------------------------------------------------------------
409 // HPC return codes
410 //----------------------------------------------------------------------------
411 #define FALSE 0x00
412 #define TRUE 0x01
413 #define HPC_ERROR 0xFF
414
415 //-----------------------------------------------------------------------------
416 // BUS INFO
417 //-----------------------------------------------------------------------------
418 #define BUS_SPEED 0x30
419 #define BUS_MODE 0x40
420 #define BUS_MODE_PCIX 0x01
421 #define BUS_MODE_PCI 0x00
422 #define BUS_SPEED_2 0x20
423 #define BUS_SPEED_1 0x10
424 #define BUS_SPEED_33 0x00
425 #define BUS_SPEED_66 0x01
426 #define BUS_SPEED_100 0x02
427 #define BUS_SPEED_133 0x03
428 #define BUS_SPEED_66PCIX 0x04
429 #define BUS_SPEED_66UNKNOWN 0x05
430 #define BUS_STATUS_AVAILABLE 0x01
431 #define BUS_CONTROL_AVAILABLE 0x02
432 #define SLOT_LATCH_REGS_SUPPORTED 0x10
433
434 #define PRGM_MODEL_REV_LEVEL 0xF0
435 #define MAX_ADAPTER_NONE 0x09
436
437 //----------------------------------------------------------------------------
438 // HPC 'write' operations/commands
439 //----------------------------------------------------------------------------
440 // Command Code State Write to reg
441 // Machine at index
442 //------------------------- ---- ------- ------------
443 #define HPC_CTLR_ENABLEIRQ 0x00 // N 15
444 #define HPC_CTLR_DISABLEIRQ 0x01 // N 15
445 #define HPC_SLOT_OFF 0x02 // Y 0-14
446 #define HPC_SLOT_ON 0x03 // Y 0-14
447 #define HPC_SLOT_ATTNOFF 0x04 // N 0-14
448 #define HPC_SLOT_ATTNON 0x05 // N 0-14
449 #define HPC_CTLR_CLEARIRQ 0x06 // N 15
450 #define HPC_CTLR_RESET 0x07 // Y 15
451 #define HPC_CTLR_IRQSTEER 0x08 // N 15
452 #define HPC_BUS_33CONVMODE 0x09 // Y 31-34
453 #define HPC_BUS_66CONVMODE 0x0A // Y 31-34
454 #define HPC_BUS_66PCIXMODE 0x0B // Y 31-34
455 #define HPC_BUS_100PCIXMODE 0x0C // Y 31-34
456 #define HPC_BUS_133PCIXMODE 0x0D // Y 31-34
457 #define HPC_ALLSLOT_OFF 0x11 // Y 15
458 #define HPC_ALLSLOT_ON 0x12 // Y 15
459 #define HPC_SLOT_BLINKLED 0x13 // N 0-14
460
461 //----------------------------------------------------------------------------
462 // read commands
463 //----------------------------------------------------------------------------
464 #define READ_SLOTSTATUS 0x01
465 #define READ_EXTSLOTSTATUS 0x02
466 #define READ_BUSSTATUS 0x03
467 #define READ_CTLRSTATUS 0x04
468 #define READ_ALLSTAT 0x05
469 #define READ_ALLSLOT 0x06
470 #define READ_SLOTLATCHLOWREG 0x07
471 #define READ_REVLEVEL 0x08
472 #define READ_HPCOPTIONS 0x09
473 //----------------------------------------------------------------------------
474 // slot status
475 //----------------------------------------------------------------------------
476 #define HPC_SLOT_POWER 0x01
477 #define HPC_SLOT_CONNECT 0x02
478 #define HPC_SLOT_ATTN 0x04
479 #define HPC_SLOT_PRSNT2 0x08
480 #define HPC_SLOT_PRSNT1 0x10
481 #define HPC_SLOT_PWRGD 0x20
482 #define HPC_SLOT_BUS_SPEED 0x40
483 #define HPC_SLOT_LATCH 0x80
484
485 //----------------------------------------------------------------------------
486 // HPC_SLOT_POWER status return codes
487 //----------------------------------------------------------------------------
488 #define HPC_SLOT_POWER_OFF 0x00
489 #define HPC_SLOT_POWER_ON 0x01
490
491 //----------------------------------------------------------------------------
492 // HPC_SLOT_CONNECT status return codes
493 //----------------------------------------------------------------------------
494 #define HPC_SLOT_CONNECTED 0x00
495 #define HPC_SLOT_DISCONNECTED 0x01
496
497 //----------------------------------------------------------------------------
498 // HPC_SLOT_ATTN status return codes
499 //----------------------------------------------------------------------------
500 #define HPC_SLOT_ATTN_OFF 0x00
501 #define HPC_SLOT_ATTN_ON 0x01
502 #define HPC_SLOT_ATTN_BLINK 0x02
503
504 //----------------------------------------------------------------------------
505 // HPC_SLOT_PRSNT status return codes
506 //----------------------------------------------------------------------------
507 #define HPC_SLOT_EMPTY 0x00
508 #define HPC_SLOT_PRSNT_7 0x01
509 #define HPC_SLOT_PRSNT_15 0x02
510 #define HPC_SLOT_PRSNT_25 0x03
511
512 //----------------------------------------------------------------------------
513 // HPC_SLOT_PWRGD status return codes
514 //----------------------------------------------------------------------------
515 #define HPC_SLOT_PWRGD_FAULT_NONE 0x00
516 #define HPC_SLOT_PWRGD_GOOD 0x01
517
518 //----------------------------------------------------------------------------
519 // HPC_SLOT_BUS_SPEED status return codes
520 //----------------------------------------------------------------------------
521 #define HPC_SLOT_BUS_SPEED_OK 0x00
522 #define HPC_SLOT_BUS_SPEED_MISM 0x01
523
524 //----------------------------------------------------------------------------
525 // HPC_SLOT_LATCH status return codes
526 //----------------------------------------------------------------------------
527 #define HPC_SLOT_LATCH_OPEN 0x01 // NOTE : in PCI spec bit off = open
528 #define HPC_SLOT_LATCH_CLOSED 0x00 // NOTE : in PCI spec bit on = closed
529
530
531 //----------------------------------------------------------------------------
532 // extended slot status
533 //----------------------------------------------------------------------------
534 #define HPC_SLOT_PCIX 0x01
535 #define HPC_SLOT_SPEED1 0x02
536 #define HPC_SLOT_SPEED2 0x04
537 #define HPC_SLOT_BLINK_ATTN 0x08
538 #define HPC_SLOT_RSRVD1 0x10
539 #define HPC_SLOT_RSRVD2 0x20
540 #define HPC_SLOT_BUS_MODE 0x40
541 #define HPC_SLOT_RSRVD3 0x80
542
543 //----------------------------------------------------------------------------
544 // HPC_XSLOT_PCIX_CAP status return codes
545 //----------------------------------------------------------------------------
546 #define HPC_SLOT_PCIX_NO 0x00
547 #define HPC_SLOT_PCIX_YES 0x01
548
549 //----------------------------------------------------------------------------
550 // HPC_XSLOT_SPEED status return codes
551 //----------------------------------------------------------------------------
552 #define HPC_SLOT_SPEED_33 0x00
553 #define HPC_SLOT_SPEED_66 0x01
554 #define HPC_SLOT_SPEED_133 0x02
555
556 //----------------------------------------------------------------------------
557 // HPC_XSLOT_ATTN_BLINK status return codes
558 //----------------------------------------------------------------------------
559 #define HPC_SLOT_ATTN_BLINK_OFF 0x00
560 #define HPC_SLOT_ATTN_BLINK_ON 0x01
561
562 //----------------------------------------------------------------------------
563 // HPC_XSLOT_BUS_MODE status return codes
564 //----------------------------------------------------------------------------
565 #define HPC_SLOT_BUS_MODE_OK 0x00
566 #define HPC_SLOT_BUS_MODE_MISM 0x01
567
568 //----------------------------------------------------------------------------
569 // Controller status
570 //----------------------------------------------------------------------------
571 #define HPC_CTLR_WORKING 0x01
572 #define HPC_CTLR_FINISHED 0x02
573 #define HPC_CTLR_RESULT0 0x04
574 #define HPC_CTLR_RESULT1 0x08
575 #define HPC_CTLR_RESULE2 0x10
576 #define HPC_CTLR_RESULT3 0x20
577 #define HPC_CTLR_IRQ_ROUTG 0x40
578 #define HPC_CTLR_IRQ_PENDG 0x80
579
580 //----------------------------------------------------------------------------
581 // HPC_CTLR_WROKING status return codes
582 //----------------------------------------------------------------------------
583 #define HPC_CTLR_WORKING_NO 0x00
584 #define HPC_CTLR_WORKING_YES 0x01
585
586 //----------------------------------------------------------------------------
587 // HPC_CTLR_FINISHED status return codes
588 //----------------------------------------------------------------------------
589 #define HPC_CTLR_FINISHED_NO 0x00
590 #define HPC_CTLR_FINISHED_YES 0x01
591
592 //----------------------------------------------------------------------------
593 // HPC_CTLR_RESULT status return codes
594 //----------------------------------------------------------------------------
595 #define HPC_CTLR_RESULT_SUCCESS 0x00
596 #define HPC_CTLR_RESULT_FAILED 0x01
597 #define HPC_CTLR_RESULT_RSVD 0x02
598 #define HPC_CTLR_RESULT_NORESP 0x03
599
600
601 //----------------------------------------------------------------------------
602 // macro for slot info
603 //----------------------------------------------------------------------------
604 #define SLOT_POWER(s) ((u8) ((s & HPC_SLOT_POWER) \
605 ? HPC_SLOT_POWER_ON : HPC_SLOT_POWER_OFF))
606
607 #define SLOT_CONNECT(s) ((u8) ((s & HPC_SLOT_CONNECT) \
608 ? HPC_SLOT_DISCONNECTED : HPC_SLOT_CONNECTED))
609
610 #define SLOT_ATTN(s,es) ((u8) ((es & HPC_SLOT_BLINK_ATTN) \
611 ? HPC_SLOT_ATTN_BLINK \
612 : ((s & HPC_SLOT_ATTN) ? HPC_SLOT_ATTN_ON : HPC_SLOT_ATTN_OFF)))
613
614 #define SLOT_PRESENT(s) ((u8) ((s & HPC_SLOT_PRSNT1) \
615 ? ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_EMPTY : HPC_SLOT_PRSNT_15) \
616 : ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_PRSNT_25 : HPC_SLOT_PRSNT_7)))
617
618 #define SLOT_PWRGD(s) ((u8) ((s & HPC_SLOT_PWRGD) \
619 ? HPC_SLOT_PWRGD_GOOD : HPC_SLOT_PWRGD_FAULT_NONE))
620
621 #define SLOT_BUS_SPEED(s) ((u8) ((s & HPC_SLOT_BUS_SPEED) \
622 ? HPC_SLOT_BUS_SPEED_MISM : HPC_SLOT_BUS_SPEED_OK))
623
624 #define SLOT_LATCH(s) ((u8) ((s & HPC_SLOT_LATCH) \
625 ? HPC_SLOT_LATCH_CLOSED : HPC_SLOT_LATCH_OPEN))
626
627 #define SLOT_PCIX(es) ((u8) ((es & HPC_SLOT_PCIX) \
628 ? HPC_SLOT_PCIX_YES : HPC_SLOT_PCIX_NO))
629
630 #define SLOT_SPEED(es) ((u8) ((es & HPC_SLOT_SPEED2) \
631 ? ((es & HPC_SLOT_SPEED1) ? HPC_SLOT_SPEED_133 \
632 : HPC_SLOT_SPEED_66) \
633 : HPC_SLOT_SPEED_33))
634
635 #define SLOT_BUS_MODE(es) ((u8) ((es & HPC_SLOT_BUS_MODE) \
636 ? HPC_SLOT_BUS_MODE_MISM : HPC_SLOT_BUS_MODE_OK))
637
638 //--------------------------------------------------------------------------
639 // macro for bus info
640 //---------------------------------------------------------------------------
641 #define CURRENT_BUS_SPEED(s) ((u8) (s & BUS_SPEED_2) \
642 ? ((s & BUS_SPEED_1) ? BUS_SPEED_133 : BUS_SPEED_100) \
643 : ((s & BUS_SPEED_1) ? BUS_SPEED_66 : BUS_SPEED_33))
644
645 #define CURRENT_BUS_MODE(s) ((u8) (s & BUS_MODE) ? BUS_MODE_PCIX : BUS_MODE_PCI)
646
647 #define READ_BUS_STATUS(s) ((u8) (s->options & BUS_STATUS_AVAILABLE))
648
649 #define READ_BUS_MODE(s) ((s->revision & PRGM_MODEL_REV_LEVEL) >= 0x20)
650
651 #define SET_BUS_STATUS(s) ((u8) (s->options & BUS_CONTROL_AVAILABLE))
652
653 #define READ_SLOT_LATCH(s) ((u8) (s->options & SLOT_LATCH_REGS_SUPPORTED))
654
655 //----------------------------------------------------------------------------
656 // macro for controller info
657 //----------------------------------------------------------------------------
658 #define CTLR_WORKING(c) ((u8) ((c & HPC_CTLR_WORKING) \
659 ? HPC_CTLR_WORKING_YES : HPC_CTLR_WORKING_NO))
660 #define CTLR_FINISHED(c) ((u8) ((c & HPC_CTLR_FINISHED) \
661 ? HPC_CTLR_FINISHED_YES : HPC_CTLR_FINISHED_NO))
662 #define CTLR_RESULT(c) ((u8) ((c & HPC_CTLR_RESULT1) \
663 ? ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_NORESP \
664 : HPC_CTLR_RESULT_RSVD) \
665 : ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_FAILED \
666 : HPC_CTLR_RESULT_SUCCESS)))
667
668 // command that affect the state machine of HPC
669 #define NEEDTOCHECK_CMDSTATUS(c) ((c == HPC_SLOT_OFF) || \
670 (c == HPC_SLOT_ON) || \
671 (c == HPC_CTLR_RESET) || \
672 (c == HPC_BUS_33CONVMODE) || \
673 (c == HPC_BUS_66CONVMODE) || \
674 (c == HPC_BUS_66PCIXMODE) || \
675 (c == HPC_BUS_100PCIXMODE) || \
676 (c == HPC_BUS_133PCIXMODE) || \
677 (c == HPC_ALLSLOT_OFF) || \
678 (c == HPC_ALLSLOT_ON))
679
680
681 /* Core part of the driver */
682
683 #define ENABLE 1
684 #define DISABLE 0
685
686 #define ADD 0
687 #define REMOVE 1
688 #define DETAIL 2
689
690 #define MAX_OPS 3
691 #define CARD_INFO 0x07
692 #define PCIX133 0x07
693 #define PCIX66 0x05
694 #define PCI66 0x04
695
696 extern struct pci_ops *ibmphp_pci_root_ops;
697
698 /* Variables */
699
700 struct pci_func {
701 struct pci_dev *dev; /* from the OS */
702 u8 busno;
703 u8 device;
704 u8 function;
705 struct resource_node *io[6];
706 struct resource_node *mem[6];
707 struct resource_node *pfmem[6];
708 struct pci_func *next;
709 int devices[32]; /* for bridge config */
710 u8 irq[4]; /* for interrupt config */
711 u8 bus; /* flag for unconfiguring, to say if PPB */
712 };
713
714 struct slot {
715 u8 bus;
716 u8 device;
717 u8 number;
718 u8 real_physical_slot_num;
719 char name[100];
720 u32 capabilities;
721 u8 supported_speed;
722 u8 supported_bus_mode;
723 struct hotplug_slot *hotplug_slot;
724 struct controller *ctrl;
725 struct pci_func *func;
726 u8 irq[4];
727 u8 flag; /* this is for disable slot and polling */
728 int bit_mode; /* 0 = 32, 1 = 64 */
729 u8 ctlr_index;
730 struct bus_info *bus_on;
731 struct list_head ibm_slot_list;
732 u8 status;
733 u8 ext_status;
734 u8 busstatus;
735 };
736
737 struct controller {
738 struct ebda_hpc_slot *slots;
739 struct ebda_hpc_bus *buses;
740 struct pci_dev *ctrl_dev; /* in case where controller is PCI */
741 u8 starting_slot_num; /* starting and ending slot #'s this ctrl controls*/
742 u8 ending_slot_num;
743 u8 revision;
744 u8 options; /* which options HPC supports */
745 u8 status;
746 u8 ctlr_id;
747 u8 slot_count;
748 u8 bus_count;
749 u8 ctlr_relative_id;
750 u32 irq;
751 union {
752 struct isa_ctlr_access isa_ctlr;
753 struct pci_ctlr_access pci_ctlr;
754 struct wpeg_i2c_ctlr_access wpeg_ctlr;
755 } u;
756 u8 ctlr_type;
757 struct list_head ebda_hpc_list;
758 };
759
760 /* Functions */
761
762 extern int ibmphp_init_devno (struct slot **); /* This function is called from EBDA, so we need it not be static */
763 extern int ibmphp_disable_slot (struct hotplug_slot *); /* This function is called from HPC, so we need it to not be static */
764 extern int ibmphp_update_slot_info (struct slot *); /* This function is called from HPC, so we need it to not be be static */
765 extern int ibmphp_configure_card (struct pci_func *, u8);
766 extern int ibmphp_unconfigure_card (struct slot **, int);
767 extern struct hotplug_slot_ops ibmphp_hotplug_slot_ops;
768
long_delay(int delay)769 static inline void long_delay (int delay)
770 {
771 set_current_state (TASK_INTERRUPTIBLE);
772 schedule_timeout (delay);
773 }
774
775 #endif //__IBMPHP_H
776
777