1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2021-2021 Hisilicon Limited.
3 
4 #ifndef __HCLGE_COMM_CMD_H
5 #define __HCLGE_COMM_CMD_H
6 #include <linux/types.h>
7 
8 #include "hnae3.h"
9 
10 #define HCLGE_COMM_CMD_FLAG_IN			BIT(0)
11 #define HCLGE_COMM_CMD_FLAG_NEXT		BIT(2)
12 #define HCLGE_COMM_CMD_FLAG_WR			BIT(3)
13 #define HCLGE_COMM_CMD_FLAG_NO_INTR		BIT(4)
14 
15 #define HCLGE_COMM_SEND_SYNC(flag) \
16 	((flag) & HCLGE_COMM_CMD_FLAG_NO_INTR)
17 
18 #define HCLGE_COMM_LINK_EVENT_REPORT_EN_B	0
19 #define HCLGE_COMM_NCSI_ERROR_REPORT_EN_B	1
20 #define HCLGE_COMM_PHY_IMP_EN_B			2
21 #define HCLGE_COMM_MAC_STATS_EXT_EN_B		3
22 #define HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B	4
23 #define HCLGE_COMM_LLRS_FEC_EN_B		5
24 
25 #define hclge_comm_dev_phy_imp_supported(ae_dev) \
26 	test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (ae_dev)->caps)
27 
28 #define HCLGE_COMM_TYPE_CRQ			0
29 #define HCLGE_COMM_TYPE_CSQ			1
30 
31 #define HCLGE_COMM_CMDQ_CLEAR_WAIT_TIME		200
32 
33 /* bar registers for cmdq */
34 #define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG	0x27000
35 #define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG	0x27004
36 #define HCLGE_COMM_NIC_CSQ_DEPTH_REG		0x27008
37 #define HCLGE_COMM_NIC_CSQ_TAIL_REG		0x27010
38 #define HCLGE_COMM_NIC_CSQ_HEAD_REG		0x27014
39 #define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG	0x27018
40 #define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG	0x2701C
41 #define HCLGE_COMM_NIC_CRQ_DEPTH_REG		0x27020
42 #define HCLGE_COMM_NIC_CRQ_TAIL_REG		0x27024
43 #define HCLGE_COMM_NIC_CRQ_HEAD_REG		0x27028
44 /* Vector0 interrupt CMDQ event source register(RW) */
45 #define HCLGE_COMM_VECTOR0_CMDQ_SRC_REG		0x27100
46 /* Vector0 interrupt CMDQ event status register(RO) */
47 #define HCLGE_COMM_VECTOR0_CMDQ_STATE_REG	0x27104
48 #define HCLGE_COMM_CMDQ_INTR_EN_REG		0x27108
49 #define HCLGE_COMM_CMDQ_INTR_GEN_REG		0x2710C
50 #define HCLGE_COMM_CMDQ_INTR_STS_REG		0x27104
51 
52 /* this bit indicates that the driver is ready for hardware reset */
53 #define HCLGE_COMM_NIC_SW_RST_RDY_B		16
54 #define HCLGE_COMM_NIC_SW_RST_RDY		BIT(HCLGE_COMM_NIC_SW_RST_RDY_B)
55 #define HCLGE_COMM_NIC_CMQ_DESC_NUM_S		3
56 #define HCLGE_COMM_NIC_CMQ_DESC_NUM		1024
57 #define HCLGE_COMM_CMDQ_TX_TIMEOUT		30000
58 
59 enum hclge_opcode_type {
60 	/* Generic commands */
61 	HCLGE_OPC_QUERY_FW_VER		= 0x0001,
62 	HCLGE_OPC_CFG_RST_TRIGGER	= 0x0020,
63 	HCLGE_OPC_GBL_RST_STATUS	= 0x0021,
64 	HCLGE_OPC_QUERY_FUNC_STATUS	= 0x0022,
65 	HCLGE_OPC_QUERY_PF_RSRC		= 0x0023,
66 	HCLGE_OPC_QUERY_VF_RSRC		= 0x0024,
67 	HCLGE_OPC_GET_CFG_PARAM		= 0x0025,
68 	HCLGE_OPC_PF_RST_DONE		= 0x0026,
69 	HCLGE_OPC_QUERY_VF_RST_RDY	= 0x0027,
70 
71 	HCLGE_OPC_STATS_64_BIT		= 0x0030,
72 	HCLGE_OPC_STATS_32_BIT		= 0x0031,
73 	HCLGE_OPC_STATS_MAC		= 0x0032,
74 	HCLGE_OPC_QUERY_MAC_REG_NUM	= 0x0033,
75 	HCLGE_OPC_STATS_MAC_ALL		= 0x0034,
76 
77 	HCLGE_OPC_QUERY_REG_NUM		= 0x0040,
78 	HCLGE_OPC_QUERY_32_BIT_REG	= 0x0041,
79 	HCLGE_OPC_QUERY_64_BIT_REG	= 0x0042,
80 	HCLGE_OPC_DFX_BD_NUM		= 0x0043,
81 	HCLGE_OPC_DFX_BIOS_COMMON_REG	= 0x0044,
82 	HCLGE_OPC_DFX_SSU_REG_0		= 0x0045,
83 	HCLGE_OPC_DFX_SSU_REG_1		= 0x0046,
84 	HCLGE_OPC_DFX_IGU_EGU_REG	= 0x0047,
85 	HCLGE_OPC_DFX_RPU_REG_0		= 0x0048,
86 	HCLGE_OPC_DFX_RPU_REG_1		= 0x0049,
87 	HCLGE_OPC_DFX_NCSI_REG		= 0x004A,
88 	HCLGE_OPC_DFX_RTC_REG		= 0x004B,
89 	HCLGE_OPC_DFX_PPP_REG		= 0x004C,
90 	HCLGE_OPC_DFX_RCB_REG		= 0x004D,
91 	HCLGE_OPC_DFX_TQP_REG		= 0x004E,
92 	HCLGE_OPC_DFX_SSU_REG_2		= 0x004F,
93 
94 	HCLGE_OPC_QUERY_DEV_SPECS	= 0x0050,
95 
96 	/* MAC command */
97 	HCLGE_OPC_CONFIG_MAC_MODE	= 0x0301,
98 	HCLGE_OPC_CONFIG_AN_MODE	= 0x0304,
99 	HCLGE_OPC_QUERY_LINK_STATUS	= 0x0307,
100 	HCLGE_OPC_CONFIG_MAX_FRM_SIZE	= 0x0308,
101 	HCLGE_OPC_CONFIG_SPEED_DUP	= 0x0309,
102 	HCLGE_OPC_QUERY_MAC_TNL_INT	= 0x0310,
103 	HCLGE_OPC_MAC_TNL_INT_EN	= 0x0311,
104 	HCLGE_OPC_CLEAR_MAC_TNL_INT	= 0x0312,
105 	HCLGE_OPC_COMMON_LOOPBACK       = 0x0315,
106 	HCLGE_OPC_QUERY_FEC_STATS	= 0x0316,
107 	HCLGE_OPC_CONFIG_FEC_MODE	= 0x031A,
108 	HCLGE_OPC_QUERY_ROH_TYPE_INFO	= 0x0389,
109 
110 	/* PTP commands */
111 	HCLGE_OPC_PTP_INT_EN		= 0x0501,
112 	HCLGE_OPC_PTP_MODE_CFG		= 0x0507,
113 
114 	/* PFC/Pause commands */
115 	HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
116 	HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
117 	HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
118 	HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
119 	HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
120 	HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
121 	HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
122 	HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
123 	HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
124 	HCLGE_OPC_QOS_MAP               = 0x070A,
125 
126 	/* ETS/scheduler commands */
127 	HCLGE_OPC_TM_PG_TO_PRI_LINK	= 0x0804,
128 	HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
129 	HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
130 	HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
131 	HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
132 	HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
133 	HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
134 	HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
135 	HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
136 	HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
137 	HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
138 	HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
139 	HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
140 	HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
141 	HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
142 	HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
143 	HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
144 	HCLGE_OPC_TM_NODES		= 0x0816,
145 	HCLGE_OPC_ETS_TC_WEIGHT		= 0x0843,
146 	HCLGE_OPC_QSET_DFX_STS		= 0x0844,
147 	HCLGE_OPC_PRI_DFX_STS		= 0x0845,
148 	HCLGE_OPC_PG_DFX_STS		= 0x0846,
149 	HCLGE_OPC_PORT_DFX_STS		= 0x0847,
150 	HCLGE_OPC_SCH_NQ_CNT		= 0x0848,
151 	HCLGE_OPC_SCH_RQ_CNT		= 0x0849,
152 	HCLGE_OPC_TM_INTERNAL_STS	= 0x0850,
153 	HCLGE_OPC_TM_INTERNAL_CNT	= 0x0851,
154 	HCLGE_OPC_TM_INTERNAL_STS_1	= 0x0852,
155 
156 	/* Packet buffer allocate commands */
157 	HCLGE_OPC_TX_BUFF_ALLOC		= 0x0901,
158 	HCLGE_OPC_RX_PRIV_BUFF_ALLOC	= 0x0902,
159 	HCLGE_OPC_RX_PRIV_WL_ALLOC	= 0x0903,
160 	HCLGE_OPC_RX_COM_THRD_ALLOC	= 0x0904,
161 	HCLGE_OPC_RX_COM_WL_ALLOC	= 0x0905,
162 	HCLGE_OPC_RX_GBL_PKT_CNT	= 0x0906,
163 
164 	/* TQP management command */
165 	HCLGE_OPC_SET_TQP_MAP		= 0x0A01,
166 
167 	/* TQP commands */
168 	HCLGE_OPC_CFG_TX_QUEUE		= 0x0B01,
169 	HCLGE_OPC_QUERY_TX_POINTER	= 0x0B02,
170 	HCLGE_OPC_QUERY_TX_STATS	= 0x0B03,
171 	HCLGE_OPC_TQP_TX_QUEUE_TC	= 0x0B04,
172 	HCLGE_OPC_CFG_RX_QUEUE		= 0x0B11,
173 	HCLGE_OPC_QUERY_RX_POINTER	= 0x0B12,
174 	HCLGE_OPC_QUERY_RX_STATS	= 0x0B13,
175 	HCLGE_OPC_STASH_RX_QUEUE_LRO	= 0x0B16,
176 	HCLGE_OPC_CFG_RX_QUEUE_LRO	= 0x0B17,
177 	HCLGE_OPC_CFG_COM_TQP_QUEUE	= 0x0B20,
178 	HCLGE_OPC_RESET_TQP_QUEUE	= 0x0B22,
179 
180 	/* PPU commands */
181 	HCLGE_OPC_PPU_PF_OTHER_INT_DFX	= 0x0B4A,
182 
183 	/* TSO command */
184 	HCLGE_OPC_TSO_GENERIC_CONFIG	= 0x0C01,
185 	HCLGE_OPC_GRO_GENERIC_CONFIG    = 0x0C10,
186 
187 	/* RSS commands */
188 	HCLGE_OPC_RSS_GENERIC_CONFIG	= 0x0D01,
189 	HCLGE_OPC_RSS_INDIR_TABLE	= 0x0D07,
190 	HCLGE_OPC_RSS_TC_MODE		= 0x0D08,
191 	HCLGE_OPC_RSS_INPUT_TUPLE	= 0x0D02,
192 
193 	/* Promisuous mode command */
194 	HCLGE_OPC_CFG_PROMISC_MODE	= 0x0E01,
195 
196 	/* Vlan offload commands */
197 	HCLGE_OPC_VLAN_PORT_TX_CFG	= 0x0F01,
198 	HCLGE_OPC_VLAN_PORT_RX_CFG	= 0x0F02,
199 
200 	/* Interrupts commands */
201 	HCLGE_OPC_ADD_RING_TO_VECTOR	= 0x1503,
202 	HCLGE_OPC_DEL_RING_TO_VECTOR	= 0x1504,
203 
204 	/* MAC commands */
205 	HCLGE_OPC_MAC_VLAN_ADD		    = 0x1000,
206 	HCLGE_OPC_MAC_VLAN_REMOVE	    = 0x1001,
207 	HCLGE_OPC_MAC_VLAN_TYPE_ID	    = 0x1002,
208 	HCLGE_OPC_MAC_VLAN_INSERT	    = 0x1003,
209 	HCLGE_OPC_MAC_VLAN_ALLOCATE	    = 0x1004,
210 	HCLGE_OPC_MAC_ETHTYPE_ADD	    = 0x1010,
211 	HCLGE_OPC_MAC_ETHTYPE_REMOVE	= 0x1011,
212 
213 	/* MAC VLAN commands */
214 	HCLGE_OPC_MAC_VLAN_SWITCH_PARAM	= 0x1033,
215 
216 	/* VLAN commands */
217 	HCLGE_OPC_VLAN_FILTER_CTRL	    = 0x1100,
218 	HCLGE_OPC_VLAN_FILTER_PF_CFG	= 0x1101,
219 	HCLGE_OPC_VLAN_FILTER_VF_CFG	= 0x1102,
220 	HCLGE_OPC_PORT_VLAN_BYPASS	= 0x1103,
221 
222 	/* Flow Director commands */
223 	HCLGE_OPC_FD_MODE_CTRL		= 0x1200,
224 	HCLGE_OPC_FD_GET_ALLOCATION	= 0x1201,
225 	HCLGE_OPC_FD_KEY_CONFIG		= 0x1202,
226 	HCLGE_OPC_FD_TCAM_OP		= 0x1203,
227 	HCLGE_OPC_FD_AD_OP		= 0x1204,
228 	HCLGE_OPC_FD_CNT_OP		= 0x1205,
229 	HCLGE_OPC_FD_USER_DEF_OP	= 0x1207,
230 	HCLGE_OPC_FD_QB_CTRL		= 0x1210,
231 	HCLGE_OPC_FD_QB_AD_OP		= 0x1211,
232 
233 	/* MDIO command */
234 	HCLGE_OPC_MDIO_CONFIG		= 0x1900,
235 
236 	/* QCN commands */
237 	HCLGE_OPC_QCN_MOD_CFG		= 0x1A01,
238 	HCLGE_OPC_QCN_GRP_TMPLT_CFG	= 0x1A02,
239 	HCLGE_OPC_QCN_SHAPPING_CFG	= 0x1A03,
240 	HCLGE_OPC_QCN_SHAPPING_BS_CFG	= 0x1A04,
241 	HCLGE_OPC_QCN_QSET_LINK_CFG	= 0x1A05,
242 	HCLGE_OPC_QCN_RP_STATUS_GET	= 0x1A06,
243 	HCLGE_OPC_QCN_AJUST_INIT	= 0x1A07,
244 	HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
245 
246 	/* Mailbox command */
247 	HCLGEVF_OPC_MBX_PF_TO_VF	= 0x2000,
248 	HCLGEVF_OPC_MBX_VF_TO_PF	= 0x2001,
249 
250 	/* Led command */
251 	HCLGE_OPC_LED_STATUS_CFG	= 0xB000,
252 
253 	/* clear hardware resource command */
254 	HCLGE_OPC_CLEAR_HW_RESOURCE	= 0x700B,
255 
256 	/* NCL config command */
257 	HCLGE_OPC_QUERY_NCL_CONFIG	= 0x7011,
258 
259 	/* IMP stats command */
260 	HCLGE_OPC_IMP_STATS_BD		= 0x7012,
261 	HCLGE_OPC_IMP_STATS_INFO		= 0x7013,
262 	HCLGE_OPC_IMP_COMPAT_CFG		= 0x701A,
263 
264 	/* SFP command */
265 	HCLGE_OPC_GET_SFP_EEPROM	= 0x7100,
266 	HCLGE_OPC_GET_SFP_EXIST		= 0x7101,
267 	HCLGE_OPC_GET_SFP_INFO		= 0x7104,
268 
269 	/* Error INT commands */
270 	HCLGE_MAC_COMMON_INT_EN		= 0x030E,
271 	HCLGE_TM_SCH_ECC_INT_EN		= 0x0829,
272 	HCLGE_SSU_ECC_INT_CMD		= 0x0989,
273 	HCLGE_SSU_COMMON_INT_CMD	= 0x098C,
274 	HCLGE_PPU_MPF_ECC_INT_CMD	= 0x0B40,
275 	HCLGE_PPU_MPF_OTHER_INT_CMD	= 0x0B41,
276 	HCLGE_PPU_PF_OTHER_INT_CMD	= 0x0B42,
277 	HCLGE_COMMON_ECC_INT_CFG	= 0x1505,
278 	HCLGE_QUERY_RAS_INT_STS_BD_NUM	= 0x1510,
279 	HCLGE_QUERY_CLEAR_MPF_RAS_INT	= 0x1511,
280 	HCLGE_QUERY_CLEAR_PF_RAS_INT	= 0x1512,
281 	HCLGE_QUERY_MSIX_INT_STS_BD_NUM	= 0x1513,
282 	HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT	= 0x1514,
283 	HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT	= 0x1515,
284 	HCLGE_QUERY_ALL_ERR_BD_NUM		= 0x1516,
285 	HCLGE_QUERY_ALL_ERR_INFO		= 0x1517,
286 	HCLGE_CONFIG_ROCEE_RAS_INT_EN	= 0x1580,
287 	HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
288 	HCLGE_ROCEE_PF_RAS_INT_CMD	= 0x1584,
289 	HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD	= 0x1585,
290 	HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD	= 0x1586,
291 	HCLGE_IGU_EGU_TNL_INT_EN	= 0x1803,
292 	HCLGE_IGU_COMMON_INT_EN		= 0x1806,
293 	HCLGE_TM_QCN_MEM_INT_CFG	= 0x1A14,
294 	HCLGE_PPP_CMD0_INT_CMD		= 0x2100,
295 	HCLGE_PPP_CMD1_INT_CMD		= 0x2101,
296 	HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
297 	HCLGE_NCSI_INT_EN		= 0x2401,
298 
299 	/* ROH MAC commands */
300 	HCLGE_OPC_MAC_ADDR_CHECK	= 0x9004,
301 
302 	/* PHY command */
303 	HCLGE_OPC_PHY_LINK_KSETTING	= 0x7025,
304 	HCLGE_OPC_PHY_REG		= 0x7026,
305 
306 	/* Query link diagnosis info command */
307 	HCLGE_OPC_QUERY_LINK_DIAGNOSIS	= 0x702A,
308 };
309 
310 enum hclge_comm_cmd_return_status {
311 	HCLGE_COMM_CMD_EXEC_SUCCESS	= 0,
312 	HCLGE_COMM_CMD_NO_AUTH		= 1,
313 	HCLGE_COMM_CMD_NOT_SUPPORTED	= 2,
314 	HCLGE_COMM_CMD_QUEUE_FULL	= 3,
315 	HCLGE_COMM_CMD_NEXT_ERR		= 4,
316 	HCLGE_COMM_CMD_UNEXE_ERR	= 5,
317 	HCLGE_COMM_CMD_PARA_ERR		= 6,
318 	HCLGE_COMM_CMD_RESULT_ERR	= 7,
319 	HCLGE_COMM_CMD_TIMEOUT		= 8,
320 	HCLGE_COMM_CMD_HILINK_ERR	= 9,
321 	HCLGE_COMM_CMD_QUEUE_ILLEGAL	= 10,
322 	HCLGE_COMM_CMD_INVALID		= 11,
323 };
324 
325 enum HCLGE_COMM_CAP_BITS {
326 	HCLGE_COMM_CAP_UDP_GSO_B,
327 	HCLGE_COMM_CAP_QB_B,
328 	HCLGE_COMM_CAP_FD_FORWARD_TC_B,
329 	HCLGE_COMM_CAP_PTP_B,
330 	HCLGE_COMM_CAP_INT_QL_B,
331 	HCLGE_COMM_CAP_HW_TX_CSUM_B,
332 	HCLGE_COMM_CAP_TX_PUSH_B,
333 	HCLGE_COMM_CAP_PHY_IMP_B,
334 	HCLGE_COMM_CAP_TQP_TXRX_INDEP_B,
335 	HCLGE_COMM_CAP_HW_PAD_B,
336 	HCLGE_COMM_CAP_STASH_B,
337 	HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B,
338 	HCLGE_COMM_CAP_RAS_IMP_B = 12,
339 	HCLGE_COMM_CAP_FEC_B = 13,
340 	HCLGE_COMM_CAP_PAUSE_B = 14,
341 	HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B = 15,
342 	HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B = 17,
343 	HCLGE_COMM_CAP_CQ_B = 18,
344 	HCLGE_COMM_CAP_GRO_B = 20,
345 	HCLGE_COMM_CAP_FD_B = 21,
346 	HCLGE_COMM_CAP_FEC_STATS_B = 25,
347 	HCLGE_COMM_CAP_LANE_NUM_B = 27,
348 };
349 
350 enum HCLGE_COMM_API_CAP_BITS {
351 	HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B,
352 };
353 
354 /* capabilities bits map between imp firmware and local driver */
355 struct hclge_comm_caps_bit_map {
356 	u16 imp_bit;
357 	u16 local_bit;
358 };
359 
360 struct hclge_comm_firmware_compat_cmd {
361 	__le32 compat;
362 	u8 rsv[20];
363 };
364 
365 enum hclge_comm_cmd_state {
366 	HCLGE_COMM_STATE_CMD_DISABLE,
367 };
368 
369 struct hclge_comm_errcode {
370 	u32 imp_errcode;
371 	int common_errno;
372 };
373 
374 #define HCLGE_COMM_QUERY_CAP_LENGTH		3
375 struct hclge_comm_query_version_cmd {
376 	__le32 firmware;
377 	__le32 hardware;
378 	__le32 api_caps;
379 	__le32 caps[HCLGE_COMM_QUERY_CAP_LENGTH]; /* capabilities of device */
380 };
381 
382 #define HCLGE_DESC_DATA_LEN		6
383 struct hclge_desc {
384 	__le16 opcode;
385 	__le16 flag;
386 	__le16 retval;
387 	__le16 rsv;
388 	__le32 data[HCLGE_DESC_DATA_LEN];
389 };
390 
391 struct hclge_comm_cmq_ring {
392 	dma_addr_t desc_dma_addr;
393 	struct hclge_desc *desc;
394 	struct pci_dev *pdev;
395 	u32 head;
396 	u32 tail;
397 
398 	u16 buf_size;
399 	u16 desc_num;
400 	int next_to_use;
401 	int next_to_clean;
402 	u8 ring_type; /* cmq ring type */
403 	spinlock_t lock; /* Command queue lock */
404 };
405 
406 enum hclge_comm_cmd_status {
407 	HCLGE_COMM_STATUS_SUCCESS	= 0,
408 	HCLGE_COMM_ERR_CSQ_FULL		= -1,
409 	HCLGE_COMM_ERR_CSQ_TIMEOUT	= -2,
410 	HCLGE_COMM_ERR_CSQ_ERROR	= -3,
411 };
412 
413 struct hclge_comm_cmq {
414 	struct hclge_comm_cmq_ring csq;
415 	struct hclge_comm_cmq_ring crq;
416 	u16 tx_timeout;
417 	enum hclge_comm_cmd_status last_status;
418 };
419 
420 struct hclge_comm_hw {
421 	void __iomem *io_base;
422 	void __iomem *mem_base;
423 	struct hclge_comm_cmq cmq;
424 	unsigned long comm_state;
425 };
426 
hclge_comm_write_reg(void __iomem * base,u32 reg,u32 value)427 static inline void hclge_comm_write_reg(void __iomem *base, u32 reg, u32 value)
428 {
429 	writel(value, base + reg);
430 }
431 
hclge_comm_read_reg(u8 __iomem * base,u32 reg)432 static inline u32 hclge_comm_read_reg(u8 __iomem *base, u32 reg)
433 {
434 	u8 __iomem *reg_addr = READ_ONCE(base);
435 
436 	return readl(reg_addr + reg);
437 }
438 
439 #define hclge_comm_write_dev(a, reg, value) \
440 	hclge_comm_write_reg((a)->io_base, reg, value)
441 #define hclge_comm_read_dev(a, reg) \
442 	hclge_comm_read_reg((a)->io_base, reg)
443 
444 void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw);
445 int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev,
446 						struct hclge_comm_hw *hw,
447 						u32 *fw_version, bool is_pf);
448 int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type);
449 int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
450 			int num);
451 void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
452 int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev,
453 				      struct hclge_comm_hw *hw, bool en);
454 void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring);
455 void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,
456 				     enum hclge_opcode_type opcode,
457 				     bool is_read);
458 void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev,
459 			   struct hclge_comm_hw *hw);
460 int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw);
461 int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw,
462 			u32 *fw_version, bool is_pf,
463 			unsigned long reset_pending);
464 
465 #endif
466