1 #ifndef __SPARC64_PCI_H
2 #define __SPARC64_PCI_H
3
4 #ifdef __KERNEL__
5
6 #include <linux/fs.h>
7 #include <linux/mm.h>
8
9 /* Can be used to override the logic in pci_scan_bus for skipping
10 * already-configured bus numbers - to be used for buggy BIOSes
11 * or architectures with incomplete PCI setup by the loader.
12 */
13 #define pcibios_assign_all_busses() 0
14 #define pcibios_scan_all_fns() 0
15
16 #define PCIBIOS_MIN_IO 0UL
17 #define PCIBIOS_MIN_MEM 0UL
18
19 #define PCI_IRQ_NONE 0xffffffff
20
pcibios_set_master(struct pci_dev * dev)21 extern inline void pcibios_set_master(struct pci_dev *dev)
22 {
23 /* No special bus mastering setup handling */
24 }
25
pcibios_penalize_isa_irq(int irq)26 extern inline void pcibios_penalize_isa_irq(int irq)
27 {
28 /* We don't do dynamic PCI IRQ allocation */
29 }
30
31 /* Dynamic DMA mapping stuff.
32 */
33
34 /* The PCI address space does not equal the physical memory
35 * address space. The networking and block device layers use
36 * this boolean for bounce buffer decisions.
37 */
38 #define PCI_DMA_BUS_IS_PHYS (0)
39
40 #include <asm/scatterlist.h>
41
42 struct pci_dev;
43
44 /* Allocate and map kernel buffer using consistent mode DMA for a device.
45 * hwdev should be valid struct pci_dev pointer for PCI devices.
46 */
47 extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle);
48
49 /* Free and unmap a consistent DMA buffer.
50 * cpu_addr is what was returned from pci_alloc_consistent,
51 * size must be the same as what as passed into pci_alloc_consistent,
52 * and likewise dma_addr must be the same as what *dma_addrp was set to.
53 *
54 * References to the memory and mappings assosciated with cpu_addr/dma_addr
55 * past this call are illegal.
56 */
57 extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle);
58
59 /* Map a single buffer of the indicated size for DMA in streaming mode.
60 * The 32-bit bus address to use is returned.
61 *
62 * Once the device is given the dma address, the device owns this memory
63 * until either pci_unmap_single or pci_dma_sync_single is performed.
64 */
65 extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction);
66
67 /* Unmap a single streaming mode DMA translation. The dma_addr and size
68 * must match what was provided for in a previous pci_map_single call. All
69 * other usages are undefined.
70 *
71 * After this call, reads by the cpu to the buffer are guarenteed to see
72 * whatever the device wrote there.
73 */
74 extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction);
75
76 /* No highmem on sparc64, plus we have an IOMMU, so mapping pages is easy. */
77 #define pci_map_page(dev, page, off, size, dir) \
78 pci_map_single(dev, (page_address(page) + (off)), size, dir)
79 #define pci_unmap_page(dev,addr,sz,dir) pci_unmap_single(dev,addr,sz,dir)
80
81 /* pci_unmap_{single,page} is not a nop, thus... */
82 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
83 dma_addr_t ADDR_NAME;
84 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
85 __u32 LEN_NAME;
86 #define pci_unmap_addr(PTR, ADDR_NAME) \
87 ((PTR)->ADDR_NAME)
88 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
89 (((PTR)->ADDR_NAME) = (VAL))
90 #define pci_unmap_len(PTR, LEN_NAME) \
91 ((PTR)->LEN_NAME)
92 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
93 (((PTR)->LEN_NAME) = (VAL))
94
95 /* Map a set of buffers described by scatterlist in streaming
96 * mode for DMA. This is the scather-gather version of the
97 * above pci_map_single interface. Here the scatter gather list
98 * elements are each tagged with the appropriate dma address
99 * and length. They are obtained via sg_dma_{address,length}(SG).
100 *
101 * NOTE: An implementation may be able to use a smaller number of
102 * DMA address/length pairs than there are SG table elements.
103 * (for example via virtual mapping capabilities)
104 * The routine returns the number of addr/length pairs actually
105 * used, at most nents.
106 *
107 * Device ownership issues as mentioned above for pci_map_single are
108 * the same here.
109 */
110 extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
111 int nents, int direction);
112
113 /* Unmap a set of streaming mode DMA translations.
114 * Again, cpu read rules concerning calls here are the same as for
115 * pci_unmap_single() above.
116 */
117 extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
118 int nhwents, int direction);
119
120 /* Make physical memory consistent for a single
121 * streaming mode DMA translation after a transfer.
122 *
123 * If you perform a pci_map_single() but wish to interrogate the
124 * buffer using the cpu, yet do not wish to teardown the PCI dma
125 * mapping, you must call this function before doing so. At the
126 * next point you give the PCI dma address back to the card, the
127 * device again owns the buffer.
128 */
129 extern void pci_dma_sync_single(struct pci_dev *hwdev, dma_addr_t dma_handle,
130 size_t size, int direction);
131
132 /* Make physical memory consistent for a set of streaming
133 * mode DMA translations after a transfer.
134 *
135 * The same as pci_dma_sync_single but for a scatter-gather list,
136 * same rules and usage.
137 */
138 extern void pci_dma_sync_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
139
140 /* Return whether the given PCI device DMA address mask can
141 * be supported properly. For example, if your device can
142 * only drive the low 24-bits during PCI bus mastering, then
143 * you would pass 0x00ffffff as the mask to this function.
144 */
145 extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
146
147 /* PCI IOMMU mapping bypass support. */
148
149 /* PCI 64-bit addressing works for all slots on all controller
150 * types on sparc64. However, it requires that the device
151 * can drive enough of the 64 bits.
152 */
153 #define PCI64_REQUIRED_MASK (~(dma64_addr_t)0)
154 #define PCI64_ADDR_BASE 0xfffc000000000000
155
156 /* Usage of the pci_dac_foo interfaces is only valid if this
157 * test passes.
158 */
159 #define pci_dac_dma_supported(pci_dev, mask) \
160 ((((mask) & PCI64_REQUIRED_MASK) == PCI64_REQUIRED_MASK) ? 1 : 0)
161
162 static __inline__ dma64_addr_t
pci_dac_page_to_dma(struct pci_dev * pdev,struct page * page,unsigned long offset,int direction)163 pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction)
164 {
165 return (PCI64_ADDR_BASE +
166 __pa(page_address(page)) + offset);
167 }
168
169 static __inline__ struct page *
pci_dac_dma_to_page(struct pci_dev * pdev,dma64_addr_t dma_addr)170 pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr)
171 {
172 unsigned long paddr = (dma_addr & PAGE_MASK) - PCI64_ADDR_BASE;
173
174 return virt_to_page(__va(paddr));
175 }
176
177 static __inline__ unsigned long
pci_dac_dma_to_offset(struct pci_dev * pdev,dma64_addr_t dma_addr)178 pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr)
179 {
180 return (dma_addr & ~PAGE_MASK);
181 }
182
183 static __inline__ void
pci_dac_dma_sync_single(struct pci_dev * pdev,dma64_addr_t dma_addr,size_t len,int direction)184 pci_dac_dma_sync_single(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
185 {
186 /* DAC cycle addressing does not make use of the
187 * PCI controller's streaming cache, so nothing to do.
188 */
189 }
190
191 /* Return the index of the PCI controller for device PDEV. */
192
193 extern int pci_controller_num(struct pci_dev *pdev);
194
195 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
196
197 #define HAVE_PCI_MMAP
198 #define HAVE_ARCH_PCI_GET_UNMAPPED_AREA
199 #define get_pci_unmapped_area get_fb_unmapped_area
200
201 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
202 enum pci_mmap_state mmap_state,
203 int write_combine);
204
205 #endif /* __KERNEL__ */
206
207 #endif /* __SPARC64_PCI_H */
208