1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Hantro VPU codec driver
4  *
5  * Copyright 2018 Google LLC.
6  *	Tomasz Figa <tfiga@chromium.org>
7  *
8  * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
9  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
10  */
11 
12 #ifndef HANTRO_H_
13 #define HANTRO_H_
14 
15 #include <linux/platform_device.h>
16 #include <linux/videodev2.h>
17 #include <linux/wait.h>
18 #include <linux/clk.h>
19 #include <linux/reset.h>
20 
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-ioctl.h>
24 #include <media/v4l2-mem2mem.h>
25 #include <media/videobuf2-core.h>
26 #include <media/videobuf2-dma-contig.h>
27 
28 #include "hantro_hw.h"
29 
30 struct hantro_ctx;
31 struct hantro_codec_ops;
32 struct hantro_postproc_ops;
33 
34 #define HANTRO_JPEG_ENCODER	BIT(0)
35 #define HANTRO_ENCODERS		0x0000ffff
36 #define HANTRO_MPEG2_DECODER	BIT(16)
37 #define HANTRO_VP8_DECODER	BIT(17)
38 #define HANTRO_H264_DECODER	BIT(18)
39 #define HANTRO_HEVC_DECODER	BIT(19)
40 #define HANTRO_VP9_DECODER	BIT(20)
41 #define HANTRO_DECODERS		0xffff0000
42 
43 /**
44  * struct hantro_irq - irq handler and name
45  *
46  * @name:			irq name for device tree lookup
47  * @handler:			interrupt handler
48  */
49 struct hantro_irq {
50 	const char *name;
51 	irqreturn_t (*handler)(int irq, void *priv);
52 };
53 
54 /**
55  * struct hantro_variant - information about VPU hardware variant
56  *
57  * @enc_offset:			Offset from VPU base to encoder registers.
58  * @dec_offset:			Offset from VPU base to decoder registers.
59  * @enc_fmts:			Encoder formats.
60  * @num_enc_fmts:		Number of encoder formats.
61  * @dec_fmts:			Decoder formats.
62  * @num_dec_fmts:		Number of decoder formats.
63  * @postproc_fmts:		Post-processor formats.
64  * @num_postproc_fmts:		Number of post-processor formats.
65  * @postproc_ops:		Post-processor ops.
66  * @codec:			Supported codecs
67  * @codec_ops:			Codec ops.
68  * @init:			Initialize hardware, optional.
69  * @runtime_resume:		reenable hardware after power gating, optional.
70  * @irqs:			array of irq names and interrupt handlers
71  * @num_irqs:			number of irqs in the array
72  * @clk_names:			array of clock names
73  * @num_clocks:			number of clocks in the array
74  * @reg_names:			array of register range names
75  * @num_regs:			number of register range names in the array
76  * @double_buffer:		core needs double buffering
77  * @legacy_regs:		core uses legacy register set
78  * @late_postproc:		postproc must be set up at the end of the job
79  */
80 struct hantro_variant {
81 	unsigned int enc_offset;
82 	unsigned int dec_offset;
83 	const struct hantro_fmt *enc_fmts;
84 	unsigned int num_enc_fmts;
85 	const struct hantro_fmt *dec_fmts;
86 	unsigned int num_dec_fmts;
87 	const struct hantro_fmt *postproc_fmts;
88 	unsigned int num_postproc_fmts;
89 	const struct hantro_postproc_ops *postproc_ops;
90 	unsigned int codec;
91 	const struct hantro_codec_ops *codec_ops;
92 	int (*init)(struct hantro_dev *vpu);
93 	int (*runtime_resume)(struct hantro_dev *vpu);
94 	const struct hantro_irq *irqs;
95 	int num_irqs;
96 	const char * const *clk_names;
97 	int num_clocks;
98 	const char * const *reg_names;
99 	int num_regs;
100 	unsigned int double_buffer : 1;
101 	unsigned int legacy_regs : 1;
102 	unsigned int late_postproc : 1;
103 };
104 
105 /**
106  * enum hantro_codec_mode - codec operating mode.
107  * @HANTRO_MODE_NONE:  No operating mode. Used for RAW video formats.
108  * @HANTRO_MODE_JPEG_ENC: JPEG encoder.
109  * @HANTRO_MODE_H264_DEC: H264 decoder.
110  * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.
111  * @HANTRO_MODE_VP8_DEC: VP8 decoder.
112  * @HANTRO_MODE_HEVC_DEC: HEVC decoder.
113  * @HANTRO_MODE_VP9_DEC: VP9 decoder.
114  */
115 enum hantro_codec_mode {
116 	HANTRO_MODE_NONE = -1,
117 	HANTRO_MODE_JPEG_ENC,
118 	HANTRO_MODE_H264_DEC,
119 	HANTRO_MODE_MPEG2_DEC,
120 	HANTRO_MODE_VP8_DEC,
121 	HANTRO_MODE_HEVC_DEC,
122 	HANTRO_MODE_VP9_DEC,
123 };
124 
125 /*
126  * struct hantro_ctrl - helper type to declare supported controls
127  * @codec:	codec id this control belong to (HANTRO_JPEG_ENCODER, etc.)
128  * @cfg:	control configuration
129  */
130 struct hantro_ctrl {
131 	unsigned int codec;
132 	struct v4l2_ctrl_config cfg;
133 };
134 
135 /*
136  * struct hantro_func - Hantro VPU functionality
137  *
138  * @id:			processing functionality ID (can be
139  *			%MEDIA_ENT_F_PROC_VIDEO_ENCODER or
140  *			%MEDIA_ENT_F_PROC_VIDEO_DECODER)
141  * @vdev:		&struct video_device that exposes the encoder or
142  *			decoder functionality
143  * @source_pad:		&struct media_pad with the source pad.
144  * @sink:		&struct media_entity pointer with the sink entity
145  * @sink_pad:		&struct media_pad with the sink pad.
146  * @proc:		&struct media_entity pointer with the M2M device itself.
147  * @proc_pads:		&struct media_pad with the @proc pads.
148  * @intf_devnode:	&struct media_intf devnode pointer with the interface
149  *			with controls the M2M device.
150  *
151  * Contains everything needed to attach the video device to the media device.
152  */
153 struct hantro_func {
154 	unsigned int id;
155 	struct video_device vdev;
156 	struct media_pad source_pad;
157 	struct media_entity sink;
158 	struct media_pad sink_pad;
159 	struct media_entity proc;
160 	struct media_pad proc_pads[2];
161 	struct media_intf_devnode *intf_devnode;
162 };
163 
164 static inline struct hantro_func *
hantro_vdev_to_func(struct video_device * vdev)165 hantro_vdev_to_func(struct video_device *vdev)
166 {
167 	return container_of(vdev, struct hantro_func, vdev);
168 }
169 
170 /**
171  * struct hantro_dev - driver data
172  * @v4l2_dev:		V4L2 device to register video devices for.
173  * @m2m_dev:		mem2mem device associated to this device.
174  * @mdev:		media device associated to this device.
175  * @encoder:		encoder functionality.
176  * @decoder:		decoder functionality.
177  * @pdev:		Pointer to VPU platform device.
178  * @dev:		Pointer to device for convenient logging using
179  *			dev_ macros.
180  * @clocks:		Array of clock handles.
181  * @resets:		Array of reset handles.
182  * @reg_bases:		Mapped addresses of VPU registers.
183  * @enc_base:		Mapped address of VPU encoder register for convenience.
184  * @dec_base:		Mapped address of VPU decoder register for convenience.
185  * @ctrl_base:		Mapped address of VPU control block.
186  * @vpu_mutex:		Mutex to synchronize V4L2 calls.
187  * @irqlock:		Spinlock to synchronize access to data structures
188  *			shared with interrupt handlers.
189  * @variant:		Hardware variant-specific parameters.
190  * @watchdog_work:	Delayed work for hardware timeout handling.
191  */
192 struct hantro_dev {
193 	struct v4l2_device v4l2_dev;
194 	struct v4l2_m2m_dev *m2m_dev;
195 	struct media_device mdev;
196 	struct hantro_func *encoder;
197 	struct hantro_func *decoder;
198 	struct platform_device *pdev;
199 	struct device *dev;
200 	struct clk_bulk_data *clocks;
201 	struct reset_control *resets;
202 	void __iomem **reg_bases;
203 	void __iomem *enc_base;
204 	void __iomem *dec_base;
205 	void __iomem *ctrl_base;
206 
207 	struct mutex vpu_mutex;	/* video_device lock */
208 	spinlock_t irqlock;
209 	const struct hantro_variant *variant;
210 	struct delayed_work watchdog_work;
211 };
212 
213 /**
214  * struct hantro_ctx - Context (instance) private data.
215  *
216  * @dev:		VPU driver data to which the context belongs.
217  * @fh:			V4L2 file handler.
218  * @is_encoder:		Decoder or encoder context?
219  *
220  * @sequence_cap:       Sequence counter for capture queue
221  * @sequence_out:       Sequence counter for output queue
222  *
223  * @vpu_src_fmt:	Descriptor of active source format.
224  * @src_fmt:		V4L2 pixel format of active source format.
225  * @vpu_dst_fmt:	Descriptor of active destination format.
226  * @dst_fmt:		V4L2 pixel format of active destination format.
227  *
228  * @ctrl_handler:	Control handler used to register controls.
229  * @jpeg_quality:	User-specified JPEG compression quality.
230  * @bit_depth:		Bit depth of current frame
231  *
232  * @codec_ops:		Set of operations related to codec mode.
233  * @postproc:		Post-processing context.
234  * @h264_dec:		H.264-decoding context.
235  * @jpeg_enc:		JPEG-encoding context.
236  * @mpeg2_dec:		MPEG-2-decoding context.
237  * @vp8_dec:		VP8-decoding context.
238  * @hevc_dec:		HEVC-decoding context.
239  * @vp9_dec:		VP9-decoding context.
240  */
241 struct hantro_ctx {
242 	struct hantro_dev *dev;
243 	struct v4l2_fh fh;
244 	bool is_encoder;
245 
246 	u32 sequence_cap;
247 	u32 sequence_out;
248 
249 	const struct hantro_fmt *vpu_src_fmt;
250 	struct v4l2_pix_format_mplane src_fmt;
251 	const struct hantro_fmt *vpu_dst_fmt;
252 	struct v4l2_pix_format_mplane dst_fmt;
253 
254 	struct v4l2_ctrl_handler ctrl_handler;
255 	int jpeg_quality;
256 	int bit_depth;
257 
258 	const struct hantro_codec_ops *codec_ops;
259 	struct hantro_postproc_ctx postproc;
260 
261 	/* Specific for particular codec modes. */
262 	union {
263 		struct hantro_h264_dec_hw_ctx h264_dec;
264 		struct hantro_mpeg2_dec_hw_ctx mpeg2_dec;
265 		struct hantro_vp8_dec_hw_ctx vp8_dec;
266 		struct hantro_hevc_dec_hw_ctx hevc_dec;
267 		struct hantro_vp9_dec_hw_ctx vp9_dec;
268 	};
269 };
270 
271 /**
272  * struct hantro_fmt - information about supported video formats.
273  * @name:	Human readable name of the format.
274  * @fourcc:	FourCC code of the format. See V4L2_PIX_FMT_*.
275  * @codec_mode:	Codec mode related to this format. See
276  *		enum hantro_codec_mode.
277  * @header_size: Optional header size. Currently used by JPEG encoder.
278  * @max_depth:	Maximum depth, for bitstream formats
279  * @enc_fmt:	Format identifier for encoder registers.
280  * @frmsize:	Supported range of frame sizes (only for bitstream formats).
281  * @postprocessed: Indicates if this format needs the post-processor.
282  * @match_depth: Indicates if format bit depth must match video bit depth
283  */
284 struct hantro_fmt {
285 	char *name;
286 	u32 fourcc;
287 	enum hantro_codec_mode codec_mode;
288 	int header_size;
289 	int max_depth;
290 	enum hantro_enc_fmt enc_fmt;
291 	struct v4l2_frmsize_stepwise frmsize;
292 	bool postprocessed;
293 	bool match_depth;
294 };
295 
296 struct hantro_reg {
297 	u32 base;
298 	u32 shift;
299 	u32 mask;
300 };
301 
302 struct hantro_postproc_regs {
303 	struct hantro_reg pipeline_en;
304 	struct hantro_reg max_burst;
305 	struct hantro_reg clk_gate;
306 	struct hantro_reg out_swap32;
307 	struct hantro_reg out_endian;
308 	struct hantro_reg out_luma_base;
309 	struct hantro_reg input_width;
310 	struct hantro_reg input_height;
311 	struct hantro_reg output_width;
312 	struct hantro_reg output_height;
313 	struct hantro_reg input_fmt;
314 	struct hantro_reg output_fmt;
315 	struct hantro_reg orig_width;
316 	struct hantro_reg display_width;
317 };
318 
319 struct hantro_vp9_decoded_buffer_info {
320 	/* Info needed when the decoded frame serves as a reference frame. */
321 	unsigned short width;
322 	unsigned short height;
323 	u32 bit_depth : 4;
324 };
325 
326 struct hantro_decoded_buffer {
327 	/* Must be the first field in this struct. */
328 	struct v4l2_m2m_buffer base;
329 
330 	union {
331 		struct hantro_vp9_decoded_buffer_info vp9;
332 	};
333 };
334 
335 /* Logging helpers */
336 
337 /**
338  * DOC: hantro_debug: Module parameter to control level of debugging messages.
339  *
340  * Level of debugging messages can be controlled by bits of
341  * module parameter called "debug". Meaning of particular
342  * bits is as follows:
343  *
344  * bit 0 - global information: mode, size, init, release
345  * bit 1 - each run start/result information
346  * bit 2 - contents of small controls from userspace
347  * bit 3 - contents of big controls from userspace
348  * bit 4 - detail fmt, ctrl, buffer q/dq information
349  * bit 5 - detail function enter/leave trace information
350  * bit 6 - register write/read information
351  */
352 extern int hantro_debug;
353 
354 #define vpu_debug(level, fmt, args...)				\
355 	do {							\
356 		if (hantro_debug & BIT(level))		\
357 			pr_info("%s:%d: " fmt,	                \
358 				 __func__, __LINE__, ##args);	\
359 	} while (0)
360 
361 #define vpu_err(fmt, args...)					\
362 	pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
363 
364 /* Structure access helpers. */
fh_to_ctx(struct v4l2_fh * fh)365 static inline struct hantro_ctx *fh_to_ctx(struct v4l2_fh *fh)
366 {
367 	return container_of(fh, struct hantro_ctx, fh);
368 }
369 
370 /* Register accessors. */
vepu_write_relaxed(struct hantro_dev * vpu,u32 val,u32 reg)371 static inline void vepu_write_relaxed(struct hantro_dev *vpu,
372 				      u32 val, u32 reg)
373 {
374 	vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
375 	writel_relaxed(val, vpu->enc_base + reg);
376 }
377 
vepu_write(struct hantro_dev * vpu,u32 val,u32 reg)378 static inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg)
379 {
380 	vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
381 	writel(val, vpu->enc_base + reg);
382 }
383 
vepu_read(struct hantro_dev * vpu,u32 reg)384 static inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)
385 {
386 	u32 val = readl(vpu->enc_base + reg);
387 
388 	vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
389 	return val;
390 }
391 
vdpu_write_relaxed(struct hantro_dev * vpu,u32 val,u32 reg)392 static inline void vdpu_write_relaxed(struct hantro_dev *vpu,
393 				      u32 val, u32 reg)
394 {
395 	vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
396 	writel_relaxed(val, vpu->dec_base + reg);
397 }
398 
vdpu_write(struct hantro_dev * vpu,u32 val,u32 reg)399 static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
400 {
401 	vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
402 	writel(val, vpu->dec_base + reg);
403 }
404 
hantro_write_addr(struct hantro_dev * vpu,unsigned long offset,dma_addr_t addr)405 static inline void hantro_write_addr(struct hantro_dev *vpu,
406 				     unsigned long offset,
407 				     dma_addr_t addr)
408 {
409 	vdpu_write(vpu, addr & 0xffffffff, offset);
410 }
411 
vdpu_read(struct hantro_dev * vpu,u32 reg)412 static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
413 {
414 	u32 val = readl(vpu->dec_base + reg);
415 
416 	vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
417 	return val;
418 }
419 
vdpu_read_mask(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)420 static inline u32 vdpu_read_mask(struct hantro_dev *vpu,
421 				 const struct hantro_reg *reg,
422 				 u32 val)
423 {
424 	u32 v;
425 
426 	v = vdpu_read(vpu, reg->base);
427 	v &= ~(reg->mask << reg->shift);
428 	v |= ((val & reg->mask) << reg->shift);
429 	return v;
430 }
431 
hantro_reg_write(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)432 static inline void hantro_reg_write(struct hantro_dev *vpu,
433 				    const struct hantro_reg *reg,
434 				    u32 val)
435 {
436 	vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
437 }
438 
hantro_reg_write_s(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)439 static inline void hantro_reg_write_s(struct hantro_dev *vpu,
440 				      const struct hantro_reg *reg,
441 				      u32 val)
442 {
443 	vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
444 }
445 
446 void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id);
447 dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts);
448 
449 static inline struct vb2_v4l2_buffer *
hantro_get_src_buf(struct hantro_ctx * ctx)450 hantro_get_src_buf(struct hantro_ctx *ctx)
451 {
452 	return v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
453 }
454 
455 static inline struct vb2_v4l2_buffer *
hantro_get_dst_buf(struct hantro_ctx * ctx)456 hantro_get_dst_buf(struct hantro_ctx *ctx)
457 {
458 	return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
459 }
460 
461 bool hantro_needs_postproc(const struct hantro_ctx *ctx,
462 			   const struct hantro_fmt *fmt);
463 
464 static inline dma_addr_t
hantro_get_dec_buf_addr(struct hantro_ctx * ctx,struct vb2_buffer * vb)465 hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb)
466 {
467 	if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
468 		return ctx->postproc.dec_q[vb->index].dma;
469 	return vb2_dma_contig_plane_dma_addr(vb, 0);
470 }
471 
472 static inline struct hantro_decoded_buffer *
vb2_to_hantro_decoded_buf(struct vb2_buffer * buf)473 vb2_to_hantro_decoded_buf(struct vb2_buffer *buf)
474 {
475 	return container_of(buf, struct hantro_decoded_buffer, base.vb.vb2_buf);
476 }
477 
478 void hantro_postproc_disable(struct hantro_ctx *ctx);
479 void hantro_postproc_enable(struct hantro_ctx *ctx);
480 void hantro_postproc_free(struct hantro_ctx *ctx);
481 int hantro_postproc_alloc(struct hantro_ctx *ctx);
482 int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx,
483 				   struct v4l2_frmsizeenum *fsize);
484 
485 #endif /* HANTRO_H_ */
486