1 /* -*- mode: c; c-basic-offset: 8 -*- */
2
3 /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
4 *
5 * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
6 */
7
8 #ifndef _53C700_H
9 #define _53C700_H
10
11 /* Turn on for general debugging---too verbose for normal use */
12 #undef NCR_700_DEBUG
13 /* Debug the tag queues, checking hash queue allocation and deallocation
14 * and search for duplicate tags */
15 #undef NCR_700_TAG_DEBUG
16
17 #ifdef NCR_700_DEBUG
18 #define DEBUG(x) printk x
19 #else
20 #define DEBUG(x)
21 #endif
22
23 /* The number of available command slots */
24 #define NCR_700_COMMAND_SLOTS_PER_HOST 64
25 /* The maximum number of Scatter Gathers we allow */
26 #define NCR_700_SG_SEGMENTS 32
27 /* The maximum number of luns (make this of the form 2^n) */
28 #define NCR_700_MAX_LUNS 32
29 #define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1)
30 /* Alter this with care: too many tags won't give the elevator a chance to
31 * work; too few will cause the device to operate less efficiently */
32 #define NCR_700_MAX_TAGS 16
33 /* magic byte identifying an internally generated REQUEST_SENSE command */
34 #define NCR_700_INTERNAL_SENSE_MAGIC 0x42
35
36 /* WARNING: Leave this in for now: the dependency preprocessor doesn't
37 * pick up file specific flags, so must define here if they are not
38 * set */
39 #if !defined(CONFIG_53C700_IO_MAPPED) && !defined(CONFIG_53C700_MEM_MAPPED)
40 #error "Config.in must define either CONFIG_53C700_IO_MAPPED or CONFIG_53C700_MEM_MAPPED to use this scsi core."
41 #endif
42
43 /* macros for consistent memory allocation */
44
45 #ifdef CONFIG_53C700_USE_CONSISTENT
46 #define NCR_700_dma_cache_wback(mem, size) \
47 if(!hostdata->consistent) \
48 dma_cache_wback(mem, size)
49 #define NCR_700_dma_cache_inv(mem, size) \
50 if(!hostdata->consistent) \
51 dma_cache_inv(mem, size)
52 #define NCR_700_dma_cache_wback_inv(mem, size) \
53 if(!hostdata->consistent) \
54 dma_cache_wback_inv(mem, size)
55 #else
56 #define NCR_700_dma_cache_wback(mem, size) dma_cache_wback(mem,size)
57 #define NCR_700_dma_cache_inv(mem, size) dma_cache_inv(mem,size)
58 #define NCR_700_dma_cache_wback_inv(mem, size) dma_cache_wback_inv(mem,size)
59 #endif
60
61
62 struct NCR_700_Host_Parameters;
63
64 /* These are the externally used routines */
65 struct Scsi_Host *NCR_700_detect(Scsi_Host_Template *, struct NCR_700_Host_Parameters *);
66 int NCR_700_release(struct Scsi_Host *host);
67 void NCR_700_intr(int, void *, struct pt_regs *);
68
69
70 enum NCR_700_Host_State {
71 NCR_700_HOST_BUSY,
72 NCR_700_HOST_FREE,
73 };
74
75 struct NCR_700_SG_List {
76 /* The following is a script fragment to move the buffer onto the
77 * bus and then link the next fragment or return */
78 #define SCRIPT_MOVE_DATA_IN 0x09000000
79 #define SCRIPT_MOVE_DATA_OUT 0x08000000
80 __u32 ins;
81 __u32 pAddr;
82 #define SCRIPT_NOP 0x80000000
83 #define SCRIPT_RETURN 0x90080000
84 };
85
86 /* We use device->hostdata to store negotiated parameters. This is
87 * supposed to be a pointer to a device private area, but we cannot
88 * really use it as such since it will never be freed, so just use the
89 * 32 bits to cram the information. The SYNC negotiation sequence looks
90 * like:
91 *
92 * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the
93 * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTATION
94 * If we get an SDTR reply, work out the SXFER parameters, squirrel
95 * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set
96 * DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel
97 *
98 *
99 * 0:7 SXFER_REG negotiated value for this device
100 * 8:15 Current queue depth
101 * 16 negotiated SYNC flag
102 * 17 begin SYNC negotiation flag
103 * 18 device supports tag queueing */
104 #define NCR_700_DEV_NEGOTIATED_SYNC (1<<16)
105 #define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17)
106 #define NCR_700_DEV_BEGIN_TAG_QUEUEING (1<<18)
107 #define NCR_700_DEV_TAG_STARVATION_WARNED (1<<19)
108
109 static inline void
NCR_700_set_SXFER(Scsi_Device * SDp,__u8 sxfer)110 NCR_700_set_SXFER(Scsi_Device *SDp, __u8 sxfer)
111 {
112 long l = (long)SDp->hostdata;
113
114 l &= 0xffffff00;
115 l |= sxfer & 0xff;
116 SDp->hostdata = (void *)l;
117 }
NCR_700_get_SXFER(Scsi_Device * SDp)118 static inline __u8 NCR_700_get_SXFER(Scsi_Device *SDp)
119 {
120 return (((unsigned long)SDp->hostdata) & 0xff);
121 }
122 static inline void
NCR_700_set_depth(Scsi_Device * SDp,__u8 depth)123 NCR_700_set_depth(Scsi_Device *SDp, __u8 depth)
124 {
125 long l = (long)SDp->hostdata;
126
127 l &= 0xffff00ff;
128 l |= 0xff00 & (depth << 8);
129 SDp->hostdata = (void *)l;
130 }
131 static inline __u8
NCR_700_get_depth(Scsi_Device * SDp)132 NCR_700_get_depth(Scsi_Device *SDp)
133 {
134 return ((((unsigned long)SDp->hostdata) & 0xff00)>>8);
135 }
136 static inline int
NCR_700_is_flag_set(Scsi_Device * SDp,__u32 flag)137 NCR_700_is_flag_set(Scsi_Device *SDp, __u32 flag)
138 {
139 return (((unsigned long)SDp->hostdata) & flag) == flag;
140 }
141 static inline int
NCR_700_is_flag_clear(Scsi_Device * SDp,__u32 flag)142 NCR_700_is_flag_clear(Scsi_Device *SDp, __u32 flag)
143 {
144 return (((unsigned long)SDp->hostdata) & flag) == 0;
145 }
146 static inline void
NCR_700_set_flag(Scsi_Device * SDp,__u32 flag)147 NCR_700_set_flag(Scsi_Device *SDp, __u32 flag)
148 {
149 SDp->hostdata = (void *)((long)SDp->hostdata | (flag & 0xffff0000));
150 }
151 static inline void
NCR_700_clear_flag(Scsi_Device * SDp,__u32 flag)152 NCR_700_clear_flag(Scsi_Device *SDp, __u32 flag)
153 {
154 SDp->hostdata = (void *)((long)SDp->hostdata & ~(flag & 0xffff0000));
155 }
156
157 /* These represent the Nexus hashing functions. A Nexus in SCSI terms
158 * just means the identification of an outstanding command, by ITL
159 * (Initiator Target Lun) or ITLQ (Initiator Target Lun Tag). I'm not
160 * very keen on XOR based hashes, so these are based on number theory
161 * instead. All you need to do is to fix your hash bucket size and
162 * then choose reasonable strides which are coprime with the chosen
163 * bucket size
164 *
165 * Note: this mathematical hash can be made very efficient, if the
166 * compiler is good at optimising: Choose the number of buckets to be
167 * 2^n and the modulo becomes a logical and with (2^n-1).
168 * Additionally, if you chose the coprimes of the form 2^n-2^n the
169 * multiplication can be done by a shift and an addition. */
170 #define MAX_ITL_HASH_BUCKETS 16
171 #define ITL_HASH_PRIME 7
172
173 #define MAX_ITLQ_HASH_BUCKETS 64
174 #define ITLQ_PUN_PRIME 7
175 #define ITLQ_LUN_PRIME 3
176
177 static inline int
hash_ITL(__u8 pun,__u8 lun)178 hash_ITL(__u8 pun, __u8 lun)
179 {
180 return (pun*ITL_HASH_PRIME + lun) % MAX_ITL_HASH_BUCKETS;
181 }
182
183 static inline int
hash_ITLQ(__u8 pun,__u8 lun,__u8 tag)184 hash_ITLQ(__u8 pun, __u8 lun, __u8 tag)
185 {
186 return (pun*ITLQ_PUN_PRIME + lun*ITLQ_LUN_PRIME + tag) % MAX_ITLQ_HASH_BUCKETS;
187 }
188
189 struct NCR_700_command_slot {
190 struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1];
191 struct NCR_700_SG_List *pSG;
192 #define NCR_700_SLOT_MASK 0xFC
193 #define NCR_700_SLOT_MAGIC 0xb8
194 #define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */
195 #define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */
196 #define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */
197 __u8 state;
198 #define NCR_700_NO_TAG 0xdead
199 __u16 tag;
200 __u32 resume_offset;
201 Scsi_Cmnd *cmnd;
202 /* The pci_mapped address of the actual command in cmnd */
203 dma_addr_t pCmd;
204 __u32 temp;
205 /* if this command is a pci_single mapping, holds the dma address
206 * for later unmapping in the done routine */
207 dma_addr_t dma_handle;
208 /* Doubly linked ITL/ITLQ list kept in strict time order
209 * (latest at the back) */
210 struct NCR_700_command_slot *ITL_forw;
211 struct NCR_700_command_slot *ITL_back;
212 struct NCR_700_command_slot *ITLQ_forw;
213 struct NCR_700_command_slot *ITLQ_back;
214 };
215
216 struct NCR_700_Host_Parameters {
217 /* These must be filled in by the calling driver */
218 int clock; /* board clock speed in MHz */
219 unsigned long base; /* the base for the port (copied to host) */
220 struct pci_dev *pci_dev;
221 __u32 dmode_extra; /* adjustable bus settings */
222 __u32 differential:1; /* if we are differential */
223 #ifdef CONFIG_53C700_LE_ON_BE
224 /* This option is for HP only. Set it if your chip is wired for
225 * little endian on this platform (which is big endian) */
226 __u32 force_le_on_be:1;
227 #endif
228 __u32 chip710:1; /* set if really a 710 not 700 */
229 __u32 burst_disable:1; /* set to 1 to disable 710 bursting */
230
231 /* NOTHING BELOW HERE NEEDS ALTERING */
232 __u32 fast:1; /* if we can alter the SCSI bus clock
233 speed (so can negiotiate sync) */
234 #ifdef CONFIG_53C700_USE_CONSISTENT
235 __u32 consistent:1;
236 #endif
237
238 int sync_clock; /* The speed of the SYNC core */
239
240 __u32 *script; /* pointer to script location */
241 __u32 pScript; /* physical mem addr of script */
242
243 /* This will be the host lock. Unfortunately, we can't use it
244 * at the moment because of the necessity of holding the
245 * io_request_lock */
246 spinlock_t lock;
247 enum NCR_700_Host_State state; /* protected by state lock */
248 Scsi_Cmnd *cmd;
249 /* Note: pScript contains the single consistent block of
250 * memory. All the msgin, msgout and status are allocated in
251 * this memory too (at separate cache lines). TOTAL_MEM_SIZE
252 * represents the total size of this area */
253 #define MSG_ARRAY_SIZE 8
254 #define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT)))
255 __u8 *msgout;
256 #define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
257 __u8 *msgin;
258 #define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
259 __u8 *status;
260 #define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
261 struct NCR_700_command_slot *slots;
262 #define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
263 int saved_slot_position;
264 int command_slot_count; /* protected by state lock */
265 __u8 tag_negotiated;
266 __u8 rev;
267 __u8 reselection_id;
268 /* flags for the host */
269
270 /* ITL list. ALL outstanding commands are hashed here in strict
271 * order, latest at the back */
272 struct NCR_700_command_slot *ITL_Hash_forw[MAX_ITL_HASH_BUCKETS];
273 struct NCR_700_command_slot *ITL_Hash_back[MAX_ITL_HASH_BUCKETS];
274
275 /* Only tagged outstanding commands are hashed here (also latest
276 * at the back) */
277 struct NCR_700_command_slot *ITLQ_Hash_forw[MAX_ITLQ_HASH_BUCKETS];
278 struct NCR_700_command_slot *ITLQ_Hash_back[MAX_ITLQ_HASH_BUCKETS];
279
280 /* Free list, singly linked by ITL_forw elements */
281 struct NCR_700_command_slot *free_list;
282 };
283
284 /*
285 * 53C700 Register Interface - the offset from the Selected base
286 * I/O address */
287 #ifdef CONFIG_53C700_LE_ON_BE
288 #define bE (hostdata->force_le_on_be ? 0 : 3)
289 #define bSWAP (hostdata->force_le_on_be)
290 #elif defined(__BIG_ENDIAN)
291 #define bE 3
292 #define bSWAP 0
293 #elif defined(__LITTLE_ENDIAN)
294 #define bE 0
295 #define bSWAP 0
296 #else
297 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?"
298 #endif
299 #define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x))
300 #define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x))
301
302 /* NOTE: These registers are in the LE register space only, the required byte
303 * swapping is done by the NCR_700_{read|write}[b] functions */
304 #define SCNTL0_REG 0x00
305 #define FULL_ARBITRATION 0xc0
306 #define PARITY 0x08
307 #define ENABLE_PARITY 0x04
308 #define AUTO_ATN 0x02
309 #define SCNTL1_REG 0x01
310 #define SLOW_BUS 0x80
311 #define ENABLE_SELECT 0x20
312 #define ASSERT_RST 0x08
313 #define ASSERT_EVEN_PARITY 0x04
314 #define SDID_REG 0x02
315 #define SIEN_REG 0x03
316 #define PHASE_MM_INT 0x80
317 #define FUNC_COMP_INT 0x40
318 #define SEL_TIMEOUT_INT 0x20
319 #define SELECT_INT 0x10
320 #define GROSS_ERR_INT 0x08
321 #define UX_DISC_INT 0x04
322 #define RST_INT 0x02
323 #define PAR_ERR_INT 0x01
324 #define SCID_REG 0x04
325 #define SXFER_REG 0x05
326 #define ASYNC_OPERATION 0x00
327 #define SODL_REG 0x06
328 #define SOCL_REG 0x07
329 #define SFBR_REG 0x08
330 #define SIDL_REG 0x09
331 #define SBDL_REG 0x0A
332 #define SBCL_REG 0x0B
333 /* read bits */
334 #define SBCL_IO 0x01
335 /*write bits */
336 #define SYNC_DIV_AS_ASYNC 0x00
337 #define SYNC_DIV_1_0 0x01
338 #define SYNC_DIV_1_5 0x02
339 #define SYNC_DIV_2_0 0x03
340 #define DSTAT_REG 0x0C
341 #define ILGL_INST_DETECTED 0x01
342 #define WATCH_DOG_INTERRUPT 0x02
343 #define SCRIPT_INT_RECEIVED 0x04
344 #define ABORTED 0x10
345 #define SSTAT0_REG 0x0D
346 #define PARITY_ERROR 0x01
347 #define SCSI_RESET_DETECTED 0x02
348 #define UNEXPECTED_DISCONNECT 0x04
349 #define SCSI_GROSS_ERROR 0x08
350 #define SELECTED 0x10
351 #define SELECTION_TIMEOUT 0x20
352 #define FUNCTION_COMPLETE 0x40
353 #define PHASE_MISMATCH 0x80
354 #define SSTAT1_REG 0x0E
355 #define SIDL_REG_FULL 0x80
356 #define SODR_REG_FULL 0x40
357 #define SODL_REG_FULL 0x20
358 #define SSTAT2_REG 0x0F
359 #define CTEST0_REG 0x14
360 #define BTB_TIMER_DISABLE 0x40
361 #define CTEST1_REG 0x15
362 #define CTEST2_REG 0x16
363 #define CTEST3_REG 0x17
364 #define CTEST4_REG 0x18
365 #define DISABLE_FIFO 0x00
366 #define SLBE 0x10
367 #define SFWR 0x08
368 #define BYTE_LANE0 0x04
369 #define BYTE_LANE1 0x05
370 #define BYTE_LANE2 0x06
371 #define BYTE_LANE3 0x07
372 #define SCSI_ZMODE 0x20
373 #define ZMODE 0x40
374 #define CTEST5_REG 0x19
375 #define MASTER_CONTROL 0x10
376 #define DMA_DIRECTION 0x08
377 #define CTEST7_REG 0x1B
378 #define BURST_DISABLE 0x80 /* 710 only */
379 #define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */
380 #define DFP 0x08
381 #define EVP 0x04
382 #define DIFF 0x01
383 #define CTEST6_REG 0x1A
384 #define TEMP_REG 0x1C
385 #define DFIFO_REG 0x20
386 #define FLUSH_DMA_FIFO 0x80
387 #define CLR_FIFO 0x40
388 #define ISTAT_REG 0x21
389 #define ABORT_OPERATION 0x80
390 #define SOFTWARE_RESET_710 0x40
391 #define DMA_INT_PENDING 0x01
392 #define SCSI_INT_PENDING 0x02
393 #define CONNECTED 0x08
394 #define CTEST8_REG 0x22
395 #define LAST_DIS_ENBL 0x01
396 #define SHORTEN_FILTERING 0x04
397 #define ENABLE_ACTIVE_NEGATION 0x10
398 #define GENERATE_RECEIVE_PARITY 0x20
399 #define CLR_FIFO_710 0x04
400 #define FLUSH_DMA_FIFO_710 0x08
401 #define CTEST9_REG 0x23
402 #define DBC_REG 0x24
403 #define DCMD_REG 0x27
404 #define DNAD_REG 0x28
405 #define DIEN_REG 0x39
406 #define BUS_FAULT 0x20
407 #define ABORT_INT 0x10
408 #define INT_INST_INT 0x04
409 #define WD_INT 0x02
410 #define ILGL_INST_INT 0x01
411 #define DCNTL_REG 0x3B
412 #define SOFTWARE_RESET 0x01
413 #define COMPAT_700_MODE 0x01
414 #define SCRPTS_16BITS 0x20
415 #define ASYNC_DIV_2_0 0x00
416 #define ASYNC_DIV_1_5 0x40
417 #define ASYNC_DIV_1_0 0x80
418 #define ASYNC_DIV_3_0 0xc0
419 #define DMODE_710_REG 0x38
420 #define DMODE_700_REG 0x34
421 #define BURST_LENGTH_1 0x00
422 #define BURST_LENGTH_2 0x40
423 #define BURST_LENGTH_4 0x80
424 #define BURST_LENGTH_8 0xC0
425 #define DMODE_FC1 0x10
426 #define DMODE_FC2 0x20
427 #define BW16 32
428 #define MODE_286 16
429 #define IO_XFER 8
430 #define FIXED_ADDR 4
431
432 #define DSP_REG 0x2C
433 #define DSPS_REG 0x30
434
435 /* Parameters to begin SDTR negotiations. Empirically, I find that
436 * the 53c700-66 cannot handle an offset >8, so don't change this */
437 #define NCR_700_MAX_OFFSET 8
438 /* Was hoping the max offset would be greater for the 710, but
439 * empirically it seems to be 8 also */
440 #define NCR_710_MAX_OFFSET 8
441 #define NCR_700_MIN_XFERP 1
442 #define NCR_710_MIN_XFERP 0
443 #define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */
444
445 #define script_patch_32(script, symbol, value) \
446 { \
447 int i; \
448 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
449 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + value; \
450 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
451 dma_cache_wback((unsigned long)&(script)[A_##symbol##_used[i]], 4); \
452 DEBUG((" script, patching %s at %d to 0x%lx\n", \
453 #symbol, A_##symbol##_used[i], (value))); \
454 } \
455 }
456
457 #define script_patch_32_abs(script, symbol, value) \
458 { \
459 int i; \
460 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
461 (script)[A_##symbol##_used[i]] = bS_to_host(value); \
462 dma_cache_wback((unsigned long)&(script)[A_##symbol##_used[i]], 4); \
463 DEBUG((" script, patching %s at %d to 0x%lx\n", \
464 #symbol, A_##symbol##_used[i], (value))); \
465 } \
466 }
467
468 /* Used for patching the SCSI ID in the SELECT instruction */
469 #define script_patch_ID(script, symbol, value) \
470 { \
471 int i; \
472 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
473 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
474 val &= 0xff00ffff; \
475 val |= ((value) & 0xff) << 16; \
476 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
477 dma_cache_wback((unsigned long)&(script)[A_##symbol##_used[i]], 4); \
478 DEBUG((" script, patching ID field %s at %d to 0x%x\n", \
479 #symbol, A_##symbol##_used[i], val)); \
480 } \
481 }
482
483 #define script_patch_16(script, symbol, value) \
484 { \
485 int i; \
486 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
487 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
488 val &= 0xffff0000; \
489 val |= ((value) & 0xffff); \
490 (script)[A_##symbol##_used[i]] = bS_to_host(val); \
491 dma_cache_wback((unsigned long)&(script)[A_##symbol##_used[i]], 4); \
492 DEBUG((" script, patching short field %s at %d to 0x%x\n", \
493 #symbol, A_##symbol##_used[i], val)); \
494 } \
495 }
496
497 #endif
498
499 #ifdef CONFIG_53C700_MEM_MAPPED
500 static inline __u8
NCR_700_readb(struct Scsi_Host * host,__u32 reg)501 NCR_700_readb(struct Scsi_Host *host, __u32 reg)
502 {
503 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
504 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
505
506 return readb(host->base + (reg^bE));
507 }
508
509 static inline __u32
NCR_700_readl(struct Scsi_Host * host,__u32 reg)510 NCR_700_readl(struct Scsi_Host *host, __u32 reg)
511 {
512 __u32 value = __raw_readl(host->base + reg);
513 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
514 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
515 #if 1
516 /* sanity check the register */
517 if((reg & 0x3) != 0)
518 BUG();
519 #endif
520
521 return bS_to_cpu(value);
522 }
523
524 static inline void
NCR_700_writeb(__u8 value,struct Scsi_Host * host,__u32 reg)525 NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
526 {
527 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
528 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
529
530 writeb(value, host->base + (reg^bE));
531 }
532
533 static inline void
NCR_700_writel(__u32 value,struct Scsi_Host * host,__u32 reg)534 NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
535 {
536 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
537 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
538
539 #if 1
540 /* sanity check the register */
541 if((reg & 0x3) != 0)
542 BUG();
543 #endif
544
545 __raw_writel(bS_to_host(value), host->base + reg);
546 }
547 #elif defined(CONFIG_53C700_IO_MAPPED)
548 static inline __u8
NCR_700_readb(struct Scsi_Host * host,__u32 reg)549 NCR_700_readb(struct Scsi_Host *host, __u32 reg)
550 {
551 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
552 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
553
554 return inb(host->base + (reg^bE));
555 }
556
557 static inline __u32
NCR_700_readl(struct Scsi_Host * host,__u32 reg)558 NCR_700_readl(struct Scsi_Host *host, __u32 reg)
559 {
560 __u32 value = inl(host->base + reg);
561 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
562 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
563
564 #if 1
565 /* sanity check the register */
566 if((reg & 0x3) != 0)
567 BUG();
568 #endif
569
570 return bS_to_cpu(value);
571 }
572
573 static inline void
NCR_700_writeb(__u8 value,struct Scsi_Host * host,__u32 reg)574 NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
575 {
576 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
577 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
578
579 outb(value, host->base + (reg^bE));
580 }
581
582 static inline void
NCR_700_writel(__u32 value,struct Scsi_Host * host,__u32 reg)583 NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
584 {
585 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused))
586 = (struct NCR_700_Host_Parameters *)host->hostdata[0];
587
588 #if 1
589 /* sanity check the register */
590 if((reg & 0x3) != 0)
591 BUG();
592 #endif
593
594 outl(bS_to_host(value), host->base + reg);
595 }
596 #endif
597