1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
3
4 #ifndef _A6XX_GMU_H_
5 #define _A6XX_GMU_H_
6
7 #include <linux/completion.h>
8 #include <linux/iopoll.h>
9 #include <linux/interrupt.h>
10 #include <linux/notifier.h>
11 #include "msm_drv.h"
12 #include "a6xx_hfi.h"
13
14 struct a6xx_gmu_bo {
15 struct drm_gem_object *obj;
16 void *virt;
17 size_t size;
18 u64 iova;
19 };
20
21 /*
22 * These define the different GMU wake up options - these define how both the
23 * CPU and the GMU bring up the hardware
24 */
25
26 /* THe GMU has already been booted and the rentention registers are active */
27 #define GMU_WARM_BOOT 0
28
29 /* the GMU is coming up for the first time or back from a power collapse */
30 #define GMU_COLD_BOOT 1
31
32 /*
33 * These define the level of control that the GMU has - the higher the number
34 * the more things that the GMU hardware controls on its own.
35 */
36
37 /* The GMU does not do any idle state management */
38 #define GMU_IDLE_STATE_ACTIVE 0
39
40 /* The GMU manages SPTP power collapse */
41 #define GMU_IDLE_STATE_SPTP 2
42
43 /* The GMU does automatic IFPC (intra-frame power collapse) */
44 #define GMU_IDLE_STATE_IFPC 3
45
46 struct a6xx_gmu {
47 struct device *dev;
48
49 /* For serializing communication with the GMU: */
50 struct mutex lock;
51
52 struct msm_gem_address_space *aspace;
53
54 void __iomem *mmio;
55 void __iomem *rscc;
56
57 int hfi_irq;
58 int gmu_irq;
59
60 struct device *gxpd;
61 struct device *cxpd;
62
63 int idle_level;
64
65 struct a6xx_gmu_bo hfi;
66 struct a6xx_gmu_bo debug;
67 struct a6xx_gmu_bo icache;
68 struct a6xx_gmu_bo dcache;
69 struct a6xx_gmu_bo dummy;
70 struct a6xx_gmu_bo log;
71
72 int nr_clocks;
73 struct clk_bulk_data *clocks;
74 struct clk *core_clk;
75 struct clk *hub_clk;
76
77 /* current performance index set externally */
78 int current_perf_index;
79
80 int nr_gpu_freqs;
81 unsigned long gpu_freqs[16];
82 u32 gx_arc_votes[16];
83
84 int nr_gmu_freqs;
85 unsigned long gmu_freqs[4];
86 u32 cx_arc_votes[4];
87
88 unsigned long freq;
89
90 struct a6xx_hfi_queue queues[2];
91
92 bool initialized;
93 bool hung;
94 bool legacy; /* a618 or a630 */
95
96 /* For power domain callback */
97 struct notifier_block pd_nb;
98 struct completion pd_gate;
99 };
100
gmu_read(struct a6xx_gmu * gmu,u32 offset)101 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
102 {
103 return msm_readl(gmu->mmio + (offset << 2));
104 }
105
gmu_write(struct a6xx_gmu * gmu,u32 offset,u32 value)106 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
107 {
108 msm_writel(value, gmu->mmio + (offset << 2));
109 }
110
111 static inline void
gmu_write_bulk(struct a6xx_gmu * gmu,u32 offset,const u32 * data,u32 size)112 gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)
113 {
114 memcpy_toio(gmu->mmio + (offset << 2), data, size);
115 wmb();
116 }
117
gmu_rmw(struct a6xx_gmu * gmu,u32 reg,u32 mask,u32 or)118 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
119 {
120 u32 val = gmu_read(gmu, reg);
121
122 val &= ~mask;
123
124 gmu_write(gmu, reg, val | or);
125 }
126
gmu_read64(struct a6xx_gmu * gmu,u32 lo,u32 hi)127 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
128 {
129 u64 val;
130
131 val = (u64) msm_readl(gmu->mmio + (lo << 2));
132 val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
133
134 return val;
135 }
136
137 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
138 readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
139 interval, timeout)
140
gmu_read_rscc(struct a6xx_gmu * gmu,u32 offset)141 static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
142 {
143 return msm_readl(gmu->rscc + (offset << 2));
144 }
145
gmu_write_rscc(struct a6xx_gmu * gmu,u32 offset,u32 value)146 static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
147 {
148 msm_writel(value, gmu->rscc + (offset << 2));
149 }
150
151 #define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
152 readl_poll_timeout((gmu)->rscc + ((addr) << 2), val, cond, \
153 interval, timeout)
154
155 /*
156 * These are the available OOB (out of band requests) to the GMU where "out of
157 * band" means that the CPU talks to the GMU directly and not through HFI.
158 * Normally this works by writing a ITCM/DTCM register and then triggering a
159 * interrupt (the "request" bit) and waiting for an acknowledgment (the "ack"
160 * bit). The state is cleared by writing the "clear' bit to the GMU interrupt.
161 *
162 * These are used to force the GMU/GPU to stay on during a critical sequence or
163 * for hardware workarounds.
164 */
165
166 enum a6xx_gmu_oob_state {
167 /*
168 * Let the GMU know that a boot or slumber operation has started. The value in
169 * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are
170 * doing
171 */
172 GMU_OOB_BOOT_SLUMBER = 0,
173 /*
174 * Let the GMU know to not turn off any GPU registers while the CPU is in a
175 * critical section
176 */
177 GMU_OOB_GPU_SET,
178 /*
179 * Set a new power level for the GPU when the CPU is doing frequency scaling
180 */
181 GMU_OOB_DCVS_SET,
182 /*
183 * Used to keep the GPU on for CPU-side reads of performance counters.
184 */
185 GMU_OOB_PERFCOUNTER_SET,
186 };
187
188 void a6xx_hfi_init(struct a6xx_gmu *gmu);
189 int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
190 void a6xx_hfi_stop(struct a6xx_gmu *gmu);
191 int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu);
192 int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index);
193
194 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
195 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
196 void a6xx_sptprac_disable(struct a6xx_gmu *gmu);
197 int a6xx_sptprac_enable(struct a6xx_gmu *gmu);
198
199 #endif
200