1 /*
2  * File:	mca_asm.h
3  * Purpose:	Machine check handling specific defines
4  *
5  * Copyright (C) 1999 Silicon Graphics, Inc.
6  * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
7  * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
8  * Copyright (C) 2000 Hewlett-Packard Co.
9  * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
10  * Copyright (C) 2002 Intel Corp.
11  * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
12  * Copyright (C) 2005 Silicon Graphics, Inc
13  * Copyright (C) 2005 Keith Owens <kaos@sgi.com>
14  */
15 #ifndef _ASM_IA64_MCA_ASM_H
16 #define _ASM_IA64_MCA_ASM_H
17 
18 #define PSR_IC		13
19 #define PSR_I		14
20 #define	PSR_DT		17
21 #define PSR_RT		27
22 #define PSR_MC		35
23 #define PSR_IT		36
24 #define PSR_BN		44
25 
26 /*
27  * This macro converts a instruction virtual address to a physical address
28  * Right now for simulation purposes the virtual addresses are
29  * direct mapped to physical addresses.
30  *	1. Lop off bits 61 thru 63 in the virtual address
31  */
32 #define INST_VA_TO_PA(addr)							\
33 	dep	addr	= 0, addr, 61, 3
34 /*
35  * This macro converts a data virtual address to a physical address
36  * Right now for simulation purposes the virtual addresses are
37  * direct mapped to physical addresses.
38  *	1. Lop off bits 61 thru 63 in the virtual address
39  */
40 #define DATA_VA_TO_PA(addr)							\
41 	tpa	addr	= addr
42 /*
43  * This macro converts a data physical address to a virtual address
44  * Right now for simulation purposes the virtual addresses are
45  * direct mapped to physical addresses.
46  *	1. Put 0x7 in bits 61 thru 63.
47  */
48 #define DATA_PA_TO_VA(addr,temp)							\
49 	mov	temp	= 0x7	;;							\
50 	dep	addr	= temp, addr, 61, 3
51 
52 #define GET_THIS_PADDR(reg, var)		\
53 	mov	reg = IA64_KR(PER_CPU_DATA);;	\
54         addl	reg = THIS_CPU(var), reg
55 
56 /*
57  * This macro jumps to the instruction at the given virtual address
58  * and starts execution in physical mode with all the address
59  * translations turned off.
60  *	1.	Save the current psr
61  *	2.	Make sure that all the upper 32 bits are off
62  *
63  *	3.	Clear the interrupt enable and interrupt state collection bits
64  *		in the psr before updating the ipsr and iip.
65  *
66  *	4.	Turn off the instruction, data and rse translation bits of the psr
67  *		and store the new value into ipsr
68  *		Also make sure that the interrupts are disabled.
69  *		Ensure that we are in little endian mode.
70  *		[psr.{rt, it, dt, i, be} = 0]
71  *
72  *	5.	Get the physical address corresponding to the virtual address
73  *		of the next instruction bundle and put it in iip.
74  *		(Using magic numbers 24 and 40 in the deposint instruction since
75  *		 the IA64_SDK code directly maps to lower 24bits as physical address
76  *		 from a virtual address).
77  *
78  *	6.	Do an rfi to move the values from ipsr to psr and iip to ip.
79  */
80 #define  PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr)				\
81 	mov	old_psr = psr;								\
82 	;;										\
83 	dep	old_psr = 0, old_psr, 32, 32;						\
84 											\
85 	mov	ar.rsc = 0 ;								\
86 	;;										\
87 	srlz.d;										\
88 	mov	temp2 = ar.bspstore;							\
89 	;;										\
90 	DATA_VA_TO_PA(temp2);								\
91 	;;										\
92 	mov	temp1 = ar.rnat;							\
93 	;;										\
94 	mov	ar.bspstore = temp2;							\
95 	;;										\
96 	mov	ar.rnat = temp1;							\
97 	mov	temp1 = psr;								\
98 	mov	temp2 = psr;								\
99 	;;										\
100 											\
101 	dep	temp2 = 0, temp2, PSR_IC, 2;						\
102 	;;										\
103 	mov	psr.l = temp2;								\
104 	;;										\
105 	srlz.d;										\
106 	dep	temp1 = 0, temp1, 32, 32;						\
107 	;;										\
108 	dep	temp1 = 0, temp1, PSR_IT, 1;						\
109 	;;										\
110 	dep	temp1 = 0, temp1, PSR_DT, 1;						\
111 	;;										\
112 	dep	temp1 = 0, temp1, PSR_RT, 1;						\
113 	;;										\
114 	dep	temp1 = 0, temp1, PSR_I, 1;						\
115 	;;										\
116 	dep	temp1 = 0, temp1, PSR_IC, 1;						\
117 	;;										\
118 	dep	temp1 = -1, temp1, PSR_MC, 1;						\
119 	;;										\
120 	mov	cr.ipsr = temp1;							\
121 	;;										\
122 	LOAD_PHYSICAL(p0, temp2, start_addr);						\
123 	;;										\
124 	mov	cr.iip = temp2;								\
125 	mov	cr.ifs = r0;								\
126 	DATA_VA_TO_PA(sp);								\
127 	DATA_VA_TO_PA(gp);								\
128 	;;										\
129 	srlz.i;										\
130 	;;										\
131 	nop	1;									\
132 	nop	2;									\
133 	nop	1;									\
134 	nop	2;									\
135 	rfi;										\
136 	;;
137 
138 /*
139  * This macro jumps to the instruction at the given virtual address
140  * and starts execution in virtual mode with all the address
141  * translations turned on.
142  *	1.	Get the old saved psr
143  *
144  *	2.	Clear the interrupt state collection bit in the current psr.
145  *
146  *	3.	Set the instruction translation bit back in the old psr
147  *		Note we have to do this since we are right now saving only the
148  *		lower 32-bits of old psr.(Also the old psr has the data and
149  *		rse translation bits on)
150  *
151  *	4.	Set ipsr to this old_psr with "it" bit set and "bn" = 1.
152  *
153  *	5.	Reset the current thread pointer (r13).
154  *
155  *	6.	Set iip to the virtual address of the next instruction bundle.
156  *
157  *	7.	Do an rfi to move ipsr to psr and iip to ip.
158  */
159 
160 #define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr)	\
161 	mov	temp2 = psr;					\
162 	;;							\
163 	mov	old_psr = temp2;				\
164 	;;							\
165 	dep	temp2 = 0, temp2, PSR_IC, 2;			\
166 	;;							\
167 	mov	psr.l = temp2;					\
168 	mov	ar.rsc = 0;					\
169 	;;							\
170 	srlz.d;							\
171 	mov	r13 = ar.k6;					\
172 	mov	temp2 = ar.bspstore;				\
173 	;;							\
174 	DATA_PA_TO_VA(temp2,temp1);				\
175 	;;							\
176 	mov	temp1 = ar.rnat;				\
177 	;;							\
178 	mov	ar.bspstore = temp2;				\
179 	;;							\
180 	mov	ar.rnat = temp1;				\
181 	;;							\
182 	mov	temp1 = old_psr;				\
183 	;;							\
184 	mov	temp2 = 1;					\
185 	;;							\
186 	dep	temp1 = temp2, temp1, PSR_IC, 1;		\
187 	;;							\
188 	dep	temp1 = temp2, temp1, PSR_IT, 1;		\
189 	;;							\
190 	dep	temp1 = temp2, temp1, PSR_DT, 1;		\
191 	;;							\
192 	dep	temp1 = temp2, temp1, PSR_RT, 1;		\
193 	;;							\
194 	dep	temp1 = temp2, temp1, PSR_BN, 1;		\
195 	;;							\
196 								\
197 	mov     cr.ipsr = temp1;				\
198 	movl	temp2 = start_addr;				\
199 	;;							\
200 	mov	cr.iip = temp2;					\
201 	movl	gp = __gp					\
202 	;;							\
203 	DATA_PA_TO_VA(sp, temp1);				\
204 	srlz.i;							\
205 	;;							\
206 	nop	1;						\
207 	nop	2;						\
208 	nop	1;						\
209 	rfi							\
210 	;;
211 
212 /*
213  * The MCA and INIT stacks in struct ia64_mca_cpu look like normal kernel
214  * stacks, except that the SAL/OS state and a switch_stack are stored near the
215  * top of the MCA/INIT stack.  To support concurrent entry to MCA or INIT, as
216  * well as MCA over INIT, each event needs its own SAL/OS state.  All entries
217  * are 16 byte aligned.
218  *
219  *      +---------------------------+
220  *      |          pt_regs          |
221  *      +---------------------------+
222  *      |        switch_stack       |
223  *      +---------------------------+
224  *      |        SAL/OS state       |
225  *      +---------------------------+
226  *      |    16 byte scratch area   |
227  *      +---------------------------+ <-------- SP at start of C MCA handler
228  *      |           .....           |
229  *      +---------------------------+
230  *      | RBS for MCA/INIT handler  |
231  *      +---------------------------+
232  *      | struct task for MCA/INIT  |
233  *      +---------------------------+ <-------- Bottom of MCA/INIT stack
234  */
235 
236 #define ALIGN16(x)			((x)&~15)
237 #define MCA_PT_REGS_OFFSET		ALIGN16(KERNEL_STACK_SIZE-IA64_PT_REGS_SIZE)
238 #define MCA_SWITCH_STACK_OFFSET		ALIGN16(MCA_PT_REGS_OFFSET-IA64_SWITCH_STACK_SIZE)
239 #define MCA_SOS_OFFSET			ALIGN16(MCA_SWITCH_STACK_OFFSET-IA64_SAL_OS_STATE_SIZE)
240 #define MCA_SP_OFFSET			ALIGN16(MCA_SOS_OFFSET-16)
241 
242 #endif /* _ASM_IA64_MCA_ASM_H */
243