1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note 2 * 3 * Copyright 2016-2022 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef HABANALABS_H_ 9 #define HABANALABS_H_ 10 11 #include <linux/types.h> 12 #include <linux/ioctl.h> 13 14 /* 15 * Defines that are asic-specific but constitutes as ABI between kernel driver 16 * and userspace 17 */ 18 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */ 19 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */ 20 21 /* 22 * 128 SOBs reserved for collective wait 23 * 16 SOBs reserved for sync stream 24 */ 25 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144 26 27 /* 28 * 64 monitors reserved for collective wait 29 * 8 monitors reserved for sync stream 30 */ 31 #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72 32 33 /* Max number of elements in timestamps registration buffers */ 34 #define TS_MAX_ELEMENTS_NUM (1 << 20) /* 1MB */ 35 36 /* 37 * Goya queue Numbering 38 * 39 * The external queues (PCI DMA channels) MUST be before the internal queues 40 * and each group (PCI DMA channels and internal) must be contiguous inside 41 * itself but there can be a gap between the two groups (although not 42 * recommended) 43 */ 44 45 enum goya_queue_id { 46 GOYA_QUEUE_ID_DMA_0 = 0, 47 GOYA_QUEUE_ID_DMA_1 = 1, 48 GOYA_QUEUE_ID_DMA_2 = 2, 49 GOYA_QUEUE_ID_DMA_3 = 3, 50 GOYA_QUEUE_ID_DMA_4 = 4, 51 GOYA_QUEUE_ID_CPU_PQ = 5, 52 GOYA_QUEUE_ID_MME = 6, /* Internal queues start here */ 53 GOYA_QUEUE_ID_TPC0 = 7, 54 GOYA_QUEUE_ID_TPC1 = 8, 55 GOYA_QUEUE_ID_TPC2 = 9, 56 GOYA_QUEUE_ID_TPC3 = 10, 57 GOYA_QUEUE_ID_TPC4 = 11, 58 GOYA_QUEUE_ID_TPC5 = 12, 59 GOYA_QUEUE_ID_TPC6 = 13, 60 GOYA_QUEUE_ID_TPC7 = 14, 61 GOYA_QUEUE_ID_SIZE 62 }; 63 64 /* 65 * Gaudi queue Numbering 66 * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*. 67 * Except one CPU queue, all the rest are internal queues. 68 */ 69 70 enum gaudi_queue_id { 71 GAUDI_QUEUE_ID_DMA_0_0 = 0, /* external */ 72 GAUDI_QUEUE_ID_DMA_0_1 = 1, /* external */ 73 GAUDI_QUEUE_ID_DMA_0_2 = 2, /* external */ 74 GAUDI_QUEUE_ID_DMA_0_3 = 3, /* external */ 75 GAUDI_QUEUE_ID_DMA_1_0 = 4, /* external */ 76 GAUDI_QUEUE_ID_DMA_1_1 = 5, /* external */ 77 GAUDI_QUEUE_ID_DMA_1_2 = 6, /* external */ 78 GAUDI_QUEUE_ID_DMA_1_3 = 7, /* external */ 79 GAUDI_QUEUE_ID_CPU_PQ = 8, /* CPU */ 80 GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */ 81 GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */ 82 GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */ 83 GAUDI_QUEUE_ID_DMA_2_3 = 12, /* internal */ 84 GAUDI_QUEUE_ID_DMA_3_0 = 13, /* internal */ 85 GAUDI_QUEUE_ID_DMA_3_1 = 14, /* internal */ 86 GAUDI_QUEUE_ID_DMA_3_2 = 15, /* internal */ 87 GAUDI_QUEUE_ID_DMA_3_3 = 16, /* internal */ 88 GAUDI_QUEUE_ID_DMA_4_0 = 17, /* internal */ 89 GAUDI_QUEUE_ID_DMA_4_1 = 18, /* internal */ 90 GAUDI_QUEUE_ID_DMA_4_2 = 19, /* internal */ 91 GAUDI_QUEUE_ID_DMA_4_3 = 20, /* internal */ 92 GAUDI_QUEUE_ID_DMA_5_0 = 21, /* internal */ 93 GAUDI_QUEUE_ID_DMA_5_1 = 22, /* internal */ 94 GAUDI_QUEUE_ID_DMA_5_2 = 23, /* internal */ 95 GAUDI_QUEUE_ID_DMA_5_3 = 24, /* internal */ 96 GAUDI_QUEUE_ID_DMA_6_0 = 25, /* internal */ 97 GAUDI_QUEUE_ID_DMA_6_1 = 26, /* internal */ 98 GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */ 99 GAUDI_QUEUE_ID_DMA_6_3 = 28, /* internal */ 100 GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */ 101 GAUDI_QUEUE_ID_DMA_7_1 = 30, /* internal */ 102 GAUDI_QUEUE_ID_DMA_7_2 = 31, /* internal */ 103 GAUDI_QUEUE_ID_DMA_7_3 = 32, /* internal */ 104 GAUDI_QUEUE_ID_MME_0_0 = 33, /* internal */ 105 GAUDI_QUEUE_ID_MME_0_1 = 34, /* internal */ 106 GAUDI_QUEUE_ID_MME_0_2 = 35, /* internal */ 107 GAUDI_QUEUE_ID_MME_0_3 = 36, /* internal */ 108 GAUDI_QUEUE_ID_MME_1_0 = 37, /* internal */ 109 GAUDI_QUEUE_ID_MME_1_1 = 38, /* internal */ 110 GAUDI_QUEUE_ID_MME_1_2 = 39, /* internal */ 111 GAUDI_QUEUE_ID_MME_1_3 = 40, /* internal */ 112 GAUDI_QUEUE_ID_TPC_0_0 = 41, /* internal */ 113 GAUDI_QUEUE_ID_TPC_0_1 = 42, /* internal */ 114 GAUDI_QUEUE_ID_TPC_0_2 = 43, /* internal */ 115 GAUDI_QUEUE_ID_TPC_0_3 = 44, /* internal */ 116 GAUDI_QUEUE_ID_TPC_1_0 = 45, /* internal */ 117 GAUDI_QUEUE_ID_TPC_1_1 = 46, /* internal */ 118 GAUDI_QUEUE_ID_TPC_1_2 = 47, /* internal */ 119 GAUDI_QUEUE_ID_TPC_1_3 = 48, /* internal */ 120 GAUDI_QUEUE_ID_TPC_2_0 = 49, /* internal */ 121 GAUDI_QUEUE_ID_TPC_2_1 = 50, /* internal */ 122 GAUDI_QUEUE_ID_TPC_2_2 = 51, /* internal */ 123 GAUDI_QUEUE_ID_TPC_2_3 = 52, /* internal */ 124 GAUDI_QUEUE_ID_TPC_3_0 = 53, /* internal */ 125 GAUDI_QUEUE_ID_TPC_3_1 = 54, /* internal */ 126 GAUDI_QUEUE_ID_TPC_3_2 = 55, /* internal */ 127 GAUDI_QUEUE_ID_TPC_3_3 = 56, /* internal */ 128 GAUDI_QUEUE_ID_TPC_4_0 = 57, /* internal */ 129 GAUDI_QUEUE_ID_TPC_4_1 = 58, /* internal */ 130 GAUDI_QUEUE_ID_TPC_4_2 = 59, /* internal */ 131 GAUDI_QUEUE_ID_TPC_4_3 = 60, /* internal */ 132 GAUDI_QUEUE_ID_TPC_5_0 = 61, /* internal */ 133 GAUDI_QUEUE_ID_TPC_5_1 = 62, /* internal */ 134 GAUDI_QUEUE_ID_TPC_5_2 = 63, /* internal */ 135 GAUDI_QUEUE_ID_TPC_5_3 = 64, /* internal */ 136 GAUDI_QUEUE_ID_TPC_6_0 = 65, /* internal */ 137 GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */ 138 GAUDI_QUEUE_ID_TPC_6_2 = 67, /* internal */ 139 GAUDI_QUEUE_ID_TPC_6_3 = 68, /* internal */ 140 GAUDI_QUEUE_ID_TPC_7_0 = 69, /* internal */ 141 GAUDI_QUEUE_ID_TPC_7_1 = 70, /* internal */ 142 GAUDI_QUEUE_ID_TPC_7_2 = 71, /* internal */ 143 GAUDI_QUEUE_ID_TPC_7_3 = 72, /* internal */ 144 GAUDI_QUEUE_ID_NIC_0_0 = 73, /* internal */ 145 GAUDI_QUEUE_ID_NIC_0_1 = 74, /* internal */ 146 GAUDI_QUEUE_ID_NIC_0_2 = 75, /* internal */ 147 GAUDI_QUEUE_ID_NIC_0_3 = 76, /* internal */ 148 GAUDI_QUEUE_ID_NIC_1_0 = 77, /* internal */ 149 GAUDI_QUEUE_ID_NIC_1_1 = 78, /* internal */ 150 GAUDI_QUEUE_ID_NIC_1_2 = 79, /* internal */ 151 GAUDI_QUEUE_ID_NIC_1_3 = 80, /* internal */ 152 GAUDI_QUEUE_ID_NIC_2_0 = 81, /* internal */ 153 GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */ 154 GAUDI_QUEUE_ID_NIC_2_2 = 83, /* internal */ 155 GAUDI_QUEUE_ID_NIC_2_3 = 84, /* internal */ 156 GAUDI_QUEUE_ID_NIC_3_0 = 85, /* internal */ 157 GAUDI_QUEUE_ID_NIC_3_1 = 86, /* internal */ 158 GAUDI_QUEUE_ID_NIC_3_2 = 87, /* internal */ 159 GAUDI_QUEUE_ID_NIC_3_3 = 88, /* internal */ 160 GAUDI_QUEUE_ID_NIC_4_0 = 89, /* internal */ 161 GAUDI_QUEUE_ID_NIC_4_1 = 90, /* internal */ 162 GAUDI_QUEUE_ID_NIC_4_2 = 91, /* internal */ 163 GAUDI_QUEUE_ID_NIC_4_3 = 92, /* internal */ 164 GAUDI_QUEUE_ID_NIC_5_0 = 93, /* internal */ 165 GAUDI_QUEUE_ID_NIC_5_1 = 94, /* internal */ 166 GAUDI_QUEUE_ID_NIC_5_2 = 95, /* internal */ 167 GAUDI_QUEUE_ID_NIC_5_3 = 96, /* internal */ 168 GAUDI_QUEUE_ID_NIC_6_0 = 97, /* internal */ 169 GAUDI_QUEUE_ID_NIC_6_1 = 98, /* internal */ 170 GAUDI_QUEUE_ID_NIC_6_2 = 99, /* internal */ 171 GAUDI_QUEUE_ID_NIC_6_3 = 100, /* internal */ 172 GAUDI_QUEUE_ID_NIC_7_0 = 101, /* internal */ 173 GAUDI_QUEUE_ID_NIC_7_1 = 102, /* internal */ 174 GAUDI_QUEUE_ID_NIC_7_2 = 103, /* internal */ 175 GAUDI_QUEUE_ID_NIC_7_3 = 104, /* internal */ 176 GAUDI_QUEUE_ID_NIC_8_0 = 105, /* internal */ 177 GAUDI_QUEUE_ID_NIC_8_1 = 106, /* internal */ 178 GAUDI_QUEUE_ID_NIC_8_2 = 107, /* internal */ 179 GAUDI_QUEUE_ID_NIC_8_3 = 108, /* internal */ 180 GAUDI_QUEUE_ID_NIC_9_0 = 109, /* internal */ 181 GAUDI_QUEUE_ID_NIC_9_1 = 110, /* internal */ 182 GAUDI_QUEUE_ID_NIC_9_2 = 111, /* internal */ 183 GAUDI_QUEUE_ID_NIC_9_3 = 112, /* internal */ 184 GAUDI_QUEUE_ID_SIZE 185 }; 186 187 /* 188 * In GAUDI2 we have two modes of operation in regard to queues: 189 * 1. Legacy mode, where each QMAN exposes 4 streams to the user 190 * 2. F/W mode, where we use F/W to schedule the JOBS to the different queues. 191 * 192 * When in legacy mode, the user sends the queue id per JOB according to 193 * enum gaudi2_queue_id below. 194 * 195 * When in F/W mode, the user sends a stream id per Command Submission. The 196 * stream id is a running number from 0 up to (N-1), where N is the number 197 * of streams the F/W exposes and is passed to the user in 198 * struct hl_info_hw_ip_info 199 */ 200 201 enum gaudi2_queue_id { 202 GAUDI2_QUEUE_ID_PDMA_0_0 = 0, 203 GAUDI2_QUEUE_ID_PDMA_0_1 = 1, 204 GAUDI2_QUEUE_ID_PDMA_0_2 = 2, 205 GAUDI2_QUEUE_ID_PDMA_0_3 = 3, 206 GAUDI2_QUEUE_ID_PDMA_1_0 = 4, 207 GAUDI2_QUEUE_ID_PDMA_1_1 = 5, 208 GAUDI2_QUEUE_ID_PDMA_1_2 = 6, 209 GAUDI2_QUEUE_ID_PDMA_1_3 = 7, 210 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0 = 8, 211 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1 = 9, 212 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2 = 10, 213 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3 = 11, 214 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0 = 12, 215 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1 = 13, 216 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2 = 14, 217 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3 = 15, 218 GAUDI2_QUEUE_ID_DCORE0_MME_0_0 = 16, 219 GAUDI2_QUEUE_ID_DCORE0_MME_0_1 = 17, 220 GAUDI2_QUEUE_ID_DCORE0_MME_0_2 = 18, 221 GAUDI2_QUEUE_ID_DCORE0_MME_0_3 = 19, 222 GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 = 20, 223 GAUDI2_QUEUE_ID_DCORE0_TPC_0_1 = 21, 224 GAUDI2_QUEUE_ID_DCORE0_TPC_0_2 = 22, 225 GAUDI2_QUEUE_ID_DCORE0_TPC_0_3 = 23, 226 GAUDI2_QUEUE_ID_DCORE0_TPC_1_0 = 24, 227 GAUDI2_QUEUE_ID_DCORE0_TPC_1_1 = 25, 228 GAUDI2_QUEUE_ID_DCORE0_TPC_1_2 = 26, 229 GAUDI2_QUEUE_ID_DCORE0_TPC_1_3 = 27, 230 GAUDI2_QUEUE_ID_DCORE0_TPC_2_0 = 28, 231 GAUDI2_QUEUE_ID_DCORE0_TPC_2_1 = 29, 232 GAUDI2_QUEUE_ID_DCORE0_TPC_2_2 = 30, 233 GAUDI2_QUEUE_ID_DCORE0_TPC_2_3 = 31, 234 GAUDI2_QUEUE_ID_DCORE0_TPC_3_0 = 32, 235 GAUDI2_QUEUE_ID_DCORE0_TPC_3_1 = 33, 236 GAUDI2_QUEUE_ID_DCORE0_TPC_3_2 = 34, 237 GAUDI2_QUEUE_ID_DCORE0_TPC_3_3 = 35, 238 GAUDI2_QUEUE_ID_DCORE0_TPC_4_0 = 36, 239 GAUDI2_QUEUE_ID_DCORE0_TPC_4_1 = 37, 240 GAUDI2_QUEUE_ID_DCORE0_TPC_4_2 = 38, 241 GAUDI2_QUEUE_ID_DCORE0_TPC_4_3 = 39, 242 GAUDI2_QUEUE_ID_DCORE0_TPC_5_0 = 40, 243 GAUDI2_QUEUE_ID_DCORE0_TPC_5_1 = 41, 244 GAUDI2_QUEUE_ID_DCORE0_TPC_5_2 = 42, 245 GAUDI2_QUEUE_ID_DCORE0_TPC_5_3 = 43, 246 GAUDI2_QUEUE_ID_DCORE0_TPC_6_0 = 44, 247 GAUDI2_QUEUE_ID_DCORE0_TPC_6_1 = 45, 248 GAUDI2_QUEUE_ID_DCORE0_TPC_6_2 = 46, 249 GAUDI2_QUEUE_ID_DCORE0_TPC_6_3 = 47, 250 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0 = 48, 251 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1 = 49, 252 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2 = 50, 253 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3 = 51, 254 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0 = 52, 255 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1 = 53, 256 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2 = 54, 257 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3 = 55, 258 GAUDI2_QUEUE_ID_DCORE1_MME_0_0 = 56, 259 GAUDI2_QUEUE_ID_DCORE1_MME_0_1 = 57, 260 GAUDI2_QUEUE_ID_DCORE1_MME_0_2 = 58, 261 GAUDI2_QUEUE_ID_DCORE1_MME_0_3 = 59, 262 GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 = 60, 263 GAUDI2_QUEUE_ID_DCORE1_TPC_0_1 = 61, 264 GAUDI2_QUEUE_ID_DCORE1_TPC_0_2 = 62, 265 GAUDI2_QUEUE_ID_DCORE1_TPC_0_3 = 63, 266 GAUDI2_QUEUE_ID_DCORE1_TPC_1_0 = 64, 267 GAUDI2_QUEUE_ID_DCORE1_TPC_1_1 = 65, 268 GAUDI2_QUEUE_ID_DCORE1_TPC_1_2 = 66, 269 GAUDI2_QUEUE_ID_DCORE1_TPC_1_3 = 67, 270 GAUDI2_QUEUE_ID_DCORE1_TPC_2_0 = 68, 271 GAUDI2_QUEUE_ID_DCORE1_TPC_2_1 = 69, 272 GAUDI2_QUEUE_ID_DCORE1_TPC_2_2 = 70, 273 GAUDI2_QUEUE_ID_DCORE1_TPC_2_3 = 71, 274 GAUDI2_QUEUE_ID_DCORE1_TPC_3_0 = 72, 275 GAUDI2_QUEUE_ID_DCORE1_TPC_3_1 = 73, 276 GAUDI2_QUEUE_ID_DCORE1_TPC_3_2 = 74, 277 GAUDI2_QUEUE_ID_DCORE1_TPC_3_3 = 75, 278 GAUDI2_QUEUE_ID_DCORE1_TPC_4_0 = 76, 279 GAUDI2_QUEUE_ID_DCORE1_TPC_4_1 = 77, 280 GAUDI2_QUEUE_ID_DCORE1_TPC_4_2 = 78, 281 GAUDI2_QUEUE_ID_DCORE1_TPC_4_3 = 79, 282 GAUDI2_QUEUE_ID_DCORE1_TPC_5_0 = 80, 283 GAUDI2_QUEUE_ID_DCORE1_TPC_5_1 = 81, 284 GAUDI2_QUEUE_ID_DCORE1_TPC_5_2 = 82, 285 GAUDI2_QUEUE_ID_DCORE1_TPC_5_3 = 83, 286 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0 = 84, 287 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1 = 85, 288 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2 = 86, 289 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3 = 87, 290 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0 = 88, 291 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1 = 89, 292 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2 = 90, 293 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3 = 91, 294 GAUDI2_QUEUE_ID_DCORE2_MME_0_0 = 92, 295 GAUDI2_QUEUE_ID_DCORE2_MME_0_1 = 93, 296 GAUDI2_QUEUE_ID_DCORE2_MME_0_2 = 94, 297 GAUDI2_QUEUE_ID_DCORE2_MME_0_3 = 95, 298 GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 = 96, 299 GAUDI2_QUEUE_ID_DCORE2_TPC_0_1 = 97, 300 GAUDI2_QUEUE_ID_DCORE2_TPC_0_2 = 98, 301 GAUDI2_QUEUE_ID_DCORE2_TPC_0_3 = 99, 302 GAUDI2_QUEUE_ID_DCORE2_TPC_1_0 = 100, 303 GAUDI2_QUEUE_ID_DCORE2_TPC_1_1 = 101, 304 GAUDI2_QUEUE_ID_DCORE2_TPC_1_2 = 102, 305 GAUDI2_QUEUE_ID_DCORE2_TPC_1_3 = 103, 306 GAUDI2_QUEUE_ID_DCORE2_TPC_2_0 = 104, 307 GAUDI2_QUEUE_ID_DCORE2_TPC_2_1 = 105, 308 GAUDI2_QUEUE_ID_DCORE2_TPC_2_2 = 106, 309 GAUDI2_QUEUE_ID_DCORE2_TPC_2_3 = 107, 310 GAUDI2_QUEUE_ID_DCORE2_TPC_3_0 = 108, 311 GAUDI2_QUEUE_ID_DCORE2_TPC_3_1 = 109, 312 GAUDI2_QUEUE_ID_DCORE2_TPC_3_2 = 110, 313 GAUDI2_QUEUE_ID_DCORE2_TPC_3_3 = 111, 314 GAUDI2_QUEUE_ID_DCORE2_TPC_4_0 = 112, 315 GAUDI2_QUEUE_ID_DCORE2_TPC_4_1 = 113, 316 GAUDI2_QUEUE_ID_DCORE2_TPC_4_2 = 114, 317 GAUDI2_QUEUE_ID_DCORE2_TPC_4_3 = 115, 318 GAUDI2_QUEUE_ID_DCORE2_TPC_5_0 = 116, 319 GAUDI2_QUEUE_ID_DCORE2_TPC_5_1 = 117, 320 GAUDI2_QUEUE_ID_DCORE2_TPC_5_2 = 118, 321 GAUDI2_QUEUE_ID_DCORE2_TPC_5_3 = 119, 322 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0 = 120, 323 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1 = 121, 324 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2 = 122, 325 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3 = 123, 326 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0 = 124, 327 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1 = 125, 328 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2 = 126, 329 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3 = 127, 330 GAUDI2_QUEUE_ID_DCORE3_MME_0_0 = 128, 331 GAUDI2_QUEUE_ID_DCORE3_MME_0_1 = 129, 332 GAUDI2_QUEUE_ID_DCORE3_MME_0_2 = 130, 333 GAUDI2_QUEUE_ID_DCORE3_MME_0_3 = 131, 334 GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 = 132, 335 GAUDI2_QUEUE_ID_DCORE3_TPC_0_1 = 133, 336 GAUDI2_QUEUE_ID_DCORE3_TPC_0_2 = 134, 337 GAUDI2_QUEUE_ID_DCORE3_TPC_0_3 = 135, 338 GAUDI2_QUEUE_ID_DCORE3_TPC_1_0 = 136, 339 GAUDI2_QUEUE_ID_DCORE3_TPC_1_1 = 137, 340 GAUDI2_QUEUE_ID_DCORE3_TPC_1_2 = 138, 341 GAUDI2_QUEUE_ID_DCORE3_TPC_1_3 = 139, 342 GAUDI2_QUEUE_ID_DCORE3_TPC_2_0 = 140, 343 GAUDI2_QUEUE_ID_DCORE3_TPC_2_1 = 141, 344 GAUDI2_QUEUE_ID_DCORE3_TPC_2_2 = 142, 345 GAUDI2_QUEUE_ID_DCORE3_TPC_2_3 = 143, 346 GAUDI2_QUEUE_ID_DCORE3_TPC_3_0 = 144, 347 GAUDI2_QUEUE_ID_DCORE3_TPC_3_1 = 145, 348 GAUDI2_QUEUE_ID_DCORE3_TPC_3_2 = 146, 349 GAUDI2_QUEUE_ID_DCORE3_TPC_3_3 = 147, 350 GAUDI2_QUEUE_ID_DCORE3_TPC_4_0 = 148, 351 GAUDI2_QUEUE_ID_DCORE3_TPC_4_1 = 149, 352 GAUDI2_QUEUE_ID_DCORE3_TPC_4_2 = 150, 353 GAUDI2_QUEUE_ID_DCORE3_TPC_4_3 = 151, 354 GAUDI2_QUEUE_ID_DCORE3_TPC_5_0 = 152, 355 GAUDI2_QUEUE_ID_DCORE3_TPC_5_1 = 153, 356 GAUDI2_QUEUE_ID_DCORE3_TPC_5_2 = 154, 357 GAUDI2_QUEUE_ID_DCORE3_TPC_5_3 = 155, 358 GAUDI2_QUEUE_ID_NIC_0_0 = 156, 359 GAUDI2_QUEUE_ID_NIC_0_1 = 157, 360 GAUDI2_QUEUE_ID_NIC_0_2 = 158, 361 GAUDI2_QUEUE_ID_NIC_0_3 = 159, 362 GAUDI2_QUEUE_ID_NIC_1_0 = 160, 363 GAUDI2_QUEUE_ID_NIC_1_1 = 161, 364 GAUDI2_QUEUE_ID_NIC_1_2 = 162, 365 GAUDI2_QUEUE_ID_NIC_1_3 = 163, 366 GAUDI2_QUEUE_ID_NIC_2_0 = 164, 367 GAUDI2_QUEUE_ID_NIC_2_1 = 165, 368 GAUDI2_QUEUE_ID_NIC_2_2 = 166, 369 GAUDI2_QUEUE_ID_NIC_2_3 = 167, 370 GAUDI2_QUEUE_ID_NIC_3_0 = 168, 371 GAUDI2_QUEUE_ID_NIC_3_1 = 169, 372 GAUDI2_QUEUE_ID_NIC_3_2 = 170, 373 GAUDI2_QUEUE_ID_NIC_3_3 = 171, 374 GAUDI2_QUEUE_ID_NIC_4_0 = 172, 375 GAUDI2_QUEUE_ID_NIC_4_1 = 173, 376 GAUDI2_QUEUE_ID_NIC_4_2 = 174, 377 GAUDI2_QUEUE_ID_NIC_4_3 = 175, 378 GAUDI2_QUEUE_ID_NIC_5_0 = 176, 379 GAUDI2_QUEUE_ID_NIC_5_1 = 177, 380 GAUDI2_QUEUE_ID_NIC_5_2 = 178, 381 GAUDI2_QUEUE_ID_NIC_5_3 = 179, 382 GAUDI2_QUEUE_ID_NIC_6_0 = 180, 383 GAUDI2_QUEUE_ID_NIC_6_1 = 181, 384 GAUDI2_QUEUE_ID_NIC_6_2 = 182, 385 GAUDI2_QUEUE_ID_NIC_6_3 = 183, 386 GAUDI2_QUEUE_ID_NIC_7_0 = 184, 387 GAUDI2_QUEUE_ID_NIC_7_1 = 185, 388 GAUDI2_QUEUE_ID_NIC_7_2 = 186, 389 GAUDI2_QUEUE_ID_NIC_7_3 = 187, 390 GAUDI2_QUEUE_ID_NIC_8_0 = 188, 391 GAUDI2_QUEUE_ID_NIC_8_1 = 189, 392 GAUDI2_QUEUE_ID_NIC_8_2 = 190, 393 GAUDI2_QUEUE_ID_NIC_8_3 = 191, 394 GAUDI2_QUEUE_ID_NIC_9_0 = 192, 395 GAUDI2_QUEUE_ID_NIC_9_1 = 193, 396 GAUDI2_QUEUE_ID_NIC_9_2 = 194, 397 GAUDI2_QUEUE_ID_NIC_9_3 = 195, 398 GAUDI2_QUEUE_ID_NIC_10_0 = 196, 399 GAUDI2_QUEUE_ID_NIC_10_1 = 197, 400 GAUDI2_QUEUE_ID_NIC_10_2 = 198, 401 GAUDI2_QUEUE_ID_NIC_10_3 = 199, 402 GAUDI2_QUEUE_ID_NIC_11_0 = 200, 403 GAUDI2_QUEUE_ID_NIC_11_1 = 201, 404 GAUDI2_QUEUE_ID_NIC_11_2 = 202, 405 GAUDI2_QUEUE_ID_NIC_11_3 = 203, 406 GAUDI2_QUEUE_ID_NIC_12_0 = 204, 407 GAUDI2_QUEUE_ID_NIC_12_1 = 205, 408 GAUDI2_QUEUE_ID_NIC_12_2 = 206, 409 GAUDI2_QUEUE_ID_NIC_12_3 = 207, 410 GAUDI2_QUEUE_ID_NIC_13_0 = 208, 411 GAUDI2_QUEUE_ID_NIC_13_1 = 209, 412 GAUDI2_QUEUE_ID_NIC_13_2 = 210, 413 GAUDI2_QUEUE_ID_NIC_13_3 = 211, 414 GAUDI2_QUEUE_ID_NIC_14_0 = 212, 415 GAUDI2_QUEUE_ID_NIC_14_1 = 213, 416 GAUDI2_QUEUE_ID_NIC_14_2 = 214, 417 GAUDI2_QUEUE_ID_NIC_14_3 = 215, 418 GAUDI2_QUEUE_ID_NIC_15_0 = 216, 419 GAUDI2_QUEUE_ID_NIC_15_1 = 217, 420 GAUDI2_QUEUE_ID_NIC_15_2 = 218, 421 GAUDI2_QUEUE_ID_NIC_15_3 = 219, 422 GAUDI2_QUEUE_ID_NIC_16_0 = 220, 423 GAUDI2_QUEUE_ID_NIC_16_1 = 221, 424 GAUDI2_QUEUE_ID_NIC_16_2 = 222, 425 GAUDI2_QUEUE_ID_NIC_16_3 = 223, 426 GAUDI2_QUEUE_ID_NIC_17_0 = 224, 427 GAUDI2_QUEUE_ID_NIC_17_1 = 225, 428 GAUDI2_QUEUE_ID_NIC_17_2 = 226, 429 GAUDI2_QUEUE_ID_NIC_17_3 = 227, 430 GAUDI2_QUEUE_ID_NIC_18_0 = 228, 431 GAUDI2_QUEUE_ID_NIC_18_1 = 229, 432 GAUDI2_QUEUE_ID_NIC_18_2 = 230, 433 GAUDI2_QUEUE_ID_NIC_18_3 = 231, 434 GAUDI2_QUEUE_ID_NIC_19_0 = 232, 435 GAUDI2_QUEUE_ID_NIC_19_1 = 233, 436 GAUDI2_QUEUE_ID_NIC_19_2 = 234, 437 GAUDI2_QUEUE_ID_NIC_19_3 = 235, 438 GAUDI2_QUEUE_ID_NIC_20_0 = 236, 439 GAUDI2_QUEUE_ID_NIC_20_1 = 237, 440 GAUDI2_QUEUE_ID_NIC_20_2 = 238, 441 GAUDI2_QUEUE_ID_NIC_20_3 = 239, 442 GAUDI2_QUEUE_ID_NIC_21_0 = 240, 443 GAUDI2_QUEUE_ID_NIC_21_1 = 241, 444 GAUDI2_QUEUE_ID_NIC_21_2 = 242, 445 GAUDI2_QUEUE_ID_NIC_21_3 = 243, 446 GAUDI2_QUEUE_ID_NIC_22_0 = 244, 447 GAUDI2_QUEUE_ID_NIC_22_1 = 245, 448 GAUDI2_QUEUE_ID_NIC_22_2 = 246, 449 GAUDI2_QUEUE_ID_NIC_22_3 = 247, 450 GAUDI2_QUEUE_ID_NIC_23_0 = 248, 451 GAUDI2_QUEUE_ID_NIC_23_1 = 249, 452 GAUDI2_QUEUE_ID_NIC_23_2 = 250, 453 GAUDI2_QUEUE_ID_NIC_23_3 = 251, 454 GAUDI2_QUEUE_ID_ROT_0_0 = 252, 455 GAUDI2_QUEUE_ID_ROT_0_1 = 253, 456 GAUDI2_QUEUE_ID_ROT_0_2 = 254, 457 GAUDI2_QUEUE_ID_ROT_0_3 = 255, 458 GAUDI2_QUEUE_ID_ROT_1_0 = 256, 459 GAUDI2_QUEUE_ID_ROT_1_1 = 257, 460 GAUDI2_QUEUE_ID_ROT_1_2 = 258, 461 GAUDI2_QUEUE_ID_ROT_1_3 = 259, 462 GAUDI2_QUEUE_ID_CPU_PQ = 260, 463 GAUDI2_QUEUE_ID_SIZE 464 }; 465 466 /* 467 * Engine Numbering 468 * 469 * Used in the "busy_engines_mask" field in `struct hl_info_hw_idle' 470 */ 471 472 enum goya_engine_id { 473 GOYA_ENGINE_ID_DMA_0 = 0, 474 GOYA_ENGINE_ID_DMA_1, 475 GOYA_ENGINE_ID_DMA_2, 476 GOYA_ENGINE_ID_DMA_3, 477 GOYA_ENGINE_ID_DMA_4, 478 GOYA_ENGINE_ID_MME_0, 479 GOYA_ENGINE_ID_TPC_0, 480 GOYA_ENGINE_ID_TPC_1, 481 GOYA_ENGINE_ID_TPC_2, 482 GOYA_ENGINE_ID_TPC_3, 483 GOYA_ENGINE_ID_TPC_4, 484 GOYA_ENGINE_ID_TPC_5, 485 GOYA_ENGINE_ID_TPC_6, 486 GOYA_ENGINE_ID_TPC_7, 487 GOYA_ENGINE_ID_SIZE 488 }; 489 490 enum gaudi_engine_id { 491 GAUDI_ENGINE_ID_DMA_0 = 0, 492 GAUDI_ENGINE_ID_DMA_1, 493 GAUDI_ENGINE_ID_DMA_2, 494 GAUDI_ENGINE_ID_DMA_3, 495 GAUDI_ENGINE_ID_DMA_4, 496 GAUDI_ENGINE_ID_DMA_5, 497 GAUDI_ENGINE_ID_DMA_6, 498 GAUDI_ENGINE_ID_DMA_7, 499 GAUDI_ENGINE_ID_MME_0, 500 GAUDI_ENGINE_ID_MME_1, 501 GAUDI_ENGINE_ID_MME_2, 502 GAUDI_ENGINE_ID_MME_3, 503 GAUDI_ENGINE_ID_TPC_0, 504 GAUDI_ENGINE_ID_TPC_1, 505 GAUDI_ENGINE_ID_TPC_2, 506 GAUDI_ENGINE_ID_TPC_3, 507 GAUDI_ENGINE_ID_TPC_4, 508 GAUDI_ENGINE_ID_TPC_5, 509 GAUDI_ENGINE_ID_TPC_6, 510 GAUDI_ENGINE_ID_TPC_7, 511 GAUDI_ENGINE_ID_NIC_0, 512 GAUDI_ENGINE_ID_NIC_1, 513 GAUDI_ENGINE_ID_NIC_2, 514 GAUDI_ENGINE_ID_NIC_3, 515 GAUDI_ENGINE_ID_NIC_4, 516 GAUDI_ENGINE_ID_NIC_5, 517 GAUDI_ENGINE_ID_NIC_6, 518 GAUDI_ENGINE_ID_NIC_7, 519 GAUDI_ENGINE_ID_NIC_8, 520 GAUDI_ENGINE_ID_NIC_9, 521 GAUDI_ENGINE_ID_SIZE 522 }; 523 524 enum gaudi2_engine_id { 525 GAUDI2_DCORE0_ENGINE_ID_EDMA_0 = 0, 526 GAUDI2_DCORE0_ENGINE_ID_EDMA_1, 527 GAUDI2_DCORE0_ENGINE_ID_MME, 528 GAUDI2_DCORE0_ENGINE_ID_TPC_0, 529 GAUDI2_DCORE0_ENGINE_ID_TPC_1, 530 GAUDI2_DCORE0_ENGINE_ID_TPC_2, 531 GAUDI2_DCORE0_ENGINE_ID_TPC_3, 532 GAUDI2_DCORE0_ENGINE_ID_TPC_4, 533 GAUDI2_DCORE0_ENGINE_ID_TPC_5, 534 GAUDI2_DCORE0_ENGINE_ID_DEC_0, 535 GAUDI2_DCORE0_ENGINE_ID_DEC_1, 536 GAUDI2_DCORE1_ENGINE_ID_EDMA_0, 537 GAUDI2_DCORE1_ENGINE_ID_EDMA_1, 538 GAUDI2_DCORE1_ENGINE_ID_MME, 539 GAUDI2_DCORE1_ENGINE_ID_TPC_0, 540 GAUDI2_DCORE1_ENGINE_ID_TPC_1, 541 GAUDI2_DCORE1_ENGINE_ID_TPC_2, 542 GAUDI2_DCORE1_ENGINE_ID_TPC_3, 543 GAUDI2_DCORE1_ENGINE_ID_TPC_4, 544 GAUDI2_DCORE1_ENGINE_ID_TPC_5, 545 GAUDI2_DCORE1_ENGINE_ID_DEC_0, 546 GAUDI2_DCORE1_ENGINE_ID_DEC_1, 547 GAUDI2_DCORE2_ENGINE_ID_EDMA_0, 548 GAUDI2_DCORE2_ENGINE_ID_EDMA_1, 549 GAUDI2_DCORE2_ENGINE_ID_MME, 550 GAUDI2_DCORE2_ENGINE_ID_TPC_0, 551 GAUDI2_DCORE2_ENGINE_ID_TPC_1, 552 GAUDI2_DCORE2_ENGINE_ID_TPC_2, 553 GAUDI2_DCORE2_ENGINE_ID_TPC_3, 554 GAUDI2_DCORE2_ENGINE_ID_TPC_4, 555 GAUDI2_DCORE2_ENGINE_ID_TPC_5, 556 GAUDI2_DCORE2_ENGINE_ID_DEC_0, 557 GAUDI2_DCORE2_ENGINE_ID_DEC_1, 558 GAUDI2_DCORE3_ENGINE_ID_EDMA_0, 559 GAUDI2_DCORE3_ENGINE_ID_EDMA_1, 560 GAUDI2_DCORE3_ENGINE_ID_MME, 561 GAUDI2_DCORE3_ENGINE_ID_TPC_0, 562 GAUDI2_DCORE3_ENGINE_ID_TPC_1, 563 GAUDI2_DCORE3_ENGINE_ID_TPC_2, 564 GAUDI2_DCORE3_ENGINE_ID_TPC_3, 565 GAUDI2_DCORE3_ENGINE_ID_TPC_4, 566 GAUDI2_DCORE3_ENGINE_ID_TPC_5, 567 GAUDI2_DCORE3_ENGINE_ID_DEC_0, 568 GAUDI2_DCORE3_ENGINE_ID_DEC_1, 569 GAUDI2_DCORE0_ENGINE_ID_TPC_6, 570 GAUDI2_ENGINE_ID_PDMA_0, 571 GAUDI2_ENGINE_ID_PDMA_1, 572 GAUDI2_ENGINE_ID_ROT_0, 573 GAUDI2_ENGINE_ID_ROT_1, 574 GAUDI2_PCIE_ENGINE_ID_DEC_0, 575 GAUDI2_PCIE_ENGINE_ID_DEC_1, 576 GAUDI2_ENGINE_ID_NIC0_0, 577 GAUDI2_ENGINE_ID_NIC0_1, 578 GAUDI2_ENGINE_ID_NIC1_0, 579 GAUDI2_ENGINE_ID_NIC1_1, 580 GAUDI2_ENGINE_ID_NIC2_0, 581 GAUDI2_ENGINE_ID_NIC2_1, 582 GAUDI2_ENGINE_ID_NIC3_0, 583 GAUDI2_ENGINE_ID_NIC3_1, 584 GAUDI2_ENGINE_ID_NIC4_0, 585 GAUDI2_ENGINE_ID_NIC4_1, 586 GAUDI2_ENGINE_ID_NIC5_0, 587 GAUDI2_ENGINE_ID_NIC5_1, 588 GAUDI2_ENGINE_ID_NIC6_0, 589 GAUDI2_ENGINE_ID_NIC6_1, 590 GAUDI2_ENGINE_ID_NIC7_0, 591 GAUDI2_ENGINE_ID_NIC7_1, 592 GAUDI2_ENGINE_ID_NIC8_0, 593 GAUDI2_ENGINE_ID_NIC8_1, 594 GAUDI2_ENGINE_ID_NIC9_0, 595 GAUDI2_ENGINE_ID_NIC9_1, 596 GAUDI2_ENGINE_ID_NIC10_0, 597 GAUDI2_ENGINE_ID_NIC10_1, 598 GAUDI2_ENGINE_ID_NIC11_0, 599 GAUDI2_ENGINE_ID_NIC11_1, 600 GAUDI2_ENGINE_ID_SIZE 601 }; 602 603 /* 604 * ASIC specific PLL index 605 * 606 * Used to retrieve in frequency info of different IPs via 607 * HL_INFO_PLL_FREQUENCY under HL_IOCTL_INFO IOCTL. The enums need to be 608 * used as an index in struct hl_pll_frequency_info 609 */ 610 611 enum hl_goya_pll_index { 612 HL_GOYA_CPU_PLL = 0, 613 HL_GOYA_IC_PLL, 614 HL_GOYA_MC_PLL, 615 HL_GOYA_MME_PLL, 616 HL_GOYA_PCI_PLL, 617 HL_GOYA_EMMC_PLL, 618 HL_GOYA_TPC_PLL, 619 HL_GOYA_PLL_MAX 620 }; 621 622 enum hl_gaudi_pll_index { 623 HL_GAUDI_CPU_PLL = 0, 624 HL_GAUDI_PCI_PLL, 625 HL_GAUDI_SRAM_PLL, 626 HL_GAUDI_HBM_PLL, 627 HL_GAUDI_NIC_PLL, 628 HL_GAUDI_DMA_PLL, 629 HL_GAUDI_MESH_PLL, 630 HL_GAUDI_MME_PLL, 631 HL_GAUDI_TPC_PLL, 632 HL_GAUDI_IF_PLL, 633 HL_GAUDI_PLL_MAX 634 }; 635 636 enum hl_gaudi2_pll_index { 637 HL_GAUDI2_CPU_PLL = 0, 638 HL_GAUDI2_PCI_PLL, 639 HL_GAUDI2_SRAM_PLL, 640 HL_GAUDI2_HBM_PLL, 641 HL_GAUDI2_NIC_PLL, 642 HL_GAUDI2_DMA_PLL, 643 HL_GAUDI2_MESH_PLL, 644 HL_GAUDI2_MME_PLL, 645 HL_GAUDI2_TPC_PLL, 646 HL_GAUDI2_IF_PLL, 647 HL_GAUDI2_VID_PLL, 648 HL_GAUDI2_MSS_PLL, 649 HL_GAUDI2_PLL_MAX 650 }; 651 652 /** 653 * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is 654 * submitted to the GOYA's DMA QMAN. This attribute is not relevant 655 * to the H/W but the kernel driver use it to parse the packet's 656 * addresses and patch/validate them. 657 * @HL_DMA_HOST_TO_DRAM: DMA operation from Host memory to GOYA's DDR. 658 * @HL_DMA_HOST_TO_SRAM: DMA operation from Host memory to GOYA's SRAM. 659 * @HL_DMA_DRAM_TO_SRAM: DMA operation from GOYA's DDR to GOYA's SRAM. 660 * @HL_DMA_SRAM_TO_DRAM: DMA operation from GOYA's SRAM to GOYA's DDR. 661 * @HL_DMA_SRAM_TO_HOST: DMA operation from GOYA's SRAM to Host memory. 662 * @HL_DMA_DRAM_TO_HOST: DMA operation from GOYA's DDR to Host memory. 663 * @HL_DMA_DRAM_TO_DRAM: DMA operation from GOYA's DDR to GOYA's DDR. 664 * @HL_DMA_SRAM_TO_SRAM: DMA operation from GOYA's SRAM to GOYA's SRAM. 665 * @HL_DMA_ENUM_MAX: number of values in enum 666 */ 667 enum hl_goya_dma_direction { 668 HL_DMA_HOST_TO_DRAM, 669 HL_DMA_HOST_TO_SRAM, 670 HL_DMA_DRAM_TO_SRAM, 671 HL_DMA_SRAM_TO_DRAM, 672 HL_DMA_SRAM_TO_HOST, 673 HL_DMA_DRAM_TO_HOST, 674 HL_DMA_DRAM_TO_DRAM, 675 HL_DMA_SRAM_TO_SRAM, 676 HL_DMA_ENUM_MAX 677 }; 678 679 /** 680 * enum hl_device_status - Device status information. 681 * @HL_DEVICE_STATUS_OPERATIONAL: Device is operational. 682 * @HL_DEVICE_STATUS_IN_RESET: Device is currently during reset. 683 * @HL_DEVICE_STATUS_MALFUNCTION: Device is unusable. 684 * @HL_DEVICE_STATUS_NEEDS_RESET: Device needs reset because auto reset was disabled. 685 * @HL_DEVICE_STATUS_IN_DEVICE_CREATION: Device is operational but its creation is still in 686 * progress. 687 * @HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE: Device is currently during reset that was 688 * triggered because the user released the device 689 * @HL_DEVICE_STATUS_LAST: Last status. 690 */ 691 enum hl_device_status { 692 HL_DEVICE_STATUS_OPERATIONAL, 693 HL_DEVICE_STATUS_IN_RESET, 694 HL_DEVICE_STATUS_MALFUNCTION, 695 HL_DEVICE_STATUS_NEEDS_RESET, 696 HL_DEVICE_STATUS_IN_DEVICE_CREATION, 697 HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE, 698 HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE 699 }; 700 701 enum hl_server_type { 702 HL_SERVER_TYPE_UNKNOWN = 0, 703 HL_SERVER_GAUDI_HLS1 = 1, 704 HL_SERVER_GAUDI_HLS1H = 2, 705 HL_SERVER_GAUDI_TYPE1 = 3, 706 HL_SERVER_GAUDI_TYPE2 = 4, 707 HL_SERVER_GAUDI2_HLS2 = 5 708 }; 709 710 /* 711 * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command 712 * 713 * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event 714 * HL_NOTIFIER_EVENT_UNDEFINED_OPCODE - Indicates undefined operation code 715 * HL_NOTIFIER_EVENT_DEVICE_RESET - Indicates device requires a reset 716 * HL_NOTIFIER_EVENT_CS_TIMEOUT - Indicates CS timeout error 717 * HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE - Indicates device is unavailable 718 * HL_NOTIFIER_EVENT_USER_ENGINE_ERR - Indicates device engine in error state 719 * HL_NOTIFIER_EVENT_GENERAL_HW_ERR - Indicates device HW error 720 */ 721 #define HL_NOTIFIER_EVENT_TPC_ASSERT (1ULL << 0) 722 #define HL_NOTIFIER_EVENT_UNDEFINED_OPCODE (1ULL << 1) 723 #define HL_NOTIFIER_EVENT_DEVICE_RESET (1ULL << 2) 724 #define HL_NOTIFIER_EVENT_CS_TIMEOUT (1ULL << 3) 725 #define HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE (1ULL << 4) 726 #define HL_NOTIFIER_EVENT_USER_ENGINE_ERR (1ULL << 5) 727 #define HL_NOTIFIER_EVENT_GENERAL_HW_ERR (1ULL << 6) 728 729 /* Opcode for management ioctl 730 * 731 * HW_IP_INFO - Receive information about different IP blocks in the 732 * device. 733 * HL_INFO_HW_EVENTS - Receive an array describing how many times each event 734 * occurred since the last hard reset. 735 * HL_INFO_DRAM_USAGE - Retrieve the dram usage inside the device and of the 736 * specific context. This is relevant only for devices 737 * where the dram is managed by the kernel driver 738 * HL_INFO_HW_IDLE - Retrieve information about the idle status of each 739 * internal engine. 740 * HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't 741 * require an open context. 742 * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device 743 * over the last period specified by the user. 744 * The period can be between 100ms to 1s, in 745 * resolution of 100ms. The return value is a 746 * percentage of the utilization rate. 747 * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each 748 * event occurred since the driver was loaded. 749 * HL_INFO_CLK_RATE - Retrieve the current and maximum clock rate 750 * of the device in MHz. The maximum clock rate is 751 * configurable via sysfs parameter 752 * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset 753 * operations performed on the device since the last 754 * time the driver was loaded. 755 * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time 756 * for synchronization. 757 * HL_INFO_CS_COUNTERS - Retrieve command submission counters 758 * HL_INFO_PCI_COUNTERS - Retrieve PCI counters 759 * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason 760 * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore 761 * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption 762 * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency 763 * HL_INFO_POWER - Retrieve power information 764 * HL_INFO_OPEN_STATS - Retrieve info regarding recent device open calls 765 * HL_INFO_DRAM_REPLACED_ROWS - Retrieve DRAM replaced rows info 766 * HL_INFO_DRAM_PENDING_ROWS - Retrieve DRAM pending rows num 767 * HL_INFO_LAST_ERR_OPEN_DEV_TIME - Retrieve timestamp of the last time the device was opened 768 * and CS timeout or razwi error occurred. 769 * HL_INFO_CS_TIMEOUT_EVENT - Retrieve CS timeout timestamp and its related CS sequence number. 770 * HL_INFO_RAZWI_EVENT - Retrieve parameters of razwi: 771 * Timestamp of razwi. 772 * The address which accessing it caused the razwi. 773 * Razwi initiator. 774 * Razwi cause, was it a page fault or MMU access error. 775 * HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES - Retrieve valid page sizes for device memory allocation 776 * HL_INFO_SECURED_ATTESTATION - Retrieve attestation report of the boot. 777 * HL_INFO_REGISTER_EVENTFD - Register eventfd for event notifications. 778 * HL_INFO_UNREGISTER_EVENTFD - Unregister eventfd 779 * HL_INFO_GET_EVENTS - Retrieve the last occurred events 780 * HL_INFO_UNDEFINED_OPCODE_EVENT - Retrieve last undefined opcode error information. 781 */ 782 #define HL_INFO_HW_IP_INFO 0 783 #define HL_INFO_HW_EVENTS 1 784 #define HL_INFO_DRAM_USAGE 2 785 #define HL_INFO_HW_IDLE 3 786 #define HL_INFO_DEVICE_STATUS 4 787 #define HL_INFO_DEVICE_UTILIZATION 6 788 #define HL_INFO_HW_EVENTS_AGGREGATE 7 789 #define HL_INFO_CLK_RATE 8 790 #define HL_INFO_RESET_COUNT 9 791 #define HL_INFO_TIME_SYNC 10 792 #define HL_INFO_CS_COUNTERS 11 793 #define HL_INFO_PCI_COUNTERS 12 794 #define HL_INFO_CLK_THROTTLE_REASON 13 795 #define HL_INFO_SYNC_MANAGER 14 796 #define HL_INFO_TOTAL_ENERGY 15 797 #define HL_INFO_PLL_FREQUENCY 16 798 #define HL_INFO_POWER 17 799 #define HL_INFO_OPEN_STATS 18 800 #define HL_INFO_DRAM_REPLACED_ROWS 21 801 #define HL_INFO_DRAM_PENDING_ROWS 22 802 #define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23 803 #define HL_INFO_CS_TIMEOUT_EVENT 24 804 #define HL_INFO_RAZWI_EVENT 25 805 #define HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES 26 806 #define HL_INFO_SECURED_ATTESTATION 27 807 #define HL_INFO_REGISTER_EVENTFD 28 808 #define HL_INFO_UNREGISTER_EVENTFD 29 809 #define HL_INFO_GET_EVENTS 30 810 #define HL_INFO_UNDEFINED_OPCODE_EVENT 31 811 #define HL_INFO_ENGINE_STATUS 32 812 813 #define HL_INFO_VERSION_MAX_LEN 128 814 #define HL_INFO_CARD_NAME_MAX_LEN 16 815 816 /* Maximum buffer size for retrieving engines status */ 817 #define HL_ENGINES_DATA_MAX_SIZE SZ_1M 818 819 /** 820 * struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC 821 * @sram_base_address: The first SRAM physical base address that is free to be 822 * used by the user. 823 * @dram_base_address: The first DRAM virtual or physical base address that is 824 * free to be used by the user. 825 * @dram_size: The DRAM size that is available to the user. 826 * @sram_size: The SRAM size that is available to the user. 827 * @num_of_events: The number of events that can be received from the f/w. This 828 * is needed so the user can what is the size of the h/w events 829 * array he needs to pass to the kernel when he wants to fetch 830 * the event counters. 831 * @device_id: PCI device ID of the ASIC. 832 * @module_id: Module ID of the ASIC for mezzanine cards in servers 833 * (From OCP spec). 834 * @decoder_enabled_mask: Bit-mask that represents which decoders are enabled. 835 * @first_available_interrupt_id: The first available interrupt ID for the user 836 * to be used when it works with user interrupts. 837 * Relevant for Gaudi2 and later. 838 * @server_type: Server type that the Gaudi ASIC is currently installed in. 839 * The value is according to enum hl_server_type 840 * @cpld_version: CPLD version on the board. 841 * @psoc_pci_pll_nr: PCI PLL NR value. Needed by the profiler in some ASICs. 842 * @psoc_pci_pll_nf: PCI PLL NF value. Needed by the profiler in some ASICs. 843 * @psoc_pci_pll_od: PCI PLL OD value. Needed by the profiler in some ASICs. 844 * @psoc_pci_pll_div_factor: PCI PLL DIV factor value. Needed by the profiler 845 * in some ASICs. 846 * @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant 847 * for Goya/Gaudi only. 848 * @dram_enabled: Whether the DRAM is enabled. 849 * @security_enabled: Whether security is enabled on device. 850 * @mme_master_slave_mode: Indicate whether the MME is working in master/slave 851 * configuration. Relevant for Greco and later. 852 * @cpucp_version: The CPUCP f/w version. 853 * @card_name: The card name as passed by the f/w. 854 * @tpc_enabled_mask_ext: Bit-mask that represents which TPCs are enabled. 855 * Relevant for Greco and later. 856 * @dram_page_size: The DRAM physical page size. 857 * @edma_enabled_mask: Bit-mask that represents which EDMAs are enabled. 858 * Relevant for Gaudi2 and later. 859 * @number_of_user_interrupts: The number of interrupts that are available to the userspace 860 * application to use. Relevant for Gaudi2 and later. 861 * @device_mem_alloc_default_page_size: default page size used in device memory allocation. 862 */ 863 struct hl_info_hw_ip_info { 864 __u64 sram_base_address; 865 __u64 dram_base_address; 866 __u64 dram_size; 867 __u32 sram_size; 868 __u32 num_of_events; 869 __u32 device_id; 870 __u32 module_id; 871 __u32 decoder_enabled_mask; 872 __u16 first_available_interrupt_id; 873 __u16 server_type; 874 __u32 cpld_version; 875 __u32 psoc_pci_pll_nr; 876 __u32 psoc_pci_pll_nf; 877 __u32 psoc_pci_pll_od; 878 __u32 psoc_pci_pll_div_factor; 879 __u8 tpc_enabled_mask; 880 __u8 dram_enabled; 881 __u8 security_enabled; 882 __u8 mme_master_slave_mode; 883 __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN]; 884 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; 885 __u64 tpc_enabled_mask_ext; 886 __u64 dram_page_size; 887 __u32 edma_enabled_mask; 888 __u16 number_of_user_interrupts; 889 __u16 pad2; 890 __u64 reserved4; 891 __u64 device_mem_alloc_default_page_size; 892 }; 893 894 struct hl_info_dram_usage { 895 __u64 dram_free_mem; 896 __u64 ctx_dram_mem; 897 }; 898 899 #define HL_BUSY_ENGINES_MASK_EXT_SIZE 2 900 901 struct hl_info_hw_idle { 902 __u32 is_idle; 903 /* 904 * Bitmask of busy engines. 905 * Bits definition is according to `enum <chip>_engine_id'. 906 */ 907 __u32 busy_engines_mask; 908 909 /* 910 * Extended Bitmask of busy engines. 911 * Bits definition is according to `enum <chip>_engine_id'. 912 */ 913 __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE]; 914 }; 915 916 struct hl_info_device_status { 917 __u32 status; 918 __u32 pad; 919 }; 920 921 struct hl_info_device_utilization { 922 __u32 utilization; 923 __u32 pad; 924 }; 925 926 struct hl_info_clk_rate { 927 __u32 cur_clk_rate_mhz; 928 __u32 max_clk_rate_mhz; 929 }; 930 931 struct hl_info_reset_count { 932 __u32 hard_reset_cnt; 933 __u32 soft_reset_cnt; 934 }; 935 936 struct hl_info_time_sync { 937 __u64 device_time; 938 __u64 host_time; 939 }; 940 941 /** 942 * struct hl_info_pci_counters - pci counters 943 * @rx_throughput: PCI rx throughput KBps 944 * @tx_throughput: PCI tx throughput KBps 945 * @replay_cnt: PCI replay counter 946 */ 947 struct hl_info_pci_counters { 948 __u64 rx_throughput; 949 __u64 tx_throughput; 950 __u64 replay_cnt; 951 }; 952 953 enum hl_clk_throttling_type { 954 HL_CLK_THROTTLE_TYPE_POWER, 955 HL_CLK_THROTTLE_TYPE_THERMAL, 956 HL_CLK_THROTTLE_TYPE_MAX 957 }; 958 959 /* clk_throttling_reason masks */ 960 #define HL_CLK_THROTTLE_POWER (1 << HL_CLK_THROTTLE_TYPE_POWER) 961 #define HL_CLK_THROTTLE_THERMAL (1 << HL_CLK_THROTTLE_TYPE_THERMAL) 962 963 /** 964 * struct hl_info_clk_throttle - clock throttling reason 965 * @clk_throttling_reason: each bit represents a clk throttling reason 966 * @clk_throttling_timestamp_us: represents CPU timestamp in microseconds of the start-event 967 * @clk_throttling_duration_ns: the clock throttle time in nanosec 968 */ 969 struct hl_info_clk_throttle { 970 __u32 clk_throttling_reason; 971 __u32 pad; 972 __u64 clk_throttling_timestamp_us[HL_CLK_THROTTLE_TYPE_MAX]; 973 __u64 clk_throttling_duration_ns[HL_CLK_THROTTLE_TYPE_MAX]; 974 }; 975 976 /** 977 * struct hl_info_energy - device energy information 978 * @total_energy_consumption: total device energy consumption 979 */ 980 struct hl_info_energy { 981 __u64 total_energy_consumption; 982 }; 983 984 #define HL_PLL_NUM_OUTPUTS 4 985 986 struct hl_pll_frequency_info { 987 __u16 output[HL_PLL_NUM_OUTPUTS]; 988 }; 989 990 /** 991 * struct hl_open_stats_info - device open statistics information 992 * @open_counter: ever growing counter, increased on each successful dev open 993 * @last_open_period_ms: duration (ms) device was open last time 994 * @is_compute_ctx_active: Whether there is an active compute context executing 995 * @compute_ctx_in_release: true if the current compute context is being released 996 */ 997 struct hl_open_stats_info { 998 __u64 open_counter; 999 __u64 last_open_period_ms; 1000 __u8 is_compute_ctx_active; 1001 __u8 compute_ctx_in_release; 1002 __u8 pad[6]; 1003 }; 1004 1005 /** 1006 * struct hl_power_info - power information 1007 * @power: power consumption 1008 */ 1009 struct hl_power_info { 1010 __u64 power; 1011 }; 1012 1013 /** 1014 * struct hl_info_sync_manager - sync manager information 1015 * @first_available_sync_object: first available sob 1016 * @first_available_monitor: first available monitor 1017 * @first_available_cq: first available cq 1018 */ 1019 struct hl_info_sync_manager { 1020 __u32 first_available_sync_object; 1021 __u32 first_available_monitor; 1022 __u32 first_available_cq; 1023 __u32 reserved; 1024 }; 1025 1026 /** 1027 * struct hl_info_cs_counters - command submission counters 1028 * @total_out_of_mem_drop_cnt: total dropped due to memory allocation issue 1029 * @ctx_out_of_mem_drop_cnt: context dropped due to memory allocation issue 1030 * @total_parsing_drop_cnt: total dropped due to error in packet parsing 1031 * @ctx_parsing_drop_cnt: context dropped due to error in packet parsing 1032 * @total_queue_full_drop_cnt: total dropped due to queue full 1033 * @ctx_queue_full_drop_cnt: context dropped due to queue full 1034 * @total_device_in_reset_drop_cnt: total dropped due to device in reset 1035 * @ctx_device_in_reset_drop_cnt: context dropped due to device in reset 1036 * @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight 1037 * @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight 1038 * @total_validation_drop_cnt: total dropped due to validation error 1039 * @ctx_validation_drop_cnt: context dropped due to validation error 1040 */ 1041 struct hl_info_cs_counters { 1042 __u64 total_out_of_mem_drop_cnt; 1043 __u64 ctx_out_of_mem_drop_cnt; 1044 __u64 total_parsing_drop_cnt; 1045 __u64 ctx_parsing_drop_cnt; 1046 __u64 total_queue_full_drop_cnt; 1047 __u64 ctx_queue_full_drop_cnt; 1048 __u64 total_device_in_reset_drop_cnt; 1049 __u64 ctx_device_in_reset_drop_cnt; 1050 __u64 total_max_cs_in_flight_drop_cnt; 1051 __u64 ctx_max_cs_in_flight_drop_cnt; 1052 __u64 total_validation_drop_cnt; 1053 __u64 ctx_validation_drop_cnt; 1054 }; 1055 1056 /** 1057 * struct hl_info_last_err_open_dev_time - last error boot information. 1058 * @timestamp: timestamp of last time the device was opened and error occurred. 1059 */ 1060 struct hl_info_last_err_open_dev_time { 1061 __s64 timestamp; 1062 }; 1063 1064 /** 1065 * struct hl_info_cs_timeout_event - last CS timeout information. 1066 * @timestamp: timestamp when last CS timeout event occurred. 1067 * @seq: sequence number of last CS timeout event. 1068 */ 1069 struct hl_info_cs_timeout_event { 1070 __s64 timestamp; 1071 __u64 seq; 1072 }; 1073 1074 #define HL_RAZWI_PAGE_FAULT 0 1075 #define HL_RAZWI_MMU_ACCESS_ERROR 1 1076 1077 /** 1078 * struct hl_info_razwi_event - razwi information. 1079 * @timestamp: timestamp of razwi. 1080 * @addr: address which accessing it caused razwi. 1081 * @engine_id_1: engine id of the razwi initiator, if it was initiated by engine that does not 1082 * have engine id it will be set to U16_MAX. 1083 * @engine_id_2: second engine id of razwi initiator. Might happen that razwi have 2 possible 1084 * engines which one them caused the razwi. In that case, it will contain the 1085 * second possible engine id, otherwise it will be set to U16_MAX. 1086 * @no_engine_id: if razwi initiator does not have engine id, this field will be set to 1, 1087 * otherwise 0. 1088 * @error_type: cause of razwi, page fault or access error, otherwise it will be set to U8_MAX. 1089 * @pad: padding to 64 bit. 1090 */ 1091 struct hl_info_razwi_event { 1092 __s64 timestamp; 1093 __u64 addr; 1094 __u16 engine_id_1; 1095 __u16 engine_id_2; 1096 __u8 no_engine_id; 1097 __u8 error_type; 1098 __u8 pad[2]; 1099 }; 1100 1101 #define MAX_QMAN_STREAMS_INFO 4 1102 #define OPCODE_INFO_MAX_ADDR_SIZE 8 1103 /** 1104 * struct hl_info_undefined_opcode_event - info about last undefined opcode error 1105 * @timestamp: timestamp of the undefined opcode error 1106 * @cb_addr_streams: CB addresses (per stream) that are currently exists in the PQ 1107 * entries. In case all streams array entries are 1108 * filled with values, it means the execution was in Lower-CP. 1109 * @cq_addr: the address of the current handled command buffer 1110 * @cq_size: the size of the current handled command buffer 1111 * @cb_addr_streams_len: num of streams - actual len of cb_addr_streams array. 1112 * should be equal to 1 in case of undefined opcode 1113 * in Upper-CP (specific stream) and equal to 4 incase 1114 * of undefined opcode in Lower-CP. 1115 * @engine_id: engine-id that the error occurred on 1116 * @stream_id: the stream id the error occurred on. In case the stream equals to 1117 * MAX_QMAN_STREAMS_INFO it means the error occurred on a Lower-CP. 1118 */ 1119 struct hl_info_undefined_opcode_event { 1120 __s64 timestamp; 1121 __u64 cb_addr_streams[MAX_QMAN_STREAMS_INFO][OPCODE_INFO_MAX_ADDR_SIZE]; 1122 __u64 cq_addr; 1123 __u32 cq_size; 1124 __u32 cb_addr_streams_len; 1125 __u32 engine_id; 1126 __u32 stream_id; 1127 }; 1128 1129 /** 1130 * struct hl_info_dev_memalloc_page_sizes - valid page sizes in device mem alloc information. 1131 * @page_order_bitmask: bitmap in which a set bit represents the order of the supported page size 1132 * (e.g. 0x2100000 means that 1MB and 32MB pages are supported). 1133 */ 1134 struct hl_info_dev_memalloc_page_sizes { 1135 __u64 page_order_bitmask; 1136 }; 1137 1138 #define SEC_PCR_DATA_BUF_SZ 256 1139 #define SEC_PCR_QUOTE_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ 1140 #define SEC_SIGNATURE_BUF_SZ 255 /* (256 - 1) 1 byte used for size */ 1141 #define SEC_PUB_DATA_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ 1142 #define SEC_CERTIFICATE_BUF_SZ 2046 /* (2048 - 2) 2 bytes used for size */ 1143 1144 /* 1145 * struct hl_info_sec_attest - attestation report of the boot 1146 * @nonce: number only used once. random number provided by host. this also passed to the quote 1147 * command as a qualifying data. 1148 * @pcr_quote_len: length of the attestation quote data (bytes) 1149 * @pub_data_len: length of the public data (bytes) 1150 * @certificate_len: length of the certificate (bytes) 1151 * @pcr_num_reg: number of PCR registers in the pcr_data array 1152 * @pcr_reg_len: length of each PCR register in the pcr_data array (bytes) 1153 * @quote_sig_len: length of the attestation report signature (bytes) 1154 * @pcr_data: raw values of the PCR registers 1155 * @pcr_quote: attestation report data structure 1156 * @quote_sig: signature structure of the attestation report 1157 * @public_data: public key for the signed attestation 1158 * (outPublic + name + qualifiedName) 1159 * @certificate: certificate for the attestation signing key 1160 */ 1161 struct hl_info_sec_attest { 1162 __u32 nonce; 1163 __u16 pcr_quote_len; 1164 __u16 pub_data_len; 1165 __u16 certificate_len; 1166 __u8 pcr_num_reg; 1167 __u8 pcr_reg_len; 1168 __u8 quote_sig_len; 1169 __u8 pcr_data[SEC_PCR_DATA_BUF_SZ]; 1170 __u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ]; 1171 __u8 quote_sig[SEC_SIGNATURE_BUF_SZ]; 1172 __u8 public_data[SEC_PUB_DATA_BUF_SZ]; 1173 __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; 1174 __u8 pad0[2]; 1175 }; 1176 1177 enum gaudi_dcores { 1178 HL_GAUDI_WS_DCORE, 1179 HL_GAUDI_WN_DCORE, 1180 HL_GAUDI_EN_DCORE, 1181 HL_GAUDI_ES_DCORE 1182 }; 1183 1184 /** 1185 * struct hl_info_args - Main structure to retrieve device related information. 1186 * @return_pointer: User space address of the relevant structure related to HL_INFO_* operation 1187 * mentioned in @op. 1188 * @return_size: Size of the structure used in @return_pointer, just like "size" in "snprintf", it 1189 * limits how many bytes the kernel can write. For hw_events array, the size should be 1190 * hl_info_hw_ip_info.num_of_events * sizeof(__u32). 1191 * @op: Defines which type of information to be retrieved. Refer HL_INFO_* for details. 1192 * @dcore_id: DCORE id for which the information is relevant (for Gaudi refer to enum gaudi_dcores). 1193 * @ctx_id: Context ID of the user. Currently not in use. 1194 * @period_ms: Period value, in milliseconds, for utilization rate in range 100ms - 1000ms in 100 ms 1195 * resolution. Currently not in use. 1196 * @pll_index: Index as defined in hl_<asic type>_pll_index enumeration. 1197 * @eventfd: event file descriptor for event notifications. 1198 * @user_buffer_actual_size: Actual data size which was copied to user allocated buffer by the 1199 * driver. It is possible for the user to allocate buffer larger than 1200 * needed, hence updating this variable so user will know the exact amount 1201 * of bytes copied by the kernel to the buffer. 1202 * @sec_attest_nonce: Nonce number used for attestation report. 1203 * @pad: Padding to 64 bit. 1204 */ 1205 struct hl_info_args { 1206 __u64 return_pointer; 1207 __u32 return_size; 1208 __u32 op; 1209 1210 union { 1211 __u32 dcore_id; 1212 __u32 ctx_id; 1213 __u32 period_ms; 1214 __u32 pll_index; 1215 __u32 eventfd; 1216 __u32 user_buffer_actual_size; 1217 __u32 sec_attest_nonce; 1218 }; 1219 1220 __u32 pad; 1221 }; 1222 1223 /* Opcode to create a new command buffer */ 1224 #define HL_CB_OP_CREATE 0 1225 /* Opcode to destroy previously created command buffer */ 1226 #define HL_CB_OP_DESTROY 1 1227 /* Opcode to retrieve information about a command buffer */ 1228 #define HL_CB_OP_INFO 2 1229 1230 /* 2MB minus 32 bytes for 2xMSG_PROT */ 1231 #define HL_MAX_CB_SIZE (0x200000 - 32) 1232 1233 /* Indicates whether the command buffer should be mapped to the device's MMU */ 1234 #define HL_CB_FLAGS_MAP 0x1 1235 1236 /* Used with HL_CB_OP_INFO opcode to get the device va address for kernel mapped CB */ 1237 #define HL_CB_FLAGS_GET_DEVICE_VA 0x2 1238 1239 struct hl_cb_in { 1240 /* Handle of CB or 0 if we want to create one */ 1241 __u64 cb_handle; 1242 /* HL_CB_OP_* */ 1243 __u32 op; 1244 1245 /* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that 1246 * will be allocated, regardless of this parameter's value, is PAGE_SIZE 1247 */ 1248 __u32 cb_size; 1249 1250 /* Context ID - Currently not in use */ 1251 __u32 ctx_id; 1252 /* HL_CB_FLAGS_* */ 1253 __u32 flags; 1254 }; 1255 1256 struct hl_cb_out { 1257 union { 1258 /* Handle of CB */ 1259 __u64 cb_handle; 1260 1261 union { 1262 /* Information about CB */ 1263 struct { 1264 /* Usage count of CB */ 1265 __u32 usage_cnt; 1266 __u32 pad; 1267 }; 1268 1269 /* CB mapped address to device MMU */ 1270 __u64 device_va; 1271 }; 1272 }; 1273 }; 1274 1275 union hl_cb_args { 1276 struct hl_cb_in in; 1277 struct hl_cb_out out; 1278 }; 1279 1280 /* HL_CS_CHUNK_FLAGS_ values 1281 * 1282 * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB: 1283 * Indicates if the CB was allocated and mapped by userspace 1284 * (relevant to greco and above). User allocated CB is a command buffer, 1285 * allocated by the user, via malloc (or similar). After allocating the 1286 * CB, the user invokes - “memory ioctl” to map the user memory into a 1287 * device virtual address. The user provides this address via the 1288 * cb_handle field. The interface provides the ability to create a 1289 * large CBs, Which aren’t limited to “HL_MAX_CB_SIZE”. Therefore, it 1290 * increases the PCI-DMA queues throughput. This CB allocation method 1291 * also reduces the use of Linux DMA-able memory pool. Which are limited 1292 * and used by other Linux sub-systems. 1293 */ 1294 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1 1295 1296 /* 1297 * This structure size must always be fixed to 64-bytes for backward 1298 * compatibility 1299 */ 1300 struct hl_cs_chunk { 1301 union { 1302 /* Goya/Gaudi: 1303 * For external queue, this represents a Handle of CB on the 1304 * Host. 1305 * For internal queue in Goya, this represents an SRAM or 1306 * a DRAM address of the internal CB. In Gaudi, this might also 1307 * represent a mapped host address of the CB. 1308 * 1309 * Greco onwards: 1310 * For H/W queue, this represents either a Handle of CB on the 1311 * Host, or an SRAM, a DRAM, or a mapped host address of the CB. 1312 * 1313 * A mapped host address is in the device address space, after 1314 * a host address was mapped by the device MMU. 1315 */ 1316 __u64 cb_handle; 1317 1318 /* Relevant only when HL_CS_FLAGS_WAIT or 1319 * HL_CS_FLAGS_COLLECTIVE_WAIT is set 1320 * This holds address of array of u64 values that contain 1321 * signal CS sequence numbers. The wait described by 1322 * this job will listen on all those signals 1323 * (wait event per signal) 1324 */ 1325 __u64 signal_seq_arr; 1326 1327 /* 1328 * Relevant only when HL_CS_FLAGS_WAIT or 1329 * HL_CS_FLAGS_COLLECTIVE_WAIT is set 1330 * along with HL_CS_FLAGS_ENCAP_SIGNALS. 1331 * This is the CS sequence which has the encapsulated signals. 1332 */ 1333 __u64 encaps_signal_seq; 1334 }; 1335 1336 /* Index of queue to put the CB on */ 1337 __u32 queue_index; 1338 1339 union { 1340 /* 1341 * Size of command buffer with valid packets 1342 * Can be smaller then actual CB size 1343 */ 1344 __u32 cb_size; 1345 1346 /* Relevant only when HL_CS_FLAGS_WAIT or 1347 * HL_CS_FLAGS_COLLECTIVE_WAIT is set. 1348 * Number of entries in signal_seq_arr 1349 */ 1350 __u32 num_signal_seq_arr; 1351 1352 /* Relevant only when HL_CS_FLAGS_WAIT or 1353 * HL_CS_FLAGS_COLLECTIVE_WAIT is set along 1354 * with HL_CS_FLAGS_ENCAP_SIGNALS 1355 * This set the signals range that the user want to wait for 1356 * out of the whole reserved signals range. 1357 * e.g if the signals range is 20, and user don't want 1358 * to wait for signal 8, so he set this offset to 7, then 1359 * he call the API again with 9 and so on till 20. 1360 */ 1361 __u32 encaps_signal_offset; 1362 }; 1363 1364 /* HL_CS_CHUNK_FLAGS_* */ 1365 __u32 cs_chunk_flags; 1366 1367 /* Relevant only when HL_CS_FLAGS_COLLECTIVE_WAIT is set. 1368 * This holds the collective engine ID. The wait described by this job 1369 * will sync with this engine and with all NICs before completion. 1370 */ 1371 __u32 collective_engine_id; 1372 1373 /* Align structure to 64 bytes */ 1374 __u32 pad[10]; 1375 }; 1376 1377 /* SIGNAL/WAIT/COLLECTIVE_WAIT flags are mutually exclusive */ 1378 #define HL_CS_FLAGS_FORCE_RESTORE 0x1 1379 #define HL_CS_FLAGS_SIGNAL 0x2 1380 #define HL_CS_FLAGS_WAIT 0x4 1381 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8 1382 1383 #define HL_CS_FLAGS_TIMESTAMP 0x20 1384 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40 1385 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80 1386 #define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100 1387 #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200 1388 #define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400 1389 1390 /* 1391 * The encapsulated signals CS is merged into the existing CS ioctls. 1392 * In order to use this feature need to follow the below procedure: 1393 * 1. Reserve signals, set the CS type to HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 1394 * the output of this API will be the SOB offset from CFG_BASE. 1395 * this address will be used to patch CB cmds to do the signaling for this 1396 * SOB by incrementing it's value. 1397 * for reverting the reservation use HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 1398 * CS type, note that this might fail if out-of-sync happened to the SOB 1399 * value, in case other signaling request to the same SOB occurred between 1400 * reserve-unreserve calls. 1401 * 2. Use the staged CS to do the encapsulated signaling jobs. 1402 * use HL_CS_FLAGS_STAGED_SUBMISSION and HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 1403 * along with HL_CS_FLAGS_ENCAP_SIGNALS flag, and set encaps_signal_offset 1404 * field. This offset allows app to wait on part of the reserved signals. 1405 * 3. Use WAIT/COLLECTIVE WAIT CS along with HL_CS_FLAGS_ENCAP_SIGNALS flag 1406 * to wait for the encapsulated signals. 1407 */ 1408 #define HL_CS_FLAGS_ENCAP_SIGNALS 0x800 1409 #define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000 1410 #define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000 1411 1412 /* 1413 * The engine cores CS is merged into the existing CS ioctls. 1414 * Use it to control the engine cores mode. 1415 */ 1416 #define HL_CS_FLAGS_ENGINE_CORE_COMMAND 0x4000 1417 1418 #define HL_CS_STATUS_SUCCESS 0 1419 1420 #define HL_MAX_JOBS_PER_CS 512 1421 1422 /* HL_ENGINE_CORE_ values 1423 * 1424 * HL_ENGINE_CORE_HALT: engine core halt 1425 * HL_ENGINE_CORE_RUN: engine core run 1426 */ 1427 #define HL_ENGINE_CORE_HALT (1 << 0) 1428 #define HL_ENGINE_CORE_RUN (1 << 1) 1429 1430 struct hl_cs_in { 1431 1432 union { 1433 struct { 1434 /* this holds address of array of hl_cs_chunk for restore phase */ 1435 __u64 chunks_restore; 1436 1437 /* holds address of array of hl_cs_chunk for execution phase */ 1438 __u64 chunks_execute; 1439 }; 1440 1441 /* Valid only when HL_CS_FLAGS_ENGINE_CORE_COMMAND is set */ 1442 struct { 1443 /* this holds address of array of uint32 for engine_cores */ 1444 __u64 engine_cores; 1445 1446 /* number of engine cores in engine_cores array */ 1447 __u32 num_engine_cores; 1448 1449 /* the core command to be sent towards engine cores */ 1450 __u32 core_command; 1451 }; 1452 }; 1453 1454 union { 1455 /* 1456 * Sequence number of a staged submission CS 1457 * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set and 1458 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST is unset. 1459 */ 1460 __u64 seq; 1461 1462 /* 1463 * Encapsulated signals handle id 1464 * Valid for two flows: 1465 * 1. CS with encapsulated signals: 1466 * when HL_CS_FLAGS_STAGED_SUBMISSION and 1467 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 1468 * and HL_CS_FLAGS_ENCAP_SIGNALS are set. 1469 * 2. unreserve signals: 1470 * valid when HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY is set. 1471 */ 1472 __u32 encaps_sig_handle_id; 1473 1474 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ 1475 struct { 1476 /* Encapsulated signals number */ 1477 __u32 encaps_signals_count; 1478 1479 /* Encapsulated signals queue index (stream) */ 1480 __u32 encaps_signals_q_idx; 1481 }; 1482 }; 1483 1484 /* Number of chunks in restore phase array. Maximum number is 1485 * HL_MAX_JOBS_PER_CS 1486 */ 1487 __u32 num_chunks_restore; 1488 1489 /* Number of chunks in execution array. Maximum number is 1490 * HL_MAX_JOBS_PER_CS 1491 */ 1492 __u32 num_chunks_execute; 1493 1494 /* timeout in seconds - valid only if HL_CS_FLAGS_CUSTOM_TIMEOUT 1495 * is set 1496 */ 1497 __u32 timeout; 1498 1499 /* HL_CS_FLAGS_* */ 1500 __u32 cs_flags; 1501 1502 /* Context ID - Currently not in use */ 1503 __u32 ctx_id; 1504 __u8 pad[4]; 1505 }; 1506 1507 struct hl_cs_out { 1508 union { 1509 /* 1510 * seq holds the sequence number of the CS to pass to wait 1511 * ioctl. All values are valid except for 0 and ULLONG_MAX 1512 */ 1513 __u64 seq; 1514 1515 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ 1516 struct { 1517 /* This is the reserved signal handle id */ 1518 __u32 handle_id; 1519 1520 /* This is the signals count */ 1521 __u32 count; 1522 }; 1523 }; 1524 1525 /* HL_CS_STATUS */ 1526 __u32 status; 1527 1528 /* 1529 * SOB base address offset 1530 * Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY or HL_CS_FLAGS_SIGNAL is set 1531 */ 1532 __u32 sob_base_addr_offset; 1533 1534 /* 1535 * Count of completed signals in SOB before current signal submission. 1536 * Valid only when (HL_CS_FLAGS_ENCAP_SIGNALS & HL_CS_FLAGS_STAGED_SUBMISSION) 1537 * or HL_CS_FLAGS_SIGNAL is set 1538 */ 1539 __u16 sob_count_before_submission; 1540 __u16 pad[3]; 1541 }; 1542 1543 union hl_cs_args { 1544 struct hl_cs_in in; 1545 struct hl_cs_out out; 1546 }; 1547 1548 #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2 1549 #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000 1550 #define HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT 0xFFF00000 1551 #define HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT 0xFFE00000 1552 #define HL_WAIT_CS_FLAGS_MULTI_CS 0x4 1553 #define HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ 0x10 1554 #define HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT 0x20 1555 1556 #define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32 1557 1558 struct hl_wait_cs_in { 1559 union { 1560 struct { 1561 /* 1562 * In case of wait_cs holds the CS sequence number. 1563 * In case of wait for multi CS hold a user pointer to 1564 * an array of CS sequence numbers 1565 */ 1566 __u64 seq; 1567 /* Absolute timeout to wait for command submission 1568 * in microseconds 1569 */ 1570 __u64 timeout_us; 1571 }; 1572 1573 struct { 1574 union { 1575 /* User address for completion comparison. 1576 * upon interrupt, driver will compare the value pointed 1577 * by this address with the supplied target value. 1578 * in order not to perform any comparison, set address 1579 * to all 1s. 1580 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set 1581 */ 1582 __u64 addr; 1583 1584 /* cq_counters_handle to a kernel mapped cb which contains 1585 * cq counters. 1586 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set 1587 */ 1588 __u64 cq_counters_handle; 1589 }; 1590 1591 /* Target value for completion comparison */ 1592 __u64 target; 1593 }; 1594 }; 1595 1596 /* Context ID - Currently not in use */ 1597 __u32 ctx_id; 1598 1599 /* HL_WAIT_CS_FLAGS_* 1600 * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include 1601 * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK 1602 * 1603 * in order to wait for any CQ interrupt, set interrupt value to 1604 * HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT. 1605 * 1606 * in order to wait for any decoder interrupt, set interrupt value to 1607 * HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT. 1608 */ 1609 __u32 flags; 1610 1611 union { 1612 struct { 1613 /* Multi CS API info- valid entries in multi-CS array */ 1614 __u8 seq_arr_len; 1615 __u8 pad[7]; 1616 }; 1617 1618 /* Absolute timeout to wait for an interrupt in microseconds. 1619 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set 1620 */ 1621 __u64 interrupt_timeout_us; 1622 }; 1623 1624 /* 1625 * cq counter offset inside the counters cb pointed by cq_counters_handle above. 1626 * upon interrupt, driver will compare the value pointed 1627 * by this address (cq_counters_handle + cq_counters_offset) 1628 * with the supplied target value. 1629 * relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set 1630 */ 1631 __u64 cq_counters_offset; 1632 1633 /* 1634 * Timestamp_handle timestamps buffer handle. 1635 * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set 1636 */ 1637 __u64 timestamp_handle; 1638 1639 /* 1640 * Timestamp_offset is offset inside the timestamp buffer pointed by timestamp_handle above. 1641 * upon interrupt, if the cq reached the target value then driver will write 1642 * timestamp to this offset. 1643 * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set 1644 */ 1645 __u64 timestamp_offset; 1646 }; 1647 1648 #define HL_WAIT_CS_STATUS_COMPLETED 0 1649 #define HL_WAIT_CS_STATUS_BUSY 1 1650 #define HL_WAIT_CS_STATUS_TIMEDOUT 2 1651 #define HL_WAIT_CS_STATUS_ABORTED 3 1652 1653 #define HL_WAIT_CS_STATUS_FLAG_GONE 0x1 1654 #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2 1655 1656 struct hl_wait_cs_out { 1657 /* HL_WAIT_CS_STATUS_* */ 1658 __u32 status; 1659 /* HL_WAIT_CS_STATUS_FLAG* */ 1660 __u32 flags; 1661 /* 1662 * valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set 1663 * for wait_cs: timestamp of CS completion 1664 * for wait_multi_cs: timestamp of FIRST CS completion 1665 */ 1666 __s64 timestamp_nsec; 1667 /* multi CS completion bitmap */ 1668 __u32 cs_completion_map; 1669 __u32 pad; 1670 }; 1671 1672 union hl_wait_cs_args { 1673 struct hl_wait_cs_in in; 1674 struct hl_wait_cs_out out; 1675 }; 1676 1677 /* Opcode to allocate device memory */ 1678 #define HL_MEM_OP_ALLOC 0 1679 1680 /* Opcode to free previously allocated device memory */ 1681 #define HL_MEM_OP_FREE 1 1682 1683 /* Opcode to map host and device memory */ 1684 #define HL_MEM_OP_MAP 2 1685 1686 /* Opcode to unmap previously mapped host and device memory */ 1687 #define HL_MEM_OP_UNMAP 3 1688 1689 /* Opcode to map a hw block */ 1690 #define HL_MEM_OP_MAP_BLOCK 4 1691 1692 /* Opcode to create DMA-BUF object for an existing device memory allocation 1693 * and to export an FD of that DMA-BUF back to the caller 1694 */ 1695 #define HL_MEM_OP_EXPORT_DMABUF_FD 5 1696 1697 /* Opcode to create timestamps pool for user interrupts registration support 1698 * The memory will be allocated by the kernel driver, A timestamp buffer which the user 1699 * will get handle to it for mmap, and another internal buffer used by the 1700 * driver for registration management 1701 * The memory will be freed when the user closes the file descriptor(ctx close) 1702 */ 1703 #define HL_MEM_OP_TS_ALLOC 6 1704 1705 /* Memory flags */ 1706 #define HL_MEM_CONTIGUOUS 0x1 1707 #define HL_MEM_SHARED 0x2 1708 #define HL_MEM_USERPTR 0x4 1709 #define HL_MEM_FORCE_HINT 0x8 1710 #define HL_MEM_PREFETCH 0x40 1711 1712 /** 1713 * structure hl_mem_in - structure that handle input args for memory IOCTL 1714 * @union arg: union of structures to be used based on the input operation 1715 * @op: specify the requested memory operation (one of the HL_MEM_OP_* definitions). 1716 * @flags: flags for the memory operation (one of the HL_MEM_* definitions). 1717 * For the HL_MEM_OP_EXPORT_DMABUF_FD opcode, this field holds the DMA-BUF file/FD flags. 1718 * @ctx_id: context ID - currently not in use. 1719 * @num_of_elements: number of timestamp elements used only with HL_MEM_OP_TS_ALLOC opcode. 1720 */ 1721 struct hl_mem_in { 1722 union { 1723 /** 1724 * structure for device memory allocation (used with the HL_MEM_OP_ALLOC op) 1725 * @mem_size: memory size to allocate 1726 * @page_size: page size to use on allocation. when the value is 0 the default page 1727 * size will be taken. 1728 */ 1729 struct { 1730 __u64 mem_size; 1731 __u64 page_size; 1732 } alloc; 1733 1734 /** 1735 * structure for free-ing device memory (used with the HL_MEM_OP_FREE op) 1736 * @handle: handle returned from HL_MEM_OP_ALLOC 1737 */ 1738 struct { 1739 __u64 handle; 1740 } free; 1741 1742 /** 1743 * structure for mapping device memory (used with the HL_MEM_OP_MAP op) 1744 * @hint_addr: requested virtual address of mapped memory. 1745 * the driver will try to map the requested region to this hint 1746 * address, as long as the address is valid and not already mapped. 1747 * the user should check the returned address of the IOCTL to make 1748 * sure he got the hint address. 1749 * passing 0 here means that the driver will choose the address itself. 1750 * @handle: handle returned from HL_MEM_OP_ALLOC. 1751 */ 1752 struct { 1753 __u64 hint_addr; 1754 __u64 handle; 1755 } map_device; 1756 1757 /** 1758 * structure for mapping host memory (used with the HL_MEM_OP_MAP op) 1759 * @host_virt_addr: address of allocated host memory. 1760 * @hint_addr: requested virtual address of mapped memory. 1761 * the driver will try to map the requested region to this hint 1762 * address, as long as the address is valid and not already mapped. 1763 * the user should check the returned address of the IOCTL to make 1764 * sure he got the hint address. 1765 * passing 0 here means that the driver will choose the address itself. 1766 * @size: size of allocated host memory. 1767 */ 1768 struct { 1769 __u64 host_virt_addr; 1770 __u64 hint_addr; 1771 __u64 mem_size; 1772 } map_host; 1773 1774 /** 1775 * structure for mapping hw block (used with the HL_MEM_OP_MAP_BLOCK op) 1776 * @block_addr:HW block address to map, a handle and size will be returned 1777 * to the user and will be used to mmap the relevant block. 1778 * only addresses from configuration space are allowed. 1779 */ 1780 struct { 1781 __u64 block_addr; 1782 } map_block; 1783 1784 /** 1785 * structure for unmapping host memory (used with the HL_MEM_OP_UNMAP op) 1786 * @device_virt_addr: virtual address returned from HL_MEM_OP_MAP 1787 */ 1788 struct { 1789 __u64 device_virt_addr; 1790 } unmap; 1791 1792 /** 1793 * structure for exporting DMABUF object (used with 1794 * the HL_MEM_OP_EXPORT_DMABUF_FD op) 1795 * @handle: handle returned from HL_MEM_OP_ALLOC. 1796 * in Gaudi, where we don't have MMU for the device memory, the 1797 * driver expects a physical address (instead of a handle) in the 1798 * device memory space. 1799 * @mem_size: size of memory allocation. Relevant only for GAUDI 1800 */ 1801 struct { 1802 __u64 handle; 1803 __u64 mem_size; 1804 } export_dmabuf_fd; 1805 }; 1806 1807 __u32 op; 1808 __u32 flags; 1809 __u32 ctx_id; 1810 __u32 num_of_elements; 1811 }; 1812 1813 struct hl_mem_out { 1814 union { 1815 /* 1816 * Used for HL_MEM_OP_MAP as the virtual address that was 1817 * assigned in the device VA space. 1818 * A value of 0 means the requested operation failed. 1819 */ 1820 __u64 device_virt_addr; 1821 1822 /* 1823 * Used in HL_MEM_OP_ALLOC 1824 * This is the assigned handle for the allocated memory 1825 */ 1826 __u64 handle; 1827 1828 struct { 1829 /* 1830 * Used in HL_MEM_OP_MAP_BLOCK. 1831 * This is the assigned handle for the mapped block 1832 */ 1833 __u64 block_handle; 1834 1835 /* 1836 * Used in HL_MEM_OP_MAP_BLOCK 1837 * This is the size of the mapped block 1838 */ 1839 __u32 block_size; 1840 1841 __u32 pad; 1842 }; 1843 1844 /* Returned in HL_MEM_OP_EXPORT_DMABUF_FD. Represents the 1845 * DMA-BUF object that was created to describe a memory 1846 * allocation on the device's memory space. The FD should be 1847 * passed to the importer driver 1848 */ 1849 __s32 fd; 1850 }; 1851 }; 1852 1853 union hl_mem_args { 1854 struct hl_mem_in in; 1855 struct hl_mem_out out; 1856 }; 1857 1858 #define HL_DEBUG_MAX_AUX_VALUES 10 1859 1860 struct hl_debug_params_etr { 1861 /* Address in memory to allocate buffer */ 1862 __u64 buffer_address; 1863 1864 /* Size of buffer to allocate */ 1865 __u64 buffer_size; 1866 1867 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ 1868 __u32 sink_mode; 1869 __u32 pad; 1870 }; 1871 1872 struct hl_debug_params_etf { 1873 /* Address in memory to allocate buffer */ 1874 __u64 buffer_address; 1875 1876 /* Size of buffer to allocate */ 1877 __u64 buffer_size; 1878 1879 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ 1880 __u32 sink_mode; 1881 __u32 pad; 1882 }; 1883 1884 struct hl_debug_params_stm { 1885 /* Two bit masks for HW event and Stimulus Port */ 1886 __u64 he_mask; 1887 __u64 sp_mask; 1888 1889 /* Trace source ID */ 1890 __u32 id; 1891 1892 /* Frequency for the timestamp register */ 1893 __u32 frequency; 1894 }; 1895 1896 struct hl_debug_params_bmon { 1897 /* Two address ranges that the user can request to filter */ 1898 __u64 start_addr0; 1899 __u64 addr_mask0; 1900 1901 __u64 start_addr1; 1902 __u64 addr_mask1; 1903 1904 /* Capture window configuration */ 1905 __u32 bw_win; 1906 __u32 win_capture; 1907 1908 /* Trace source ID */ 1909 __u32 id; 1910 1911 /* Control register */ 1912 __u32 control; 1913 1914 /* Two more address ranges that the user can request to filter */ 1915 __u64 start_addr2; 1916 __u64 end_addr2; 1917 1918 __u64 start_addr3; 1919 __u64 end_addr3; 1920 }; 1921 1922 struct hl_debug_params_spmu { 1923 /* Event types selection */ 1924 __u64 event_types[HL_DEBUG_MAX_AUX_VALUES]; 1925 1926 /* Number of event types selection */ 1927 __u32 event_types_num; 1928 1929 /* TRC configuration register values */ 1930 __u32 pmtrc_val; 1931 __u32 trc_ctrl_host_val; 1932 __u32 trc_en_host_val; 1933 }; 1934 1935 /* Opcode for ETR component */ 1936 #define HL_DEBUG_OP_ETR 0 1937 /* Opcode for ETF component */ 1938 #define HL_DEBUG_OP_ETF 1 1939 /* Opcode for STM component */ 1940 #define HL_DEBUG_OP_STM 2 1941 /* Opcode for FUNNEL component */ 1942 #define HL_DEBUG_OP_FUNNEL 3 1943 /* Opcode for BMON component */ 1944 #define HL_DEBUG_OP_BMON 4 1945 /* Opcode for SPMU component */ 1946 #define HL_DEBUG_OP_SPMU 5 1947 /* Opcode for timestamp (deprecated) */ 1948 #define HL_DEBUG_OP_TIMESTAMP 6 1949 /* Opcode for setting the device into or out of debug mode. The enable 1950 * variable should be 1 for enabling debug mode and 0 for disabling it 1951 */ 1952 #define HL_DEBUG_OP_SET_MODE 7 1953 1954 struct hl_debug_args { 1955 /* 1956 * Pointer to user input structure. 1957 * This field is relevant to specific opcodes. 1958 */ 1959 __u64 input_ptr; 1960 /* Pointer to user output structure */ 1961 __u64 output_ptr; 1962 /* Size of user input structure */ 1963 __u32 input_size; 1964 /* Size of user output structure */ 1965 __u32 output_size; 1966 /* HL_DEBUG_OP_* */ 1967 __u32 op; 1968 /* 1969 * Register index in the component, taken from the debug_regs_index enum 1970 * in the various ASIC header files 1971 */ 1972 __u32 reg_idx; 1973 /* Enable/disable */ 1974 __u32 enable; 1975 /* Context ID - Currently not in use */ 1976 __u32 ctx_id; 1977 }; 1978 1979 /* 1980 * Various information operations such as: 1981 * - H/W IP information 1982 * - Current dram usage 1983 * 1984 * The user calls this IOCTL with an opcode that describes the required 1985 * information. The user should supply a pointer to a user-allocated memory 1986 * chunk, which will be filled by the driver with the requested information. 1987 * 1988 * The user supplies the maximum amount of size to copy into the user's memory, 1989 * in order to prevent data corruption in case of differences between the 1990 * definitions of structures in kernel and userspace, e.g. in case of old 1991 * userspace and new kernel driver 1992 */ 1993 #define HL_IOCTL_INFO \ 1994 _IOWR('H', 0x01, struct hl_info_args) 1995 1996 /* 1997 * Command Buffer 1998 * - Request a Command Buffer 1999 * - Destroy a Command Buffer 2000 * 2001 * The command buffers are memory blocks that reside in DMA-able address 2002 * space and are physically contiguous so they can be accessed by the device 2003 * directly. They are allocated using the coherent DMA API. 2004 * 2005 * When creating a new CB, the IOCTL returns a handle of it, and the user-space 2006 * process needs to use that handle to mmap the buffer so it can access them. 2007 * 2008 * In some instances, the device must access the command buffer through the 2009 * device's MMU, and thus its memory should be mapped. In these cases, user can 2010 * indicate the driver that such a mapping is required. 2011 * The resulting device virtual address will be used internally by the driver, 2012 * and won't be returned to user. 2013 * 2014 */ 2015 #define HL_IOCTL_CB \ 2016 _IOWR('H', 0x02, union hl_cb_args) 2017 2018 /* 2019 * Command Submission 2020 * 2021 * To submit work to the device, the user need to call this IOCTL with a set 2022 * of JOBS. That set of JOBS constitutes a CS object. 2023 * Each JOB will be enqueued on a specific queue, according to the user's input. 2024 * There can be more then one JOB per queue. 2025 * 2026 * The CS IOCTL will receive two sets of JOBS. One set is for "restore" phase 2027 * and a second set is for "execution" phase. 2028 * The JOBS on the "restore" phase are enqueued only after context-switch 2029 * (or if its the first CS for this context). The user can also order the 2030 * driver to run the "restore" phase explicitly 2031 * 2032 * Goya/Gaudi: 2033 * There are two types of queues - external and internal. External queues 2034 * are DMA queues which transfer data from/to the Host. All other queues are 2035 * internal. The driver will get completion notifications from the device only 2036 * on JOBS which are enqueued in the external queues. 2037 * 2038 * Greco onwards: 2039 * There is a single type of queue for all types of engines, either DMA engines 2040 * for transfers from/to the host or inside the device, or compute engines. 2041 * The driver will get completion notifications from the device for all queues. 2042 * 2043 * For jobs on external queues, the user needs to create command buffers 2044 * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on 2045 * internal queues, the user needs to prepare a "command buffer" with packets 2046 * on either the device SRAM/DRAM or the host, and give the device address of 2047 * that buffer to the CS ioctl. 2048 * For jobs on H/W queues both options of command buffers are valid. 2049 * 2050 * This IOCTL is asynchronous in regard to the actual execution of the CS. This 2051 * means it returns immediately after ALL the JOBS were enqueued on their 2052 * relevant queues. Therefore, the user mustn't assume the CS has been completed 2053 * or has even started to execute. 2054 * 2055 * Upon successful enqueue, the IOCTL returns a sequence number which the user 2056 * can use with the "Wait for CS" IOCTL to check whether the handle's CS 2057 * non-internal JOBS have been completed. Note that if the CS has internal JOBS 2058 * which can execute AFTER the external JOBS have finished, the driver might 2059 * report that the CS has finished executing BEFORE the internal JOBS have 2060 * actually finished executing. 2061 * 2062 * Even though the sequence number increments per CS, the user can NOT 2063 * automatically assume that if CS with sequence number N finished, then CS 2064 * with sequence number N-1 also finished. The user can make this assumption if 2065 * and only if CS N and CS N-1 are exactly the same (same CBs for the same 2066 * queues). 2067 */ 2068 #define HL_IOCTL_CS \ 2069 _IOWR('H', 0x03, union hl_cs_args) 2070 2071 /* 2072 * Wait for Command Submission 2073 * 2074 * The user can call this IOCTL with a handle it received from the CS IOCTL 2075 * to wait until the handle's CS has finished executing. The user will wait 2076 * inside the kernel until the CS has finished or until the user-requested 2077 * timeout has expired. 2078 * 2079 * If the timeout value is 0, the driver won't sleep at all. It will check 2080 * the status of the CS and return immediately 2081 * 2082 * The return value of the IOCTL is a standard Linux error code. The possible 2083 * values are: 2084 * 2085 * EINTR - Kernel waiting has been interrupted, e.g. due to OS signal 2086 * that the user process received 2087 * ETIMEDOUT - The CS has caused a timeout on the device 2088 * EIO - The CS was aborted (usually because the device was reset) 2089 * ENODEV - The device wants to do hard-reset (so user need to close FD) 2090 * 2091 * The driver also returns a custom define in case the IOCTL call returned 0. 2092 * The define can be one of the following: 2093 * 2094 * HL_WAIT_CS_STATUS_COMPLETED - The CS has been completed successfully (0) 2095 * HL_WAIT_CS_STATUS_BUSY - The CS is still executing (0) 2096 * HL_WAIT_CS_STATUS_TIMEDOUT - The CS has caused a timeout on the device 2097 * (ETIMEDOUT) 2098 * HL_WAIT_CS_STATUS_ABORTED - The CS was aborted, usually because the 2099 * device was reset (EIO) 2100 */ 2101 2102 #define HL_IOCTL_WAIT_CS \ 2103 _IOWR('H', 0x04, union hl_wait_cs_args) 2104 2105 /* 2106 * Memory 2107 * - Map host memory to device MMU 2108 * - Unmap host memory from device MMU 2109 * 2110 * This IOCTL allows the user to map host memory to the device MMU 2111 * 2112 * For host memory, the IOCTL doesn't allocate memory. The user is supposed 2113 * to allocate the memory in user-space (malloc/new). The driver pins the 2114 * physical pages (up to the allowed limit by the OS), assigns a virtual 2115 * address in the device VA space and initializes the device MMU. 2116 * 2117 * There is an option for the user to specify the requested virtual address. 2118 * 2119 */ 2120 #define HL_IOCTL_MEMORY \ 2121 _IOWR('H', 0x05, union hl_mem_args) 2122 2123 /* 2124 * Debug 2125 * - Enable/disable the ETR/ETF/FUNNEL/STM/BMON/SPMU debug traces 2126 * 2127 * This IOCTL allows the user to get debug traces from the chip. 2128 * 2129 * Before the user can send configuration requests of the various 2130 * debug/profile engines, it needs to set the device into debug mode. 2131 * This is because the debug/profile infrastructure is shared component in the 2132 * device and we can't allow multiple users to access it at the same time. 2133 * 2134 * Once a user set the device into debug mode, the driver won't allow other 2135 * users to "work" with the device, i.e. open a FD. If there are multiple users 2136 * opened on the device, the driver won't allow any user to debug the device. 2137 * 2138 * For each configuration request, the user needs to provide the register index 2139 * and essential data such as buffer address and size. 2140 * 2141 * Once the user has finished using the debug/profile engines, he should 2142 * set the device into non-debug mode, i.e. disable debug mode. 2143 * 2144 * The driver can decide to "kick out" the user if he abuses this interface. 2145 * 2146 */ 2147 #define HL_IOCTL_DEBUG \ 2148 _IOWR('H', 0x06, struct hl_debug_args) 2149 2150 #define HL_COMMAND_START 0x01 2151 #define HL_COMMAND_END 0x07 2152 2153 #endif /* HABANALABS_H_ */ 2154