1 #define A_SG_CONTROL 0x0
2 
3 #define S_CONGMODE    29
4 #define V_CONGMODE(x) ((x) << S_CONGMODE)
5 #define F_CONGMODE    V_CONGMODE(1U)
6 
7 #define S_TNLFLMODE    28
8 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE)
9 #define F_TNLFLMODE    V_TNLFLMODE(1U)
10 
11 #define S_FATLPERREN    27
12 #define V_FATLPERREN(x) ((x) << S_FATLPERREN)
13 #define F_FATLPERREN    V_FATLPERREN(1U)
14 
15 #define S_DROPPKT    20
16 #define V_DROPPKT(x) ((x) << S_DROPPKT)
17 #define F_DROPPKT    V_DROPPKT(1U)
18 
19 #define S_EGRGENCTRL    19
20 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL)
21 #define F_EGRGENCTRL    V_EGRGENCTRL(1U)
22 
23 #define S_USERSPACESIZE    14
24 #define M_USERSPACESIZE    0x1f
25 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE)
26 
27 #define S_HOSTPAGESIZE    11
28 #define M_HOSTPAGESIZE    0x7
29 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE)
30 
31 #define S_FLMODE    9
32 #define V_FLMODE(x) ((x) << S_FLMODE)
33 #define F_FLMODE    V_FLMODE(1U)
34 
35 #define S_PKTSHIFT    6
36 #define M_PKTSHIFT    0x7
37 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
38 
39 #define S_ONEINTMULTQ    5
40 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ)
41 #define F_ONEINTMULTQ    V_ONEINTMULTQ(1U)
42 
43 #define S_BIGENDIANINGRESS    2
44 #define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS)
45 #define F_BIGENDIANINGRESS    V_BIGENDIANINGRESS(1U)
46 
47 #define S_ISCSICOALESCING    1
48 #define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING)
49 #define F_ISCSICOALESCING    V_ISCSICOALESCING(1U)
50 
51 #define S_GLOBALENABLE    0
52 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
53 #define F_GLOBALENABLE    V_GLOBALENABLE(1U)
54 
55 #define S_AVOIDCQOVFL    24
56 #define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL)
57 #define F_AVOIDCQOVFL    V_AVOIDCQOVFL(1U)
58 
59 #define S_OPTONEINTMULTQ    23
60 #define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ)
61 #define F_OPTONEINTMULTQ    V_OPTONEINTMULTQ(1U)
62 
63 #define S_CQCRDTCTRL    22
64 #define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL)
65 #define F_CQCRDTCTRL    V_CQCRDTCTRL(1U)
66 
67 #define A_SG_KDOORBELL 0x4
68 
69 #define S_SELEGRCNTX    31
70 #define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX)
71 #define F_SELEGRCNTX    V_SELEGRCNTX(1U)
72 
73 #define S_EGRCNTX    0
74 #define M_EGRCNTX    0xffff
75 #define V_EGRCNTX(x) ((x) << S_EGRCNTX)
76 
77 #define A_SG_GTS 0x8
78 
79 #define S_RSPQ    29
80 #define M_RSPQ    0x7
81 #define V_RSPQ(x) ((x) << S_RSPQ)
82 #define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ)
83 
84 #define S_NEWTIMER    16
85 #define M_NEWTIMER    0x1fff
86 #define V_NEWTIMER(x) ((x) << S_NEWTIMER)
87 
88 #define S_NEWINDEX    0
89 #define M_NEWINDEX    0xffff
90 #define V_NEWINDEX(x) ((x) << S_NEWINDEX)
91 
92 #define A_SG_CONTEXT_CMD 0xc
93 
94 #define S_CONTEXT_CMD_OPCODE    28
95 #define M_CONTEXT_CMD_OPCODE    0xf
96 #define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE)
97 
98 #define S_CONTEXT_CMD_BUSY    27
99 #define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY)
100 #define F_CONTEXT_CMD_BUSY    V_CONTEXT_CMD_BUSY(1U)
101 
102 #define S_CQ_CREDIT    20
103 
104 #define M_CQ_CREDIT    0x7f
105 
106 #define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT)
107 
108 #define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT)
109 
110 #define S_CQ    19
111 
112 #define V_CQ(x) ((x) << S_CQ)
113 #define F_CQ    V_CQ(1U)
114 
115 #define S_RESPONSEQ    18
116 #define V_RESPONSEQ(x) ((x) << S_RESPONSEQ)
117 #define F_RESPONSEQ    V_RESPONSEQ(1U)
118 
119 #define S_EGRESS    17
120 #define V_EGRESS(x) ((x) << S_EGRESS)
121 #define F_EGRESS    V_EGRESS(1U)
122 
123 #define S_FREELIST    16
124 #define V_FREELIST(x) ((x) << S_FREELIST)
125 #define F_FREELIST    V_FREELIST(1U)
126 
127 #define S_CONTEXT    0
128 #define M_CONTEXT    0xffff
129 #define V_CONTEXT(x) ((x) << S_CONTEXT)
130 
131 #define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT)
132 
133 #define A_SG_CONTEXT_DATA0 0x10
134 
135 #define A_SG_CONTEXT_DATA1 0x14
136 
137 #define A_SG_CONTEXT_DATA2 0x18
138 
139 #define A_SG_CONTEXT_DATA3 0x1c
140 
141 #define A_SG_CONTEXT_MASK0 0x20
142 
143 #define A_SG_CONTEXT_MASK1 0x24
144 
145 #define A_SG_CONTEXT_MASK2 0x28
146 
147 #define A_SG_CONTEXT_MASK3 0x2c
148 
149 #define A_SG_RSPQ_CREDIT_RETURN 0x30
150 
151 #define S_CREDITS    0
152 #define M_CREDITS    0xffff
153 #define V_CREDITS(x) ((x) << S_CREDITS)
154 
155 #define A_SG_DATA_INTR 0x34
156 
157 #define S_ERRINTR    31
158 #define V_ERRINTR(x) ((x) << S_ERRINTR)
159 #define F_ERRINTR    V_ERRINTR(1U)
160 
161 #define A_SG_HI_DRB_HI_THRSH 0x38
162 
163 #define A_SG_HI_DRB_LO_THRSH 0x3c
164 
165 #define A_SG_LO_DRB_HI_THRSH 0x40
166 
167 #define A_SG_LO_DRB_LO_THRSH 0x44
168 
169 #define A_SG_RSPQ_FL_STATUS 0x4c
170 
171 #define S_RSPQ0DISABLED    8
172 
173 #define S_FL0EMPTY    16
174 #define V_FL0EMPTY(x) ((x) << S_FL0EMPTY)
175 #define F_FL0EMPTY    V_FL0EMPTY(1U)
176 
177 #define A_SG_EGR_RCQ_DRB_THRSH 0x54
178 
179 #define S_HIRCQDRBTHRSH    16
180 #define M_HIRCQDRBTHRSH    0x7ff
181 #define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH)
182 
183 #define S_LORCQDRBTHRSH    0
184 #define M_LORCQDRBTHRSH    0x7ff
185 #define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH)
186 
187 #define A_SG_EGR_CNTX_BADDR 0x58
188 
189 #define A_SG_INT_CAUSE 0x5c
190 
191 #define S_HIRCQPARITYERROR    31
192 #define V_HIRCQPARITYERROR(x) ((x) << S_HIRCQPARITYERROR)
193 #define F_HIRCQPARITYERROR    V_HIRCQPARITYERROR(1U)
194 
195 #define S_LORCQPARITYERROR    30
196 #define V_LORCQPARITYERROR(x) ((x) << S_LORCQPARITYERROR)
197 #define F_LORCQPARITYERROR    V_LORCQPARITYERROR(1U)
198 
199 #define S_HIDRBPARITYERROR    29
200 #define V_HIDRBPARITYERROR(x) ((x) << S_HIDRBPARITYERROR)
201 #define F_HIDRBPARITYERROR    V_HIDRBPARITYERROR(1U)
202 
203 #define S_LODRBPARITYERROR    28
204 #define V_LODRBPARITYERROR(x) ((x) << S_LODRBPARITYERROR)
205 #define F_LODRBPARITYERROR    V_LODRBPARITYERROR(1U)
206 
207 #define S_FLPARITYERROR    22
208 #define M_FLPARITYERROR    0x3f
209 #define V_FLPARITYERROR(x) ((x) << S_FLPARITYERROR)
210 #define G_FLPARITYERROR(x) (((x) >> S_FLPARITYERROR) & M_FLPARITYERROR)
211 
212 #define S_ITPARITYERROR    20
213 #define M_ITPARITYERROR    0x3
214 #define V_ITPARITYERROR(x) ((x) << S_ITPARITYERROR)
215 #define G_ITPARITYERROR(x) (((x) >> S_ITPARITYERROR) & M_ITPARITYERROR)
216 
217 #define S_IRPARITYERROR    19
218 #define V_IRPARITYERROR(x) ((x) << S_IRPARITYERROR)
219 #define F_IRPARITYERROR    V_IRPARITYERROR(1U)
220 
221 #define S_RCPARITYERROR    18
222 #define V_RCPARITYERROR(x) ((x) << S_RCPARITYERROR)
223 #define F_RCPARITYERROR    V_RCPARITYERROR(1U)
224 
225 #define S_OCPARITYERROR    17
226 #define V_OCPARITYERROR(x) ((x) << S_OCPARITYERROR)
227 #define F_OCPARITYERROR    V_OCPARITYERROR(1U)
228 
229 #define S_CPPARITYERROR    16
230 #define V_CPPARITYERROR(x) ((x) << S_CPPARITYERROR)
231 #define F_CPPARITYERROR    V_CPPARITYERROR(1U)
232 
233 #define S_R_REQ_FRAMINGERROR    15
234 #define V_R_REQ_FRAMINGERROR(x) ((x) << S_R_REQ_FRAMINGERROR)
235 #define F_R_REQ_FRAMINGERROR    V_R_REQ_FRAMINGERROR(1U)
236 
237 #define S_UC_REQ_FRAMINGERROR    14
238 #define V_UC_REQ_FRAMINGERROR(x) ((x) << S_UC_REQ_FRAMINGERROR)
239 #define F_UC_REQ_FRAMINGERROR    V_UC_REQ_FRAMINGERROR(1U)
240 
241 #define S_HICTLDRBDROPERR    13
242 #define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR)
243 #define F_HICTLDRBDROPERR    V_HICTLDRBDROPERR(1U)
244 
245 #define S_LOCTLDRBDROPERR    12
246 #define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR)
247 #define F_LOCTLDRBDROPERR    V_LOCTLDRBDROPERR(1U)
248 
249 #define S_HIPIODRBDROPERR    11
250 #define V_HIPIODRBDROPERR(x) ((x) << S_HIPIODRBDROPERR)
251 #define F_HIPIODRBDROPERR    V_HIPIODRBDROPERR(1U)
252 
253 #define S_LOPIODRBDROPERR    10
254 #define V_LOPIODRBDROPERR(x) ((x) << S_LOPIODRBDROPERR)
255 #define F_LOPIODRBDROPERR    V_LOPIODRBDROPERR(1U)
256 
257 #define S_HIPRIORITYDBFULL    7
258 #define V_HIPRIORITYDBFULL(x) ((x) << S_HIPRIORITYDBFULL)
259 #define F_HIPRIORITYDBFULL    V_HIPRIORITYDBFULL(1U)
260 
261 #define S_HIPRIORITYDBEMPTY   6
262 #define V_HIPRIORITYDBEMPTY(x) ((x) << S_HIPRIORITYDBEMPTY)
263 #define F_HIPRIORITYDBEMPTY    V_HIPRIORITYDBEMPTY(1U)
264 
265 #define S_LOPRIORITYDBFULL    5
266 #define V_LOPRIORITYDBFULL(x) ((x) << S_LOPRIORITYDBFULL)
267 #define F_LOPRIORITYDBFULL    V_LOPRIORITYDBFULL(1U)
268 
269 #define S_LOPRIORITYDBEMPTY   4
270 #define V_LOPRIORITYDBEMPTY(x) ((x) << S_LOPRIORITYDBEMPTY)
271 #define F_LOPRIORITYDBEMPTY    V_LOPRIORITYDBEMPTY(1U)
272 
273 #define S_RSPQDISABLED    3
274 #define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED)
275 #define F_RSPQDISABLED    V_RSPQDISABLED(1U)
276 
277 #define S_RSPQCREDITOVERFOW    2
278 #define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW)
279 #define F_RSPQCREDITOVERFOW    V_RSPQCREDITOVERFOW(1U)
280 
281 #define S_FLEMPTY    1
282 #define V_FLEMPTY(x) ((x) << S_FLEMPTY)
283 #define F_FLEMPTY    V_FLEMPTY(1U)
284 
285 #define A_SG_INT_ENABLE 0x60
286 
287 #define A_SG_CMDQ_CREDIT_TH 0x64
288 
289 #define S_TIMEOUT    8
290 #define M_TIMEOUT    0xffffff
291 #define V_TIMEOUT(x) ((x) << S_TIMEOUT)
292 
293 #define S_THRESHOLD    0
294 #define M_THRESHOLD    0xff
295 #define V_THRESHOLD(x) ((x) << S_THRESHOLD)
296 
297 #define A_SG_TIMER_TICK 0x68
298 
299 #define A_SG_CQ_CONTEXT_BADDR 0x6c
300 
301 #define A_SG_OCO_BASE 0x70
302 
303 #define S_BASE1    16
304 #define M_BASE1    0xffff
305 #define V_BASE1(x) ((x) << S_BASE1)
306 
307 #define A_SG_DRB_PRI_THRESH 0x74
308 
309 #define A_PCIX_INT_ENABLE 0x80
310 
311 #define S_MSIXPARERR    22
312 #define M_MSIXPARERR    0x7
313 
314 #define V_MSIXPARERR(x) ((x) << S_MSIXPARERR)
315 
316 #define S_CFPARERR    18
317 #define M_CFPARERR    0xf
318 
319 #define V_CFPARERR(x) ((x) << S_CFPARERR)
320 
321 #define S_RFPARERR    14
322 #define M_RFPARERR    0xf
323 
324 #define V_RFPARERR(x) ((x) << S_RFPARERR)
325 
326 #define S_WFPARERR    12
327 #define M_WFPARERR    0x3
328 
329 #define V_WFPARERR(x) ((x) << S_WFPARERR)
330 
331 #define S_PIOPARERR    11
332 #define V_PIOPARERR(x) ((x) << S_PIOPARERR)
333 #define F_PIOPARERR    V_PIOPARERR(1U)
334 
335 #define S_DETUNCECCERR    10
336 #define V_DETUNCECCERR(x) ((x) << S_DETUNCECCERR)
337 #define F_DETUNCECCERR    V_DETUNCECCERR(1U)
338 
339 #define S_DETCORECCERR    9
340 #define V_DETCORECCERR(x) ((x) << S_DETCORECCERR)
341 #define F_DETCORECCERR    V_DETCORECCERR(1U)
342 
343 #define S_RCVSPLCMPERR    8
344 #define V_RCVSPLCMPERR(x) ((x) << S_RCVSPLCMPERR)
345 #define F_RCVSPLCMPERR    V_RCVSPLCMPERR(1U)
346 
347 #define S_UNXSPLCMP    7
348 #define V_UNXSPLCMP(x) ((x) << S_UNXSPLCMP)
349 #define F_UNXSPLCMP    V_UNXSPLCMP(1U)
350 
351 #define S_SPLCMPDIS    6
352 #define V_SPLCMPDIS(x) ((x) << S_SPLCMPDIS)
353 #define F_SPLCMPDIS    V_SPLCMPDIS(1U)
354 
355 #define S_DETPARERR    5
356 #define V_DETPARERR(x) ((x) << S_DETPARERR)
357 #define F_DETPARERR    V_DETPARERR(1U)
358 
359 #define S_SIGSYSERR    4
360 #define V_SIGSYSERR(x) ((x) << S_SIGSYSERR)
361 #define F_SIGSYSERR    V_SIGSYSERR(1U)
362 
363 #define S_RCVMSTABT    3
364 #define V_RCVMSTABT(x) ((x) << S_RCVMSTABT)
365 #define F_RCVMSTABT    V_RCVMSTABT(1U)
366 
367 #define S_RCVTARABT    2
368 #define V_RCVTARABT(x) ((x) << S_RCVTARABT)
369 #define F_RCVTARABT    V_RCVTARABT(1U)
370 
371 #define S_SIGTARABT    1
372 #define V_SIGTARABT(x) ((x) << S_SIGTARABT)
373 #define F_SIGTARABT    V_SIGTARABT(1U)
374 
375 #define S_MSTDETPARERR    0
376 #define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR)
377 #define F_MSTDETPARERR    V_MSTDETPARERR(1U)
378 
379 #define A_PCIX_INT_CAUSE 0x84
380 
381 #define A_PCIX_CFG 0x88
382 
383 #define S_DMASTOPEN    19
384 #define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)
385 #define F_DMASTOPEN    V_DMASTOPEN(1U)
386 
387 #define S_CLIDECEN    18
388 #define V_CLIDECEN(x) ((x) << S_CLIDECEN)
389 #define F_CLIDECEN    V_CLIDECEN(1U)
390 
391 #define A_PCIX_MODE 0x8c
392 
393 #define S_PCLKRANGE    6
394 #define M_PCLKRANGE    0x3
395 #define V_PCLKRANGE(x) ((x) << S_PCLKRANGE)
396 #define G_PCLKRANGE(x) (((x) >> S_PCLKRANGE) & M_PCLKRANGE)
397 
398 #define S_PCIXINITPAT    2
399 #define M_PCIXINITPAT    0xf
400 #define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT)
401 #define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT)
402 
403 #define S_64BIT    0
404 #define V_64BIT(x) ((x) << S_64BIT)
405 #define F_64BIT    V_64BIT(1U)
406 
407 #define A_PCIE_INT_ENABLE 0x80
408 
409 #define S_BISTERR    15
410 #define M_BISTERR    0xff
411 
412 #define V_BISTERR(x) ((x) << S_BISTERR)
413 
414 #define S_TXPARERR    18
415 #define V_TXPARERR(x) ((x) << S_TXPARERR)
416 #define F_TXPARERR    V_TXPARERR(1U)
417 
418 #define S_RXPARERR    17
419 #define V_RXPARERR(x) ((x) << S_RXPARERR)
420 #define F_RXPARERR    V_RXPARERR(1U)
421 
422 #define S_RETRYLUTPARERR    16
423 #define V_RETRYLUTPARERR(x) ((x) << S_RETRYLUTPARERR)
424 #define F_RETRYLUTPARERR    V_RETRYLUTPARERR(1U)
425 
426 #define S_RETRYBUFPARERR    15
427 #define V_RETRYBUFPARERR(x) ((x) << S_RETRYBUFPARERR)
428 #define F_RETRYBUFPARERR    V_RETRYBUFPARERR(1U)
429 
430 #define S_PCIE_MSIXPARERR    12
431 #define M_PCIE_MSIXPARERR    0x7
432 
433 #define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR)
434 
435 #define S_PCIE_CFPARERR    11
436 #define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR)
437 #define F_PCIE_CFPARERR    V_PCIE_CFPARERR(1U)
438 
439 #define S_PCIE_RFPARERR    10
440 #define V_PCIE_RFPARERR(x) ((x) << S_PCIE_RFPARERR)
441 #define F_PCIE_RFPARERR    V_PCIE_RFPARERR(1U)
442 
443 #define S_PCIE_WFPARERR    9
444 #define V_PCIE_WFPARERR(x) ((x) << S_PCIE_WFPARERR)
445 #define F_PCIE_WFPARERR    V_PCIE_WFPARERR(1U)
446 
447 #define S_PCIE_PIOPARERR    8
448 #define V_PCIE_PIOPARERR(x) ((x) << S_PCIE_PIOPARERR)
449 #define F_PCIE_PIOPARERR    V_PCIE_PIOPARERR(1U)
450 
451 #define S_UNXSPLCPLERRC    7
452 #define V_UNXSPLCPLERRC(x) ((x) << S_UNXSPLCPLERRC)
453 #define F_UNXSPLCPLERRC    V_UNXSPLCPLERRC(1U)
454 
455 #define S_UNXSPLCPLERRR    6
456 #define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR)
457 #define F_UNXSPLCPLERRR    V_UNXSPLCPLERRR(1U)
458 
459 #define S_PEXERR    0
460 #define V_PEXERR(x) ((x) << S_PEXERR)
461 #define F_PEXERR    V_PEXERR(1U)
462 
463 #define A_PCIE_INT_CAUSE 0x84
464 
465 #define S_PCIE_DMASTOPEN    24
466 #define V_PCIE_DMASTOPEN(x) ((x) << S_PCIE_DMASTOPEN)
467 #define F_PCIE_DMASTOPEN    V_PCIE_DMASTOPEN(1U)
468 
469 #define A_PCIE_CFG 0x88
470 
471 #define S_ENABLELINKDWNDRST    21
472 #define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST)
473 #define F_ENABLELINKDWNDRST    V_ENABLELINKDWNDRST(1U)
474 
475 #define S_ENABLELINKDOWNRST    20
476 #define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST)
477 #define F_ENABLELINKDOWNRST    V_ENABLELINKDOWNRST(1U)
478 
479 #define S_PCIE_CLIDECEN    16
480 #define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN)
481 #define F_PCIE_CLIDECEN    V_PCIE_CLIDECEN(1U)
482 
483 #define S_CRSTWRMMODE    0
484 #define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE)
485 #define F_CRSTWRMMODE    V_CRSTWRMMODE(1U)
486 
487 #define A_PCIE_MODE 0x8c
488 
489 #define S_NUMFSTTRNSEQRX    10
490 #define M_NUMFSTTRNSEQRX    0xff
491 #define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX)
492 #define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX)
493 
494 #define A_PCIE_PEX_CTRL0 0x98
495 
496 #define S_NUMFSTTRNSEQ    22
497 #define M_NUMFSTTRNSEQ    0xff
498 #define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ)
499 #define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ)
500 
501 #define S_REPLAYLMT    2
502 #define M_REPLAYLMT    0xfffff
503 
504 #define V_REPLAYLMT(x) ((x) << S_REPLAYLMT)
505 
506 #define A_PCIE_PEX_CTRL1 0x9c
507 
508 #define S_T3A_ACKLAT    0
509 #define M_T3A_ACKLAT    0x7ff
510 
511 #define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT)
512 
513 #define S_ACKLAT    0
514 #define M_ACKLAT    0x1fff
515 
516 #define V_ACKLAT(x) ((x) << S_ACKLAT)
517 
518 #define A_PCIE_PEX_ERR 0xa4
519 
520 #define A_T3DBG_GPIO_EN 0xd0
521 
522 #define S_GPIO11_OEN    27
523 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
524 #define F_GPIO11_OEN    V_GPIO11_OEN(1U)
525 
526 #define S_GPIO10_OEN    26
527 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
528 #define F_GPIO10_OEN    V_GPIO10_OEN(1U)
529 
530 #define S_GPIO7_OEN    23
531 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
532 #define F_GPIO7_OEN    V_GPIO7_OEN(1U)
533 
534 #define S_GPIO6_OEN    22
535 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
536 #define F_GPIO6_OEN    V_GPIO6_OEN(1U)
537 
538 #define S_GPIO5_OEN    21
539 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
540 #define F_GPIO5_OEN    V_GPIO5_OEN(1U)
541 
542 #define S_GPIO4_OEN    20
543 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
544 #define F_GPIO4_OEN    V_GPIO4_OEN(1U)
545 
546 #define S_GPIO2_OEN    18
547 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
548 #define F_GPIO2_OEN    V_GPIO2_OEN(1U)
549 
550 #define S_GPIO1_OEN    17
551 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
552 #define F_GPIO1_OEN    V_GPIO1_OEN(1U)
553 
554 #define S_GPIO0_OEN    16
555 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
556 #define F_GPIO0_OEN    V_GPIO0_OEN(1U)
557 
558 #define S_GPIO10_OUT_VAL    10
559 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
560 #define F_GPIO10_OUT_VAL    V_GPIO10_OUT_VAL(1U)
561 
562 #define S_GPIO7_OUT_VAL    7
563 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
564 #define F_GPIO7_OUT_VAL    V_GPIO7_OUT_VAL(1U)
565 
566 #define S_GPIO6_OUT_VAL    6
567 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
568 #define F_GPIO6_OUT_VAL    V_GPIO6_OUT_VAL(1U)
569 
570 #define S_GPIO5_OUT_VAL    5
571 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
572 #define F_GPIO5_OUT_VAL    V_GPIO5_OUT_VAL(1U)
573 
574 #define S_GPIO4_OUT_VAL    4
575 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
576 #define F_GPIO4_OUT_VAL    V_GPIO4_OUT_VAL(1U)
577 
578 #define S_GPIO2_OUT_VAL    2
579 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
580 #define F_GPIO2_OUT_VAL    V_GPIO2_OUT_VAL(1U)
581 
582 #define S_GPIO1_OUT_VAL    1
583 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
584 #define F_GPIO1_OUT_VAL    V_GPIO1_OUT_VAL(1U)
585 
586 #define S_GPIO0_OUT_VAL    0
587 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
588 #define F_GPIO0_OUT_VAL    V_GPIO0_OUT_VAL(1U)
589 
590 #define A_T3DBG_INT_ENABLE 0xd8
591 
592 #define S_GPIO11    11
593 #define V_GPIO11(x) ((x) << S_GPIO11)
594 #define F_GPIO11    V_GPIO11(1U)
595 
596 #define S_GPIO10    10
597 #define V_GPIO10(x) ((x) << S_GPIO10)
598 #define F_GPIO10    V_GPIO10(1U)
599 
600 #define S_GPIO9    9
601 #define V_GPIO9(x) ((x) << S_GPIO9)
602 #define F_GPIO9    V_GPIO9(1U)
603 
604 #define S_GPIO7    7
605 #define V_GPIO7(x) ((x) << S_GPIO7)
606 #define F_GPIO7    V_GPIO7(1U)
607 
608 #define S_GPIO6    6
609 #define V_GPIO6(x) ((x) << S_GPIO6)
610 #define F_GPIO6    V_GPIO6(1U)
611 
612 #define S_GPIO5    5
613 #define V_GPIO5(x) ((x) << S_GPIO5)
614 #define F_GPIO5    V_GPIO5(1U)
615 
616 #define S_GPIO4    4
617 #define V_GPIO4(x) ((x) << S_GPIO4)
618 #define F_GPIO4    V_GPIO4(1U)
619 
620 #define S_GPIO3    3
621 #define V_GPIO3(x) ((x) << S_GPIO3)
622 #define F_GPIO3    V_GPIO3(1U)
623 
624 #define S_GPIO2    2
625 #define V_GPIO2(x) ((x) << S_GPIO2)
626 #define F_GPIO2    V_GPIO2(1U)
627 
628 #define S_GPIO1    1
629 #define V_GPIO1(x) ((x) << S_GPIO1)
630 #define F_GPIO1    V_GPIO1(1U)
631 
632 #define S_GPIO0    0
633 #define V_GPIO0(x) ((x) << S_GPIO0)
634 #define F_GPIO0    V_GPIO0(1U)
635 
636 #define A_T3DBG_INT_CAUSE 0xdc
637 
638 #define A_T3DBG_GPIO_ACT_LOW 0xf0
639 
640 #define MC7_PMRX_BASE_ADDR 0x100
641 
642 #define A_MC7_CFG 0x100
643 
644 #define S_IFEN    13
645 #define V_IFEN(x) ((x) << S_IFEN)
646 #define F_IFEN    V_IFEN(1U)
647 
648 #define S_TERM150    11
649 #define V_TERM150(x) ((x) << S_TERM150)
650 #define F_TERM150    V_TERM150(1U)
651 
652 #define S_SLOW    10
653 #define V_SLOW(x) ((x) << S_SLOW)
654 #define F_SLOW    V_SLOW(1U)
655 
656 #define S_WIDTH    8
657 #define M_WIDTH    0x3
658 #define V_WIDTH(x) ((x) << S_WIDTH)
659 #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
660 
661 #define S_BKS    6
662 #define V_BKS(x) ((x) << S_BKS)
663 #define F_BKS    V_BKS(1U)
664 
665 #define S_ORG    5
666 #define V_ORG(x) ((x) << S_ORG)
667 #define F_ORG    V_ORG(1U)
668 
669 #define S_DEN    2
670 #define M_DEN    0x7
671 #define V_DEN(x) ((x) << S_DEN)
672 #define G_DEN(x) (((x) >> S_DEN) & M_DEN)
673 
674 #define S_RDY    1
675 #define V_RDY(x) ((x) << S_RDY)
676 #define F_RDY    V_RDY(1U)
677 
678 #define S_CLKEN    0
679 #define V_CLKEN(x) ((x) << S_CLKEN)
680 #define F_CLKEN    V_CLKEN(1U)
681 
682 #define A_MC7_MODE 0x104
683 
684 #define S_BUSY    31
685 #define V_BUSY(x) ((x) << S_BUSY)
686 #define F_BUSY    V_BUSY(1U)
687 
688 #define S_BUSY    31
689 #define V_BUSY(x) ((x) << S_BUSY)
690 #define F_BUSY    V_BUSY(1U)
691 
692 #define A_MC7_EXT_MODE1 0x108
693 
694 #define A_MC7_EXT_MODE2 0x10c
695 
696 #define A_MC7_EXT_MODE3 0x110
697 
698 #define A_MC7_PRE 0x114
699 
700 #define A_MC7_REF 0x118
701 
702 #define S_PREREFDIV    1
703 #define M_PREREFDIV    0x3fff
704 #define V_PREREFDIV(x) ((x) << S_PREREFDIV)
705 
706 #define S_PERREFEN    0
707 #define V_PERREFEN(x) ((x) << S_PERREFEN)
708 #define F_PERREFEN    V_PERREFEN(1U)
709 
710 #define A_MC7_DLL 0x11c
711 
712 #define S_DLLENB    1
713 #define V_DLLENB(x) ((x) << S_DLLENB)
714 #define F_DLLENB    V_DLLENB(1U)
715 
716 #define S_DLLRST    0
717 #define V_DLLRST(x) ((x) << S_DLLRST)
718 #define F_DLLRST    V_DLLRST(1U)
719 
720 #define A_MC7_PARM 0x120
721 
722 #define S_ACTTOPREDLY    26
723 #define M_ACTTOPREDLY    0xf
724 #define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY)
725 
726 #define S_ACTTORDWRDLY    23
727 #define M_ACTTORDWRDLY    0x7
728 #define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY)
729 
730 #define S_PRECYC    20
731 #define M_PRECYC    0x7
732 #define V_PRECYC(x) ((x) << S_PRECYC)
733 
734 #define S_REFCYC    13
735 #define M_REFCYC    0x7f
736 #define V_REFCYC(x) ((x) << S_REFCYC)
737 
738 #define S_BKCYC    8
739 #define M_BKCYC    0x1f
740 #define V_BKCYC(x) ((x) << S_BKCYC)
741 
742 #define S_WRTORDDLY    4
743 #define M_WRTORDDLY    0xf
744 #define V_WRTORDDLY(x) ((x) << S_WRTORDDLY)
745 
746 #define S_RDTOWRDLY    0
747 #define M_RDTOWRDLY    0xf
748 #define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY)
749 
750 #define A_MC7_CAL 0x128
751 
752 #define S_BUSY    31
753 #define V_BUSY(x) ((x) << S_BUSY)
754 #define F_BUSY    V_BUSY(1U)
755 
756 #define S_BUSY    31
757 #define V_BUSY(x) ((x) << S_BUSY)
758 #define F_BUSY    V_BUSY(1U)
759 
760 #define S_CAL_FAULT    30
761 #define V_CAL_FAULT(x) ((x) << S_CAL_FAULT)
762 #define F_CAL_FAULT    V_CAL_FAULT(1U)
763 
764 #define S_SGL_CAL_EN    20
765 #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN)
766 #define F_SGL_CAL_EN    V_SGL_CAL_EN(1U)
767 
768 #define A_MC7_ERR_ADDR 0x12c
769 
770 #define A_MC7_ECC 0x130
771 
772 #define S_ECCCHKEN    1
773 #define V_ECCCHKEN(x) ((x) << S_ECCCHKEN)
774 #define F_ECCCHKEN    V_ECCCHKEN(1U)
775 
776 #define S_ECCGENEN    0
777 #define V_ECCGENEN(x) ((x) << S_ECCGENEN)
778 #define F_ECCGENEN    V_ECCGENEN(1U)
779 
780 #define A_MC7_CE_ADDR 0x134
781 
782 #define A_MC7_CE_DATA0 0x138
783 
784 #define A_MC7_CE_DATA1 0x13c
785 
786 #define A_MC7_CE_DATA2 0x140
787 
788 #define S_DATA    0
789 #define M_DATA    0xff
790 
791 #define G_DATA(x) (((x) >> S_DATA) & M_DATA)
792 
793 #define A_MC7_UE_ADDR 0x144
794 
795 #define A_MC7_UE_DATA0 0x148
796 
797 #define A_MC7_UE_DATA1 0x14c
798 
799 #define A_MC7_UE_DATA2 0x150
800 
801 #define A_MC7_BD_ADDR 0x154
802 
803 #define S_ADDR    3
804 
805 #define M_ADDR    0x1fffffff
806 
807 #define A_MC7_BD_DATA0 0x158
808 
809 #define A_MC7_BD_DATA1 0x15c
810 
811 #define A_MC7_BD_OP 0x164
812 
813 #define S_OP    0
814 
815 #define V_OP(x) ((x) << S_OP)
816 #define F_OP    V_OP(1U)
817 
818 #define F_OP    V_OP(1U)
819 #define A_SF_OP 0x6dc
820 
821 #define A_MC7_BIST_ADDR_BEG 0x168
822 
823 #define A_MC7_BIST_ADDR_END 0x16c
824 
825 #define A_MC7_BIST_DATA 0x170
826 
827 #define A_MC7_BIST_OP 0x174
828 
829 #define S_CONT    3
830 #define V_CONT(x) ((x) << S_CONT)
831 #define F_CONT    V_CONT(1U)
832 
833 #define F_CONT    V_CONT(1U)
834 
835 #define A_MC7_INT_ENABLE 0x178
836 
837 #define S_AE    17
838 #define V_AE(x) ((x) << S_AE)
839 #define F_AE    V_AE(1U)
840 
841 #define S_PE    2
842 #define M_PE    0x7fff
843 
844 #define V_PE(x) ((x) << S_PE)
845 
846 #define G_PE(x) (((x) >> S_PE) & M_PE)
847 
848 #define S_UE    1
849 #define V_UE(x) ((x) << S_UE)
850 #define F_UE    V_UE(1U)
851 
852 #define S_CE    0
853 #define V_CE(x) ((x) << S_CE)
854 #define F_CE    V_CE(1U)
855 
856 #define A_MC7_INT_CAUSE 0x17c
857 
858 #define MC7_PMTX_BASE_ADDR 0x180
859 
860 #define MC7_CM_BASE_ADDR 0x200
861 
862 #define A_CIM_BOOT_CFG 0x280
863 
864 #define S_BOOTADDR    2
865 #define M_BOOTADDR    0x3fffffff
866 #define V_BOOTADDR(x) ((x) << S_BOOTADDR)
867 
868 #define A_CIM_SDRAM_BASE_ADDR 0x28c
869 
870 #define A_CIM_SDRAM_ADDR_SIZE 0x290
871 
872 #define A_CIM_HOST_INT_ENABLE 0x298
873 
874 #define S_DTAGPARERR    28
875 #define V_DTAGPARERR(x) ((x) << S_DTAGPARERR)
876 #define F_DTAGPARERR    V_DTAGPARERR(1U)
877 
878 #define S_ITAGPARERR    27
879 #define V_ITAGPARERR(x) ((x) << S_ITAGPARERR)
880 #define F_ITAGPARERR    V_ITAGPARERR(1U)
881 
882 #define S_IBQTPPARERR    26
883 #define V_IBQTPPARERR(x) ((x) << S_IBQTPPARERR)
884 #define F_IBQTPPARERR    V_IBQTPPARERR(1U)
885 
886 #define S_IBQULPPARERR    25
887 #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
888 #define F_IBQULPPARERR    V_IBQULPPARERR(1U)
889 
890 #define S_IBQSGEHIPARERR    24
891 #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
892 #define F_IBQSGEHIPARERR    V_IBQSGEHIPARERR(1U)
893 
894 #define S_IBQSGELOPARERR    23
895 #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
896 #define F_IBQSGELOPARERR    V_IBQSGELOPARERR(1U)
897 
898 #define S_OBQULPLOPARERR    22
899 #define V_OBQULPLOPARERR(x) ((x) << S_OBQULPLOPARERR)
900 #define F_OBQULPLOPARERR    V_OBQULPLOPARERR(1U)
901 
902 #define S_OBQULPHIPARERR    21
903 #define V_OBQULPHIPARERR(x) ((x) << S_OBQULPHIPARERR)
904 #define F_OBQULPHIPARERR    V_OBQULPHIPARERR(1U)
905 
906 #define S_OBQSGEPARERR    20
907 #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
908 #define F_OBQSGEPARERR    V_OBQSGEPARERR(1U)
909 
910 #define S_DCACHEPARERR    19
911 #define V_DCACHEPARERR(x) ((x) << S_DCACHEPARERR)
912 #define F_DCACHEPARERR    V_DCACHEPARERR(1U)
913 
914 #define S_ICACHEPARERR    18
915 #define V_ICACHEPARERR(x) ((x) << S_ICACHEPARERR)
916 #define F_ICACHEPARERR    V_ICACHEPARERR(1U)
917 
918 #define S_DRAMPARERR    17
919 #define V_DRAMPARERR(x) ((x) << S_DRAMPARERR)
920 #define F_DRAMPARERR    V_DRAMPARERR(1U)
921 
922 #define A_CIM_HOST_INT_CAUSE 0x29c
923 
924 #define S_BLKWRPLINT    12
925 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
926 #define F_BLKWRPLINT    V_BLKWRPLINT(1U)
927 
928 #define S_BLKRDPLINT    11
929 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
930 #define F_BLKRDPLINT    V_BLKRDPLINT(1U)
931 
932 #define S_BLKWRCTLINT    10
933 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
934 #define F_BLKWRCTLINT    V_BLKWRCTLINT(1U)
935 
936 #define S_BLKRDCTLINT    9
937 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
938 #define F_BLKRDCTLINT    V_BLKRDCTLINT(1U)
939 
940 #define S_BLKWRFLASHINT    8
941 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
942 #define F_BLKWRFLASHINT    V_BLKWRFLASHINT(1U)
943 
944 #define S_BLKRDFLASHINT    7
945 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
946 #define F_BLKRDFLASHINT    V_BLKRDFLASHINT(1U)
947 
948 #define S_SGLWRFLASHINT    6
949 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
950 #define F_SGLWRFLASHINT    V_SGLWRFLASHINT(1U)
951 
952 #define S_WRBLKFLASHINT    5
953 #define V_WRBLKFLASHINT(x) ((x) << S_WRBLKFLASHINT)
954 #define F_WRBLKFLASHINT    V_WRBLKFLASHINT(1U)
955 
956 #define S_BLKWRBOOTINT    4
957 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
958 #define F_BLKWRBOOTINT    V_BLKWRBOOTINT(1U)
959 
960 #define S_FLASHRANGEINT    2
961 #define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT)
962 #define F_FLASHRANGEINT    V_FLASHRANGEINT(1U)
963 
964 #define S_SDRAMRANGEINT    1
965 #define V_SDRAMRANGEINT(x) ((x) << S_SDRAMRANGEINT)
966 #define F_SDRAMRANGEINT    V_SDRAMRANGEINT(1U)
967 
968 #define S_RSVDSPACEINT    0
969 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
970 #define F_RSVDSPACEINT    V_RSVDSPACEINT(1U)
971 
972 #define A_CIM_HOST_ACC_CTRL 0x2b0
973 
974 #define S_HOSTBUSY    17
975 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
976 #define F_HOSTBUSY    V_HOSTBUSY(1U)
977 
978 #define A_CIM_HOST_ACC_DATA 0x2b4
979 
980 #define A_CIM_IBQ_DBG_CFG 0x2c0
981 
982 #define S_IBQDBGADDR    16
983 #define M_IBQDBGADDR    0x1ff
984 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
985 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
986 
987 #define S_IBQDBGQID    3
988 #define M_IBQDBGQID    0x3
989 #define V_IBQDBGQID(x) ((x) << S_IBQDBGQID)
990 #define G_IBQDBGQID(x) (((x) >> S_IBQDBGQID) & M_IBQDBGQID)
991 
992 #define S_IBQDBGWR    2
993 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
994 #define F_IBQDBGWR    V_IBQDBGWR(1U)
995 
996 #define S_IBQDBGBUSY    1
997 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
998 #define F_IBQDBGBUSY    V_IBQDBGBUSY(1U)
999 
1000 #define S_IBQDBGEN    0
1001 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
1002 #define F_IBQDBGEN    V_IBQDBGEN(1U)
1003 
1004 #define A_CIM_IBQ_DBG_DATA 0x2c8
1005 
1006 #define A_TP_IN_CONFIG 0x300
1007 
1008 #define S_RXFBARBPRIO    25
1009 #define V_RXFBARBPRIO(x) ((x) << S_RXFBARBPRIO)
1010 #define F_RXFBARBPRIO    V_RXFBARBPRIO(1U)
1011 
1012 #define S_TXFBARBPRIO    24
1013 #define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO)
1014 #define F_TXFBARBPRIO    V_TXFBARBPRIO(1U)
1015 
1016 #define S_NICMODE    14
1017 #define V_NICMODE(x) ((x) << S_NICMODE)
1018 #define F_NICMODE    V_NICMODE(1U)
1019 
1020 #define F_NICMODE    V_NICMODE(1U)
1021 
1022 #define S_IPV6ENABLE    15
1023 #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
1024 #define F_IPV6ENABLE    V_IPV6ENABLE(1U)
1025 
1026 #define A_TP_OUT_CONFIG 0x304
1027 
1028 #define S_VLANEXTRACTIONENABLE    12
1029 
1030 #define A_TP_GLOBAL_CONFIG 0x308
1031 
1032 #define S_TXPACINGENABLE    24
1033 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
1034 #define F_TXPACINGENABLE    V_TXPACINGENABLE(1U)
1035 
1036 #define S_PATHMTU    15
1037 #define V_PATHMTU(x) ((x) << S_PATHMTU)
1038 #define F_PATHMTU    V_PATHMTU(1U)
1039 
1040 #define S_IPCHECKSUMOFFLOAD    13
1041 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
1042 #define F_IPCHECKSUMOFFLOAD    V_IPCHECKSUMOFFLOAD(1U)
1043 
1044 #define S_UDPCHECKSUMOFFLOAD    12
1045 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
1046 #define F_UDPCHECKSUMOFFLOAD    V_UDPCHECKSUMOFFLOAD(1U)
1047 
1048 #define S_TCPCHECKSUMOFFLOAD    11
1049 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
1050 #define F_TCPCHECKSUMOFFLOAD    V_TCPCHECKSUMOFFLOAD(1U)
1051 
1052 #define S_IPTTL    0
1053 #define M_IPTTL    0xff
1054 #define V_IPTTL(x) ((x) << S_IPTTL)
1055 
1056 #define A_TP_CMM_MM_BASE 0x314
1057 
1058 #define A_TP_CMM_TIMER_BASE 0x318
1059 
1060 #define S_CMTIMERMAXNUM    28
1061 #define M_CMTIMERMAXNUM    0x3
1062 #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
1063 
1064 #define A_TP_PMM_SIZE 0x31c
1065 
1066 #define A_TP_PMM_TX_BASE 0x320
1067 
1068 #define A_TP_PMM_RX_BASE 0x328
1069 
1070 #define A_TP_PMM_RX_PAGE_SIZE 0x32c
1071 
1072 #define A_TP_PMM_RX_MAX_PAGE 0x330
1073 
1074 #define A_TP_PMM_TX_PAGE_SIZE 0x334
1075 
1076 #define A_TP_PMM_TX_MAX_PAGE 0x338
1077 
1078 #define A_TP_TCP_OPTIONS 0x340
1079 
1080 #define S_MTUDEFAULT    16
1081 #define M_MTUDEFAULT    0xffff
1082 #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
1083 
1084 #define S_MTUENABLE    10
1085 #define V_MTUENABLE(x) ((x) << S_MTUENABLE)
1086 #define F_MTUENABLE    V_MTUENABLE(1U)
1087 
1088 #define S_SACKRX    8
1089 #define V_SACKRX(x) ((x) << S_SACKRX)
1090 #define F_SACKRX    V_SACKRX(1U)
1091 
1092 #define S_SACKMODE    4
1093 
1094 #define M_SACKMODE    0x3
1095 
1096 #define V_SACKMODE(x) ((x) << S_SACKMODE)
1097 
1098 #define S_WINDOWSCALEMODE    2
1099 #define M_WINDOWSCALEMODE    0x3
1100 #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
1101 
1102 #define S_TIMESTAMPSMODE    0
1103 
1104 #define M_TIMESTAMPSMODE    0x3
1105 
1106 #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
1107 
1108 #define A_TP_DACK_CONFIG 0x344
1109 
1110 #define S_AUTOSTATE3    30
1111 #define M_AUTOSTATE3    0x3
1112 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
1113 
1114 #define S_AUTOSTATE2    28
1115 #define M_AUTOSTATE2    0x3
1116 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
1117 
1118 #define S_AUTOSTATE1    26
1119 #define M_AUTOSTATE1    0x3
1120 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
1121 
1122 #define S_BYTETHRESHOLD    5
1123 #define M_BYTETHRESHOLD    0xfffff
1124 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
1125 
1126 #define S_MSSTHRESHOLD    3
1127 #define M_MSSTHRESHOLD    0x3
1128 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
1129 
1130 #define S_AUTOCAREFUL    2
1131 #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
1132 #define F_AUTOCAREFUL    V_AUTOCAREFUL(1U)
1133 
1134 #define S_AUTOENABLE    1
1135 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
1136 #define F_AUTOENABLE    V_AUTOENABLE(1U)
1137 
1138 #define S_DACK_MODE    0
1139 #define V_DACK_MODE(x) ((x) << S_DACK_MODE)
1140 #define F_DACK_MODE    V_DACK_MODE(1U)
1141 
1142 #define A_TP_PC_CONFIG 0x348
1143 
1144 #define S_TXTOSQUEUEMAPMODE    26
1145 #define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE)
1146 #define F_TXTOSQUEUEMAPMODE    V_TXTOSQUEUEMAPMODE(1U)
1147 
1148 #define S_ENABLEEPCMDAFULL    23
1149 #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
1150 #define F_ENABLEEPCMDAFULL    V_ENABLEEPCMDAFULL(1U)
1151 
1152 #define S_MODULATEUNIONMODE    22
1153 #define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE)
1154 #define F_MODULATEUNIONMODE    V_MODULATEUNIONMODE(1U)
1155 
1156 #define S_TXDEFERENABLE    20
1157 #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
1158 #define F_TXDEFERENABLE    V_TXDEFERENABLE(1U)
1159 
1160 #define S_RXCONGESTIONMODE    19
1161 #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
1162 #define F_RXCONGESTIONMODE    V_RXCONGESTIONMODE(1U)
1163 
1164 #define S_HEARBEATDACK    16
1165 #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
1166 #define F_HEARBEATDACK    V_HEARBEATDACK(1U)
1167 
1168 #define S_TXCONGESTIONMODE    15
1169 #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
1170 #define F_TXCONGESTIONMODE    V_TXCONGESTIONMODE(1U)
1171 
1172 #define S_ENABLEOCSPIFULL    30
1173 #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
1174 #define F_ENABLEOCSPIFULL    V_ENABLEOCSPIFULL(1U)
1175 
1176 #define S_LOCKTID    28
1177 #define V_LOCKTID(x) ((x) << S_LOCKTID)
1178 #define F_LOCKTID    V_LOCKTID(1U)
1179 
1180 #define S_TABLELATENCYDELTA    0
1181 #define M_TABLELATENCYDELTA    0xf
1182 #define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA)
1183 #define G_TABLELATENCYDELTA(x) \
1184 	(((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA)
1185 
1186 #define A_TP_PC_CONFIG2 0x34c
1187 
1188 #define S_DISBLEDAPARBIT0    15
1189 #define V_DISBLEDAPARBIT0(x) ((x) << S_DISBLEDAPARBIT0)
1190 #define F_DISBLEDAPARBIT0    V_DISBLEDAPARBIT0(1U)
1191 
1192 #define S_ENABLEARPMISS    13
1193 #define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)
1194 #define F_ENABLEARPMISS    V_ENABLEARPMISS(1U)
1195 
1196 #define S_ENABLENONOFDTNLSYN    12
1197 #define V_ENABLENONOFDTNLSYN(x) ((x) << S_ENABLENONOFDTNLSYN)
1198 #define F_ENABLENONOFDTNLSYN    V_ENABLENONOFDTNLSYN(1U)
1199 
1200 #define S_ENABLEIPV6RSS    11
1201 #define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)
1202 #define F_ENABLEIPV6RSS    V_ENABLEIPV6RSS(1U)
1203 
1204 #define S_CHDRAFULL    4
1205 #define V_CHDRAFULL(x) ((x) << S_CHDRAFULL)
1206 #define F_CHDRAFULL    V_CHDRAFULL(1U)
1207 
1208 #define A_TP_TCP_BACKOFF_REG0 0x350
1209 
1210 #define A_TP_TCP_BACKOFF_REG1 0x354
1211 
1212 #define A_TP_TCP_BACKOFF_REG2 0x358
1213 
1214 #define A_TP_TCP_BACKOFF_REG3 0x35c
1215 
1216 #define A_TP_PARA_REG2 0x368
1217 
1218 #define S_MAXRXDATA    16
1219 #define M_MAXRXDATA    0xffff
1220 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
1221 
1222 #define S_RXCOALESCESIZE    0
1223 #define M_RXCOALESCESIZE    0xffff
1224 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
1225 
1226 #define A_TP_PARA_REG3 0x36c
1227 
1228 #define S_TXDATAACKIDX    16
1229 #define M_TXDATAACKIDX    0xf
1230 
1231 #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
1232 
1233 #define S_TXPACEAUTOSTRICT    10
1234 #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
1235 #define F_TXPACEAUTOSTRICT    V_TXPACEAUTOSTRICT(1U)
1236 
1237 #define S_TXPACEFIXED    9
1238 #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
1239 #define F_TXPACEFIXED    V_TXPACEFIXED(1U)
1240 
1241 #define S_TXPACEAUTO    8
1242 #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
1243 #define F_TXPACEAUTO    V_TXPACEAUTO(1U)
1244 
1245 #define S_RXCOALESCEENABLE    1
1246 #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
1247 #define F_RXCOALESCEENABLE    V_RXCOALESCEENABLE(1U)
1248 
1249 #define S_RXCOALESCEPSHEN    0
1250 #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
1251 #define F_RXCOALESCEPSHEN    V_RXCOALESCEPSHEN(1U)
1252 
1253 #define A_TP_PARA_REG4 0x370
1254 
1255 #define A_TP_PARA_REG5 0x374
1256 
1257 #define S_RXDDPOFFINIT    3
1258 #define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)
1259 #define F_RXDDPOFFINIT    V_RXDDPOFFINIT(1U)
1260 
1261 #define A_TP_PARA_REG6 0x378
1262 
1263 #define S_T3A_ENABLEESND    13
1264 #define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND)
1265 #define F_T3A_ENABLEESND    V_T3A_ENABLEESND(1U)
1266 
1267 #define S_ENABLEESND    11
1268 #define V_ENABLEESND(x) ((x) << S_ENABLEESND)
1269 #define F_ENABLEESND    V_ENABLEESND(1U)
1270 
1271 #define A_TP_PARA_REG7 0x37c
1272 
1273 #define S_PMMAXXFERLEN1    16
1274 #define M_PMMAXXFERLEN1    0xffff
1275 #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
1276 
1277 #define S_PMMAXXFERLEN0    0
1278 #define M_PMMAXXFERLEN0    0xffff
1279 #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
1280 
1281 #define A_TP_TIMER_RESOLUTION 0x390
1282 
1283 #define S_TIMERRESOLUTION    16
1284 #define M_TIMERRESOLUTION    0xff
1285 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
1286 
1287 #define S_TIMESTAMPRESOLUTION    8
1288 #define M_TIMESTAMPRESOLUTION    0xff
1289 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
1290 
1291 #define S_DELAYEDACKRESOLUTION    0
1292 #define M_DELAYEDACKRESOLUTION    0xff
1293 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
1294 
1295 #define A_TP_MSL 0x394
1296 
1297 #define A_TP_RXT_MIN 0x398
1298 
1299 #define A_TP_RXT_MAX 0x39c
1300 
1301 #define A_TP_PERS_MIN 0x3a0
1302 
1303 #define A_TP_PERS_MAX 0x3a4
1304 
1305 #define A_TP_KEEP_IDLE 0x3a8
1306 
1307 #define A_TP_KEEP_INTVL 0x3ac
1308 
1309 #define A_TP_INIT_SRTT 0x3b0
1310 
1311 #define A_TP_DACK_TIMER 0x3b4
1312 
1313 #define A_TP_FINWAIT2_TIMER 0x3b8
1314 
1315 #define A_TP_SHIFT_CNT 0x3c0
1316 
1317 #define S_SYNSHIFTMAX    24
1318 
1319 #define M_SYNSHIFTMAX    0xff
1320 
1321 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
1322 
1323 #define S_RXTSHIFTMAXR1    20
1324 
1325 #define M_RXTSHIFTMAXR1    0xf
1326 
1327 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
1328 
1329 #define S_RXTSHIFTMAXR2    16
1330 
1331 #define M_RXTSHIFTMAXR2    0xf
1332 
1333 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
1334 
1335 #define S_PERSHIFTBACKOFFMAX    12
1336 #define M_PERSHIFTBACKOFFMAX    0xf
1337 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
1338 
1339 #define S_PERSHIFTMAX    8
1340 #define M_PERSHIFTMAX    0xf
1341 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
1342 
1343 #define S_KEEPALIVEMAX    0
1344 
1345 #define M_KEEPALIVEMAX    0xff
1346 
1347 #define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX)
1348 
1349 #define A_TP_MTU_PORT_TABLE 0x3d0
1350 
1351 #define A_TP_CCTRL_TABLE 0x3dc
1352 
1353 #define A_TP_MTU_TABLE 0x3e4
1354 
1355 #define A_TP_RSS_MAP_TABLE 0x3e8
1356 
1357 #define A_TP_RSS_LKP_TABLE 0x3ec
1358 
1359 #define A_TP_RSS_CONFIG 0x3f0
1360 
1361 #define S_TNL4TUPEN    29
1362 #define V_TNL4TUPEN(x) ((x) << S_TNL4TUPEN)
1363 #define F_TNL4TUPEN    V_TNL4TUPEN(1U)
1364 
1365 #define S_TNL2TUPEN    28
1366 #define V_TNL2TUPEN(x) ((x) << S_TNL2TUPEN)
1367 #define F_TNL2TUPEN    V_TNL2TUPEN(1U)
1368 
1369 #define S_TNLPRTEN    26
1370 #define V_TNLPRTEN(x) ((x) << S_TNLPRTEN)
1371 #define F_TNLPRTEN    V_TNLPRTEN(1U)
1372 
1373 #define S_TNLMAPEN    25
1374 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
1375 #define F_TNLMAPEN    V_TNLMAPEN(1U)
1376 
1377 #define S_TNLLKPEN    24
1378 #define V_TNLLKPEN(x) ((x) << S_TNLLKPEN)
1379 #define F_TNLLKPEN    V_TNLLKPEN(1U)
1380 
1381 #define S_RRCPLMAPEN    7
1382 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
1383 #define F_RRCPLMAPEN    V_RRCPLMAPEN(1U)
1384 
1385 #define S_RRCPLCPUSIZE    4
1386 #define M_RRCPLCPUSIZE    0x7
1387 #define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE)
1388 
1389 #define S_RQFEEDBACKENABLE    3
1390 #define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE)
1391 #define F_RQFEEDBACKENABLE    V_RQFEEDBACKENABLE(1U)
1392 
1393 #define S_HASHTOEPLITZ    2
1394 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
1395 #define F_HASHTOEPLITZ    V_HASHTOEPLITZ(1U)
1396 
1397 #define S_DISABLE    0
1398 
1399 #define A_TP_TM_PIO_ADDR 0x418
1400 
1401 #define A_TP_TM_PIO_DATA 0x41c
1402 
1403 #define A_TP_TX_MOD_QUE_TABLE 0x420
1404 
1405 #define A_TP_TX_RESOURCE_LIMIT 0x424
1406 
1407 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428
1408 
1409 #define S_TX_MOD_QUEUE_REQ_MAP    0
1410 #define M_TX_MOD_QUEUE_REQ_MAP    0xff
1411 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
1412 
1413 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c
1414 
1415 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430
1416 
1417 #define A_TP_MOD_CHANNEL_WEIGHT 0x434
1418 
1419 #define A_TP_MOD_RATE_LIMIT 0x438
1420 
1421 #define A_TP_PIO_ADDR 0x440
1422 
1423 #define A_TP_PIO_DATA 0x444
1424 
1425 #define A_TP_RESET 0x44c
1426 
1427 #define S_FLSTINITENABLE    1
1428 #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
1429 #define F_FLSTINITENABLE    V_FLSTINITENABLE(1U)
1430 
1431 #define S_TPRESET    0
1432 #define V_TPRESET(x) ((x) << S_TPRESET)
1433 #define F_TPRESET    V_TPRESET(1U)
1434 
1435 #define A_TP_CMM_MM_RX_FLST_BASE 0x460
1436 
1437 #define A_TP_CMM_MM_TX_FLST_BASE 0x464
1438 
1439 #define A_TP_CMM_MM_PS_FLST_BASE 0x468
1440 
1441 #define A_TP_MIB_INDEX 0x450
1442 
1443 #define A_TP_MIB_RDATA 0x454
1444 
1445 #define A_TP_CMM_MM_MAX_PSTRUCT 0x46c
1446 
1447 #define A_TP_INT_ENABLE 0x470
1448 
1449 #define S_FLMTXFLSTEMPTY    30
1450 #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
1451 #define F_FLMTXFLSTEMPTY    V_FLMTXFLSTEMPTY(1U)
1452 
1453 #define S_FLMRXFLSTEMPTY    29
1454 #define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY)
1455 #define F_FLMRXFLSTEMPTY    V_FLMRXFLSTEMPTY(1U)
1456 
1457 #define S_ARPLUTPERR    26
1458 #define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)
1459 #define F_ARPLUTPERR    V_ARPLUTPERR(1U)
1460 
1461 #define S_CMCACHEPERR    24
1462 #define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)
1463 #define F_CMCACHEPERR    V_CMCACHEPERR(1U)
1464 
1465 #define A_TP_INT_CAUSE 0x474
1466 
1467 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
1468 
1469 #define A_TP_TX_DROP_CFG_CH0 0x12b
1470 
1471 #define A_TP_TX_DROP_MODE 0x12f
1472 
1473 #define A_TP_EGRESS_CONFIG 0x145
1474 
1475 #define S_REWRITEFORCETOSIZE    0
1476 #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
1477 #define F_REWRITEFORCETOSIZE    V_REWRITEFORCETOSIZE(1U)
1478 
1479 #define A_TP_TX_TRC_KEY0 0x20
1480 
1481 #define A_TP_RX_TRC_KEY0 0x120
1482 
1483 #define A_TP_TX_DROP_CNT_CH0 0x12d
1484 
1485 #define S_TXDROPCNTCH0RCVD    0
1486 #define M_TXDROPCNTCH0RCVD    0xffff
1487 #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
1488 #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & \
1489 			       M_TXDROPCNTCH0RCVD)
1490 
1491 #define A_TP_PROXY_FLOW_CNTL 0x4b0
1492 
1493 #define A_TP_EMBED_OP_FIELD0 0x4e8
1494 #define A_TP_EMBED_OP_FIELD1 0x4ec
1495 #define A_TP_EMBED_OP_FIELD2 0x4f0
1496 #define A_TP_EMBED_OP_FIELD3 0x4f4
1497 #define A_TP_EMBED_OP_FIELD4 0x4f8
1498 #define A_TP_EMBED_OP_FIELD5 0x4fc
1499 
1500 #define A_ULPRX_CTL 0x500
1501 
1502 #define S_ROUND_ROBIN    4
1503 #define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN)
1504 #define F_ROUND_ROBIN    V_ROUND_ROBIN(1U)
1505 
1506 #define A_ULPRX_INT_ENABLE 0x504
1507 
1508 #define S_DATASELFRAMEERR0    7
1509 #define V_DATASELFRAMEERR0(x) ((x) << S_DATASELFRAMEERR0)
1510 #define F_DATASELFRAMEERR0    V_DATASELFRAMEERR0(1U)
1511 
1512 #define S_DATASELFRAMEERR1    6
1513 #define V_DATASELFRAMEERR1(x) ((x) << S_DATASELFRAMEERR1)
1514 #define F_DATASELFRAMEERR1    V_DATASELFRAMEERR1(1U)
1515 
1516 #define S_PCMDMUXPERR    5
1517 #define V_PCMDMUXPERR(x) ((x) << S_PCMDMUXPERR)
1518 #define F_PCMDMUXPERR    V_PCMDMUXPERR(1U)
1519 
1520 #define S_ARBFPERR    4
1521 #define V_ARBFPERR(x) ((x) << S_ARBFPERR)
1522 #define F_ARBFPERR    V_ARBFPERR(1U)
1523 
1524 #define S_ARBPF0PERR    3
1525 #define V_ARBPF0PERR(x) ((x) << S_ARBPF0PERR)
1526 #define F_ARBPF0PERR    V_ARBPF0PERR(1U)
1527 
1528 #define S_ARBPF1PERR    2
1529 #define V_ARBPF1PERR(x) ((x) << S_ARBPF1PERR)
1530 #define F_ARBPF1PERR    V_ARBPF1PERR(1U)
1531 
1532 #define S_PARERRPCMD    1
1533 #define V_PARERRPCMD(x) ((x) << S_PARERRPCMD)
1534 #define F_PARERRPCMD    V_PARERRPCMD(1U)
1535 
1536 #define S_PARERRDATA    0
1537 #define V_PARERRDATA(x) ((x) << S_PARERRDATA)
1538 #define F_PARERRDATA    V_PARERRDATA(1U)
1539 
1540 #define A_ULPRX_INT_CAUSE 0x508
1541 
1542 #define A_ULPRX_ISCSI_LLIMIT 0x50c
1543 
1544 #define A_ULPRX_ISCSI_ULIMIT 0x510
1545 
1546 #define A_ULPRX_ISCSI_TAGMASK 0x514
1547 
1548 #define A_ULPRX_ISCSI_PSZ 0x518
1549 
1550 #define A_ULPRX_TDDP_LLIMIT 0x51c
1551 
1552 #define A_ULPRX_TDDP_ULIMIT 0x520
1553 #define A_ULPRX_TDDP_PSZ 0x528
1554 
1555 #define S_HPZ0    0
1556 #define M_HPZ0    0xf
1557 #define V_HPZ0(x) ((x) << S_HPZ0)
1558 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
1559 
1560 #define A_ULPRX_STAG_LLIMIT 0x52c
1561 
1562 #define A_ULPRX_STAG_ULIMIT 0x530
1563 
1564 #define A_ULPRX_RQ_LLIMIT 0x534
1565 #define A_ULPRX_RQ_LLIMIT 0x534
1566 
1567 #define A_ULPRX_RQ_ULIMIT 0x538
1568 #define A_ULPRX_RQ_ULIMIT 0x538
1569 
1570 #define A_ULPRX_PBL_LLIMIT 0x53c
1571 
1572 #define A_ULPRX_PBL_ULIMIT 0x540
1573 #define A_ULPRX_PBL_ULIMIT 0x540
1574 
1575 #define A_ULPRX_TDDP_TAGMASK 0x524
1576 
1577 #define A_ULPRX_RQ_LLIMIT 0x534
1578 #define A_ULPRX_RQ_LLIMIT 0x534
1579 
1580 #define A_ULPRX_RQ_ULIMIT 0x538
1581 #define A_ULPRX_RQ_ULIMIT 0x538
1582 
1583 #define A_ULPRX_PBL_ULIMIT 0x540
1584 #define A_ULPRX_PBL_ULIMIT 0x540
1585 
1586 #define A_ULPTX_CONFIG 0x580
1587 
1588 #define S_CFG_CQE_SOP_MASK    1
1589 #define V_CFG_CQE_SOP_MASK(x) ((x) << S_CFG_CQE_SOP_MASK)
1590 #define F_CFG_CQE_SOP_MASK    V_CFG_CQE_SOP_MASK(1U)
1591 
1592 #define S_CFG_RR_ARB    0
1593 #define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB)
1594 #define F_CFG_RR_ARB    V_CFG_RR_ARB(1U)
1595 
1596 #define A_ULPTX_INT_ENABLE 0x584
1597 
1598 #define S_PBL_BOUND_ERR_CH1    1
1599 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
1600 #define F_PBL_BOUND_ERR_CH1    V_PBL_BOUND_ERR_CH1(1U)
1601 
1602 #define S_PBL_BOUND_ERR_CH0    0
1603 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
1604 #define F_PBL_BOUND_ERR_CH0    V_PBL_BOUND_ERR_CH0(1U)
1605 
1606 #define A_ULPTX_INT_CAUSE 0x588
1607 
1608 #define A_ULPTX_TPT_LLIMIT 0x58c
1609 
1610 #define A_ULPTX_TPT_ULIMIT 0x590
1611 
1612 #define A_ULPTX_PBL_LLIMIT 0x594
1613 
1614 #define A_ULPTX_PBL_ULIMIT 0x598
1615 
1616 #define A_ULPTX_DMA_WEIGHT 0x5ac
1617 
1618 #define S_D1_WEIGHT    16
1619 #define M_D1_WEIGHT    0xffff
1620 #define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT)
1621 
1622 #define S_D0_WEIGHT    0
1623 #define M_D0_WEIGHT    0xffff
1624 #define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT)
1625 
1626 #define A_PM1_RX_CFG 0x5c0
1627 #define A_PM1_RX_MODE 0x5c4
1628 
1629 #define A_PM1_RX_INT_ENABLE 0x5d8
1630 
1631 #define S_ZERO_E_CMD_ERROR    18
1632 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
1633 #define F_ZERO_E_CMD_ERROR    V_ZERO_E_CMD_ERROR(1U)
1634 
1635 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR    17
1636 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
1637 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR    V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
1638 
1639 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR    16
1640 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
1641 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR    V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
1642 
1643 #define S_IESPI0_RX_FRAMING_ERROR    15
1644 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
1645 #define F_IESPI0_RX_FRAMING_ERROR    V_IESPI0_RX_FRAMING_ERROR(1U)
1646 
1647 #define S_IESPI1_RX_FRAMING_ERROR    14
1648 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
1649 #define F_IESPI1_RX_FRAMING_ERROR    V_IESPI1_RX_FRAMING_ERROR(1U)
1650 
1651 #define S_IESPI0_TX_FRAMING_ERROR    13
1652 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
1653 #define F_IESPI0_TX_FRAMING_ERROR    V_IESPI0_TX_FRAMING_ERROR(1U)
1654 
1655 #define S_IESPI1_TX_FRAMING_ERROR    12
1656 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
1657 #define F_IESPI1_TX_FRAMING_ERROR    V_IESPI1_TX_FRAMING_ERROR(1U)
1658 
1659 #define S_OCSPI0_RX_FRAMING_ERROR    11
1660 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
1661 #define F_OCSPI0_RX_FRAMING_ERROR    V_OCSPI0_RX_FRAMING_ERROR(1U)
1662 
1663 #define S_OCSPI1_RX_FRAMING_ERROR    10
1664 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
1665 #define F_OCSPI1_RX_FRAMING_ERROR    V_OCSPI1_RX_FRAMING_ERROR(1U)
1666 
1667 #define S_OCSPI0_TX_FRAMING_ERROR    9
1668 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
1669 #define F_OCSPI0_TX_FRAMING_ERROR    V_OCSPI0_TX_FRAMING_ERROR(1U)
1670 
1671 #define S_OCSPI1_TX_FRAMING_ERROR    8
1672 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
1673 #define F_OCSPI1_TX_FRAMING_ERROR    V_OCSPI1_TX_FRAMING_ERROR(1U)
1674 
1675 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    7
1676 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
1677 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
1678 
1679 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    6
1680 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
1681 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
1682 
1683 #define S_IESPI_PAR_ERROR    3
1684 #define M_IESPI_PAR_ERROR    0x7
1685 
1686 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
1687 
1688 #define S_OCSPI_PAR_ERROR    0
1689 #define M_OCSPI_PAR_ERROR    0x7
1690 
1691 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
1692 
1693 #define A_PM1_RX_INT_CAUSE 0x5dc
1694 
1695 #define A_PM1_TX_CFG 0x5e0
1696 #define A_PM1_TX_MODE 0x5e4
1697 
1698 #define A_PM1_TX_INT_ENABLE 0x5f8
1699 
1700 #define S_ZERO_C_CMD_ERROR    18
1701 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
1702 #define F_ZERO_C_CMD_ERROR    V_ZERO_C_CMD_ERROR(1U)
1703 
1704 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR    17
1705 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
1706 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
1707 
1708 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR    16
1709 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
1710 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
1711 
1712 #define S_ICSPI0_RX_FRAMING_ERROR    15
1713 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
1714 #define F_ICSPI0_RX_FRAMING_ERROR    V_ICSPI0_RX_FRAMING_ERROR(1U)
1715 
1716 #define S_ICSPI1_RX_FRAMING_ERROR    14
1717 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
1718 #define F_ICSPI1_RX_FRAMING_ERROR    V_ICSPI1_RX_FRAMING_ERROR(1U)
1719 
1720 #define S_ICSPI0_TX_FRAMING_ERROR    13
1721 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
1722 #define F_ICSPI0_TX_FRAMING_ERROR    V_ICSPI0_TX_FRAMING_ERROR(1U)
1723 
1724 #define S_ICSPI1_TX_FRAMING_ERROR    12
1725 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
1726 #define F_ICSPI1_TX_FRAMING_ERROR    V_ICSPI1_TX_FRAMING_ERROR(1U)
1727 
1728 #define S_OESPI0_RX_FRAMING_ERROR    11
1729 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
1730 #define F_OESPI0_RX_FRAMING_ERROR    V_OESPI0_RX_FRAMING_ERROR(1U)
1731 
1732 #define S_OESPI1_RX_FRAMING_ERROR    10
1733 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
1734 #define F_OESPI1_RX_FRAMING_ERROR    V_OESPI1_RX_FRAMING_ERROR(1U)
1735 
1736 #define S_OESPI0_TX_FRAMING_ERROR    9
1737 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
1738 #define F_OESPI0_TX_FRAMING_ERROR    V_OESPI0_TX_FRAMING_ERROR(1U)
1739 
1740 #define S_OESPI1_TX_FRAMING_ERROR    8
1741 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
1742 #define F_OESPI1_TX_FRAMING_ERROR    V_OESPI1_TX_FRAMING_ERROR(1U)
1743 
1744 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR    7
1745 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
1746 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
1747 
1748 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR    6
1749 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
1750 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
1751 
1752 #define S_ICSPI_PAR_ERROR    3
1753 #define M_ICSPI_PAR_ERROR    0x7
1754 
1755 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
1756 
1757 #define S_OESPI_PAR_ERROR    0
1758 #define M_OESPI_PAR_ERROR    0x7
1759 
1760 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
1761 
1762 #define A_PM1_TX_INT_CAUSE 0x5fc
1763 
1764 #define A_MPS_CFG 0x600
1765 
1766 #define S_TPRXPORTEN    4
1767 #define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN)
1768 #define F_TPRXPORTEN    V_TPRXPORTEN(1U)
1769 
1770 #define S_TPTXPORT1EN    3
1771 #define V_TPTXPORT1EN(x) ((x) << S_TPTXPORT1EN)
1772 #define F_TPTXPORT1EN    V_TPTXPORT1EN(1U)
1773 
1774 #define S_TPTXPORT0EN    2
1775 #define V_TPTXPORT0EN(x) ((x) << S_TPTXPORT0EN)
1776 #define F_TPTXPORT0EN    V_TPTXPORT0EN(1U)
1777 
1778 #define S_PORT1ACTIVE    1
1779 #define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE)
1780 #define F_PORT1ACTIVE    V_PORT1ACTIVE(1U)
1781 
1782 #define S_PORT0ACTIVE    0
1783 #define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE)
1784 #define F_PORT0ACTIVE    V_PORT0ACTIVE(1U)
1785 
1786 #define S_ENFORCEPKT    11
1787 #define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT)
1788 #define F_ENFORCEPKT    V_ENFORCEPKT(1U)
1789 
1790 #define A_MPS_INT_ENABLE 0x61c
1791 
1792 #define S_MCAPARERRENB    6
1793 #define M_MCAPARERRENB    0x7
1794 
1795 #define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB)
1796 
1797 #define S_RXTPPARERRENB    4
1798 #define M_RXTPPARERRENB    0x3
1799 
1800 #define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB)
1801 
1802 #define S_TX1TPPARERRENB    2
1803 #define M_TX1TPPARERRENB    0x3
1804 
1805 #define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB)
1806 
1807 #define S_TX0TPPARERRENB    0
1808 #define M_TX0TPPARERRENB    0x3
1809 
1810 #define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB)
1811 
1812 #define A_MPS_INT_CAUSE 0x620
1813 
1814 #define S_MCAPARERR    6
1815 #define M_MCAPARERR    0x7
1816 
1817 #define V_MCAPARERR(x) ((x) << S_MCAPARERR)
1818 
1819 #define S_RXTPPARERR    4
1820 #define M_RXTPPARERR    0x3
1821 
1822 #define V_RXTPPARERR(x) ((x) << S_RXTPPARERR)
1823 
1824 #define S_TX1TPPARERR    2
1825 #define M_TX1TPPARERR    0x3
1826 
1827 #define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR)
1828 
1829 #define S_TX0TPPARERR    0
1830 #define M_TX0TPPARERR    0x3
1831 
1832 #define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR)
1833 
1834 #define A_CPL_SWITCH_CNTRL 0x640
1835 
1836 #define A_CPL_INTR_ENABLE 0x650
1837 
1838 #define S_CIM_OP_MAP_PERR    5
1839 #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
1840 #define F_CIM_OP_MAP_PERR    V_CIM_OP_MAP_PERR(1U)
1841 
1842 #define S_CIM_OVFL_ERROR    4
1843 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
1844 #define F_CIM_OVFL_ERROR    V_CIM_OVFL_ERROR(1U)
1845 
1846 #define S_TP_FRAMING_ERROR    3
1847 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
1848 #define F_TP_FRAMING_ERROR    V_TP_FRAMING_ERROR(1U)
1849 
1850 #define S_SGE_FRAMING_ERROR    2
1851 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
1852 #define F_SGE_FRAMING_ERROR    V_SGE_FRAMING_ERROR(1U)
1853 
1854 #define S_CIM_FRAMING_ERROR    1
1855 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
1856 #define F_CIM_FRAMING_ERROR    V_CIM_FRAMING_ERROR(1U)
1857 
1858 #define S_ZERO_SWITCH_ERROR    0
1859 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
1860 #define F_ZERO_SWITCH_ERROR    V_ZERO_SWITCH_ERROR(1U)
1861 
1862 #define A_CPL_INTR_CAUSE 0x654
1863 
1864 #define A_CPL_MAP_TBL_DATA 0x65c
1865 
1866 #define A_SMB_GLOBAL_TIME_CFG 0x660
1867 
1868 #define A_I2C_CFG 0x6a0
1869 
1870 #define S_I2C_CLKDIV    0
1871 #define M_I2C_CLKDIV    0xfff
1872 #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
1873 
1874 #define A_MI1_CFG 0x6b0
1875 
1876 #define S_CLKDIV    5
1877 #define M_CLKDIV    0xff
1878 #define V_CLKDIV(x) ((x) << S_CLKDIV)
1879 
1880 #define S_ST    3
1881 
1882 #define M_ST    0x3
1883 
1884 #define V_ST(x) ((x) << S_ST)
1885 
1886 #define G_ST(x) (((x) >> S_ST) & M_ST)
1887 
1888 #define S_PREEN    2
1889 #define V_PREEN(x) ((x) << S_PREEN)
1890 #define F_PREEN    V_PREEN(1U)
1891 
1892 #define S_MDIINV    1
1893 #define V_MDIINV(x) ((x) << S_MDIINV)
1894 #define F_MDIINV    V_MDIINV(1U)
1895 
1896 #define S_MDIEN    0
1897 #define V_MDIEN(x) ((x) << S_MDIEN)
1898 #define F_MDIEN    V_MDIEN(1U)
1899 
1900 #define A_MI1_ADDR 0x6b4
1901 
1902 #define S_PHYADDR    5
1903 #define M_PHYADDR    0x1f
1904 #define V_PHYADDR(x) ((x) << S_PHYADDR)
1905 
1906 #define S_REGADDR    0
1907 #define M_REGADDR    0x1f
1908 #define V_REGADDR(x) ((x) << S_REGADDR)
1909 
1910 #define A_MI1_DATA 0x6b8
1911 
1912 #define A_MI1_OP 0x6bc
1913 
1914 #define S_MDI_OP    0
1915 #define M_MDI_OP    0x3
1916 #define V_MDI_OP(x) ((x) << S_MDI_OP)
1917 
1918 #define A_SF_DATA 0x6d8
1919 
1920 #define A_SF_OP 0x6dc
1921 
1922 #define S_BYTECNT    1
1923 #define M_BYTECNT    0x3
1924 #define V_BYTECNT(x) ((x) << S_BYTECNT)
1925 
1926 #define A_PL_INT_ENABLE0 0x6e0
1927 
1928 #define S_T3DBG    23
1929 #define V_T3DBG(x) ((x) << S_T3DBG)
1930 #define F_T3DBG    V_T3DBG(1U)
1931 
1932 #define S_XGMAC0_1    20
1933 #define V_XGMAC0_1(x) ((x) << S_XGMAC0_1)
1934 #define F_XGMAC0_1    V_XGMAC0_1(1U)
1935 
1936 #define S_XGMAC0_0    19
1937 #define V_XGMAC0_0(x) ((x) << S_XGMAC0_0)
1938 #define F_XGMAC0_0    V_XGMAC0_0(1U)
1939 
1940 #define S_MC5A    18
1941 #define V_MC5A(x) ((x) << S_MC5A)
1942 #define F_MC5A    V_MC5A(1U)
1943 
1944 #define S_CPL_SWITCH    12
1945 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
1946 #define F_CPL_SWITCH    V_CPL_SWITCH(1U)
1947 
1948 #define S_MPS0    11
1949 #define V_MPS0(x) ((x) << S_MPS0)
1950 #define F_MPS0    V_MPS0(1U)
1951 
1952 #define S_PM1_TX    10
1953 #define V_PM1_TX(x) ((x) << S_PM1_TX)
1954 #define F_PM1_TX    V_PM1_TX(1U)
1955 
1956 #define S_PM1_RX    9
1957 #define V_PM1_RX(x) ((x) << S_PM1_RX)
1958 #define F_PM1_RX    V_PM1_RX(1U)
1959 
1960 #define S_ULP2_TX    8
1961 #define V_ULP2_TX(x) ((x) << S_ULP2_TX)
1962 #define F_ULP2_TX    V_ULP2_TX(1U)
1963 
1964 #define S_ULP2_RX    7
1965 #define V_ULP2_RX(x) ((x) << S_ULP2_RX)
1966 #define F_ULP2_RX    V_ULP2_RX(1U)
1967 
1968 #define S_TP1    6
1969 #define V_TP1(x) ((x) << S_TP1)
1970 #define F_TP1    V_TP1(1U)
1971 
1972 #define S_CIM    5
1973 #define V_CIM(x) ((x) << S_CIM)
1974 #define F_CIM    V_CIM(1U)
1975 
1976 #define S_MC7_CM    4
1977 #define V_MC7_CM(x) ((x) << S_MC7_CM)
1978 #define F_MC7_CM    V_MC7_CM(1U)
1979 
1980 #define S_MC7_PMTX    3
1981 #define V_MC7_PMTX(x) ((x) << S_MC7_PMTX)
1982 #define F_MC7_PMTX    V_MC7_PMTX(1U)
1983 
1984 #define S_MC7_PMRX    2
1985 #define V_MC7_PMRX(x) ((x) << S_MC7_PMRX)
1986 #define F_MC7_PMRX    V_MC7_PMRX(1U)
1987 
1988 #define S_PCIM0    1
1989 #define V_PCIM0(x) ((x) << S_PCIM0)
1990 #define F_PCIM0    V_PCIM0(1U)
1991 
1992 #define S_SGE3    0
1993 #define V_SGE3(x) ((x) << S_SGE3)
1994 #define F_SGE3    V_SGE3(1U)
1995 
1996 #define A_PL_INT_CAUSE0 0x6e4
1997 
1998 #define A_PL_RST 0x6f0
1999 
2000 #define S_FATALPERREN    4
2001 #define V_FATALPERREN(x) ((x) << S_FATALPERREN)
2002 #define F_FATALPERREN    V_FATALPERREN(1U)
2003 
2004 #define S_CRSTWRM    1
2005 #define V_CRSTWRM(x) ((x) << S_CRSTWRM)
2006 #define F_CRSTWRM    V_CRSTWRM(1U)
2007 
2008 #define A_PL_REV 0x6f4
2009 
2010 #define A_PL_CLI 0x6f8
2011 
2012 #define A_MC5_DB_CONFIG 0x704
2013 
2014 #define S_TMTYPEHI    30
2015 #define V_TMTYPEHI(x) ((x) << S_TMTYPEHI)
2016 #define F_TMTYPEHI    V_TMTYPEHI(1U)
2017 
2018 #define S_TMPARTSIZE    28
2019 #define M_TMPARTSIZE    0x3
2020 #define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE)
2021 #define G_TMPARTSIZE(x) (((x) >> S_TMPARTSIZE) & M_TMPARTSIZE)
2022 
2023 #define S_TMTYPE    26
2024 #define M_TMTYPE    0x3
2025 #define V_TMTYPE(x) ((x) << S_TMTYPE)
2026 #define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE)
2027 
2028 #define S_COMPEN    17
2029 #define V_COMPEN(x) ((x) << S_COMPEN)
2030 #define F_COMPEN    V_COMPEN(1U)
2031 
2032 #define S_PRTYEN    6
2033 #define V_PRTYEN(x) ((x) << S_PRTYEN)
2034 #define F_PRTYEN    V_PRTYEN(1U)
2035 
2036 #define S_MBUSEN    5
2037 #define V_MBUSEN(x) ((x) << S_MBUSEN)
2038 #define F_MBUSEN    V_MBUSEN(1U)
2039 
2040 #define S_DBGIEN    4
2041 #define V_DBGIEN(x) ((x) << S_DBGIEN)
2042 #define F_DBGIEN    V_DBGIEN(1U)
2043 
2044 #define S_TMRDY    2
2045 #define V_TMRDY(x) ((x) << S_TMRDY)
2046 #define F_TMRDY    V_TMRDY(1U)
2047 
2048 #define S_TMRST    1
2049 #define V_TMRST(x) ((x) << S_TMRST)
2050 #define F_TMRST    V_TMRST(1U)
2051 
2052 #define S_TMMODE    0
2053 #define V_TMMODE(x) ((x) << S_TMMODE)
2054 #define F_TMMODE    V_TMMODE(1U)
2055 
2056 #define F_TMMODE    V_TMMODE(1U)
2057 
2058 #define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c
2059 
2060 #define A_MC5_DB_FILTER_TABLE 0x710
2061 
2062 #define A_MC5_DB_SERVER_INDEX 0x714
2063 
2064 #define A_MC5_DB_RSP_LATENCY 0x720
2065 
2066 #define S_RDLAT    16
2067 #define M_RDLAT    0x1f
2068 #define V_RDLAT(x) ((x) << S_RDLAT)
2069 
2070 #define S_LRNLAT    8
2071 #define M_LRNLAT    0x1f
2072 #define V_LRNLAT(x) ((x) << S_LRNLAT)
2073 
2074 #define S_SRCHLAT    0
2075 #define M_SRCHLAT    0x1f
2076 #define V_SRCHLAT(x) ((x) << S_SRCHLAT)
2077 
2078 #define A_MC5_DB_PART_ID_INDEX 0x72c
2079 
2080 #define A_MC5_DB_INT_ENABLE 0x740
2081 
2082 #define S_DELACTEMPTY    18
2083 #define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY)
2084 #define F_DELACTEMPTY    V_DELACTEMPTY(1U)
2085 
2086 #define S_DISPQPARERR    17
2087 #define V_DISPQPARERR(x) ((x) << S_DISPQPARERR)
2088 #define F_DISPQPARERR    V_DISPQPARERR(1U)
2089 
2090 #define S_REQQPARERR    16
2091 #define V_REQQPARERR(x) ((x) << S_REQQPARERR)
2092 #define F_REQQPARERR    V_REQQPARERR(1U)
2093 
2094 #define S_UNKNOWNCMD    15
2095 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
2096 #define F_UNKNOWNCMD    V_UNKNOWNCMD(1U)
2097 
2098 #define S_NFASRCHFAIL    8
2099 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
2100 #define F_NFASRCHFAIL    V_NFASRCHFAIL(1U)
2101 
2102 #define S_ACTRGNFULL    7
2103 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
2104 #define F_ACTRGNFULL    V_ACTRGNFULL(1U)
2105 
2106 #define S_PARITYERR    6
2107 #define V_PARITYERR(x) ((x) << S_PARITYERR)
2108 #define F_PARITYERR    V_PARITYERR(1U)
2109 
2110 #define A_MC5_DB_INT_CAUSE 0x744
2111 
2112 #define A_MC5_DB_DBGI_CONFIG 0x774
2113 
2114 #define A_MC5_DB_DBGI_REQ_CMD 0x778
2115 
2116 #define A_MC5_DB_DBGI_REQ_ADDR0 0x77c
2117 
2118 #define A_MC5_DB_DBGI_REQ_ADDR1 0x780
2119 
2120 #define A_MC5_DB_DBGI_REQ_ADDR2 0x784
2121 
2122 #define A_MC5_DB_DBGI_REQ_DATA0 0x788
2123 
2124 #define A_MC5_DB_DBGI_REQ_DATA1 0x78c
2125 
2126 #define A_MC5_DB_DBGI_REQ_DATA2 0x790
2127 
2128 #define A_MC5_DB_DBGI_RSP_STATUS 0x7b0
2129 
2130 #define S_DBGIRSPVALID    0
2131 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
2132 #define F_DBGIRSPVALID    V_DBGIRSPVALID(1U)
2133 
2134 #define A_MC5_DB_DBGI_RSP_DATA0 0x7b4
2135 
2136 #define A_MC5_DB_DBGI_RSP_DATA1 0x7b8
2137 
2138 #define A_MC5_DB_DBGI_RSP_DATA2 0x7bc
2139 
2140 #define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc
2141 
2142 #define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0
2143 
2144 #define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4
2145 
2146 #define A_MC5_DB_AOPEN_LRN_CMD 0x7d8
2147 
2148 #define A_MC5_DB_SYN_SRCH_CMD 0x7dc
2149 
2150 #define A_MC5_DB_SYN_LRN_CMD 0x7e0
2151 
2152 #define A_MC5_DB_ACK_SRCH_CMD 0x7e4
2153 
2154 #define A_MC5_DB_ACK_LRN_CMD 0x7e8
2155 
2156 #define A_MC5_DB_ILOOKUP_CMD 0x7ec
2157 
2158 #define A_MC5_DB_ELOOKUP_CMD 0x7f0
2159 
2160 #define A_MC5_DB_DATA_WRITE_CMD 0x7f4
2161 
2162 #define A_MC5_DB_DATA_READ_CMD 0x7f8
2163 
2164 #define XGMAC0_0_BASE_ADDR 0x800
2165 
2166 #define A_XGM_TX_CTRL 0x800
2167 
2168 #define S_TXEN    0
2169 #define V_TXEN(x) ((x) << S_TXEN)
2170 #define F_TXEN    V_TXEN(1U)
2171 
2172 #define A_XGM_TX_CFG 0x804
2173 
2174 #define S_TXPAUSEEN    0
2175 #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
2176 #define F_TXPAUSEEN    V_TXPAUSEEN(1U)
2177 
2178 #define A_XGM_TX_PAUSE_QUANTA 0x808
2179 
2180 #define A_XGM_RX_CTRL 0x80c
2181 
2182 #define S_RXEN    0
2183 #define V_RXEN(x) ((x) << S_RXEN)
2184 #define F_RXEN    V_RXEN(1U)
2185 
2186 #define A_XGM_RX_CFG 0x810
2187 
2188 #define S_DISPAUSEFRAMES    9
2189 #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
2190 #define F_DISPAUSEFRAMES    V_DISPAUSEFRAMES(1U)
2191 
2192 #define S_EN1536BFRAMES    8
2193 #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
2194 #define F_EN1536BFRAMES    V_EN1536BFRAMES(1U)
2195 
2196 #define S_ENJUMBO    7
2197 #define V_ENJUMBO(x) ((x) << S_ENJUMBO)
2198 #define F_ENJUMBO    V_ENJUMBO(1U)
2199 
2200 #define S_RMFCS    6
2201 #define V_RMFCS(x) ((x) << S_RMFCS)
2202 #define F_RMFCS    V_RMFCS(1U)
2203 
2204 #define S_ENHASHMCAST    2
2205 #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
2206 #define F_ENHASHMCAST    V_ENHASHMCAST(1U)
2207 
2208 #define S_COPYALLFRAMES    0
2209 #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
2210 #define F_COPYALLFRAMES    V_COPYALLFRAMES(1U)
2211 
2212 #define S_DISBCAST    1
2213 #define V_DISBCAST(x) ((x) << S_DISBCAST)
2214 #define F_DISBCAST    V_DISBCAST(1U)
2215 
2216 #define A_XGM_RX_HASH_LOW 0x814
2217 
2218 #define A_XGM_RX_HASH_HIGH 0x818
2219 
2220 #define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c
2221 
2222 #define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820
2223 
2224 #define A_XGM_RX_EXACT_MATCH_LOW_2 0x824
2225 
2226 #define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c
2227 
2228 #define A_XGM_RX_EXACT_MATCH_LOW_4 0x834
2229 
2230 #define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c
2231 
2232 #define A_XGM_RX_EXACT_MATCH_LOW_6 0x844
2233 
2234 #define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c
2235 
2236 #define A_XGM_RX_EXACT_MATCH_LOW_8 0x854
2237 
2238 #define A_XGM_INT_STATUS 0x86c
2239 
2240 #define S_LINKFAULTCHANGE    9
2241 #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE)
2242 #define F_LINKFAULTCHANGE    V_LINKFAULTCHANGE(1U)
2243 
2244 #define A_XGM_XGM_INT_ENABLE 0x874
2245 #define A_XGM_XGM_INT_DISABLE 0x878
2246 
2247 #define A_XGM_STAT_CTRL 0x880
2248 
2249 #define S_CLRSTATS    2
2250 #define V_CLRSTATS(x) ((x) << S_CLRSTATS)
2251 #define F_CLRSTATS    V_CLRSTATS(1U)
2252 
2253 #define A_XGM_RXFIFO_CFG 0x884
2254 
2255 #define S_RXFIFO_EMPTY    31
2256 #define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY)
2257 #define F_RXFIFO_EMPTY    V_RXFIFO_EMPTY(1U)
2258 
2259 #define S_RXFIFOPAUSEHWM    17
2260 #define M_RXFIFOPAUSEHWM    0xfff
2261 
2262 #define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM)
2263 
2264 #define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM)
2265 
2266 #define S_RXFIFOPAUSELWM    5
2267 #define M_RXFIFOPAUSELWM    0xfff
2268 
2269 #define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM)
2270 
2271 #define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM)
2272 
2273 #define S_RXSTRFRWRD    1
2274 #define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD)
2275 #define F_RXSTRFRWRD    V_RXSTRFRWRD(1U)
2276 
2277 #define S_DISERRFRAMES    0
2278 #define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES)
2279 #define F_DISERRFRAMES    V_DISERRFRAMES(1U)
2280 
2281 #define A_XGM_TXFIFO_CFG 0x888
2282 
2283 #define S_UNDERUNFIX    22
2284 #define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX)
2285 #define F_UNDERUNFIX    V_UNDERUNFIX(1U)
2286 
2287 #define S_TXIPG    13
2288 #define M_TXIPG    0xff
2289 #define V_TXIPG(x) ((x) << S_TXIPG)
2290 #define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
2291 
2292 #define S_TXFIFOTHRESH    4
2293 #define M_TXFIFOTHRESH    0x1ff
2294 
2295 #define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH)
2296 
2297 #define S_ENDROPPKT    21
2298 #define V_ENDROPPKT(x) ((x) << S_ENDROPPKT)
2299 #define F_ENDROPPKT    V_ENDROPPKT(1U)
2300 
2301 #define A_XGM_SERDES_CTRL 0x890
2302 #define A_XGM_SERDES_CTRL0 0x8e0
2303 
2304 #define S_SERDESRESET_    24
2305 #define V_SERDESRESET_(x) ((x) << S_SERDESRESET_)
2306 #define F_SERDESRESET_    V_SERDESRESET_(1U)
2307 
2308 #define S_RXENABLE    4
2309 #define V_RXENABLE(x) ((x) << S_RXENABLE)
2310 #define F_RXENABLE    V_RXENABLE(1U)
2311 
2312 #define S_TXENABLE    3
2313 #define V_TXENABLE(x) ((x) << S_TXENABLE)
2314 #define F_TXENABLE    V_TXENABLE(1U)
2315 
2316 #define A_XGM_PAUSE_TIMER 0x890
2317 
2318 #define A_XGM_RGMII_IMP 0x89c
2319 
2320 #define S_XGM_IMPSETUPDATE    6
2321 #define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE)
2322 #define F_XGM_IMPSETUPDATE    V_XGM_IMPSETUPDATE(1U)
2323 
2324 #define S_RGMIIIMPPD    3
2325 #define M_RGMIIIMPPD    0x7
2326 #define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD)
2327 
2328 #define S_RGMIIIMPPU    0
2329 #define M_RGMIIIMPPU    0x7
2330 #define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU)
2331 
2332 #define S_CALRESET    8
2333 #define V_CALRESET(x) ((x) << S_CALRESET)
2334 #define F_CALRESET    V_CALRESET(1U)
2335 
2336 #define S_CALUPDATE    7
2337 #define V_CALUPDATE(x) ((x) << S_CALUPDATE)
2338 #define F_CALUPDATE    V_CALUPDATE(1U)
2339 
2340 #define A_XGM_XAUI_IMP 0x8a0
2341 
2342 #define S_CALBUSY    31
2343 #define V_CALBUSY(x) ((x) << S_CALBUSY)
2344 #define F_CALBUSY    V_CALBUSY(1U)
2345 
2346 #define S_XGM_CALFAULT    29
2347 #define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT)
2348 #define F_XGM_CALFAULT    V_XGM_CALFAULT(1U)
2349 
2350 #define S_CALIMP    24
2351 #define M_CALIMP    0x1f
2352 #define V_CALIMP(x) ((x) << S_CALIMP)
2353 #define G_CALIMP(x) (((x) >> S_CALIMP) & M_CALIMP)
2354 
2355 #define S_XAUIIMP    0
2356 #define M_XAUIIMP    0x7
2357 #define V_XAUIIMP(x) ((x) << S_XAUIIMP)
2358 
2359 #define A_XGM_RX_MAX_PKT_SIZE 0x8a8
2360 
2361 #define S_RXMAXFRAMERSIZE    17
2362 #define M_RXMAXFRAMERSIZE    0x3fff
2363 #define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE)
2364 #define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE)
2365 
2366 #define S_RXENFRAMER    14
2367 #define V_RXENFRAMER(x) ((x) << S_RXENFRAMER)
2368 #define F_RXENFRAMER    V_RXENFRAMER(1U)
2369 
2370 #define S_RXMAXPKTSIZE    0
2371 #define M_RXMAXPKTSIZE    0x3fff
2372 #define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE)
2373 #define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE)
2374 
2375 #define A_XGM_RESET_CTRL 0x8ac
2376 
2377 #define S_XGMAC_STOP_EN    4
2378 #define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN)
2379 #define F_XGMAC_STOP_EN    V_XGMAC_STOP_EN(1U)
2380 
2381 #define S_XG2G_RESET_    3
2382 #define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_)
2383 #define F_XG2G_RESET_    V_XG2G_RESET_(1U)
2384 
2385 #define S_RGMII_RESET_    2
2386 #define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_)
2387 #define F_RGMII_RESET_    V_RGMII_RESET_(1U)
2388 
2389 #define S_PCS_RESET_    1
2390 #define V_PCS_RESET_(x) ((x) << S_PCS_RESET_)
2391 #define F_PCS_RESET_    V_PCS_RESET_(1U)
2392 
2393 #define S_MAC_RESET_    0
2394 #define V_MAC_RESET_(x) ((x) << S_MAC_RESET_)
2395 #define F_MAC_RESET_    V_MAC_RESET_(1U)
2396 
2397 #define A_XGM_PORT_CFG 0x8b8
2398 
2399 #define S_CLKDIVRESET_    3
2400 #define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_)
2401 #define F_CLKDIVRESET_    V_CLKDIVRESET_(1U)
2402 
2403 #define S_PORTSPEED    1
2404 #define M_PORTSPEED    0x3
2405 
2406 #define V_PORTSPEED(x) ((x) << S_PORTSPEED)
2407 
2408 #define S_ENRGMII    0
2409 #define V_ENRGMII(x) ((x) << S_ENRGMII)
2410 #define F_ENRGMII    V_ENRGMII(1U)
2411 
2412 #define A_XGM_INT_ENABLE 0x8d4
2413 
2414 #define S_TXFIFO_PRTY_ERR    17
2415 #define M_TXFIFO_PRTY_ERR    0x7
2416 
2417 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
2418 
2419 #define S_RXFIFO_PRTY_ERR    14
2420 #define M_RXFIFO_PRTY_ERR    0x7
2421 
2422 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
2423 
2424 #define S_TXFIFO_UNDERRUN    13
2425 #define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN)
2426 #define F_TXFIFO_UNDERRUN    V_TXFIFO_UNDERRUN(1U)
2427 
2428 #define S_RXFIFO_OVERFLOW    12
2429 #define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW)
2430 #define F_RXFIFO_OVERFLOW    V_RXFIFO_OVERFLOW(1U)
2431 
2432 #define S_SERDES_LOS    4
2433 #define M_SERDES_LOS    0xf
2434 
2435 #define V_SERDES_LOS(x) ((x) << S_SERDES_LOS)
2436 
2437 #define S_XAUIPCSCTCERR    3
2438 #define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR)
2439 #define F_XAUIPCSCTCERR    V_XAUIPCSCTCERR(1U)
2440 
2441 #define S_XAUIPCSALIGNCHANGE    2
2442 #define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE)
2443 #define F_XAUIPCSALIGNCHANGE    V_XAUIPCSALIGNCHANGE(1U)
2444 
2445 #define S_XGM_INT    0
2446 #define V_XGM_INT(x) ((x) << S_XGM_INT)
2447 #define F_XGM_INT    V_XGM_INT(1U)
2448 
2449 #define A_XGM_INT_CAUSE 0x8d8
2450 
2451 #define A_XGM_XAUI_ACT_CTRL 0x8dc
2452 
2453 #define S_TXACTENABLE    1
2454 #define V_TXACTENABLE(x) ((x) << S_TXACTENABLE)
2455 #define F_TXACTENABLE    V_TXACTENABLE(1U)
2456 
2457 #define A_XGM_SERDES_CTRL0 0x8e0
2458 
2459 #define S_RESET3    23
2460 #define V_RESET3(x) ((x) << S_RESET3)
2461 #define F_RESET3    V_RESET3(1U)
2462 
2463 #define S_RESET2    22
2464 #define V_RESET2(x) ((x) << S_RESET2)
2465 #define F_RESET2    V_RESET2(1U)
2466 
2467 #define S_RESET1    21
2468 #define V_RESET1(x) ((x) << S_RESET1)
2469 #define F_RESET1    V_RESET1(1U)
2470 
2471 #define S_RESET0    20
2472 #define V_RESET0(x) ((x) << S_RESET0)
2473 #define F_RESET0    V_RESET0(1U)
2474 
2475 #define S_PWRDN3    19
2476 #define V_PWRDN3(x) ((x) << S_PWRDN3)
2477 #define F_PWRDN3    V_PWRDN3(1U)
2478 
2479 #define S_PWRDN2    18
2480 #define V_PWRDN2(x) ((x) << S_PWRDN2)
2481 #define F_PWRDN2    V_PWRDN2(1U)
2482 
2483 #define S_PWRDN1    17
2484 #define V_PWRDN1(x) ((x) << S_PWRDN1)
2485 #define F_PWRDN1    V_PWRDN1(1U)
2486 
2487 #define S_PWRDN0    16
2488 #define V_PWRDN0(x) ((x) << S_PWRDN0)
2489 #define F_PWRDN0    V_PWRDN0(1U)
2490 
2491 #define S_RESETPLL23    15
2492 #define V_RESETPLL23(x) ((x) << S_RESETPLL23)
2493 #define F_RESETPLL23    V_RESETPLL23(1U)
2494 
2495 #define S_RESETPLL01    14
2496 #define V_RESETPLL01(x) ((x) << S_RESETPLL01)
2497 #define F_RESETPLL01    V_RESETPLL01(1U)
2498 
2499 #define A_XGM_SERDES_STAT0 0x8f0
2500 #define A_XGM_SERDES_STAT1 0x8f4
2501 #define A_XGM_SERDES_STAT2 0x8f8
2502 
2503 #define S_LOWSIG0    0
2504 #define V_LOWSIG0(x) ((x) << S_LOWSIG0)
2505 #define F_LOWSIG0    V_LOWSIG0(1U)
2506 
2507 #define A_XGM_SERDES_STAT3 0x8fc
2508 
2509 #define A_XGM_STAT_TX_BYTE_LOW 0x900
2510 
2511 #define A_XGM_STAT_TX_BYTE_HIGH 0x904
2512 
2513 #define A_XGM_STAT_TX_FRAME_LOW 0x908
2514 
2515 #define A_XGM_STAT_TX_FRAME_HIGH 0x90c
2516 
2517 #define A_XGM_STAT_TX_BCAST 0x910
2518 
2519 #define A_XGM_STAT_TX_MCAST 0x914
2520 
2521 #define A_XGM_STAT_TX_PAUSE 0x918
2522 
2523 #define A_XGM_STAT_TX_64B_FRAMES 0x91c
2524 
2525 #define A_XGM_STAT_TX_65_127B_FRAMES 0x920
2526 
2527 #define A_XGM_STAT_TX_128_255B_FRAMES 0x924
2528 
2529 #define A_XGM_STAT_TX_256_511B_FRAMES 0x928
2530 
2531 #define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c
2532 
2533 #define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930
2534 
2535 #define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934
2536 
2537 #define A_XGM_STAT_TX_ERR_FRAMES 0x938
2538 
2539 #define A_XGM_STAT_RX_BYTES_LOW 0x93c
2540 
2541 #define A_XGM_STAT_RX_BYTES_HIGH 0x940
2542 
2543 #define A_XGM_STAT_RX_FRAMES_LOW 0x944
2544 
2545 #define A_XGM_STAT_RX_FRAMES_HIGH 0x948
2546 
2547 #define A_XGM_STAT_RX_BCAST_FRAMES 0x94c
2548 
2549 #define A_XGM_STAT_RX_MCAST_FRAMES 0x950
2550 
2551 #define A_XGM_STAT_RX_PAUSE_FRAMES 0x954
2552 
2553 #define A_XGM_STAT_RX_64B_FRAMES 0x958
2554 
2555 #define A_XGM_STAT_RX_65_127B_FRAMES 0x95c
2556 
2557 #define A_XGM_STAT_RX_128_255B_FRAMES 0x960
2558 
2559 #define A_XGM_STAT_RX_256_511B_FRAMES 0x964
2560 
2561 #define A_XGM_STAT_RX_512_1023B_FRAMES 0x968
2562 
2563 #define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c
2564 
2565 #define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970
2566 
2567 #define A_XGM_STAT_RX_SHORT_FRAMES 0x974
2568 
2569 #define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978
2570 
2571 #define A_XGM_STAT_RX_JABBER_FRAMES 0x97c
2572 
2573 #define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980
2574 
2575 #define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984
2576 
2577 #define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988
2578 
2579 #define A_XGM_SERDES_STATUS0 0x98c
2580 
2581 #define A_XGM_SERDES_STATUS1 0x990
2582 
2583 #define S_CMULOCK    31
2584 #define V_CMULOCK(x) ((x) << S_CMULOCK)
2585 #define F_CMULOCK    V_CMULOCK(1U)
2586 
2587 #define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
2588 
2589 #define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8
2590 
2591 #define S_TXSPI4SOPCNT    16
2592 #define M_TXSPI4SOPCNT    0xffff
2593 #define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
2594 #define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
2595 
2596 #define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac
2597 
2598 #define XGMAC0_1_BASE_ADDR 0xa00
2599