1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #ifndef __INTEL_UNCORE_H__
26 #define __INTEL_UNCORE_H__
27
28 #include <linux/spinlock.h>
29 #include <linux/notifier.h>
30 #include <linux/hrtimer.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32 #include <linux/types.h>
33
34 #include "i915_reg_defs.h"
35
36 struct drm_device;
37 struct drm_i915_private;
38 struct intel_runtime_pm;
39 struct intel_uncore;
40 struct intel_gt;
41
42 struct intel_uncore_mmio_debug {
43 spinlock_t lock; /** lock is also taken in irq contexts. */
44 int unclaimed_mmio_check;
45 int saved_mmio_check;
46 u32 suspend_count;
47 };
48
49 enum forcewake_domain_id {
50 FW_DOMAIN_ID_RENDER = 0,
51 FW_DOMAIN_ID_GT, /* also includes blitter engine */
52 FW_DOMAIN_ID_MEDIA,
53 FW_DOMAIN_ID_MEDIA_VDBOX0,
54 FW_DOMAIN_ID_MEDIA_VDBOX1,
55 FW_DOMAIN_ID_MEDIA_VDBOX2,
56 FW_DOMAIN_ID_MEDIA_VDBOX3,
57 FW_DOMAIN_ID_MEDIA_VDBOX4,
58 FW_DOMAIN_ID_MEDIA_VDBOX5,
59 FW_DOMAIN_ID_MEDIA_VDBOX6,
60 FW_DOMAIN_ID_MEDIA_VDBOX7,
61 FW_DOMAIN_ID_MEDIA_VEBOX0,
62 FW_DOMAIN_ID_MEDIA_VEBOX1,
63 FW_DOMAIN_ID_MEDIA_VEBOX2,
64 FW_DOMAIN_ID_MEDIA_VEBOX3,
65
66 FW_DOMAIN_ID_COUNT
67 };
68
69 enum forcewake_domains {
70 FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),
71 FORCEWAKE_GT = BIT(FW_DOMAIN_ID_GT),
72 FORCEWAKE_MEDIA = BIT(FW_DOMAIN_ID_MEDIA),
73 FORCEWAKE_MEDIA_VDBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
74 FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
75 FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
76 FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
77 FORCEWAKE_MEDIA_VDBOX4 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX4),
78 FORCEWAKE_MEDIA_VDBOX5 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX5),
79 FORCEWAKE_MEDIA_VDBOX6 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX6),
80 FORCEWAKE_MEDIA_VDBOX7 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX7),
81 FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
82 FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
83 FORCEWAKE_MEDIA_VEBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX2),
84 FORCEWAKE_MEDIA_VEBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX3),
85
86 FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1,
87 };
88
89 struct intel_uncore_fw_get {
90 void (*force_wake_get)(struct intel_uncore *uncore,
91 enum forcewake_domains domains);
92 };
93
94 struct intel_uncore_funcs {
95 enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore,
96 i915_reg_t r);
97 enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore,
98 i915_reg_t r);
99
100 u8 (*mmio_readb)(struct intel_uncore *uncore,
101 i915_reg_t r, bool trace);
102 u16 (*mmio_readw)(struct intel_uncore *uncore,
103 i915_reg_t r, bool trace);
104 u32 (*mmio_readl)(struct intel_uncore *uncore,
105 i915_reg_t r, bool trace);
106 u64 (*mmio_readq)(struct intel_uncore *uncore,
107 i915_reg_t r, bool trace);
108
109 void (*mmio_writeb)(struct intel_uncore *uncore,
110 i915_reg_t r, u8 val, bool trace);
111 void (*mmio_writew)(struct intel_uncore *uncore,
112 i915_reg_t r, u16 val, bool trace);
113 void (*mmio_writel)(struct intel_uncore *uncore,
114 i915_reg_t r, u32 val, bool trace);
115 };
116
117 struct intel_forcewake_range {
118 u32 start;
119 u32 end;
120
121 enum forcewake_domains domains;
122 };
123
124 /* Other register ranges (e.g., shadow tables, MCR tables, etc.) */
125 struct i915_range {
126 u32 start;
127 u32 end;
128 };
129
130 struct intel_uncore {
131 void __iomem *regs;
132
133 struct drm_i915_private *i915;
134 struct intel_gt *gt;
135 struct intel_runtime_pm *rpm;
136
137 spinlock_t lock; /** lock is also taken in irq contexts. */
138
139 /*
140 * Do we need to apply an additional offset to reach the beginning
141 * of the basic non-engine GT registers (referred to as "GSI" on
142 * newer platforms, or "GT block" on older platforms)? If so, we'll
143 * track that here and apply it transparently to registers in the
144 * appropriate range to maintain compatibility with our existing
145 * register definitions and GT code.
146 */
147 u32 gsi_offset;
148
149 unsigned int flags;
150 #define UNCORE_HAS_FORCEWAKE BIT(0)
151 #define UNCORE_HAS_FPGA_DBG_UNCLAIMED BIT(1)
152 #define UNCORE_HAS_DBG_UNCLAIMED BIT(2)
153 #define UNCORE_HAS_FIFO BIT(3)
154
155 const struct intel_forcewake_range *fw_domains_table;
156 unsigned int fw_domains_table_entries;
157
158 /*
159 * Shadowed registers are special cases where we can safely write
160 * to the register *without* grabbing forcewake.
161 */
162 const struct i915_range *shadowed_reg_table;
163 unsigned int shadowed_reg_table_entries;
164
165 struct notifier_block pmic_bus_access_nb;
166 const struct intel_uncore_fw_get *fw_get_funcs;
167 struct intel_uncore_funcs funcs;
168
169 unsigned int fifo_count;
170
171 enum forcewake_domains fw_domains;
172 enum forcewake_domains fw_domains_active;
173 enum forcewake_domains fw_domains_timer;
174 enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
175
176 struct intel_uncore_forcewake_domain {
177 struct intel_uncore *uncore;
178 enum forcewake_domain_id id;
179 enum forcewake_domains mask;
180 unsigned int wake_count;
181 bool active;
182 struct hrtimer timer;
183 u32 __iomem *reg_set;
184 u32 __iomem *reg_ack;
185 } *fw_domain[FW_DOMAIN_ID_COUNT];
186
187 unsigned int user_forcewake_count;
188
189 struct intel_uncore_mmio_debug *debug;
190 };
191
192 /* Iterate over initialised fw domains */
193 #define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \
194 for (tmp__ = (mask__); tmp__ ;) \
195 for_each_if(domain__ = (uncore__)->fw_domain[__mask_next_bit(tmp__)])
196
197 #define for_each_fw_domain(domain__, uncore__, tmp__) \
198 for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__)
199
200 static inline bool
intel_uncore_has_forcewake(const struct intel_uncore * uncore)201 intel_uncore_has_forcewake(const struct intel_uncore *uncore)
202 {
203 return uncore->flags & UNCORE_HAS_FORCEWAKE;
204 }
205
206 static inline bool
intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore * uncore)207 intel_uncore_has_fpga_dbg_unclaimed(const struct intel_uncore *uncore)
208 {
209 return uncore->flags & UNCORE_HAS_FPGA_DBG_UNCLAIMED;
210 }
211
212 static inline bool
intel_uncore_has_dbg_unclaimed(const struct intel_uncore * uncore)213 intel_uncore_has_dbg_unclaimed(const struct intel_uncore *uncore)
214 {
215 return uncore->flags & UNCORE_HAS_DBG_UNCLAIMED;
216 }
217
218 static inline bool
intel_uncore_has_fifo(const struct intel_uncore * uncore)219 intel_uncore_has_fifo(const struct intel_uncore *uncore)
220 {
221 return uncore->flags & UNCORE_HAS_FIFO;
222 }
223
224 void intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915);
225 void intel_uncore_init_early(struct intel_uncore *uncore,
226 struct intel_gt *gt);
227 int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr);
228 int intel_uncore_init_mmio(struct intel_uncore *uncore);
229 void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
230 struct intel_gt *gt);
231 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
232 bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore);
233 void intel_uncore_cleanup_mmio(struct intel_uncore *uncore);
234 void intel_uncore_fini_mmio(struct drm_device *dev, void *data);
235 void intel_uncore_suspend(struct intel_uncore *uncore);
236 void intel_uncore_resume_early(struct intel_uncore *uncore);
237 void intel_uncore_runtime_resume(struct intel_uncore *uncore);
238
239 void assert_forcewakes_inactive(struct intel_uncore *uncore);
240 void assert_forcewakes_active(struct intel_uncore *uncore,
241 enum forcewake_domains fw_domains);
242 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
243
244 enum forcewake_domains
245 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore,
246 i915_reg_t reg, unsigned int op);
247 #define FW_REG_READ (1)
248 #define FW_REG_WRITE (2)
249
250 void intel_uncore_forcewake_get(struct intel_uncore *uncore,
251 enum forcewake_domains domains);
252 void intel_uncore_forcewake_put(struct intel_uncore *uncore,
253 enum forcewake_domains domains);
254 void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
255 enum forcewake_domains domains);
256 void intel_uncore_forcewake_flush(struct intel_uncore *uncore,
257 enum forcewake_domains fw_domains);
258
259 /*
260 * Like above but the caller must manage the uncore.lock itself.
261 * Must be used with intel_uncore_read_fw() and friends.
262 */
263 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,
264 enum forcewake_domains domains);
265 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,
266 enum forcewake_domains domains);
267
268 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore);
269 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore);
270
271 int __intel_wait_for_register(struct intel_uncore *uncore,
272 i915_reg_t reg,
273 u32 mask,
274 u32 value,
275 unsigned int fast_timeout_us,
276 unsigned int slow_timeout_ms,
277 u32 *out_value);
278 static inline int
intel_wait_for_register(struct intel_uncore * uncore,i915_reg_t reg,u32 mask,u32 value,unsigned int timeout_ms)279 intel_wait_for_register(struct intel_uncore *uncore,
280 i915_reg_t reg,
281 u32 mask,
282 u32 value,
283 unsigned int timeout_ms)
284 {
285 return __intel_wait_for_register(uncore, reg, mask, value, 2,
286 timeout_ms, NULL);
287 }
288
289 int __intel_wait_for_register_fw(struct intel_uncore *uncore,
290 i915_reg_t reg,
291 u32 mask,
292 u32 value,
293 unsigned int fast_timeout_us,
294 unsigned int slow_timeout_ms,
295 u32 *out_value);
296 static inline int
intel_wait_for_register_fw(struct intel_uncore * uncore,i915_reg_t reg,u32 mask,u32 value,unsigned int timeout_ms)297 intel_wait_for_register_fw(struct intel_uncore *uncore,
298 i915_reg_t reg,
299 u32 mask,
300 u32 value,
301 unsigned int timeout_ms)
302 {
303 return __intel_wait_for_register_fw(uncore, reg, mask, value,
304 2, timeout_ms, NULL);
305 }
306
307 #define IS_GSI_REG(reg) ((reg) < 0x40000)
308
309 /* register access functions */
310 #define __raw_read(x__, s__) \
311 static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
312 i915_reg_t reg) \
313 { \
314 u32 offset = i915_mmio_reg_offset(reg); \
315 if (IS_GSI_REG(offset)) \
316 offset += uncore->gsi_offset; \
317 return read##s__(uncore->regs + offset); \
318 }
319
320 #define __raw_write(x__, s__) \
321 static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
322 i915_reg_t reg, u##x__ val) \
323 { \
324 u32 offset = i915_mmio_reg_offset(reg); \
325 if (IS_GSI_REG(offset)) \
326 offset += uncore->gsi_offset; \
327 write##s__(val, uncore->regs + offset); \
328 }
329 __raw_read(8, b)
330 __raw_read(16, w)
331 __raw_read(32, l)
332 __raw_read(64, q)
333
334 __raw_write(8, b)
335 __raw_write(16, w)
336 __raw_write(32, l)
337 __raw_write(64, q)
338
339 #undef __raw_read
340 #undef __raw_write
341
342 #define __uncore_read(name__, x__, s__, trace__) \
343 static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
344 i915_reg_t reg) \
345 { \
346 return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \
347 }
348
349 #define __uncore_write(name__, x__, s__, trace__) \
350 static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
351 i915_reg_t reg, u##x__ val) \
352 { \
353 uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \
354 }
355
356 __uncore_read(read8, 8, b, true)
357 __uncore_read(read16, 16, w, true)
358 __uncore_read(read, 32, l, true)
359 __uncore_read(read16_notrace, 16, w, false)
360 __uncore_read(read_notrace, 32, l, false)
361
362 __uncore_write(write8, 8, b, true)
363 __uncore_write(write16, 16, w, true)
364 __uncore_write(write, 32, l, true)
365 __uncore_write(write_notrace, 32, l, false)
366
367 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
368 * will be implemented using 2 32-bit writes in an arbitrary order with
369 * an arbitrary delay between them. This can cause the hardware to
370 * act upon the intermediate value, possibly leading to corruption and
371 * machine death. For this reason we do not support intel_uncore_write64,
372 * or uncore->funcs.mmio_writeq.
373 *
374 * When reading a 64-bit value as two 32-bit values, the delay may cause
375 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
376 * occasionally a 64-bit register does not actually support a full readq
377 * and must be read using two 32-bit reads.
378 *
379 * You have been warned.
380 */
381 __uncore_read(read64, 64, q, true)
382
383 static inline u64
intel_uncore_read64_2x32(struct intel_uncore * uncore,i915_reg_t lower_reg,i915_reg_t upper_reg)384 intel_uncore_read64_2x32(struct intel_uncore *uncore,
385 i915_reg_t lower_reg, i915_reg_t upper_reg)
386 {
387 u32 upper, lower, old_upper, loop = 0;
388 upper = intel_uncore_read(uncore, upper_reg);
389 do {
390 old_upper = upper;
391 lower = intel_uncore_read(uncore, lower_reg);
392 upper = intel_uncore_read(uncore, upper_reg);
393 } while (upper != old_upper && loop++ < 2);
394 return (u64)upper << 32 | lower;
395 }
396
397 #define intel_uncore_posting_read(...) ((void)intel_uncore_read_notrace(__VA_ARGS__))
398 #define intel_uncore_posting_read16(...) ((void)intel_uncore_read16_notrace(__VA_ARGS__))
399
400 #undef __uncore_read
401 #undef __uncore_write
402
403 /* These are untraced mmio-accessors that are only valid to be used inside
404 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
405 * controlled.
406 *
407 * Think twice, and think again, before using these.
408 *
409 * As an example, these accessors can possibly be used between:
410 *
411 * spin_lock_irq(&uncore->lock);
412 * intel_uncore_forcewake_get__locked();
413 *
414 * and
415 *
416 * intel_uncore_forcewake_put__locked();
417 * spin_unlock_irq(&uncore->lock);
418 *
419 *
420 * Note: some registers may not need forcewake held, so
421 * intel_uncore_forcewake_{get,put} can be omitted, see
422 * intel_uncore_forcewake_for_reg().
423 *
424 * Certain architectures will die if the same cacheline is concurrently accessed
425 * by different clients (e.g. on Ivybridge). Access to registers should
426 * therefore generally be serialised, by either the dev_priv->uncore.lock or
427 * a more localised lock guarding all access to that bank of registers.
428 */
429 #define intel_uncore_read_fw(...) __raw_uncore_read32(__VA_ARGS__)
430 #define intel_uncore_write_fw(...) __raw_uncore_write32(__VA_ARGS__)
431 #define intel_uncore_write64_fw(...) __raw_uncore_write64(__VA_ARGS__)
432 #define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__))
433
intel_uncore_rmw(struct intel_uncore * uncore,i915_reg_t reg,u32 clear,u32 set)434 static inline void intel_uncore_rmw(struct intel_uncore *uncore,
435 i915_reg_t reg, u32 clear, u32 set)
436 {
437 u32 old, val;
438
439 old = intel_uncore_read(uncore, reg);
440 val = (old & ~clear) | set;
441 if (val != old)
442 intel_uncore_write(uncore, reg, val);
443 }
444
intel_uncore_rmw_fw(struct intel_uncore * uncore,i915_reg_t reg,u32 clear,u32 set)445 static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
446 i915_reg_t reg, u32 clear, u32 set)
447 {
448 u32 old, val;
449
450 old = intel_uncore_read_fw(uncore, reg);
451 val = (old & ~clear) | set;
452 if (val != old)
453 intel_uncore_write_fw(uncore, reg, val);
454 }
455
intel_uncore_write_and_verify(struct intel_uncore * uncore,i915_reg_t reg,u32 val,u32 mask,u32 expected_val)456 static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
457 i915_reg_t reg, u32 val,
458 u32 mask, u32 expected_val)
459 {
460 u32 reg_val;
461
462 intel_uncore_write(uncore, reg, val);
463 reg_val = intel_uncore_read(uncore, reg);
464
465 return (reg_val & mask) != expected_val ? -EINVAL : 0;
466 }
467
468 /*
469 * The raw_reg_{read,write} macros are intended as a micro-optimization for
470 * interrupt handlers so that the pointer indirection on uncore->regs can
471 * be computed once (and presumably cached in a register) instead of generating
472 * extra load instructions for each MMIO access.
473 *
474 * Given that these macros are only intended for non-GSI interrupt registers
475 * (and the goal is to avoid extra instructions generated by the compiler),
476 * these macros do not account for uncore->gsi_offset. Any caller that needs
477 * to use these macros on a GSI register is responsible for adding the
478 * appropriate GSI offset to the 'base' parameter.
479 */
480 #define raw_reg_read(base, reg) \
481 readl(base + i915_mmio_reg_offset(reg))
482 #define raw_reg_write(base, reg, value) \
483 writel(value, base + i915_mmio_reg_offset(reg))
484
485 #endif /* !__INTEL_UNCORE_H__ */
486