1 /*
2 * NCR 5380 defines
3 *
4 * Copyright 1993, Drew Eckhardt
5 * Visionary Computing
6 * (Unix consulting and custom programming)
7 * drew@colorado.edu
8 * +1 (303) 666-5836
9 *
10 * DISTRIBUTION RELEASE 7
11 *
12 * For more information, please consult
13 *
14 * NCR 5380 Family
15 * SCSI Protocol Controller
16 * Databook
17 * NCR Microelectronics
18 * 1635 Aeroplaza Drive
19 * Colorado Springs, CO 80916
20 * 1+ (719) 578-3400
21 * 1+ (800) 334-5454
22 */
23
24 /*
25 * $Log: NCR5380.h,v $
26 */
27
28 #ifndef NCR5380_H
29 #define NCR5380_H
30
31 #define NCR5380_PUBLIC_RELEASE 7
32 #define NCR53C400_PUBLIC_RELEASE 2
33
34 #define NDEBUG_ARBITRATION 0x1
35 #define NDEBUG_AUTOSENSE 0x2
36 #define NDEBUG_DMA 0x4
37 #define NDEBUG_HANDSHAKE 0x8
38 #define NDEBUG_INFORMATION 0x10
39 #define NDEBUG_INIT 0x20
40 #define NDEBUG_INTR 0x40
41 #define NDEBUG_LINKED 0x80
42 #define NDEBUG_MAIN 0x100
43 #define NDEBUG_NO_DATAOUT 0x200
44 #define NDEBUG_NO_WRITE 0x400
45 #define NDEBUG_PIO 0x800
46 #define NDEBUG_PSEUDO_DMA 0x1000
47 #define NDEBUG_QUEUES 0x2000
48 #define NDEBUG_RESELECTION 0x4000
49 #define NDEBUG_SELECTION 0x8000
50 #define NDEBUG_USLEEP 0x10000
51 #define NDEBUG_LAST_BYTE_SENT 0x20000
52 #define NDEBUG_RESTART_SELECT 0x40000
53 #define NDEBUG_EXTENDED 0x80000
54 #define NDEBUG_C400_PREAD 0x100000
55 #define NDEBUG_C400_PWRITE 0x200000
56 #define NDEBUG_LISTS 0x400000
57
58 #define NDEBUG_ANY 0xFFFFFFFFUL
59
60 /*
61 * The contents of the OUTPUT DATA register are asserted on the bus when
62 * either arbitration is occurring or the phase-indicating signals (
63 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
64 * bit in the INITIATOR COMMAND register is set.
65 */
66
67 #define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
68 #define CURRENT_SCSI_DATA_REG 0 /* ro same */
69
70 #define INITIATOR_COMMAND_REG 1 /* rw */
71 #define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
72 #define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
73 #define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
74 #define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
75 #define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
76 #define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
77 #define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
78 #define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
79 #define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
80 #define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
81
82 #ifdef DIFFERENTIAL
83 #define ICR_BASE ICR_DIFF_ENABLE
84 #else
85 #define ICR_BASE 0
86 #endif
87
88 #define MODE_REG 2
89 /*
90 * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
91 * transfer, causing the chip to hog the bus. You probably don't want
92 * this.
93 */
94 #define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
95 #define MR_TARGET 0x40 /* rw target mode */
96 #define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
97 #define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
98 #define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
99 #define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
100 #define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
101 #define MR_ARBITRATE 0x01 /* rw start arbitration */
102
103 #ifdef PARITY
104 #define MR_BASE MR_ENABLE_PAR_CHECK
105 #else
106 #define MR_BASE 0
107 #endif
108
109 #define TARGET_COMMAND_REG 3
110 #define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
111 #define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
112 #define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
113 #define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
114 #define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
115
116 #define STATUS_REG 4 /* ro */
117 /*
118 * Note : a set bit indicates an active signal, driven by us or another
119 * device.
120 */
121 #define SR_RST 0x80
122 #define SR_BSY 0x40
123 #define SR_REQ 0x20
124 #define SR_MSG 0x10
125 #define SR_CD 0x08
126 #define SR_IO 0x04
127 #define SR_SEL 0x02
128 #define SR_DBP 0x01
129
130 /*
131 * Setting a bit in this register will cause an interrupt to be generated when
132 * BSY is false and SEL true and this bit is asserted on the bus.
133 */
134 #define SELECT_ENABLE_REG 4 /* wo */
135
136 #define BUS_AND_STATUS_REG 5 /* ro */
137 #define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
138 #define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
139 #define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
140 #define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
141 #define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
142 #define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
143 #define BASR_ATN 0x02 /* ro BUS status */
144 #define BASR_ACK 0x01 /* ro BUS status */
145
146 /* Write any value to this register to start a DMA send */
147 #define START_DMA_SEND_REG 5 /* wo */
148
149 /*
150 * Used in DMA transfer mode, data is latched from the SCSI bus on
151 * the falling edge of REQ (ini) or ACK (tgt)
152 */
153 #define INPUT_DATA_REG 6 /* ro */
154
155 /* Write any value to this register to start a DMA receive */
156 #define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
157
158 /* Read this register to clear interrupt conditions */
159 #define RESET_PARITY_INTERRUPT_REG 7 /* ro */
160
161 /* Write any value to this register to start an ini mode DMA receive */
162 #define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
163
164 #define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */
165
166 #define CSR_RESET 0x80 /* wo Resets 53c400 */
167 #define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
168 #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
169 #define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
170 #define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
171 #define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
172 #define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
173 #define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
174 #define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
175
176 #if 0
177 #define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
178 #else
179 #define CSR_BASE CSR_53C80_INTR
180 #endif
181
182 /* Number of 128-byte blocks to be transferred */
183 #define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */
184
185 /* Resume transfer after disconnect */
186 #define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */
187
188 /* Access to host buffer stack */
189 #define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */
190
191
192 /* Note : PHASE_* macros are based on the values of the STATUS register */
193 #define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
194
195 #define PHASE_DATAOUT 0
196 #define PHASE_DATAIN SR_IO
197 #define PHASE_CMDOUT SR_CD
198 #define PHASE_STATIN (SR_CD | SR_IO)
199 #define PHASE_MSGOUT (SR_MSG | SR_CD)
200 #define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
201 #define PHASE_UNKNOWN 0xff
202
203 /*
204 * Convert status register phase to something we can use to set phase in
205 * the target register so we can get phase mismatch interrupts on DMA
206 * transfers.
207 */
208
209 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
210
211 /*
212 * The internal should_disconnect() function returns these based on the
213 * expected length of a disconnect if a device supports disconnect/
214 * reconnect.
215 */
216
217 #define DISCONNECT_NONE 0
218 #define DISCONNECT_TIME_TO_DATA 1
219 #define DISCONNECT_LONG 2
220
221 /*
222 * These are "special" values for the tag parameter passed to NCR5380_select.
223 */
224
225 #define TAG_NEXT -1 /* Use next free tag */
226 #define TAG_NONE -2 /*
227 * Establish I_T_L nexus instead of I_T_L_Q
228 * even on SCSI-II devices.
229 */
230
231 /*
232 * These are "special" values for the irq and dma_channel fields of the
233 * Scsi_Host structure
234 */
235
236 #define SCSI_IRQ_NONE 255
237 #define DMA_NONE 255
238 #define IRQ_AUTO 254
239 #define DMA_AUTO 254
240 #define PORT_AUTO 0xffff /* autoprobe io port for 53c400a */
241
242 #define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */
243 #define FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */
244 #define FLAG_NCR53C400 4 /* NCR53c400 */
245 #define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
246 #define FLAG_DTC3181E 16 /* DTC3181E */
247
248 #ifndef ASM
249 struct NCR5380_hostdata {
250 NCR5380_implementation_fields; /* implementation specific */
251 unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */
252 unsigned char targets_present; /* targets we have connected
253 to, so we can call a select
254 failure a retryable condition */
255 volatile unsigned char busy[8]; /* index = target, bit = lun */
256 #if defined(REAL_DMA) || defined(REAL_DMA_POLL)
257 volatile int dma_len; /* requested length of DMA */
258 #endif
259 volatile unsigned char last_message; /* last message OUT */
260 volatile Scsi_Cmnd *connected; /* currently connected command */
261 volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */
262 volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
263 volatile int restart_select; /* we have disconnected,
264 used to restart
265 NCR5380_select() */
266 volatile unsigned aborted:1; /* flag, says aborted */
267 int flags;
268 unsigned long time_expires; /* in jiffies, set prior to sleeping */
269 struct Scsi_Host *next_timer;
270 int select_time; /* timer in select for target response */
271 volatile Scsi_Cmnd *selecting;
272 #ifdef NCR5380_STATS
273 unsigned timebase; /* Base for time calcs */
274 long time_read[8]; /* time to do reads */
275 long time_write[8]; /* time to do writes */
276 unsigned long bytes_read[8]; /* bytes read */
277 unsigned long bytes_write[8]; /* bytes written */
278 unsigned pendingr;
279 unsigned pendingw;
280 #endif
281 };
282
283 #ifdef __KERNEL__
284 static struct Scsi_Host *first_instance; /* linked list of 5380's */
285
286 #define dprintk(a,b) do {} while(0)
287 #define NCR5380_dprint(a,b) do {} while(0)
288 #define NCR5380_dprint_phase(a,b) do {} while(0)
289
290 #if defined(AUTOPROBE_IRQ)
291 static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
292 #endif
293 static void NCR5380_init(struct Scsi_Host *instance, int flags);
294 static void NCR5380_information_transfer(struct Scsi_Host *instance);
295 #ifndef DONT_USE_INTR
296 static void NCR5380_intr(int irq, void *dev_id, struct pt_regs *regs);
297 static void do_NCR5380_intr(int irq, void *dev_id, struct pt_regs *regs);
298 #endif
299 static void NCR5380_main(void);
300 static void NCR5380_print_options(struct Scsi_Host *instance);
301 static void NCR5380_print_phase(struct Scsi_Host *instance);
302 static void NCR5380_print(struct Scsi_Host *instance);
303 #ifndef NCR5380_abort
304 static
305 #endif
306 int NCR5380_abort(Scsi_Cmnd * cmd);
307 #ifndef NCR5380_reset
308 static
309 #endif
310 int NCR5380_reset(Scsi_Cmnd * cmd, unsigned int reset_flags);
311 #ifndef NCR5380_queue_command
312 static
313 #endif
314 int NCR5380_queue_command(Scsi_Cmnd * cmd, void (*done) (Scsi_Cmnd *));
315
316
317 static void NCR5380_reselect(struct Scsi_Host *instance);
318 static int NCR5380_select(struct Scsi_Host *instance, Scsi_Cmnd * cmd, int tag);
319 #if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
320 static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
321 #endif
322 static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
323
324 #if (defined(REAL_DMA) || defined(REAL_DMA_POLL))
325
326 #if defined(i386) || defined(__alpha__)
327
328 /**
329 * NCR5380_pc_dma_setup - setup ISA DMA
330 * @instance: adapter to set up
331 * @ptr: block to transfer (virtual address)
332 * @count: number of bytes to transfer
333 * @mode: DMA controller mode to use
334 *
335 * Program the DMA controller ready to perform an ISA DMA transfer
336 * on this chip.
337 *
338 * Locks: takes and releases the ISA DMA lock.
339 */
340
NCR5380_pc_dma_setup(struct Scsi_Host * instance,unsigned char * ptr,unsigned int count,unsigned char mode)341 static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host *instance, unsigned char *ptr, unsigned int count, unsigned char mode)
342 {
343 unsigned limit;
344 unsigned long bus_addr = virt_to_bus(ptr);
345 unsigned long flags;
346
347 if (instance->dma_channel <= 3) {
348 if (count > 65536)
349 count = 65536;
350 limit = 65536 - (bus_addr & 0xFFFF);
351 } else {
352 if (count > 65536 * 2)
353 count = 65536 * 2;
354 limit = 65536 * 2 - (bus_addr & 0x1FFFF);
355 }
356
357 if (count > limit)
358 count = limit;
359
360 if ((count & 1) || (bus_addr & 1))
361 panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
362
363 flags=claim_dma_lock();
364 disable_dma(instance->dma_channel);
365 clear_dma_ff(instance->dma_channel);
366 set_dma_addr(instance->dma_channel, bus_addr);
367 set_dma_count(instance->dma_channel, count);
368 set_dma_mode(instance->dma_channel, mode);
369 enable_dma(instance->dma_channel);
370 release_dma_lock(flags);
371
372 return count;
373 }
374
375 /**
376 * NCR5380_pc_dma_write_setup - setup ISA DMA write
377 * @instance: adapter to set up
378 * @ptr: block to transfer (virtual address)
379 * @count: number of bytes to transfer
380 *
381 * Program the DMA controller ready to perform an ISA DMA write to the
382 * SCSI controller.
383 *
384 * Locks: called routines take and release the ISA DMA lock.
385 */
386
NCR5380_pc_dma_write_setup(struct Scsi_Host * instance,unsigned char * src,unsigned int count)387 static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
388 {
389 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE);
390 }
391
392 /**
393 * NCR5380_pc_dma_read_setup - setup ISA DMA read
394 * @instance: adapter to set up
395 * @ptr: block to transfer (virtual address)
396 * @count: number of bytes to transfer
397 *
398 * Program the DMA controller ready to perform an ISA DMA read from the
399 * SCSI controller.
400 *
401 * Locks: called routines take and release the ISA DMA lock.
402 */
403
NCR5380_pc_dma_read_setup(struct Scsi_Host * instance,unsigned char * src,unsigned int count)404 static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
405 {
406 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ);
407 }
408
409 /**
410 * NCR5380_pc_dma_residual - return bytes left
411 * @instance: adapter
412 *
413 * Reports the number of bytes left over after the DMA was terminated.
414 *
415 * Locks: takes and releases the ISA DMA lock.
416 */
417
NCR5380_pc_dma_residual(struct Scsi_Host * instance)418 static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance)
419 {
420 unsigned long flags;
421 int tmp;
422
423 flags = claim_dma_lock();
424 clear_dma_ff(instance->dma_channel);
425 tmp = get_dma_residue(instance->dma_channel);
426 release_dma_lock(flags);
427
428 return tmp;
429 }
430 #endif /* defined(i386) || defined(__alpha__) */
431 #endif /* defined(REAL_DMA) */
432 #endif /* __KERNEL__ */
433 #endif /* ndef ASM */
434 #endif /* NCR5380_H */
435