1 /*******************************************************************************
2 
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2012 Intel Corporation.
5 
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9 
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14 
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21 
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 /* Linux PRO/1000 Ethernet Driver main header file */
30 
31 #ifndef _E1000_H_
32 #define _E1000_H_
33 
34 #include <linux/bitops.h>
35 #include <linux/types.h>
36 #include <linux/timer.h>
37 #include <linux/workqueue.h>
38 #include <linux/io.h>
39 #include <linux/netdevice.h>
40 #include <linux/pci.h>
41 #include <linux/pci-aspm.h>
42 #include <linux/crc32.h>
43 #include <linux/if_vlan.h>
44 
45 #include "hw.h"
46 
47 struct e1000_info;
48 
49 #define e_dbg(format, arg...) \
50 	netdev_dbg(hw->adapter->netdev, format, ## arg)
51 #define e_err(format, arg...) \
52 	netdev_err(adapter->netdev, format, ## arg)
53 #define e_info(format, arg...) \
54 	netdev_info(adapter->netdev, format, ## arg)
55 #define e_warn(format, arg...) \
56 	netdev_warn(adapter->netdev, format, ## arg)
57 #define e_notice(format, arg...) \
58 	netdev_notice(adapter->netdev, format, ## arg)
59 
60 
61 /* Interrupt modes, as used by the IntMode parameter */
62 #define E1000E_INT_MODE_LEGACY		0
63 #define E1000E_INT_MODE_MSI		1
64 #define E1000E_INT_MODE_MSIX		2
65 
66 /* Tx/Rx descriptor defines */
67 #define E1000_DEFAULT_TXD		256
68 #define E1000_MAX_TXD			4096
69 #define E1000_MIN_TXD			64
70 
71 #define E1000_DEFAULT_RXD		256
72 #define E1000_MAX_RXD			4096
73 #define E1000_MIN_RXD			64
74 
75 #define E1000_MIN_ITR_USECS		10 /* 100000 irq/sec */
76 #define E1000_MAX_ITR_USECS		10000 /* 100    irq/sec */
77 
78 /* Early Receive defines */
79 #define E1000_ERT_2048			0x100
80 
81 #define E1000_FC_PAUSE_TIME		0x0680 /* 858 usec */
82 
83 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
84 /* How many Rx Buffers do we bundle into one write to the hardware ? */
85 #define E1000_RX_BUFFER_WRITE		16 /* Must be power of 2 */
86 
87 #define AUTO_ALL_MODES			0
88 #define E1000_EEPROM_APME		0x0400
89 
90 #define E1000_MNG_VLAN_NONE		(-1)
91 
92 /* Number of packet split data buffers (not including the header buffer) */
93 #define PS_PAGE_BUFFERS			(MAX_PS_BUFFERS - 1)
94 
95 #define DEFAULT_JUMBO			9234
96 
97 /* BM/HV Specific Registers */
98 #define BM_PORT_CTRL_PAGE                 769
99 
100 #define PHY_UPPER_SHIFT                   21
101 #define BM_PHY_REG(page, reg) \
102 	(((reg) & MAX_PHY_REG_ADDRESS) |\
103 	 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
104 	 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
105 
106 /* PHY Wakeup Registers and defines */
107 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
108 #define BM_RCTL         PHY_REG(BM_WUC_PAGE, 0)
109 #define BM_WUC          PHY_REG(BM_WUC_PAGE, 1)
110 #define BM_WUFC         PHY_REG(BM_WUC_PAGE, 2)
111 #define BM_WUS          PHY_REG(BM_WUC_PAGE, 3)
112 #define BM_RAR_L(_i)    (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
113 #define BM_RAR_M(_i)    (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
114 #define BM_RAR_H(_i)    (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
115 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
116 #define BM_MTA(_i)      (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
117 
118 #define BM_RCTL_UPE           0x0001          /* Unicast Promiscuous Mode */
119 #define BM_RCTL_MPE           0x0002          /* Multicast Promiscuous Mode */
120 #define BM_RCTL_MO_SHIFT      3               /* Multicast Offset Shift */
121 #define BM_RCTL_MO_MASK       (3 << 3)        /* Multicast Offset Mask */
122 #define BM_RCTL_BAM           0x0020          /* Broadcast Accept Mode */
123 #define BM_RCTL_PMCF          0x0040          /* Pass MAC Control Frames */
124 #define BM_RCTL_RFCE          0x0080          /* Rx Flow Control Enable */
125 
126 #define HV_STATS_PAGE	778
127 #define HV_SCC_UPPER	PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
128 #define HV_SCC_LOWER	PHY_REG(HV_STATS_PAGE, 17)
129 #define HV_ECOL_UPPER	PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
130 #define HV_ECOL_LOWER	PHY_REG(HV_STATS_PAGE, 19)
131 #define HV_MCC_UPPER	PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
132 #define HV_MCC_LOWER	PHY_REG(HV_STATS_PAGE, 21)
133 #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
134 #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
135 #define HV_COLC_UPPER	PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
136 #define HV_COLC_LOWER	PHY_REG(HV_STATS_PAGE, 26)
137 #define HV_DC_UPPER	PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
138 #define HV_DC_LOWER	PHY_REG(HV_STATS_PAGE, 28)
139 #define HV_TNCRS_UPPER	PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
140 #define HV_TNCRS_LOWER	PHY_REG(HV_STATS_PAGE, 30)
141 
142 #define E1000_FCRTV_PCH     0x05F40 /* PCH Flow Control Refresh Timer Value */
143 
144 /* BM PHY Copper Specific Status */
145 #define BM_CS_STATUS                      17
146 #define BM_CS_STATUS_LINK_UP              0x0400
147 #define BM_CS_STATUS_RESOLVED             0x0800
148 #define BM_CS_STATUS_SPEED_MASK           0xC000
149 #define BM_CS_STATUS_SPEED_1000           0x8000
150 
151 /* 82577 Mobile Phy Status Register */
152 #define HV_M_STATUS                       26
153 #define HV_M_STATUS_AUTONEG_COMPLETE      0x1000
154 #define HV_M_STATUS_SPEED_MASK            0x0300
155 #define HV_M_STATUS_SPEED_1000            0x0200
156 #define HV_M_STATUS_LINK_UP               0x0040
157 
158 #define E1000_ICH_FWSM_PCIM2PCI		0x01000000 /* ME PCIm-to-PCI active */
159 #define E1000_ICH_FWSM_PCIM2PCI_COUNT	2000
160 
161 /* Time to wait before putting the device into D3 if there's no link (in ms). */
162 #define LINK_TIMEOUT		100
163 
164 /*
165  * Count for polling __E1000_RESET condition every 10-20msec.
166  * Experimentation has shown the reset can take approximately 210msec.
167  */
168 #define E1000_CHECK_RESET_COUNT		25
169 
170 #define DEFAULT_RDTR			0
171 #define DEFAULT_RADV			8
172 #define BURST_RDTR			0x20
173 #define BURST_RADV			0x20
174 
175 /*
176  * in the case of WTHRESH, it appears at least the 82571/2 hardware
177  * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
178  * WTHRESH=4, so a setting of 5 gives the most efficient bus
179  * utilization but to avoid possible Tx stalls, set it to 1
180  */
181 #define E1000_TXDCTL_DMA_BURST_ENABLE                          \
182 	(E1000_TXDCTL_GRAN | /* set descriptor granularity */  \
183 	 E1000_TXDCTL_COUNT_DESC |                             \
184 	 (1 << 16) | /* wthresh must be +1 more than desired */\
185 	 (1 << 8)  | /* hthresh */                             \
186 	 0x1f)       /* pthresh */
187 
188 #define E1000_RXDCTL_DMA_BURST_ENABLE                          \
189 	(0x01000000 | /* set descriptor granularity */         \
190 	 (4 << 16)  | /* set writeback threshold    */         \
191 	 (4 << 8)   | /* set prefetch threshold     */         \
192 	 0x20)        /* set hthresh                */
193 
194 #define E1000_TIDV_FPD (1 << 31)
195 #define E1000_RDTR_FPD (1 << 31)
196 
197 enum e1000_boards {
198 	board_82571,
199 	board_82572,
200 	board_82573,
201 	board_82574,
202 	board_82583,
203 	board_80003es2lan,
204 	board_ich8lan,
205 	board_ich9lan,
206 	board_ich10lan,
207 	board_pchlan,
208 	board_pch2lan,
209 };
210 
211 struct e1000_ps_page {
212 	struct page *page;
213 	u64 dma; /* must be u64 - written to hw */
214 };
215 
216 /*
217  * wrappers around a pointer to a socket buffer,
218  * so a DMA handle can be stored along with the buffer
219  */
220 struct e1000_buffer {
221 	dma_addr_t dma;
222 	struct sk_buff *skb;
223 	union {
224 		/* Tx */
225 		struct {
226 			unsigned long time_stamp;
227 			u16 length;
228 			u16 next_to_watch;
229 			unsigned int segs;
230 			unsigned int bytecount;
231 			u16 mapped_as_page;
232 		};
233 		/* Rx */
234 		struct {
235 			/* arrays of page information for packet split */
236 			struct e1000_ps_page *ps_pages;
237 			struct page *page;
238 		};
239 	};
240 };
241 
242 struct e1000_ring {
243 	struct e1000_adapter *adapter;	/* back pointer to adapter */
244 	void *desc;			/* pointer to ring memory  */
245 	dma_addr_t dma;			/* phys address of ring    */
246 	unsigned int size;		/* length of ring in bytes */
247 	unsigned int count;		/* number of desc. in ring */
248 
249 	u16 next_to_use;
250 	u16 next_to_clean;
251 
252 	void __iomem *head;
253 	void __iomem *tail;
254 
255 	/* array of buffer information structs */
256 	struct e1000_buffer *buffer_info;
257 
258 	char name[IFNAMSIZ + 5];
259 	u32 ims_val;
260 	u32 itr_val;
261 	void __iomem *itr_register;
262 	int set_itr;
263 
264 	struct sk_buff *rx_skb_top;
265 };
266 
267 /* PHY register snapshot values */
268 struct e1000_phy_regs {
269 	u16 bmcr;		/* basic mode control register    */
270 	u16 bmsr;		/* basic mode status register     */
271 	u16 advertise;		/* auto-negotiation advertisement */
272 	u16 lpa;		/* link partner ability register  */
273 	u16 expansion;		/* auto-negotiation expansion reg */
274 	u16 ctrl1000;		/* 1000BASE-T control register    */
275 	u16 stat1000;		/* 1000BASE-T status register     */
276 	u16 estatus;		/* extended status register       */
277 };
278 
279 /* board specific private data structure */
280 struct e1000_adapter {
281 	struct timer_list watchdog_timer;
282 	struct timer_list phy_info_timer;
283 	struct timer_list blink_timer;
284 
285 	struct work_struct reset_task;
286 	struct work_struct watchdog_task;
287 
288 	const struct e1000_info *ei;
289 
290 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
291 	u32 bd_number;
292 	u32 rx_buffer_len;
293 	u16 mng_vlan_id;
294 	u16 link_speed;
295 	u16 link_duplex;
296 	u16 eeprom_vers;
297 
298 	/* track device up/down/testing state */
299 	unsigned long state;
300 
301 	/* Interrupt Throttle Rate */
302 	u32 itr;
303 	u32 itr_setting;
304 	u16 tx_itr;
305 	u16 rx_itr;
306 
307 	/*
308 	 * Tx
309 	 */
310 	struct e1000_ring *tx_ring /* One per active queue */
311 						____cacheline_aligned_in_smp;
312 	u32 tx_fifo_limit;
313 
314 	struct napi_struct napi;
315 
316 	unsigned int restart_queue;
317 	u32 txd_cmd;
318 
319 	bool detect_tx_hung;
320 	bool tx_hang_recheck;
321 	u8 tx_timeout_factor;
322 
323 	u32 tx_int_delay;
324 	u32 tx_abs_int_delay;
325 
326 	unsigned int total_tx_bytes;
327 	unsigned int total_tx_packets;
328 	unsigned int total_rx_bytes;
329 	unsigned int total_rx_packets;
330 
331 	/* Tx stats */
332 	u64 tpt_old;
333 	u64 colc_old;
334 	u32 gotc;
335 	u64 gotc_old;
336 	u32 tx_timeout_count;
337 	u32 tx_fifo_head;
338 	u32 tx_head_addr;
339 	u32 tx_fifo_size;
340 	u32 tx_dma_failed;
341 
342 	/*
343 	 * Rx
344 	 */
345 	bool (*clean_rx) (struct e1000_ring *ring, int *work_done,
346 			  int work_to_do) ____cacheline_aligned_in_smp;
347 	void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,
348 			      gfp_t gfp);
349 	struct e1000_ring *rx_ring;
350 
351 	u32 rx_int_delay;
352 	u32 rx_abs_int_delay;
353 
354 	/* Rx stats */
355 	u64 hw_csum_err;
356 	u64 hw_csum_good;
357 	u64 rx_hdr_split;
358 	u32 gorc;
359 	u64 gorc_old;
360 	u32 alloc_rx_buff_failed;
361 	u32 rx_dma_failed;
362 
363 	unsigned int rx_ps_pages;
364 	u16 rx_ps_bsize0;
365 	u32 max_frame_size;
366 	u32 min_frame_size;
367 
368 	/* OS defined structs */
369 	struct net_device *netdev;
370 	struct pci_dev *pdev;
371 
372 	/* structs defined in e1000_hw.h */
373 	struct e1000_hw hw;
374 
375 	spinlock_t stats64_lock;
376 	struct e1000_hw_stats stats;
377 	struct e1000_phy_info phy_info;
378 	struct e1000_phy_stats phy_stats;
379 
380 	/* Snapshot of PHY registers */
381 	struct e1000_phy_regs phy_regs;
382 
383 	struct e1000_ring test_tx_ring;
384 	struct e1000_ring test_rx_ring;
385 	u32 test_icr;
386 
387 	u32 msg_enable;
388 	unsigned int num_vectors;
389 	struct msix_entry *msix_entries;
390 	int int_mode;
391 	u32 eiac_mask;
392 
393 	u32 eeprom_wol;
394 	u32 wol;
395 	u32 pba;
396 	u32 max_hw_frame_size;
397 
398 	bool fc_autoneg;
399 
400 	unsigned int flags;
401 	unsigned int flags2;
402 	struct work_struct downshift_task;
403 	struct work_struct update_phy_task;
404 	struct work_struct print_hang_task;
405 
406 	bool idle_check;
407 	int phy_hang_count;
408 
409 	u16 tx_ring_count;
410 	u16 rx_ring_count;
411 };
412 
413 struct e1000_info {
414 	enum e1000_mac_type	mac;
415 	unsigned int		flags;
416 	unsigned int		flags2;
417 	u32			pba;
418 	u32			max_hw_frame_size;
419 	s32			(*get_variants)(struct e1000_adapter *);
420 	const struct e1000_mac_operations *mac_ops;
421 	const struct e1000_phy_operations *phy_ops;
422 	const struct e1000_nvm_operations *nvm_ops;
423 };
424 
425 /* hardware capability, feature, and workaround flags */
426 #define FLAG_HAS_AMT                      (1 << 0)
427 #define FLAG_HAS_FLASH                    (1 << 1)
428 #define FLAG_HAS_HW_VLAN_FILTER           (1 << 2)
429 #define FLAG_HAS_WOL                      (1 << 3)
430 /* reserved bit4 */
431 #define FLAG_HAS_CTRLEXT_ON_LOAD          (1 << 5)
432 #define FLAG_HAS_SWSM_ON_LOAD             (1 << 6)
433 #define FLAG_HAS_JUMBO_FRAMES             (1 << 7)
434 #define FLAG_READ_ONLY_NVM                (1 << 8)
435 #define FLAG_IS_ICH                       (1 << 9)
436 #define FLAG_HAS_MSIX                     (1 << 10)
437 #define FLAG_HAS_SMART_POWER_DOWN         (1 << 11)
438 #define FLAG_IS_QUAD_PORT_A               (1 << 12)
439 #define FLAG_IS_QUAD_PORT                 (1 << 13)
440 /* reserved bit14 */
441 #define FLAG_APME_IN_WUC                  (1 << 15)
442 #define FLAG_APME_IN_CTRL3                (1 << 16)
443 #define FLAG_APME_CHECK_PORT_B            (1 << 17)
444 #define FLAG_DISABLE_FC_PAUSE_TIME        (1 << 18)
445 #define FLAG_NO_WAKE_UCAST                (1 << 19)
446 #define FLAG_MNG_PT_ENABLED               (1 << 20)
447 #define FLAG_RESET_OVERWRITES_LAA         (1 << 21)
448 #define FLAG_TARC_SPEED_MODE_BIT          (1 << 22)
449 #define FLAG_TARC_SET_BIT_ZERO            (1 << 23)
450 #define FLAG_RX_NEEDS_RESTART             (1 << 24)
451 #define FLAG_LSC_GIG_SPEED_DROP           (1 << 25)
452 #define FLAG_SMART_POWER_DOWN             (1 << 26)
453 #define FLAG_MSI_ENABLED                  (1 << 27)
454 /* reserved (1 << 28) */
455 #define FLAG_TSO_FORCE                    (1 << 29)
456 #define FLAG_RX_RESTART_NOW               (1 << 30)
457 #define FLAG_MSI_TEST_FAILED              (1 << 31)
458 
459 #define FLAG2_CRC_STRIPPING               (1 << 0)
460 #define FLAG2_HAS_PHY_WAKEUP              (1 << 1)
461 #define FLAG2_IS_DISCARDING               (1 << 2)
462 #define FLAG2_DISABLE_ASPM_L1             (1 << 3)
463 #define FLAG2_HAS_PHY_STATS               (1 << 4)
464 #define FLAG2_HAS_EEE                     (1 << 5)
465 #define FLAG2_DMA_BURST                   (1 << 6)
466 #define FLAG2_DISABLE_ASPM_L0S            (1 << 7)
467 #define FLAG2_DISABLE_AIM                 (1 << 8)
468 #define FLAG2_CHECK_PHY_HANG              (1 << 9)
469 #define FLAG2_NO_DISABLE_RX               (1 << 10)
470 #define FLAG2_PCIM2PCI_ARBITER_WA         (1 << 11)
471 #define FLAG2_DFLT_CRC_STRIPPING          (1 << 12)
472 
473 #define E1000_RX_DESC_PS(R, i)	    \
474 	(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
475 #define E1000_RX_DESC_EXT(R, i)	    \
476 	(&(((union e1000_rx_desc_extended *)((R).desc))[i]))
477 #define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
478 #define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
479 #define E1000_CONTEXT_DESC(R, i)	E1000_GET_DESC(R, i, e1000_context_desc)
480 
481 enum e1000_state_t {
482 	__E1000_TESTING,
483 	__E1000_RESETTING,
484 	__E1000_ACCESS_SHARED_RESOURCE,
485 	__E1000_DOWN
486 };
487 
488 enum latency_range {
489 	lowest_latency = 0,
490 	low_latency = 1,
491 	bulk_latency = 2,
492 	latency_invalid = 255
493 };
494 
495 extern char e1000e_driver_name[];
496 extern const char e1000e_driver_version[];
497 
498 extern void e1000e_check_options(struct e1000_adapter *adapter);
499 extern void e1000e_set_ethtool_ops(struct net_device *netdev);
500 
501 extern int e1000e_up(struct e1000_adapter *adapter);
502 extern void e1000e_down(struct e1000_adapter *adapter);
503 extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
504 extern void e1000e_reset(struct e1000_adapter *adapter);
505 extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
506 extern int e1000e_setup_rx_resources(struct e1000_ring *ring);
507 extern int e1000e_setup_tx_resources(struct e1000_ring *ring);
508 extern void e1000e_free_rx_resources(struct e1000_ring *ring);
509 extern void e1000e_free_tx_resources(struct e1000_ring *ring);
510 extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
511                                                     struct rtnl_link_stats64
512                                                     *stats);
513 extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
514 extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
515 extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
516 extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
517 
518 extern unsigned int copybreak;
519 
520 extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
521 
522 extern const struct e1000_info e1000_82571_info;
523 extern const struct e1000_info e1000_82572_info;
524 extern const struct e1000_info e1000_82573_info;
525 extern const struct e1000_info e1000_82574_info;
526 extern const struct e1000_info e1000_82583_info;
527 extern const struct e1000_info e1000_ich8_info;
528 extern const struct e1000_info e1000_ich9_info;
529 extern const struct e1000_info e1000_ich10_info;
530 extern const struct e1000_info e1000_pch_info;
531 extern const struct e1000_info e1000_pch2_info;
532 extern const struct e1000_info e1000_es2_info;
533 
534 extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
535 					 u32 pba_num_size);
536 
537 extern s32  e1000e_commit_phy(struct e1000_hw *hw);
538 
539 extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
540 
541 extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
542 extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
543 
544 extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
545 extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
546 						 bool state);
547 extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
548 extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
549 extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
550 extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
551 extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
552 extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
553 extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
554 
555 extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
556 extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
557 extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
558 extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
559 extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
560 extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
561 extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
562 extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
563 extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
564 extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
565 extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
566 extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
567 extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
568 extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
569 extern s32 e1000e_id_led_init_generic(struct e1000_hw *hw);
570 extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
571 extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
572 extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
573 extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
574 extern s32 e1000e_setup_link_generic(struct e1000_hw *hw);
575 extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
576 extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
577 extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
578 					       u8 *mc_addr_list,
579 					       u32 mc_addr_count);
580 extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
581 extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
582 extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
583 extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
584 extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
585 extern void e1000e_config_collision_dist_generic(struct e1000_hw *hw);
586 extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
587 extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
588 extern s32 e1000e_blink_led_generic(struct e1000_hw *hw);
589 extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
590 extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
591 extern void e1000e_reset_adaptive(struct e1000_hw *hw);
592 extern void e1000e_update_adaptive(struct e1000_hw *hw);
593 
594 extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
595 extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
596 extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
597 extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
598 extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
599 extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
600 extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
601 extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
602 extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
603 extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
604                                           u16 *data);
605 extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
606 extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
607 extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
608 extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
609                                            u16 data);
610 extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
611 extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
612 extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
613 extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
614 extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
615 extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
616 extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
617 extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
618 extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
619 extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
620 extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
621 extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
622 extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
623 						 u16 *phy_reg);
624 extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
625 						  u16 *phy_reg);
626 extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
627 extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
628 extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
629 extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
630 extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
631                                         u16 data);
632 extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
633 extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
634                                        u16 *data);
635 extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
636 			       u32 usec_interval, bool *success);
637 extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
638 extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
639 extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
640 extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
641 extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
642 extern s32 e1000e_check_downshift(struct e1000_hw *hw);
643 extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
644 extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
645                                         u16 *data);
646 extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
647 				      u16 *data);
648 extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
649 extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
650                                          u16 data);
651 extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
652 				       u16 data);
653 extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
654 extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
655 extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
656 extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
657 extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
658 extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
659 
660 extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
661 extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
662 extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
663 extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
664 extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
665 extern bool e1000_check_phy_82574(struct e1000_hw *hw);
666 
e1000_phy_hw_reset(struct e1000_hw * hw)667 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
668 {
669 	return hw->phy.ops.reset(hw);
670 }
671 
e1e_rphy(struct e1000_hw * hw,u32 offset,u16 * data)672 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
673 {
674 	return hw->phy.ops.read_reg(hw, offset, data);
675 }
676 
e1e_wphy(struct e1000_hw * hw,u32 offset,u16 data)677 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
678 {
679 	return hw->phy.ops.write_reg(hw, offset, data);
680 }
681 
e1000_get_cable_length(struct e1000_hw * hw)682 static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
683 {
684 	return hw->phy.ops.get_cable_length(hw);
685 }
686 
687 extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
688 extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
689 extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
690 extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
691 extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
692 extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
693 extern void e1000e_release_nvm(struct e1000_hw *hw);
694 extern void e1000e_reload_nvm_generic(struct e1000_hw *hw);
695 extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
696 
e1000e_read_mac_addr(struct e1000_hw * hw)697 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
698 {
699 	if (hw->mac.ops.read_mac_addr)
700 		return hw->mac.ops.read_mac_addr(hw);
701 
702 	return e1000_read_mac_addr_generic(hw);
703 }
704 
e1000_validate_nvm_checksum(struct e1000_hw * hw)705 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
706 {
707 	return hw->nvm.ops.validate(hw);
708 }
709 
e1000e_update_nvm_checksum(struct e1000_hw * hw)710 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
711 {
712 	return hw->nvm.ops.update(hw);
713 }
714 
e1000_read_nvm(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)715 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
716 {
717 	return hw->nvm.ops.read(hw, offset, words, data);
718 }
719 
e1000_write_nvm(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)720 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
721 {
722 	return hw->nvm.ops.write(hw, offset, words, data);
723 }
724 
e1000_get_phy_info(struct e1000_hw * hw)725 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
726 {
727 	return hw->phy.ops.get_info(hw);
728 }
729 
730 extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
731 extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
732 extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
733 
__er32(struct e1000_hw * hw,unsigned long reg)734 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
735 {
736 	return readl(hw->hw_addr + reg);
737 }
738 
__ew32(struct e1000_hw * hw,unsigned long reg,u32 val)739 static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
740 {
741 	writel(val, hw->hw_addr + reg);
742 }
743 
744 #endif /* _E1000_H_ */
745