1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include "i915_reg_defs.h" 29 30 /** 31 * DOC: The i915 register macro definition style guide 32 * 33 * Follow the style described here for new macros, and while changing existing 34 * macros. Do **not** mass change existing definitions just to update the style. 35 * 36 * File Layout 37 * ~~~~~~~~~~~ 38 * 39 * Keep helper macros near the top. For example, _PIPE() and friends. 40 * 41 * Prefix macros that generally should not be used outside of this file with 42 * underscore '_'. For example, _PIPE() and friends, single instances of 43 * registers that are defined solely for the use by function-like macros. 44 * 45 * Avoid using the underscore prefixed macros outside of this file. There are 46 * exceptions, but keep them to a minimum. 47 * 48 * There are two basic types of register definitions: Single registers and 49 * register groups. Register groups are registers which have two or more 50 * instances, for example one per pipe, port, transcoder, etc. Register groups 51 * should be defined using function-like macros. 52 * 53 * For single registers, define the register offset first, followed by register 54 * contents. 55 * 56 * For register groups, define the register instance offsets first, prefixed 57 * with underscore, followed by a function-like macro choosing the right 58 * instance based on the parameter, followed by register contents. 59 * 60 * Define the register contents (i.e. bit and bit field macros) from most 61 * significant to least significant bit. Indent the register content macros 62 * using two extra spaces between ``#define`` and the macro name. 63 * 64 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 65 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 66 * shifted in place, so they can be directly OR'd together. For convenience, 67 * function-like macros may be used to define bit fields, but do note that the 68 * macros may be needed to read as well as write the register contents. 69 * 70 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 71 * 72 * Group the register and its contents together without blank lines, separate 73 * from other registers and their contents with one blank line. 74 * 75 * Indent macro values from macro names using TABs. Align values vertically. Use 76 * braces in macro values as needed to avoid unintended precedence after macro 77 * substitution. Use spaces in macro values according to kernel coding 78 * style. Use lower case in hexadecimal values. 79 * 80 * Naming 81 * ~~~~~~ 82 * 83 * Try to name registers according to the specs. If the register name changes in 84 * the specs from platform to another, stick to the original name. 85 * 86 * Try to re-use existing register macro definitions. Only add new macros for 87 * new register offsets, or when the register contents have changed enough to 88 * warrant a full redefinition. 89 * 90 * When a register macro changes for a new platform, prefix the new macro using 91 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 92 * prefix signifies the start platform/generation using the register. 93 * 94 * When a bit (field) macro changes or gets added for a new platform, while 95 * retaining the existing register macro, add a platform acronym or generation 96 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 97 * 98 * Examples 99 * ~~~~~~~~ 100 * 101 * (Note that the values in the example are indented using spaces instead of 102 * TABs to avoid misalignment in generated documentation. Use TABs in the 103 * definitions.):: 104 * 105 * #define _FOO_A 0xf000 106 * #define _FOO_B 0xf001 107 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 108 * #define FOO_ENABLE REG_BIT(31) 109 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 110 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 111 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 112 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 113 * 114 * #define BAR _MMIO(0xb000) 115 * #define GEN8_BAR _MMIO(0xb888) 116 */ 117 118 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display.mmio_offset) 119 120 /* 121 * Given the first two numbers __a and __b of arbitrarily many evenly spaced 122 * numbers, pick the 0-based __index'th value. 123 * 124 * Always prefer this over _PICK() if the numbers are evenly spaced. 125 */ 126 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) 127 128 /* 129 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. 130 * 131 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. 132 */ 133 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) 134 135 /* 136 * Named helper wrappers around _PICK_EVEN() and _PICK(). 137 */ 138 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 139 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 140 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 141 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) 142 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 143 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) 144 145 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 146 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 147 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 148 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 149 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 150 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) 151 152 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) 153 154 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 155 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 156 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) 157 #define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__)) 158 159 160 /* 161 * Device info offset array based helpers for groups of registers with unevenly 162 * spaced base offsets. 163 */ 164 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \ 165 INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \ 166 DISPLAY_MMIO_BASE(dev_priv) + (reg)) 167 #define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \ 168 INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \ 169 DISPLAY_MMIO_BASE(dev_priv) + (reg)) 170 #define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \ 171 INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \ 172 DISPLAY_MMIO_BASE(dev_priv) + (reg)) 173 174 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) 175 #define _MASKED_FIELD(mask, value) ({ \ 176 if (__builtin_constant_p(mask)) \ 177 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 178 if (__builtin_constant_p(value)) \ 179 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 180 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 181 BUILD_BUG_ON_MSG((value) & ~(mask), \ 182 "Incorrect value for mask"); \ 183 __MASKED_FIELD(mask, value); }) 184 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 185 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 186 187 #define GU_CNTL _MMIO(0x101010) 188 #define LMEM_INIT REG_BIT(7) 189 190 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 191 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 192 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 193 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 194 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 195 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 196 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 197 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 198 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 199 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 200 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 201 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 202 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 203 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 204 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 205 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 206 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 207 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 208 209 #define _VGA_MSR_WRITE _MMIO(0x3c2) 210 211 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 212 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 213 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 214 215 /* 216 * Reset registers 217 */ 218 #define DEBUG_RESET_I830 _MMIO(0x6070) 219 #define DEBUG_RESET_FULL (1 << 7) 220 #define DEBUG_RESET_RENDER (1 << 8) 221 #define DEBUG_RESET_DISPLAY (1 << 9) 222 223 /* 224 * IOSF sideband 225 */ 226 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 227 #define IOSF_DEVFN_SHIFT 24 228 #define IOSF_OPCODE_SHIFT 16 229 #define IOSF_PORT_SHIFT 8 230 #define IOSF_BYTE_ENABLES_SHIFT 4 231 #define IOSF_BAR_SHIFT 1 232 #define IOSF_SB_BUSY (1 << 0) 233 #define IOSF_PORT_BUNIT 0x03 234 #define IOSF_PORT_PUNIT 0x04 235 #define IOSF_PORT_NC 0x11 236 #define IOSF_PORT_DPIO 0x12 237 #define IOSF_PORT_GPIO_NC 0x13 238 #define IOSF_PORT_CCK 0x14 239 #define IOSF_PORT_DPIO_2 0x1a 240 #define IOSF_PORT_FLISDSI 0x1b 241 #define IOSF_PORT_GPIO_SC 0x48 242 #define IOSF_PORT_GPIO_SUS 0xa8 243 #define IOSF_PORT_CCU 0xa9 244 #define CHV_IOSF_PORT_GPIO_N 0x13 245 #define CHV_IOSF_PORT_GPIO_SE 0x48 246 #define CHV_IOSF_PORT_GPIO_E 0xa8 247 #define CHV_IOSF_PORT_GPIO_SW 0xb2 248 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 249 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 250 251 /* DPIO registers */ 252 #define DPIO_DEVFN 0 253 254 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 255 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 256 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 257 #define DPIO_SFR_BYPASS (1 << 1) 258 #define DPIO_CMNRST (1 << 0) 259 260 #define DPIO_PHY(pipe) ((pipe) >> 1) 261 262 /* 263 * Per pipe/PLL DPIO regs 264 */ 265 #define _VLV_PLL_DW3_CH0 0x800c 266 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 267 #define DPIO_POST_DIV_DAC 0 268 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 269 #define DPIO_POST_DIV_LVDS1 2 270 #define DPIO_POST_DIV_LVDS2 3 271 #define DPIO_K_SHIFT (24) /* 4 bits */ 272 #define DPIO_P1_SHIFT (21) /* 3 bits */ 273 #define DPIO_P2_SHIFT (16) /* 5 bits */ 274 #define DPIO_N_SHIFT (12) /* 4 bits */ 275 #define DPIO_ENABLE_CALIBRATION (1 << 11) 276 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 277 #define DPIO_M2DIV_MASK 0xff 278 #define _VLV_PLL_DW3_CH1 0x802c 279 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 280 281 #define _VLV_PLL_DW5_CH0 0x8014 282 #define DPIO_REFSEL_OVERRIDE 27 283 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 284 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 285 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 286 #define DPIO_PLL_REFCLK_SEL_MASK 3 287 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 288 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 289 #define _VLV_PLL_DW5_CH1 0x8034 290 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 291 292 #define _VLV_PLL_DW7_CH0 0x801c 293 #define _VLV_PLL_DW7_CH1 0x803c 294 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 295 296 #define _VLV_PLL_DW8_CH0 0x8040 297 #define _VLV_PLL_DW8_CH1 0x8060 298 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 299 300 #define VLV_PLL_DW9_BCAST 0xc044 301 #define _VLV_PLL_DW9_CH0 0x8044 302 #define _VLV_PLL_DW9_CH1 0x8064 303 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 304 305 #define _VLV_PLL_DW10_CH0 0x8048 306 #define _VLV_PLL_DW10_CH1 0x8068 307 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 308 309 #define _VLV_PLL_DW11_CH0 0x804c 310 #define _VLV_PLL_DW11_CH1 0x806c 311 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 312 313 /* Spec for ref block start counts at DW10 */ 314 #define VLV_REF_DW13 0x80ac 315 316 #define VLV_CMN_DW0 0x8100 317 318 /* 319 * Per DDI channel DPIO regs 320 */ 321 322 #define _VLV_PCS_DW0_CH0 0x8200 323 #define _VLV_PCS_DW0_CH1 0x8400 324 #define DPIO_PCS_TX_LANE2_RESET (1 << 16) 325 #define DPIO_PCS_TX_LANE1_RESET (1 << 7) 326 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) 327 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) 328 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 329 330 #define _VLV_PCS01_DW0_CH0 0x200 331 #define _VLV_PCS23_DW0_CH0 0x400 332 #define _VLV_PCS01_DW0_CH1 0x2600 333 #define _VLV_PCS23_DW0_CH1 0x2800 334 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 335 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 336 337 #define _VLV_PCS_DW1_CH0 0x8204 338 #define _VLV_PCS_DW1_CH1 0x8404 339 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) 340 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) 341 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) 342 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 343 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) 344 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 345 346 #define _VLV_PCS01_DW1_CH0 0x204 347 #define _VLV_PCS23_DW1_CH0 0x404 348 #define _VLV_PCS01_DW1_CH1 0x2604 349 #define _VLV_PCS23_DW1_CH1 0x2804 350 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 351 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 352 353 #define _VLV_PCS_DW8_CH0 0x8220 354 #define _VLV_PCS_DW8_CH1 0x8420 355 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 356 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 357 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 358 359 #define _VLV_PCS01_DW8_CH0 0x0220 360 #define _VLV_PCS23_DW8_CH0 0x0420 361 #define _VLV_PCS01_DW8_CH1 0x2620 362 #define _VLV_PCS23_DW8_CH1 0x2820 363 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 364 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 365 366 #define _VLV_PCS_DW9_CH0 0x8224 367 #define _VLV_PCS_DW9_CH1 0x8424 368 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) 369 #define DPIO_PCS_TX2MARGIN_000 (0 << 13) 370 #define DPIO_PCS_TX2MARGIN_101 (1 << 13) 371 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) 372 #define DPIO_PCS_TX1MARGIN_000 (0 << 10) 373 #define DPIO_PCS_TX1MARGIN_101 (1 << 10) 374 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 375 376 #define _VLV_PCS01_DW9_CH0 0x224 377 #define _VLV_PCS23_DW9_CH0 0x424 378 #define _VLV_PCS01_DW9_CH1 0x2624 379 #define _VLV_PCS23_DW9_CH1 0x2824 380 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 381 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 382 383 #define _CHV_PCS_DW10_CH0 0x8228 384 #define _CHV_PCS_DW10_CH1 0x8428 385 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) 386 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) 387 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) 388 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) 389 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) 390 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) 391 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) 392 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) 393 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 394 395 #define _VLV_PCS01_DW10_CH0 0x0228 396 #define _VLV_PCS23_DW10_CH0 0x0428 397 #define _VLV_PCS01_DW10_CH1 0x2628 398 #define _VLV_PCS23_DW10_CH1 0x2828 399 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 400 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 401 402 #define _VLV_PCS_DW11_CH0 0x822c 403 #define _VLV_PCS_DW11_CH1 0x842c 404 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) 405 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) 406 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) 407 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) 408 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 409 410 #define _VLV_PCS01_DW11_CH0 0x022c 411 #define _VLV_PCS23_DW11_CH0 0x042c 412 #define _VLV_PCS01_DW11_CH1 0x262c 413 #define _VLV_PCS23_DW11_CH1 0x282c 414 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 415 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 416 417 #define _VLV_PCS01_DW12_CH0 0x0230 418 #define _VLV_PCS23_DW12_CH0 0x0430 419 #define _VLV_PCS01_DW12_CH1 0x2630 420 #define _VLV_PCS23_DW12_CH1 0x2830 421 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 422 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 423 424 #define _VLV_PCS_DW12_CH0 0x8230 425 #define _VLV_PCS_DW12_CH1 0x8430 426 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) 427 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) 428 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) 429 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) 430 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) 431 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 432 433 #define _VLV_PCS_DW14_CH0 0x8238 434 #define _VLV_PCS_DW14_CH1 0x8438 435 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 436 437 #define _VLV_PCS_DW23_CH0 0x825c 438 #define _VLV_PCS_DW23_CH1 0x845c 439 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 440 441 #define _VLV_TX_DW2_CH0 0x8288 442 #define _VLV_TX_DW2_CH1 0x8488 443 #define DPIO_SWING_MARGIN000_SHIFT 16 444 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 445 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 446 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 447 448 #define _VLV_TX_DW3_CH0 0x828c 449 #define _VLV_TX_DW3_CH1 0x848c 450 /* The following bit for CHV phy */ 451 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) 452 #define DPIO_SWING_MARGIN101_SHIFT 16 453 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 454 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 455 456 #define _VLV_TX_DW4_CH0 0x8290 457 #define _VLV_TX_DW4_CH1 0x8490 458 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 459 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 460 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 461 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 462 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 463 464 #define _VLV_TX3_DW4_CH0 0x690 465 #define _VLV_TX3_DW4_CH1 0x2a90 466 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 467 468 #define _VLV_TX_DW5_CH0 0x8294 469 #define _VLV_TX_DW5_CH1 0x8494 470 #define DPIO_TX_OCALINIT_EN (1 << 31) 471 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 472 473 #define _VLV_TX_DW11_CH0 0x82ac 474 #define _VLV_TX_DW11_CH1 0x84ac 475 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 476 477 #define _VLV_TX_DW14_CH0 0x82b8 478 #define _VLV_TX_DW14_CH1 0x84b8 479 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 480 481 /* CHV dpPhy registers */ 482 #define _CHV_PLL_DW0_CH0 0x8000 483 #define _CHV_PLL_DW0_CH1 0x8180 484 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 485 486 #define _CHV_PLL_DW1_CH0 0x8004 487 #define _CHV_PLL_DW1_CH1 0x8184 488 #define DPIO_CHV_N_DIV_SHIFT 8 489 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 490 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 491 492 #define _CHV_PLL_DW2_CH0 0x8008 493 #define _CHV_PLL_DW2_CH1 0x8188 494 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 495 496 #define _CHV_PLL_DW3_CH0 0x800c 497 #define _CHV_PLL_DW3_CH1 0x818c 498 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 499 #define DPIO_CHV_FIRST_MOD (0 << 8) 500 #define DPIO_CHV_SECOND_MOD (1 << 8) 501 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 502 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 503 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 504 505 #define _CHV_PLL_DW6_CH0 0x8018 506 #define _CHV_PLL_DW6_CH1 0x8198 507 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 508 #define DPIO_CHV_INT_COEFF_SHIFT 8 509 #define DPIO_CHV_PROP_COEFF_SHIFT 0 510 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 511 512 #define _CHV_PLL_DW8_CH0 0x8020 513 #define _CHV_PLL_DW8_CH1 0x81A0 514 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 515 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 516 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 517 518 #define _CHV_PLL_DW9_CH0 0x8024 519 #define _CHV_PLL_DW9_CH1 0x81A4 520 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 521 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 522 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 523 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 524 525 #define _CHV_CMN_DW0_CH0 0x8100 526 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 527 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 528 #define DPIO_ALLDL_POWERDOWN (1 << 1) 529 #define DPIO_ANYDL_POWERDOWN (1 << 0) 530 531 #define _CHV_CMN_DW5_CH0 0x8114 532 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 533 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 534 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 535 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 536 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 537 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 538 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 539 #define CHV_BUFLEFTENA1_MASK (3 << 22) 540 541 #define _CHV_CMN_DW13_CH0 0x8134 542 #define _CHV_CMN_DW0_CH1 0x8080 543 #define DPIO_CHV_S1_DIV_SHIFT 21 544 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 545 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 546 #define DPIO_CHV_K_DIV_SHIFT 4 547 #define DPIO_PLL_FREQLOCK (1 << 1) 548 #define DPIO_PLL_LOCK (1 << 0) 549 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 550 551 #define _CHV_CMN_DW14_CH0 0x8138 552 #define _CHV_CMN_DW1_CH1 0x8084 553 #define DPIO_AFC_RECAL (1 << 14) 554 #define DPIO_DCLKP_EN (1 << 13) 555 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 556 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 557 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 558 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 559 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 560 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 561 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 562 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 563 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 564 565 #define _CHV_CMN_DW19_CH0 0x814c 566 #define _CHV_CMN_DW6_CH1 0x8098 567 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 568 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 569 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 570 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 571 572 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 573 574 #define CHV_CMN_DW28 0x8170 575 #define DPIO_CL1POWERDOWNEN (1 << 23) 576 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 577 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 578 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 579 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 580 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 581 582 #define CHV_CMN_DW30 0x8178 583 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 584 #define DPIO_LRC_BYPASS (1 << 3) 585 586 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 587 (lane) * 0x200 + (offset)) 588 589 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 590 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 591 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 592 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 593 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 594 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 595 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 596 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 597 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 598 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 599 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 600 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 601 #define DPIO_FRC_LATENCY_SHFIT 8 602 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 603 #define DPIO_UPAR_SHIFT 30 604 605 /* BXT PHY registers */ 606 #define _BXT_PHY0_BASE 0x6C000 607 #define _BXT_PHY1_BASE 0x162000 608 #define _BXT_PHY2_BASE 0x163000 609 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ 610 _BXT_PHY1_BASE, \ 611 _BXT_PHY2_BASE) 612 613 #define _BXT_PHY(phy, reg) \ 614 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) 615 616 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 617 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ 618 (reg_ch1) - _BXT_PHY0_BASE)) 619 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 620 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) 621 622 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 623 #define MIPIO_RST_CTRL (1 << 2) 624 625 #define _BXT_PHY_CTL_DDI_A 0x64C00 626 #define _BXT_PHY_CTL_DDI_B 0x64C10 627 #define _BXT_PHY_CTL_DDI_C 0x64C20 628 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 629 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 630 #define BXT_PHY_LANE_ENABLED (1 << 8) 631 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 632 _BXT_PHY_CTL_DDI_B) 633 634 #define _PHY_CTL_FAMILY_EDP 0x64C80 635 #define _PHY_CTL_FAMILY_DDI 0x64C90 636 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 637 #define COMMON_RESET_DIS (1 << 31) 638 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ 639 _PHY_CTL_FAMILY_EDP, \ 640 _PHY_CTL_FAMILY_DDI_C) 641 642 /* BXT PHY PLL registers */ 643 #define _PORT_PLL_A 0x46074 644 #define _PORT_PLL_B 0x46078 645 #define _PORT_PLL_C 0x4607c 646 #define PORT_PLL_ENABLE REG_BIT(31) 647 #define PORT_PLL_LOCK REG_BIT(30) 648 #define PORT_PLL_REF_SEL REG_BIT(27) 649 #define PORT_PLL_POWER_ENABLE REG_BIT(26) 650 #define PORT_PLL_POWER_STATE REG_BIT(25) 651 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 652 653 #define _PORT_PLL_EBB_0_A 0x162034 654 #define _PORT_PLL_EBB_0_B 0x6C034 655 #define _PORT_PLL_EBB_0_C 0x6C340 656 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13) 657 #define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1)) 658 #define PORT_PLL_P2_MASK REG_GENMASK(12, 8) 659 #define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2)) 660 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 661 _PORT_PLL_EBB_0_B, \ 662 _PORT_PLL_EBB_0_C) 663 664 #define _PORT_PLL_EBB_4_A 0x162038 665 #define _PORT_PLL_EBB_4_B 0x6C038 666 #define _PORT_PLL_EBB_4_C 0x6C344 667 #define PORT_PLL_RECALIBRATE REG_BIT(14) 668 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13) 669 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 670 _PORT_PLL_EBB_4_B, \ 671 _PORT_PLL_EBB_4_C) 672 673 #define _PORT_PLL_0_A 0x162100 674 #define _PORT_PLL_0_B 0x6C100 675 #define _PORT_PLL_0_C 0x6C380 676 /* PORT_PLL_0_A */ 677 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0) 678 #define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int)) 679 /* PORT_PLL_1_A */ 680 #define PORT_PLL_N_MASK REG_GENMASK(11, 8) 681 #define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n)) 682 /* PORT_PLL_2_A */ 683 #define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0) 684 #define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac)) 685 /* PORT_PLL_3_A */ 686 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16) 687 /* PORT_PLL_6_A */ 688 #define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16) 689 #define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x)) 690 #define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8) 691 #define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x)) 692 #define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0) 693 #define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x)) 694 /* PORT_PLL_8_A */ 695 #define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0) 696 #define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x)) 697 /* PORT_PLL_9_A */ 698 #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1) 699 #define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x)) 700 /* PORT_PLL_10_A */ 701 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27) 702 #define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10) 703 #define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x)) 704 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ 705 _PORT_PLL_0_B, \ 706 _PORT_PLL_0_C) 707 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ 708 (idx) * 4) 709 710 /* BXT PHY common lane registers */ 711 #define _PORT_CL1CM_DW0_A 0x162000 712 #define _PORT_CL1CM_DW0_BC 0x6C000 713 #define PHY_POWER_GOOD (1 << 16) 714 #define PHY_RESERVED (1 << 7) 715 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 716 717 #define _PORT_CL1CM_DW9_A 0x162024 718 #define _PORT_CL1CM_DW9_BC 0x6C024 719 #define IREF0RC_OFFSET_SHIFT 8 720 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 721 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) 722 723 #define _PORT_CL1CM_DW10_A 0x162028 724 #define _PORT_CL1CM_DW10_BC 0x6C028 725 #define IREF1RC_OFFSET_SHIFT 8 726 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 727 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 728 729 #define _PORT_CL1CM_DW28_A 0x162070 730 #define _PORT_CL1CM_DW28_BC 0x6C070 731 #define OCL1_POWER_DOWN_EN (1 << 23) 732 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 733 #define SUS_CLK_CONFIG 0x3 734 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) 735 736 #define _PORT_CL1CM_DW30_A 0x162078 737 #define _PORT_CL1CM_DW30_BC 0x6C078 738 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 739 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 740 741 /* The spec defines this only for BXT PHY0, but lets assume that this 742 * would exist for PHY1 too if it had a second channel. 743 */ 744 #define _PORT_CL2CM_DW6_A 0x162358 745 #define _PORT_CL2CM_DW6_BC 0x6C358 746 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 747 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 748 749 /* BXT PHY Ref registers */ 750 #define _PORT_REF_DW3_A 0x16218C 751 #define _PORT_REF_DW3_BC 0x6C18C 752 #define GRC_DONE (1 << 22) 753 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) 754 755 #define _PORT_REF_DW6_A 0x162198 756 #define _PORT_REF_DW6_BC 0x6C198 757 #define GRC_CODE_SHIFT 24 758 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 759 #define GRC_CODE_FAST_SHIFT 16 760 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 761 #define GRC_CODE_SLOW_SHIFT 8 762 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 763 #define GRC_CODE_NOM_MASK 0xFF 764 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) 765 766 #define _PORT_REF_DW8_A 0x1621A0 767 #define _PORT_REF_DW8_BC 0x6C1A0 768 #define GRC_DIS (1 << 15) 769 #define GRC_RDY_OVRD (1 << 1) 770 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) 771 772 /* BXT PHY PCS registers */ 773 #define _PORT_PCS_DW10_LN01_A 0x162428 774 #define _PORT_PCS_DW10_LN01_B 0x6C428 775 #define _PORT_PCS_DW10_LN01_C 0x6C828 776 #define _PORT_PCS_DW10_GRP_A 0x162C28 777 #define _PORT_PCS_DW10_GRP_B 0x6CC28 778 #define _PORT_PCS_DW10_GRP_C 0x6CE28 779 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 780 _PORT_PCS_DW10_LN01_B, \ 781 _PORT_PCS_DW10_LN01_C) 782 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 783 _PORT_PCS_DW10_GRP_B, \ 784 _PORT_PCS_DW10_GRP_C) 785 786 #define TX2_SWING_CALC_INIT (1 << 31) 787 #define TX1_SWING_CALC_INIT (1 << 30) 788 789 #define _PORT_PCS_DW12_LN01_A 0x162430 790 #define _PORT_PCS_DW12_LN01_B 0x6C430 791 #define _PORT_PCS_DW12_LN01_C 0x6C830 792 #define _PORT_PCS_DW12_LN23_A 0x162630 793 #define _PORT_PCS_DW12_LN23_B 0x6C630 794 #define _PORT_PCS_DW12_LN23_C 0x6CA30 795 #define _PORT_PCS_DW12_GRP_A 0x162c30 796 #define _PORT_PCS_DW12_GRP_B 0x6CC30 797 #define _PORT_PCS_DW12_GRP_C 0x6CE30 798 #define LANESTAGGER_STRAP_OVRD (1 << 6) 799 #define LANE_STAGGER_MASK 0x1F 800 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 801 _PORT_PCS_DW12_LN01_B, \ 802 _PORT_PCS_DW12_LN01_C) 803 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 804 _PORT_PCS_DW12_LN23_B, \ 805 _PORT_PCS_DW12_LN23_C) 806 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 807 _PORT_PCS_DW12_GRP_B, \ 808 _PORT_PCS_DW12_GRP_C) 809 810 /* BXT PHY TX registers */ 811 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 812 ((lane) & 1) * 0x80) 813 814 #define _PORT_TX_DW2_LN0_A 0x162508 815 #define _PORT_TX_DW2_LN0_B 0x6C508 816 #define _PORT_TX_DW2_LN0_C 0x6C908 817 #define _PORT_TX_DW2_GRP_A 0x162D08 818 #define _PORT_TX_DW2_GRP_B 0x6CD08 819 #define _PORT_TX_DW2_GRP_C 0x6CF08 820 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 821 _PORT_TX_DW2_LN0_B, \ 822 _PORT_TX_DW2_LN0_C) 823 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 824 _PORT_TX_DW2_GRP_B, \ 825 _PORT_TX_DW2_GRP_C) 826 #define MARGIN_000_SHIFT 16 827 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 828 #define UNIQ_TRANS_SCALE_SHIFT 8 829 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 830 831 #define _PORT_TX_DW3_LN0_A 0x16250C 832 #define _PORT_TX_DW3_LN0_B 0x6C50C 833 #define _PORT_TX_DW3_LN0_C 0x6C90C 834 #define _PORT_TX_DW3_GRP_A 0x162D0C 835 #define _PORT_TX_DW3_GRP_B 0x6CD0C 836 #define _PORT_TX_DW3_GRP_C 0x6CF0C 837 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 838 _PORT_TX_DW3_LN0_B, \ 839 _PORT_TX_DW3_LN0_C) 840 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 841 _PORT_TX_DW3_GRP_B, \ 842 _PORT_TX_DW3_GRP_C) 843 #define SCALE_DCOMP_METHOD (1 << 26) 844 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 845 846 #define _PORT_TX_DW4_LN0_A 0x162510 847 #define _PORT_TX_DW4_LN0_B 0x6C510 848 #define _PORT_TX_DW4_LN0_C 0x6C910 849 #define _PORT_TX_DW4_GRP_A 0x162D10 850 #define _PORT_TX_DW4_GRP_B 0x6CD10 851 #define _PORT_TX_DW4_GRP_C 0x6CF10 852 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 853 _PORT_TX_DW4_LN0_B, \ 854 _PORT_TX_DW4_LN0_C) 855 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 856 _PORT_TX_DW4_GRP_B, \ 857 _PORT_TX_DW4_GRP_C) 858 #define DEEMPH_SHIFT 24 859 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 860 861 #define _PORT_TX_DW5_LN0_A 0x162514 862 #define _PORT_TX_DW5_LN0_B 0x6C514 863 #define _PORT_TX_DW5_LN0_C 0x6C914 864 #define _PORT_TX_DW5_GRP_A 0x162D14 865 #define _PORT_TX_DW5_GRP_B 0x6CD14 866 #define _PORT_TX_DW5_GRP_C 0x6CF14 867 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 868 _PORT_TX_DW5_LN0_B, \ 869 _PORT_TX_DW5_LN0_C) 870 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 871 _PORT_TX_DW5_GRP_B, \ 872 _PORT_TX_DW5_GRP_C) 873 #define DCC_DELAY_RANGE_1 (1 << 9) 874 #define DCC_DELAY_RANGE_2 (1 << 8) 875 876 #define _PORT_TX_DW14_LN0_A 0x162538 877 #define _PORT_TX_DW14_LN0_B 0x6C538 878 #define _PORT_TX_DW14_LN0_C 0x6C938 879 #define LATENCY_OPTIM_SHIFT 30 880 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 881 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ 882 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ 883 _PORT_TX_DW14_LN0_C) + \ 884 _BXT_LANE_OFFSET(lane)) 885 886 /* UAIMI scratch pad register 1 */ 887 #define UAIMI_SPR1 _MMIO(0x4F074) 888 /* SKL VccIO mask */ 889 #define SKL_VCCIO_MASK 0x1 890 /* SKL balance leg register */ 891 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 892 /* I_boost values */ 893 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 894 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 895 /* Balance leg disable bits */ 896 #define BALANCE_LEG_DISABLE_SHIFT 23 897 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 898 899 /* 900 * Fence registers 901 * [0-7] @ 0x2000 gen2,gen3 902 * [8-15] @ 0x3000 945,g33,pnv 903 * 904 * [0-15] @ 0x3000 gen4,gen5 905 * 906 * [0-15] @ 0x100000 gen6,vlv,chv 907 * [0-31] @ 0x100000 gen7+ 908 */ 909 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 910 #define I830_FENCE_START_MASK 0x07f80000 911 #define I830_FENCE_TILING_Y_SHIFT 12 912 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 913 #define I830_FENCE_PITCH_SHIFT 4 914 #define I830_FENCE_REG_VALID (1 << 0) 915 #define I915_FENCE_MAX_PITCH_VAL 4 916 #define I830_FENCE_MAX_PITCH_VAL 6 917 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 918 919 #define I915_FENCE_START_MASK 0x0ff00000 920 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 921 922 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 923 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 924 #define I965_FENCE_PITCH_SHIFT 2 925 #define I965_FENCE_TILING_Y_SHIFT 1 926 #define I965_FENCE_REG_VALID (1 << 0) 927 #define I965_FENCE_MAX_PITCH_VAL 0x0400 928 929 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 930 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 931 #define GEN6_FENCE_PITCH_SHIFT 32 932 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 933 934 935 /* control register for cpu gtt access */ 936 #define TILECTL _MMIO(0x101000) 937 #define TILECTL_SWZCTL (1 << 0) 938 #define TILECTL_TLBPF (1 << 1) 939 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 940 #define TILECTL_BACKSNOOP_DIS (1 << 3) 941 942 /* 943 * Instruction and interrupt control regs 944 */ 945 #define PGTBL_CTL _MMIO(0x02020) 946 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 947 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 948 #define PGTBL_ER _MMIO(0x02024) 949 #define PRB0_BASE (0x2030 - 0x30) 950 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 951 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 952 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 953 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 954 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 955 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 956 #define RENDER_RING_BASE 0x02000 957 #define BSD_RING_BASE 0x04000 958 #define GEN6_BSD_RING_BASE 0x12000 959 #define GEN8_BSD2_RING_BASE 0x1c000 960 #define GEN11_BSD_RING_BASE 0x1c0000 961 #define GEN11_BSD2_RING_BASE 0x1c4000 962 #define GEN11_BSD3_RING_BASE 0x1d0000 963 #define GEN11_BSD4_RING_BASE 0x1d4000 964 #define XEHP_BSD5_RING_BASE 0x1e0000 965 #define XEHP_BSD6_RING_BASE 0x1e4000 966 #define XEHP_BSD7_RING_BASE 0x1f0000 967 #define XEHP_BSD8_RING_BASE 0x1f4000 968 #define VEBOX_RING_BASE 0x1a000 969 #define GEN11_VEBOX_RING_BASE 0x1c8000 970 #define GEN11_VEBOX2_RING_BASE 0x1d8000 971 #define XEHP_VEBOX3_RING_BASE 0x1e8000 972 #define XEHP_VEBOX4_RING_BASE 0x1f8000 973 #define GEN12_COMPUTE0_RING_BASE 0x1a000 974 #define GEN12_COMPUTE1_RING_BASE 0x1c000 975 #define GEN12_COMPUTE2_RING_BASE 0x1e000 976 #define GEN12_COMPUTE3_RING_BASE 0x26000 977 #define BLT_RING_BASE 0x22000 978 #define XEHPC_BCS1_RING_BASE 0x3e0000 979 #define XEHPC_BCS2_RING_BASE 0x3e2000 980 #define XEHPC_BCS3_RING_BASE 0x3e4000 981 #define XEHPC_BCS4_RING_BASE 0x3e6000 982 #define XEHPC_BCS5_RING_BASE 0x3e8000 983 #define XEHPC_BCS6_RING_BASE 0x3ea000 984 #define XEHPC_BCS7_RING_BASE 0x3ec000 985 #define XEHPC_BCS8_RING_BASE 0x3ee000 986 #define DG1_GSC_HECI1_BASE 0x00258000 987 #define DG1_GSC_HECI2_BASE 0x00259000 988 #define DG2_GSC_HECI1_BASE 0x00373000 989 #define DG2_GSC_HECI2_BASE 0x00374000 990 991 992 993 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 994 #define GTT_CACHE_EN_ALL 0xF0007FFF 995 #define GEN7_WR_WATERMARK _MMIO(0x4028) 996 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 997 #define ARB_MODE _MMIO(0x4030) 998 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 999 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 1000 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 1001 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 1002 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 1003 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 1004 #define GEN7_LRA_LIMITS_REG_NUM 13 1005 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 1006 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 1007 1008 #define GEN7_ERR_INT _MMIO(0x44040) 1009 #define ERR_INT_POISON (1 << 31) 1010 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 1011 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 1012 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 1013 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 1014 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 1015 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 1016 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 1017 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 1018 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 1019 1020 #define FPGA_DBG _MMIO(0x42300) 1021 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) 1022 1023 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 1024 #define CLAIM_ER_CLR REG_BIT(31) 1025 #define CLAIM_ER_OVERFLOW REG_BIT(16) 1026 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) 1027 1028 #define DERRMR _MMIO(0x44050) 1029 /* Note that HBLANK events are reserved on bdw+ */ 1030 #define DERRMR_PIPEA_SCANLINE (1 << 0) 1031 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 1032 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 1033 #define DERRMR_PIPEA_VBLANK (1 << 3) 1034 #define DERRMR_PIPEA_HBLANK (1 << 5) 1035 #define DERRMR_PIPEB_SCANLINE (1 << 8) 1036 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 1037 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 1038 #define DERRMR_PIPEB_VBLANK (1 << 11) 1039 #define DERRMR_PIPEB_HBLANK (1 << 13) 1040 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 1041 #define DERRMR_PIPEC_SCANLINE (1 << 14) 1042 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 1043 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 1044 #define DERRMR_PIPEC_VBLANK (1 << 21) 1045 #define DERRMR_PIPEC_HBLANK (1 << 22) 1046 1047 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 1048 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 1049 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 1050 #define SCPD_FBC_IGNORE_3D (1 << 6) 1051 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 1052 #define GEN2_IER _MMIO(0x20a0) 1053 #define GEN2_IIR _MMIO(0x20a4) 1054 #define GEN2_IMR _MMIO(0x20a8) 1055 #define GEN2_ISR _MMIO(0x20ac) 1056 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 1057 #define GINT_DIS (1 << 22) 1058 #define GCFG_DIS (1 << 8) 1059 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 1060 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 1061 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 1062 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 1063 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 1064 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 1065 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 1066 #define VLV_PCBR_ADDR_SHIFT 12 1067 1068 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 1069 #define EIR _MMIO(0x20b0) 1070 #define EMR _MMIO(0x20b4) 1071 #define ESR _MMIO(0x20b8) 1072 #define GM45_ERROR_PAGE_TABLE (1 << 5) 1073 #define GM45_ERROR_MEM_PRIV (1 << 4) 1074 #define I915_ERROR_PAGE_TABLE (1 << 4) 1075 #define GM45_ERROR_CP_PRIV (1 << 3) 1076 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 1077 #define I915_ERROR_INSTRUCTION (1 << 0) 1078 #define INSTPM _MMIO(0x20c0) 1079 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 1080 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 1081 will not assert AGPBUSY# and will only 1082 be delivered when out of C3. */ 1083 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 1084 #define INSTPM_TLB_INVALIDATE (1 << 9) 1085 #define INSTPM_SYNC_FLUSH (1 << 5) 1086 #define MEM_MODE _MMIO(0x20cc) 1087 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 1088 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 1089 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 1090 #define FW_BLC _MMIO(0x20d8) 1091 #define FW_BLC2 _MMIO(0x20dc) 1092 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 1093 #define FW_BLC_SELF_EN_MASK (1 << 31) 1094 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 1095 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 1096 #define MM_BURST_LENGTH 0x00700000 1097 #define MM_FIFO_WATERMARK 0x0001F000 1098 #define LM_BURST_LENGTH 0x00000700 1099 #define LM_FIFO_WATERMARK 0x0000001F 1100 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 1101 1102 #define _MBUS_ABOX0_CTL 0x45038 1103 #define _MBUS_ABOX1_CTL 0x45048 1104 #define _MBUS_ABOX2_CTL 0x4504C 1105 #define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \ 1106 _MBUS_ABOX1_CTL, \ 1107 _MBUS_ABOX2_CTL)) 1108 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 1109 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 1110 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 1111 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 1112 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 1113 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 1114 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 1115 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 1116 1117 #define _PIPEA_MBUS_DBOX_CTL 0x7003C 1118 #define _PIPEB_MBUS_DBOX_CTL 0x7103C 1119 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ 1120 _PIPEB_MBUS_DBOX_CTL) 1121 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */ 1122 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x) 1123 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */ 1124 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x) 1125 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */ 1126 #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14) 1127 #define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x) 1128 #define MBUS_DBOX_BW_4CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x2) 1129 #define MBUS_DBOX_BW_8CREDITS_MTL REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, 0x3) 1130 #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8) 1131 #define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x) 1132 #define MBUS_DBOX_I_CREDIT_MASK REG_GENMASK(7, 5) 1133 #define MBUS_DBOX_I_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_I_CREDIT_MASK, x) 1134 #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0) 1135 #define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x) 1136 1137 #define MBUS_UBOX_CTL _MMIO(0x4503C) 1138 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) 1139 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) 1140 1141 #define MBUS_CTL _MMIO(0x4438C) 1142 #define MBUS_JOIN REG_BIT(31) 1143 #define MBUS_HASHING_MODE_MASK REG_BIT(30) 1144 #define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0) 1145 #define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1) 1146 #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26) 1147 #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe) 1148 #define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7) 1149 1150 #define HDPORT_STATE _MMIO(0x45050) 1151 #define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12) 1152 #define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1) 1153 #define HDPORT_ENABLED REG_BIT(0) 1154 1155 /* Make render/texture TLB fetches lower priorty than associated data 1156 * fetches. This is not turned on by default 1157 */ 1158 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 1159 1160 /* Isoch request wait on GTT enable (Display A/B/C streams). 1161 * Make isoch requests stall on the TLB update. May cause 1162 * display underruns (test mode only) 1163 */ 1164 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 1165 1166 /* Block grant count for isoch requests when block count is 1167 * set to a finite value. 1168 */ 1169 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 1170 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 1171 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 1172 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 1173 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 1174 1175 /* Enable render writes to complete in C2/C3/C4 power states. 1176 * If this isn't enabled, render writes are prevented in low 1177 * power states. That seems bad to me. 1178 */ 1179 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 1180 1181 /* This acknowledges an async flip immediately instead 1182 * of waiting for 2TLB fetches. 1183 */ 1184 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 1185 1186 /* Enables non-sequential data reads through arbiter 1187 */ 1188 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 1189 1190 /* Disable FSB snooping of cacheable write cycles from binner/render 1191 * command stream 1192 */ 1193 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 1194 1195 /* Arbiter time slice for non-isoch streams */ 1196 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 1197 #define MI_ARB_TIME_SLICE_1 (0 << 5) 1198 #define MI_ARB_TIME_SLICE_2 (1 << 5) 1199 #define MI_ARB_TIME_SLICE_4 (2 << 5) 1200 #define MI_ARB_TIME_SLICE_6 (3 << 5) 1201 #define MI_ARB_TIME_SLICE_8 (4 << 5) 1202 #define MI_ARB_TIME_SLICE_10 (5 << 5) 1203 #define MI_ARB_TIME_SLICE_14 (6 << 5) 1204 #define MI_ARB_TIME_SLICE_16 (7 << 5) 1205 1206 /* Low priority grace period page size */ 1207 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 1208 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 1209 1210 /* Disable display A/B trickle feed */ 1211 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 1212 1213 /* Set display plane priority */ 1214 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1215 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1216 1217 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 1218 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 1219 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 1220 1221 /* On modern GEN architectures interrupt control consists of two sets 1222 * of registers. The first set pertains to the ring generating the 1223 * interrupt. The second control is for the functional block generating the 1224 * interrupt. These are PM, GT, DE, etc. 1225 * 1226 * Luckily *knocks on wood* all the ring interrupt bits match up with the 1227 * GT interrupt bits, so we don't need to duplicate the defines. 1228 * 1229 * These defines should cover us well from SNB->HSW with minor exceptions 1230 * it can also work on ILK. 1231 */ 1232 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 1233 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 1234 #define GT_BLT_USER_INTERRUPT (1 << 22) 1235 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 1236 #define GT_BSD_USER_INTERRUPT (1 << 12) 1237 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 1238 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 1239 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 1240 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 1241 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 1242 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 1243 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 1244 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 1245 #define GT_RENDER_USER_INTERRUPT (1 << 0) 1246 1247 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 1248 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 1249 1250 #define GT_PARITY_ERROR(dev_priv) \ 1251 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 1252 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 1253 1254 /* These are all the "old" interrupts */ 1255 #define ILK_BSD_USER_INTERRUPT (1 << 5) 1256 1257 #define I915_PM_INTERRUPT (1 << 31) 1258 #define I915_ISP_INTERRUPT (1 << 22) 1259 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 1260 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 1261 #define I915_MIPIC_INTERRUPT (1 << 19) 1262 #define I915_MIPIA_INTERRUPT (1 << 18) 1263 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 1264 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 1265 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 1266 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 1267 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 1268 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 1269 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 1270 #define I915_HWB_OOM_INTERRUPT (1 << 13) 1271 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 1272 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 1273 #define I915_MISC_INTERRUPT (1 << 11) 1274 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 1275 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 1276 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 1277 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 1278 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 1279 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 1280 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 1281 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 1282 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 1283 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 1284 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 1285 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 1286 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 1287 #define I915_DEBUG_INTERRUPT (1 << 2) 1288 #define I915_WINVALID_INTERRUPT (1 << 1) 1289 #define I915_USER_INTERRUPT (1 << 1) 1290 #define I915_ASLE_INTERRUPT (1 << 0) 1291 #define I915_BSD_USER_INTERRUPT (1 << 25) 1292 1293 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 1294 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 1295 1296 /* DisplayPort Audio w/ LPE */ 1297 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 1298 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 1299 1300 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 1301 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 1302 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 1303 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 1304 _VLV_AUD_PORT_EN_B_DBG, \ 1305 _VLV_AUD_PORT_EN_C_DBG, \ 1306 _VLV_AUD_PORT_EN_D_DBG) 1307 #define VLV_AMP_MUTE (1 << 1) 1308 1309 #define GEN6_BSD_RNCID _MMIO(0x12198) 1310 1311 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 1312 #define GEN7_FF_SCHED_MASK 0x0077070 1313 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 1314 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 1315 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 1316 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 1317 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 1318 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 1319 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 1320 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 1321 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 1322 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 1323 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 1324 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 1325 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 1326 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 1327 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 1328 1329 /* 1330 * Framebuffer compression (915+ only) 1331 */ 1332 1333 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 1334 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 1335 #define FBC_CONTROL _MMIO(0x3208) 1336 #define FBC_CTL_EN REG_BIT(31) 1337 #define FBC_CTL_PERIODIC REG_BIT(30) 1338 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) 1339 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) 1340 #define FBC_CTL_STOP_ON_MOD REG_BIT(15) 1341 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ 1342 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ 1343 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) 1344 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) 1345 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1346 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) 1347 #define FBC_COMMAND _MMIO(0x320c) 1348 #define FBC_CMD_COMPRESS REG_BIT(0) 1349 #define FBC_STATUS _MMIO(0x3210) 1350 #define FBC_STAT_COMPRESSING REG_BIT(31) 1351 #define FBC_STAT_COMPRESSED REG_BIT(30) 1352 #define FBC_STAT_MODIFIED REG_BIT(29) 1353 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) 1354 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ 1355 #define FBC_CTL_FENCE_DBL REG_BIT(4) 1356 #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) 1357 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) 1358 #define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) 1359 #define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) 1360 #define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) 1361 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1) 1362 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) 1363 #define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) 1364 #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ 1365 #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ 1366 #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) 1367 #define FBC_MOD_NUM_VALID REG_BIT(0) 1368 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ 1369 #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ 1370 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) 1371 #define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) 1372 #define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) 1373 #define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) 1374 1375 #define FBC_LL_SIZE (1536) 1376 1377 /* Framebuffer compression for GM45+ */ 1378 #define DPFC_CB_BASE _MMIO(0x3200) 1379 #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) 1380 #define DPFC_CONTROL _MMIO(0x3208) 1381 #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) 1382 #define DPFC_CTL_EN REG_BIT(31) 1383 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ 1384 #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) 1385 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */ 1386 #define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ 1387 #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) 1388 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ 1389 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ 1390 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ 1391 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ 1392 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ 1393 #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6) 1394 #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0) 1395 #define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1) 1396 #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2) 1397 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1398 #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence)) 1399 #define DPFC_RECOMP_CTL _MMIO(0x320c) 1400 #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c) 1401 #define DPFC_RECOMP_STALL_EN REG_BIT(27) 1402 #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16) 1403 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0) 1404 #define DPFC_STATUS _MMIO(0x3210) 1405 #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250) 1406 #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16) 1407 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0) 1408 #define DPFC_STATUS2 _MMIO(0x3214) 1409 #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254) 1410 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0) 1411 #define DPFC_FENCE_YOFF _MMIO(0x3218) 1412 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) 1413 #define DPFC_CHICKEN _MMIO(0x3224) 1414 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) 1415 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ 1416 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ 1417 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */ 1418 #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */ 1419 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */ 1420 1421 #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268) 1422 #define FBC_STRIDE_OVERRIDE REG_BIT(15) 1423 #define FBC_STRIDE_MASK REG_GENMASK(14, 0) 1424 #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) 1425 1426 #define ILK_FBC_RT_BASE _MMIO(0x2128) 1427 #define ILK_FBC_RT_VALID REG_BIT(0) 1428 #define SNB_FBC_FRONT_BUFFER REG_BIT(1) 1429 1430 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 1431 #define ILK_FBCQ_DIS (1 << 22) 1432 #define ILK_PABSTRETCH_DIS REG_BIT(21) 1433 #define ILK_SABSTRETCH_DIS REG_BIT(20) 1434 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) 1435 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) 1436 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) 1437 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) 1438 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) 1439 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) 1440 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) 1441 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) 1442 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) 1443 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) 1444 1445 1446 /* 1447 * Framebuffer compression for Sandybridge 1448 * 1449 * The following two registers are of type GTTMMADR 1450 */ 1451 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 1452 #define SNB_DPFC_FENCE_EN REG_BIT(29) 1453 #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0) 1454 #define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence)) 1455 #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 1456 1457 /* Framebuffer compression for Ivybridge */ 1458 #define IVB_FBC_RT_BASE _MMIO(0x7020) 1459 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) 1460 1461 #define IPS_CTL _MMIO(0x43408) 1462 #define IPS_ENABLE (1 << 31) 1463 1464 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384) 1465 #define FBC_REND_NUKE REG_BIT(2) 1466 #define FBC_REND_CACHE_CLEAN REG_BIT(1) 1467 1468 /* 1469 * Clock control & power management 1470 */ 1471 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) 1472 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) 1473 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) 1474 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 1475 1476 #define VGA0 _MMIO(0x6000) 1477 #define VGA1 _MMIO(0x6004) 1478 #define VGA_PD _MMIO(0x6010) 1479 #define VGA0_PD_P2_DIV_4 (1 << 7) 1480 #define VGA0_PD_P1_DIV_2 (1 << 5) 1481 #define VGA0_PD_P1_SHIFT 0 1482 #define VGA0_PD_P1_MASK (0x1f << 0) 1483 #define VGA1_PD_P2_DIV_4 (1 << 15) 1484 #define VGA1_PD_P1_DIV_2 (1 << 13) 1485 #define VGA1_PD_P1_SHIFT 8 1486 #define VGA1_PD_P1_MASK (0x1f << 8) 1487 #define DPLL_VCO_ENABLE (1 << 31) 1488 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 1489 #define DPLL_DVO_2X_MODE (1 << 30) 1490 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 1491 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 1492 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 1493 #define DPLL_VGA_MODE_DIS (1 << 28) 1494 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 1495 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 1496 #define DPLL_MODE_MASK (3 << 26) 1497 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 1498 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 1499 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 1500 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 1501 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 1502 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 1503 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 1504 #define DPLL_LOCK_VLV (1 << 15) 1505 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 1506 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 1507 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 1508 #define DPLL_PORTC_READY_MASK (0xf << 4) 1509 #define DPLL_PORTB_READY_MASK (0xf) 1510 1511 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 1512 1513 /* Additional CHV pll/phy registers */ 1514 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 1515 #define DPLL_PORTD_READY_MASK (0xf) 1516 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 1517 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 1518 #define PHY_LDO_DELAY_0NS 0x0 1519 #define PHY_LDO_DELAY_200NS 0x1 1520 #define PHY_LDO_DELAY_600NS 0x2 1521 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 1522 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 1523 #define PHY_CH_SU_PSR 0x1 1524 #define PHY_CH_DEEP_PSR 0x7 1525 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 1526 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 1527 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 1528 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 1529 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 1530 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 1531 1532 /* 1533 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1534 * this field (only one bit may be set). 1535 */ 1536 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 1537 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 1538 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 1539 /* i830, required in DVO non-gang */ 1540 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 1541 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 1542 #define PLL_REF_INPUT_DREFCLK (0 << 13) 1543 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 1544 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 1545 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 1546 #define PLL_REF_INPUT_MASK (3 << 13) 1547 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 1548 /* Ironlake */ 1549 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 1550 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 1551 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 1552 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 1553 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 1554 1555 /* 1556 * Parallel to Serial Load Pulse phase selection. 1557 * Selects the phase for the 10X DPLL clock for the PCIe 1558 * digital display port. The range is 4 to 13; 10 or more 1559 * is just a flip delay. The default is 6 1560 */ 1561 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1562 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1563 /* 1564 * SDVO multiplier for 945G/GM. Not used on 965. 1565 */ 1566 #define SDVO_MULTIPLIER_MASK 0x000000ff 1567 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 1568 #define SDVO_MULTIPLIER_SHIFT_VGA 0 1569 1570 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) 1571 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) 1572 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) 1573 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 1574 1575 /* 1576 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1577 * 1578 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1579 */ 1580 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1581 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 1582 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1583 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1584 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1585 /* 1586 * SDVO/UDI pixel multiplier. 1587 * 1588 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1589 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1590 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1591 * dummy bytes in the datastream at an increased clock rate, with both sides of 1592 * the link knowing how many bytes are fill. 1593 * 1594 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1595 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1596 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1597 * through an SDVO command. 1598 * 1599 * This register field has values of multiplication factor minus 1, with 1600 * a maximum multiplier of 5 for SDVO. 1601 */ 1602 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1603 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1604 /* 1605 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1606 * This best be set to the default value (3) or the CRT won't work. No, 1607 * I don't entirely understand what this does... 1608 */ 1609 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1610 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1611 1612 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 1613 1614 #define _FPA0 0x6040 1615 #define _FPA1 0x6044 1616 #define _FPB0 0x6048 1617 #define _FPB1 0x604c 1618 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 1619 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 1620 #define FP_N_DIV_MASK 0x003f0000 1621 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1622 #define FP_N_DIV_SHIFT 16 1623 #define FP_M1_DIV_MASK 0x00003f00 1624 #define FP_M1_DIV_SHIFT 8 1625 #define FP_M2_DIV_MASK 0x0000003f 1626 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1627 #define FP_M2_DIV_SHIFT 0 1628 #define DPLL_TEST _MMIO(0x606c) 1629 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1630 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1631 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1632 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1633 #define DPLLB_TEST_N_BYPASS (1 << 19) 1634 #define DPLLB_TEST_M_BYPASS (1 << 18) 1635 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1636 #define DPLLA_TEST_N_BYPASS (1 << 3) 1637 #define DPLLA_TEST_M_BYPASS (1 << 2) 1638 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1639 #define D_STATE _MMIO(0x6104) 1640 #define DSTATE_GFX_RESET_I830 (1 << 6) 1641 #define DSTATE_PLL_D3_OFF (1 << 3) 1642 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 1643 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 1644 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200) 1645 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1646 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1647 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1648 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1649 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1650 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1651 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1652 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 1653 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1654 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1655 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1656 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1657 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1658 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1659 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1660 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1661 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1662 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1663 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1664 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1665 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1666 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1667 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1668 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1669 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1670 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1671 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1672 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1673 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1674 /* 1675 * This bit must be set on the 830 to prevent hangs when turning off the 1676 * overlay scaler. 1677 */ 1678 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1679 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1680 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1681 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1682 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1683 1684 #define RENCLK_GATE_D1 _MMIO(0x6204) 1685 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1686 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1687 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1688 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1689 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1690 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1691 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1692 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1693 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1694 /* This bit must be unset on 855,865 */ 1695 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1696 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1697 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1698 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1699 /* This bit must be set on 855,865. */ 1700 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1701 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1702 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1703 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1704 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1705 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1706 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1707 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1708 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1709 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1710 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1711 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1712 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1713 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1714 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1715 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1716 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1717 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1718 1719 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1720 /* This bit must always be set on 965G/965GM */ 1721 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1722 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1723 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1724 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1725 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1726 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1727 /* This bit must always be set on 965G */ 1728 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1729 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1730 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1731 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1732 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1733 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1734 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1735 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1736 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1737 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1738 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1739 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1740 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1741 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1742 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1743 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1744 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1745 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1746 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1747 1748 #define RENCLK_GATE_D2 _MMIO(0x6208) 1749 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1750 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1751 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1752 1753 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 1754 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 1755 1756 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 1757 #define DEUC _MMIO(0x6214) /* CRL only */ 1758 1759 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 1760 #define FW_CSPWRDWNEN (1 << 15) 1761 1762 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 1763 1764 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 1765 #define CDCLK_FREQ_SHIFT 4 1766 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 1767 #define CZCLK_FREQ_MASK 0xf 1768 1769 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 1770 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 1771 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 1772 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 1773 #define PFI_CREDIT_RESEND (1 << 27) 1774 #define VGA_FAST_MODE_DISABLE (1 << 14) 1775 1776 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 1777 1778 /* 1779 * Palette regs 1780 */ 1781 #define _PALETTE_A 0xa000 1782 #define _PALETTE_B 0xa800 1783 #define _CHV_PALETTE_C 0xc000 1784 #define PALETTE_RED_MASK REG_GENMASK(23, 16) 1785 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8) 1786 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0) 1787 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ 1788 _PICK((pipe), _PALETTE_A, \ 1789 _PALETTE_B, _CHV_PALETTE_C) + \ 1790 (i) * 4) 1791 1792 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 1793 1794 #define BXT_RP_STATE_CAP _MMIO(0x138170) 1795 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 1796 #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014) 1797 #define PVC_RP_STATE_CAP _MMIO(0x281014) 1798 1799 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) 1800 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 1801 #define PROCHOT_MASK REG_BIT(0) 1802 #define THERMAL_LIMIT_MASK REG_BIT(1) 1803 #define RATL_MASK REG_BIT(5) 1804 #define VR_THERMALERT_MASK REG_BIT(6) 1805 #define VR_TDC_MASK REG_BIT(7) 1806 #define POWER_LIMIT_4_MASK REG_BIT(8) 1807 #define POWER_LIMIT_1_MASK REG_BIT(10) 1808 #define POWER_LIMIT_2_MASK REG_BIT(11) 1809 1810 #define CHV_CLK_CTL1 _MMIO(0x101100) 1811 #define VLV_CLK_CTL2 _MMIO(0x101104) 1812 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 1813 1814 /* 1815 * Overlay regs 1816 */ 1817 1818 #define OVADD _MMIO(0x30000) 1819 #define DOVSTA _MMIO(0x30008) 1820 #define OC_BUF (0x3 << 20) 1821 #define OGAMC5 _MMIO(0x30010) 1822 #define OGAMC4 _MMIO(0x30014) 1823 #define OGAMC3 _MMIO(0x30018) 1824 #define OGAMC2 _MMIO(0x3001c) 1825 #define OGAMC1 _MMIO(0x30020) 1826 #define OGAMC0 _MMIO(0x30024) 1827 1828 /* 1829 * GEN9 clock gating regs 1830 */ 1831 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 1832 #define DARBF_GATING_DIS (1 << 27) 1833 #define PWM2_GATING_DIS (1 << 14) 1834 #define PWM1_GATING_DIS (1 << 13) 1835 1836 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) 1837 #define TGL_VRH_GATING_DIS REG_BIT(31) 1838 #define DPT_GATING_DIS REG_BIT(22) 1839 1840 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 1841 #define BXT_GMBUS_GATING_DIS (1 << 14) 1842 1843 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) 1844 #define DPCE_GATING_DIS REG_BIT(17) 1845 1846 #define _CLKGATE_DIS_PSL_A 0x46520 1847 #define _CLKGATE_DIS_PSL_B 0x46524 1848 #define _CLKGATE_DIS_PSL_C 0x46528 1849 #define DUPS1_GATING_DIS (1 << 15) 1850 #define DUPS2_GATING_DIS (1 << 19) 1851 #define DUPS3_GATING_DIS (1 << 23) 1852 #define CURSOR_GATING_DIS REG_BIT(28) 1853 #define DPF_GATING_DIS (1 << 10) 1854 #define DPF_RAM_GATING_DIS (1 << 9) 1855 #define DPFR_GATING_DIS (1 << 8) 1856 1857 #define CLKGATE_DIS_PSL(pipe) \ 1858 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 1859 1860 #define _CLKGATE_DIS_PSL_EXT_A 0x4654C 1861 #define _CLKGATE_DIS_PSL_EXT_B 0x46550 1862 #define PIPEDMC_GATING_DIS REG_BIT(12) 1863 1864 #define CLKGATE_DIS_PSL_EXT(pipe) \ 1865 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B) 1866 1867 /* 1868 * Display engine regs 1869 */ 1870 1871 /* Pipe A CRC regs */ 1872 #define _PIPE_CRC_CTL_A 0x60050 1873 #define PIPE_CRC_ENABLE REG_BIT(31) 1874 /* skl+ source selection */ 1875 #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) 1876 #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) 1877 #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) 1878 #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) 1879 #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) 1880 #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) 1881 #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) 1882 #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) 1883 #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) 1884 /* ivb+ source selection */ 1885 #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) 1886 #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) 1887 #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) 1888 #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) 1889 /* ilk+ source selection */ 1890 #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) 1891 #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) 1892 #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) 1893 #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) 1894 /* embedded DP port on the north display block */ 1895 #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) 1896 #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) 1897 /* vlv source selection */ 1898 #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) 1899 #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) 1900 #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) 1901 #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) 1902 /* with DP port the pipe source is invalid */ 1903 #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) 1904 #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) 1905 #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) 1906 /* gen3+ source selection */ 1907 #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) 1908 #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) 1909 #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) 1910 #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) 1911 /* with DP/TV port the pipe source is invalid */ 1912 #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) 1913 #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) 1914 #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) 1915 #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) 1916 #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) 1917 /* gen2 doesn't have source selection bits */ 1918 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) 1919 1920 #define _PIPE_CRC_RES_1_A_IVB 0x60064 1921 #define _PIPE_CRC_RES_2_A_IVB 0x60068 1922 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 1923 #define _PIPE_CRC_RES_4_A_IVB 0x60070 1924 #define _PIPE_CRC_RES_5_A_IVB 0x60074 1925 1926 #define _PIPE_CRC_RES_RED_A 0x60060 1927 #define _PIPE_CRC_RES_GREEN_A 0x60064 1928 #define _PIPE_CRC_RES_BLUE_A 0x60068 1929 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 1930 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 1931 1932 /* Pipe B CRC regs */ 1933 #define _PIPE_CRC_RES_1_B_IVB 0x61064 1934 #define _PIPE_CRC_RES_2_B_IVB 0x61068 1935 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 1936 #define _PIPE_CRC_RES_4_B_IVB 0x61070 1937 #define _PIPE_CRC_RES_5_B_IVB 0x61074 1938 1939 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 1940 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 1941 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 1942 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 1943 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 1944 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 1945 1946 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 1947 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 1948 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 1949 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 1950 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 1951 1952 /* Pipe A timing regs */ 1953 #define _HTOTAL_A 0x60000 1954 #define _HBLANK_A 0x60004 1955 #define _HSYNC_A 0x60008 1956 #define _VTOTAL_A 0x6000c 1957 #define _VBLANK_A 0x60010 1958 #define _VSYNC_A 0x60014 1959 #define _EXITLINE_A 0x60018 1960 #define _PIPEASRC 0x6001c 1961 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) 1962 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) 1963 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) 1964 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) 1965 #define _BCLRPAT_A 0x60020 1966 #define _VSYNCSHIFT_A 0x60028 1967 #define _PIPE_MULT_A 0x6002c 1968 1969 /* Pipe B timing regs */ 1970 #define _HTOTAL_B 0x61000 1971 #define _HBLANK_B 0x61004 1972 #define _HSYNC_B 0x61008 1973 #define _VTOTAL_B 0x6100c 1974 #define _VBLANK_B 0x61010 1975 #define _VSYNC_B 0x61014 1976 #define _PIPEBSRC 0x6101c 1977 #define _BCLRPAT_B 0x61020 1978 #define _VSYNCSHIFT_B 0x61028 1979 #define _PIPE_MULT_B 0x6102c 1980 1981 /* DSI 0 timing regs */ 1982 #define _HTOTAL_DSI0 0x6b000 1983 #define _HSYNC_DSI0 0x6b008 1984 #define _VTOTAL_DSI0 0x6b00c 1985 #define _VSYNC_DSI0 0x6b014 1986 #define _VSYNCSHIFT_DSI0 0x6b028 1987 1988 /* DSI 1 timing regs */ 1989 #define _HTOTAL_DSI1 0x6b800 1990 #define _HSYNC_DSI1 0x6b808 1991 #define _VTOTAL_DSI1 0x6b80c 1992 #define _VSYNC_DSI1 0x6b814 1993 #define _VSYNCSHIFT_DSI1 0x6b828 1994 1995 #define TRANSCODER_A_OFFSET 0x60000 1996 #define TRANSCODER_B_OFFSET 0x61000 1997 #define TRANSCODER_C_OFFSET 0x62000 1998 #define CHV_TRANSCODER_C_OFFSET 0x63000 1999 #define TRANSCODER_D_OFFSET 0x63000 2000 #define TRANSCODER_EDP_OFFSET 0x6f000 2001 #define TRANSCODER_DSI0_OFFSET 0x6b000 2002 #define TRANSCODER_DSI1_OFFSET 0x6b800 2003 2004 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 2005 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 2006 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 2007 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 2008 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 2009 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 2010 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 2011 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 2012 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 2013 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 2014 2015 #define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) 2016 #define EXITLINE_ENABLE REG_BIT(31) 2017 #define EXITLINE_MASK REG_GENMASK(12, 0) 2018 #define EXITLINE_SHIFT 0 2019 2020 /* VRR registers */ 2021 #define _TRANS_VRR_CTL_A 0x60420 2022 #define _TRANS_VRR_CTL_B 0x61420 2023 #define _TRANS_VRR_CTL_C 0x62420 2024 #define _TRANS_VRR_CTL_D 0x63420 2025 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) 2026 #define VRR_CTL_VRR_ENABLE REG_BIT(31) 2027 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) 2028 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) 2029 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) 2030 #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) 2031 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) 2032 #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) 2033 #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) 2034 2035 #define _TRANS_VRR_VMAX_A 0x60424 2036 #define _TRANS_VRR_VMAX_B 0x61424 2037 #define _TRANS_VRR_VMAX_C 0x62424 2038 #define _TRANS_VRR_VMAX_D 0x63424 2039 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A) 2040 #define VRR_VMAX_MASK REG_GENMASK(19, 0) 2041 2042 #define _TRANS_VRR_VMIN_A 0x60434 2043 #define _TRANS_VRR_VMIN_B 0x61434 2044 #define _TRANS_VRR_VMIN_C 0x62434 2045 #define _TRANS_VRR_VMIN_D 0x63434 2046 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A) 2047 #define VRR_VMIN_MASK REG_GENMASK(15, 0) 2048 2049 #define _TRANS_VRR_VMAXSHIFT_A 0x60428 2050 #define _TRANS_VRR_VMAXSHIFT_B 0x61428 2051 #define _TRANS_VRR_VMAXSHIFT_C 0x62428 2052 #define _TRANS_VRR_VMAXSHIFT_D 0x63428 2053 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \ 2054 _TRANS_VRR_VMAXSHIFT_A) 2055 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) 2056 #define VRR_VMAXSHIFT_DEC REG_BIT(16) 2057 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) 2058 2059 #define _TRANS_VRR_STATUS_A 0x6042C 2060 #define _TRANS_VRR_STATUS_B 0x6142C 2061 #define _TRANS_VRR_STATUS_C 0x6242C 2062 #define _TRANS_VRR_STATUS_D 0x6342C 2063 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A) 2064 #define VRR_STATUS_VMAX_REACHED REG_BIT(31) 2065 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) 2066 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) 2067 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) 2068 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) 2069 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) 2070 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) 2071 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) 2072 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) 2073 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) 2074 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) 2075 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) 2076 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) 2077 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) 2078 2079 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480 2080 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 2081 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 2082 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 2083 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \ 2084 _TRANS_VRR_VTOTAL_PREV_A) 2085 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) 2086 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) 2087 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) 2088 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) 2089 2090 #define _TRANS_VRR_FLIPLINE_A 0x60438 2091 #define _TRANS_VRR_FLIPLINE_B 0x61438 2092 #define _TRANS_VRR_FLIPLINE_C 0x62438 2093 #define _TRANS_VRR_FLIPLINE_D 0x63438 2094 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \ 2095 _TRANS_VRR_FLIPLINE_A) 2096 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) 2097 2098 #define _TRANS_VRR_STATUS2_A 0x6043C 2099 #define _TRANS_VRR_STATUS2_B 0x6143C 2100 #define _TRANS_VRR_STATUS2_C 0x6243C 2101 #define _TRANS_VRR_STATUS2_D 0x6343C 2102 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) 2103 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) 2104 2105 #define _TRANS_PUSH_A 0x60A70 2106 #define _TRANS_PUSH_B 0x61A70 2107 #define _TRANS_PUSH_C 0x62A70 2108 #define _TRANS_PUSH_D 0x63A70 2109 #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A) 2110 #define TRANS_PUSH_EN REG_BIT(31) 2111 #define TRANS_PUSH_SEND REG_BIT(30) 2112 2113 /* 2114 * HSW+ eDP PSR registers 2115 * 2116 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one 2117 * instance of it 2118 */ 2119 #define _SRD_CTL_A 0x60800 2120 #define _SRD_CTL_EDP 0x6f800 2121 #define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A) 2122 #define EDP_PSR_ENABLE (1 << 31) 2123 #define BDW_PSR_SINGLE_FRAME (1 << 30) 2124 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */ 2125 #define EDP_PSR_LINK_STANDBY (1 << 27) 2126 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25) 2127 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25) 2128 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25) 2129 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25) 2130 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25) 2131 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 2132 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12) 2133 #define EDP_PSR_TP1_TP2_SEL (0 << 11) 2134 #define EDP_PSR_TP1_TP3_SEL (1 << 11) 2135 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */ 2136 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8) 2137 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) 2138 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) 2139 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) 2140 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */ 2141 #define EDP_PSR_TP1_TIME_500us (0 << 4) 2142 #define EDP_PSR_TP1_TIME_100us (1 << 4) 2143 #define EDP_PSR_TP1_TIME_2500us (2 << 4) 2144 #define EDP_PSR_TP1_TIME_0us (3 << 4) 2145 #define EDP_PSR_IDLE_FRAME_SHIFT 0 2146 2147 /* 2148 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative 2149 * to transcoder and bits defined for each one as if using no shift (i.e. as if 2150 * it was for TRANSCODER_EDP) 2151 */ 2152 #define EDP_PSR_IMR _MMIO(0x64834) 2153 #define EDP_PSR_IIR _MMIO(0x64838) 2154 #define _PSR_IMR_A 0x60814 2155 #define _PSR_IIR_A 0x60818 2156 #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) 2157 #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) 2158 #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 2159 0 : ((trans) - TRANSCODER_A + 1) * 8) 2160 #define TGL_PSR_MASK REG_GENMASK(2, 0) 2161 #define TGL_PSR_ERROR REG_BIT(2) 2162 #define TGL_PSR_POST_EXIT REG_BIT(1) 2163 #define TGL_PSR_PRE_ENTRY REG_BIT(0) 2164 #define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \ 2165 _EDP_PSR_TRANS_SHIFT(trans)) 2166 #define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \ 2167 _EDP_PSR_TRANS_SHIFT(trans)) 2168 #define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \ 2169 _EDP_PSR_TRANS_SHIFT(trans)) 2170 #define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \ 2171 _EDP_PSR_TRANS_SHIFT(trans)) 2172 2173 #define _SRD_AUX_DATA_A 0x60814 2174 #define _SRD_AUX_DATA_EDP 0x6f814 2175 #define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */ 2176 2177 #define _SRD_STATUS_A 0x60840 2178 #define _SRD_STATUS_EDP 0x6f840 2179 #define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A) 2180 #define EDP_PSR_STATUS_STATE_MASK (7 << 29) 2181 #define EDP_PSR_STATUS_STATE_SHIFT 29 2182 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29) 2183 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29) 2184 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29) 2185 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29) 2186 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29) 2187 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29) 2188 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29) 2189 #define EDP_PSR_STATUS_LINK_MASK (3 << 26) 2190 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26) 2191 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26) 2192 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26) 2193 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 2194 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 2195 #define EDP_PSR_STATUS_COUNT_SHIFT 16 2196 #define EDP_PSR_STATUS_COUNT_MASK 0xf 2197 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15) 2198 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12) 2199 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9) 2200 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8) 2201 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4) 2202 #define EDP_PSR_STATUS_IDLE_MASK 0xf 2203 2204 #define _SRD_PERF_CNT_A 0x60844 2205 #define _SRD_PERF_CNT_EDP 0x6f844 2206 #define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A) 2207 #define EDP_PSR_PERF_CNT_MASK 0xffffff 2208 2209 /* PSR_MASK on SKL+ */ 2210 #define _SRD_DEBUG_A 0x60860 2211 #define _SRD_DEBUG_EDP 0x6f860 2212 #define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A) 2213 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28) 2214 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) 2215 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) 2216 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25) 2217 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ 2218 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ 2219 2220 #define _PSR2_CTL_A 0x60900 2221 #define _PSR2_CTL_EDP 0x6f900 2222 #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) 2223 #define EDP_PSR2_ENABLE (1 << 31) 2224 #define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */ 2225 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) 2226 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) 2227 #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */ 2228 #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */ 2229 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) 2230 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) 2231 #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 2232 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) 2233 #define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) 2234 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 2235 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT 13 2236 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT) 2237 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) 2238 #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 2239 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) 2240 #define EDP_PSR2_FAST_WAKE_MASK (3 << 11) 2241 #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 2242 #define TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT 10 2243 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT) 2244 #define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) 2245 #define EDP_PSR2_TP2_TIME_500us (0 << 8) 2246 #define EDP_PSR2_TP2_TIME_100us (1 << 8) 2247 #define EDP_PSR2_TP2_TIME_2500us (2 << 8) 2248 #define EDP_PSR2_TP2_TIME_50us (3 << 8) 2249 #define EDP_PSR2_TP2_TIME_MASK (3 << 8) 2250 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 2251 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) 2252 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) 2253 #define EDP_PSR2_IDLE_FRAME_MASK 0xf 2254 #define EDP_PSR2_IDLE_FRAME_SHIFT 0 2255 2256 #define _PSR_EVENT_TRANS_A 0x60848 2257 #define _PSR_EVENT_TRANS_B 0x61848 2258 #define _PSR_EVENT_TRANS_C 0x62848 2259 #define _PSR_EVENT_TRANS_D 0x63848 2260 #define _PSR_EVENT_TRANS_EDP 0x6f848 2261 #define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A) 2262 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) 2263 #define PSR_EVENT_PSR2_DISABLED (1 << 16) 2264 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) 2265 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14) 2266 #define PSR_EVENT_GRAPHICS_RESET (1 << 12) 2267 #define PSR_EVENT_PCH_INTERRUPT (1 << 11) 2268 #define PSR_EVENT_MEMORY_UP (1 << 10) 2269 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) 2270 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) 2271 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) 2272 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */ 2273 #define PSR_EVENT_HDCP_ENABLE (1 << 4) 2274 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) 2275 #define PSR_EVENT_VBI_ENABLE (1 << 2) 2276 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1) 2277 #define PSR_EVENT_PSR_DISABLE (1 << 0) 2278 2279 #define _PSR2_STATUS_A 0x60940 2280 #define _PSR2_STATUS_EDP 0x6f940 2281 #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A) 2282 #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28) 2283 #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8) 2284 2285 #define _PSR2_SU_STATUS_A 0x60914 2286 #define _PSR2_SU_STATUS_EDP 0x6f914 2287 #define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4) 2288 #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) 2289 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) 2290 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) 2291 #define PSR2_SU_STATUS_FRAMES 8 2292 2293 #define _PSR2_MAN_TRK_CTL_A 0x60910 2294 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910 2295 #define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) 2296 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) 2297 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) 2298 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 2299 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11) 2300 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 2301 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) 2302 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) 2303 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) 2304 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16) 2305 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 2306 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0) 2307 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 2308 #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31) 2309 #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14) 2310 #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13) 2311 2312 /* Icelake DSC Rate Control Range Parameter Registers */ 2313 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) 2314 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) 2315 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) 2316 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) 2317 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) 2318 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) 2319 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) 2320 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) 2321 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) 2322 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) 2323 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) 2324 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) 2325 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2326 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ 2327 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) 2328 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2329 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ 2330 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) 2331 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2332 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ 2333 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) 2334 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2335 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ 2336 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) 2337 #define RC_BPG_OFFSET_SHIFT 10 2338 #define RC_MAX_QP_SHIFT 5 2339 #define RC_MIN_QP_SHIFT 0 2340 2341 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) 2342 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) 2343 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) 2344 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) 2345 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) 2346 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) 2347 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) 2348 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) 2349 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) 2350 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) 2351 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) 2352 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) 2353 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2354 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ 2355 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) 2356 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2357 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ 2358 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) 2359 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2360 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ 2361 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) 2362 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2363 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ 2364 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) 2365 2366 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) 2367 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) 2368 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) 2369 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) 2370 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) 2371 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) 2372 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) 2373 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) 2374 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) 2375 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) 2376 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) 2377 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) 2378 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2379 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ 2380 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) 2381 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2382 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ 2383 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) 2384 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2385 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ 2386 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) 2387 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2388 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ 2389 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) 2390 2391 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) 2392 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) 2393 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) 2394 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) 2395 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) 2396 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) 2397 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) 2398 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) 2399 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) 2400 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) 2401 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) 2402 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) 2403 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2404 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ 2405 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) 2406 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2407 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ 2408 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) 2409 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2410 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ 2411 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) 2412 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2413 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ 2414 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) 2415 2416 /* VGA port control */ 2417 #define ADPA _MMIO(0x61100) 2418 #define PCH_ADPA _MMIO(0xe1100) 2419 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 2420 2421 #define ADPA_DAC_ENABLE (1 << 31) 2422 #define ADPA_DAC_DISABLE 0 2423 #define ADPA_PIPE_SEL_SHIFT 30 2424 #define ADPA_PIPE_SEL_MASK (1 << 30) 2425 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 2426 #define ADPA_PIPE_SEL_SHIFT_CPT 29 2427 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 2428 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2429 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 2430 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 2431 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 2432 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 2433 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 2434 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 2435 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 2436 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 2437 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 2438 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 2439 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 2440 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 2441 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 2442 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 2443 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 2444 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 2445 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 2446 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 2447 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 2448 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 2449 #define ADPA_SETS_HVPOLARITY 0 2450 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 2451 #define ADPA_VSYNC_CNTL_ENABLE 0 2452 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 2453 #define ADPA_HSYNC_CNTL_ENABLE 0 2454 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 2455 #define ADPA_VSYNC_ACTIVE_LOW 0 2456 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 2457 #define ADPA_HSYNC_ACTIVE_LOW 0 2458 #define ADPA_DPMS_MASK (~(3 << 10)) 2459 #define ADPA_DPMS_ON (0 << 10) 2460 #define ADPA_DPMS_SUSPEND (1 << 10) 2461 #define ADPA_DPMS_STANDBY (2 << 10) 2462 #define ADPA_DPMS_OFF (3 << 10) 2463 2464 2465 /* Hotplug control (945+ only) */ 2466 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 2467 #define PORTB_HOTPLUG_INT_EN (1 << 29) 2468 #define PORTC_HOTPLUG_INT_EN (1 << 28) 2469 #define PORTD_HOTPLUG_INT_EN (1 << 27) 2470 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 2471 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 2472 #define TV_HOTPLUG_INT_EN (1 << 18) 2473 #define CRT_HOTPLUG_INT_EN (1 << 9) 2474 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 2475 PORTC_HOTPLUG_INT_EN | \ 2476 PORTD_HOTPLUG_INT_EN | \ 2477 SDVOC_HOTPLUG_INT_EN | \ 2478 SDVOB_HOTPLUG_INT_EN | \ 2479 CRT_HOTPLUG_INT_EN) 2480 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 2481 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 2482 /* must use period 64 on GM45 according to docs */ 2483 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 2484 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 2485 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 2486 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 2487 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 2488 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 2489 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 2490 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 2491 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 2492 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 2493 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 2494 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 2495 2496 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 2497 /* 2498 * HDMI/DP bits are g4x+ 2499 * 2500 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 2501 * Please check the detailed lore in the commit message for for experimental 2502 * evidence. 2503 */ 2504 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 2505 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 2506 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 2507 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 2508 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 2509 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 2510 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 2511 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 2512 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 2513 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 2514 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 2515 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 2516 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 2517 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 2518 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 2519 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 2520 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 2521 /* CRT/TV common between gen3+ */ 2522 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 2523 #define TV_HOTPLUG_INT_STATUS (1 << 10) 2524 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 2525 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 2526 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 2527 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 2528 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 2529 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 2530 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 2531 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 2532 2533 /* SDVO is different across gen3/4 */ 2534 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 2535 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 2536 /* 2537 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 2538 * since reality corrobates that they're the same as on gen3. But keep these 2539 * bits here (and the comment!) to help any other lost wanderers back onto the 2540 * right tracks. 2541 */ 2542 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 2543 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 2544 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 2545 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 2546 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 2547 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 2548 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 2549 PORTB_HOTPLUG_INT_STATUS | \ 2550 PORTC_HOTPLUG_INT_STATUS | \ 2551 PORTD_HOTPLUG_INT_STATUS) 2552 2553 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 2554 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 2555 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 2556 PORTB_HOTPLUG_INT_STATUS | \ 2557 PORTC_HOTPLUG_INT_STATUS | \ 2558 PORTD_HOTPLUG_INT_STATUS) 2559 2560 /* SDVO and HDMI port control. 2561 * The same register may be used for SDVO or HDMI */ 2562 #define _GEN3_SDVOB 0x61140 2563 #define _GEN3_SDVOC 0x61160 2564 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 2565 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 2566 #define GEN4_HDMIB GEN3_SDVOB 2567 #define GEN4_HDMIC GEN3_SDVOC 2568 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 2569 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 2570 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 2571 #define PCH_SDVOB _MMIO(0xe1140) 2572 #define PCH_HDMIB PCH_SDVOB 2573 #define PCH_HDMIC _MMIO(0xe1150) 2574 #define PCH_HDMID _MMIO(0xe1160) 2575 2576 #define PORT_DFT_I9XX _MMIO(0x61150) 2577 #define DC_BALANCE_RESET (1 << 25) 2578 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 2579 #define DC_BALANCE_RESET_VLV (1 << 31) 2580 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 2581 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ 2582 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1) 2583 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0) 2584 2585 /* Gen 3 SDVO bits: */ 2586 #define SDVO_ENABLE (1 << 31) 2587 #define SDVO_PIPE_SEL_SHIFT 30 2588 #define SDVO_PIPE_SEL_MASK (1 << 30) 2589 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 2590 #define SDVO_STALL_SELECT (1 << 29) 2591 #define SDVO_INTERRUPT_ENABLE (1 << 26) 2592 /* 2593 * 915G/GM SDVO pixel multiplier. 2594 * Programmed value is multiplier - 1, up to 5x. 2595 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 2596 */ 2597 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 2598 #define SDVO_PORT_MULTIPLY_SHIFT 23 2599 #define SDVO_PHASE_SELECT_MASK (15 << 19) 2600 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 2601 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 2602 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 2603 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 2604 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 2605 #define SDVO_DETECTED (1 << 2) 2606 /* Bits to be preserved when writing */ 2607 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 2608 SDVO_INTERRUPT_ENABLE) 2609 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 2610 2611 /* Gen 4 SDVO/HDMI bits: */ 2612 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 2613 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 2614 #define SDVO_ENCODING_SDVO (0 << 10) 2615 #define SDVO_ENCODING_HDMI (2 << 10) 2616 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 2617 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 2618 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 2619 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 2620 /* VSYNC/HSYNC bits new with 965, default is to be set */ 2621 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 2622 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 2623 2624 /* Gen 5 (IBX) SDVO/HDMI bits: */ 2625 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 2626 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 2627 2628 /* Gen 6 (CPT) SDVO/HDMI bits: */ 2629 #define SDVO_PIPE_SEL_SHIFT_CPT 29 2630 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 2631 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2632 2633 /* CHV SDVO/HDMI bits: */ 2634 #define SDVO_PIPE_SEL_SHIFT_CHV 24 2635 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 2636 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 2637 2638 2639 /* DVO port control */ 2640 #define _DVOA 0x61120 2641 #define DVOA _MMIO(_DVOA) 2642 #define _DVOB 0x61140 2643 #define DVOB _MMIO(_DVOB) 2644 #define _DVOC 0x61160 2645 #define DVOC _MMIO(_DVOC) 2646 #define DVO_ENABLE (1 << 31) 2647 #define DVO_PIPE_SEL_SHIFT 30 2648 #define DVO_PIPE_SEL_MASK (1 << 30) 2649 #define DVO_PIPE_SEL(pipe) ((pipe) << 30) 2650 #define DVO_PIPE_STALL_UNUSED (0 << 28) 2651 #define DVO_PIPE_STALL (1 << 28) 2652 #define DVO_PIPE_STALL_TV (2 << 28) 2653 #define DVO_PIPE_STALL_MASK (3 << 28) 2654 #define DVO_USE_VGA_SYNC (1 << 15) 2655 #define DVO_DATA_ORDER_I740 (0 << 14) 2656 #define DVO_DATA_ORDER_FP (1 << 14) 2657 #define DVO_VSYNC_DISABLE (1 << 11) 2658 #define DVO_HSYNC_DISABLE (1 << 10) 2659 #define DVO_VSYNC_TRISTATE (1 << 9) 2660 #define DVO_HSYNC_TRISTATE (1 << 8) 2661 #define DVO_BORDER_ENABLE (1 << 7) 2662 #define DVO_DATA_ORDER_GBRG (1 << 6) 2663 #define DVO_DATA_ORDER_RGGB (0 << 6) 2664 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 2665 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 2666 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 2667 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 2668 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 2669 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 2670 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 2671 #define DVO_PRESERVE_MASK (0x7 << 24) 2672 #define DVOA_SRCDIM _MMIO(0x61124) 2673 #define DVOB_SRCDIM _MMIO(0x61144) 2674 #define DVOC_SRCDIM _MMIO(0x61164) 2675 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 2676 #define DVO_SRCDIM_VERTICAL_SHIFT 0 2677 2678 /* LVDS port control */ 2679 #define LVDS _MMIO(0x61180) 2680 /* 2681 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 2682 * the DPLL semantics change when the LVDS is assigned to that pipe. 2683 */ 2684 #define LVDS_PORT_EN (1 << 31) 2685 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 2686 #define LVDS_PIPE_SEL_SHIFT 30 2687 #define LVDS_PIPE_SEL_MASK (1 << 30) 2688 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30) 2689 #define LVDS_PIPE_SEL_SHIFT_CPT 29 2690 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29) 2691 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2692 /* LVDS dithering flag on 965/g4x platform */ 2693 #define LVDS_ENABLE_DITHER (1 << 25) 2694 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 2695 #define LVDS_VSYNC_POLARITY (1 << 21) 2696 #define LVDS_HSYNC_POLARITY (1 << 20) 2697 2698 /* Enable border for unscaled (or aspect-scaled) display */ 2699 #define LVDS_BORDER_ENABLE (1 << 15) 2700 /* 2701 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 2702 * pixel. 2703 */ 2704 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 2705 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 2706 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 2707 /* 2708 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 2709 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 2710 * on. 2711 */ 2712 #define LVDS_A3_POWER_MASK (3 << 6) 2713 #define LVDS_A3_POWER_DOWN (0 << 6) 2714 #define LVDS_A3_POWER_UP (3 << 6) 2715 /* 2716 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 2717 * is set. 2718 */ 2719 #define LVDS_CLKB_POWER_MASK (3 << 4) 2720 #define LVDS_CLKB_POWER_DOWN (0 << 4) 2721 #define LVDS_CLKB_POWER_UP (3 << 4) 2722 /* 2723 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 2724 * setting for whether we are in dual-channel mode. The B3 pair will 2725 * additionally only be powered up when LVDS_A3_POWER_UP is set. 2726 */ 2727 #define LVDS_B0B3_POWER_MASK (3 << 2) 2728 #define LVDS_B0B3_POWER_DOWN (0 << 2) 2729 #define LVDS_B0B3_POWER_UP (3 << 2) 2730 2731 /* Video Data Island Packet control */ 2732 #define VIDEO_DIP_DATA _MMIO(0x61178) 2733 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 2734 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 2735 * of the infoframe structure specified by CEA-861. */ 2736 #define VIDEO_DIP_DATA_SIZE 32 2737 #define VIDEO_DIP_GMP_DATA_SIZE 36 2738 #define VIDEO_DIP_VSC_DATA_SIZE 36 2739 #define VIDEO_DIP_PPS_DATA_SIZE 132 2740 #define VIDEO_DIP_CTL _MMIO(0x61170) 2741 /* Pre HSW: */ 2742 #define VIDEO_DIP_ENABLE (1 << 31) 2743 #define VIDEO_DIP_PORT(port) ((port) << 29) 2744 #define VIDEO_DIP_PORT_MASK (3 << 29) 2745 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 2746 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 2747 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 2748 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 2749 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 2750 #define VIDEO_DIP_SELECT_AVI (0 << 19) 2751 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 2752 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 2753 #define VIDEO_DIP_SELECT_SPD (3 << 19) 2754 #define VIDEO_DIP_SELECT_MASK (3 << 19) 2755 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 2756 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 2757 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 2758 #define VIDEO_DIP_FREQ_MASK (3 << 16) 2759 /* HSW and later: */ 2760 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 2761 #define PSR_VSC_BIT_7_SET (1 << 27) 2762 #define VSC_SELECT_MASK (0x3 << 25) 2763 #define VSC_SELECT_SHIFT 25 2764 #define VSC_DIP_HW_HEA_DATA (0 << 25) 2765 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 2766 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 2767 #define VSC_DIP_SW_HEA_DATA (3 << 25) 2768 #define VDIP_ENABLE_PPS (1 << 24) 2769 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 2770 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 2771 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 2772 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 2773 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 2774 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 2775 2776 /* Panel power sequencing */ 2777 #define PPS_BASE 0x61200 2778 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 2779 #define PCH_PPS_BASE 0xC7200 2780 2781 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps.mmio_base - \ 2782 PPS_BASE + (reg) + \ 2783 (pps_idx) * 0x100) 2784 2785 #define _PP_STATUS 0x61200 2786 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 2787 #define PP_ON REG_BIT(31) 2788 /* 2789 * Indicates that all dependencies of the panel are on: 2790 * 2791 * - PLL enabled 2792 * - pipe enabled 2793 * - LVDS/DVOB/DVOC on 2794 */ 2795 #define PP_READY REG_BIT(30) 2796 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28) 2797 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) 2798 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) 2799 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) 2800 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) 2801 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) 2802 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) 2803 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) 2804 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) 2805 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) 2806 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) 2807 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) 2808 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) 2809 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) 2810 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) 2811 2812 #define _PP_CONTROL 0x61204 2813 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 2814 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) 2815 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) 2816 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 2817 #define EDP_FORCE_VDD REG_BIT(3) 2818 #define EDP_BLC_ENABLE REG_BIT(2) 2819 #define PANEL_POWER_RESET REG_BIT(1) 2820 #define PANEL_POWER_ON REG_BIT(0) 2821 2822 #define _PP_ON_DELAYS 0x61208 2823 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 2824 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) 2825 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) 2826 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) 2827 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) 2828 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) 2829 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) 2830 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) 2831 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) 2832 2833 #define _PP_OFF_DELAYS 0x6120C 2834 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 2835 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) 2836 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) 2837 2838 #define _PP_DIVISOR 0x61210 2839 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 2840 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) 2841 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) 2842 2843 /* Panel fitting */ 2844 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 2845 #define PFIT_ENABLE (1 << 31) 2846 #define PFIT_PIPE_MASK (3 << 29) 2847 #define PFIT_PIPE_SHIFT 29 2848 #define PFIT_PIPE(pipe) ((pipe) << 29) 2849 #define VERT_INTERP_DISABLE (0 << 10) 2850 #define VERT_INTERP_BILINEAR (1 << 10) 2851 #define VERT_INTERP_MASK (3 << 10) 2852 #define VERT_AUTO_SCALE (1 << 9) 2853 #define HORIZ_INTERP_DISABLE (0 << 6) 2854 #define HORIZ_INTERP_BILINEAR (1 << 6) 2855 #define HORIZ_INTERP_MASK (3 << 6) 2856 #define HORIZ_AUTO_SCALE (1 << 5) 2857 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 2858 #define PFIT_FILTER_FUZZY (0 << 24) 2859 #define PFIT_SCALING_AUTO (0 << 26) 2860 #define PFIT_SCALING_PROGRAMMED (1 << 26) 2861 #define PFIT_SCALING_PILLAR (2 << 26) 2862 #define PFIT_SCALING_LETTER (3 << 26) 2863 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 2864 /* Pre-965 */ 2865 #define PFIT_VERT_SCALE_SHIFT 20 2866 #define PFIT_VERT_SCALE_MASK 0xfff00000 2867 #define PFIT_HORIZ_SCALE_SHIFT 4 2868 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 2869 /* 965+ */ 2870 #define PFIT_VERT_SCALE_SHIFT_965 16 2871 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 2872 #define PFIT_HORIZ_SCALE_SHIFT_965 0 2873 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 2874 2875 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 2876 2877 #define PCH_GTC_CTL _MMIO(0xe7000) 2878 #define PCH_GTC_ENABLE (1 << 31) 2879 2880 /* TV port control */ 2881 #define TV_CTL _MMIO(0x68000) 2882 /* Enables the TV encoder */ 2883 # define TV_ENC_ENABLE (1 << 31) 2884 /* Sources the TV encoder input from pipe B instead of A. */ 2885 # define TV_ENC_PIPE_SEL_SHIFT 30 2886 # define TV_ENC_PIPE_SEL_MASK (1 << 30) 2887 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30) 2888 /* Outputs composite video (DAC A only) */ 2889 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 2890 /* Outputs SVideo video (DAC B/C) */ 2891 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 2892 /* Outputs Component video (DAC A/B/C) */ 2893 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 2894 /* Outputs Composite and SVideo (DAC A/B/C) */ 2895 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 2896 # define TV_TRILEVEL_SYNC (1 << 21) 2897 /* Enables slow sync generation (945GM only) */ 2898 # define TV_SLOW_SYNC (1 << 20) 2899 /* Selects 4x oversampling for 480i and 576p */ 2900 # define TV_OVERSAMPLE_4X (0 << 18) 2901 /* Selects 2x oversampling for 720p and 1080i */ 2902 # define TV_OVERSAMPLE_2X (1 << 18) 2903 /* Selects no oversampling for 1080p */ 2904 # define TV_OVERSAMPLE_NONE (2 << 18) 2905 /* Selects 8x oversampling */ 2906 # define TV_OVERSAMPLE_8X (3 << 18) 2907 # define TV_OVERSAMPLE_MASK (3 << 18) 2908 /* Selects progressive mode rather than interlaced */ 2909 # define TV_PROGRESSIVE (1 << 17) 2910 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 2911 # define TV_PAL_BURST (1 << 16) 2912 /* Field for setting delay of Y compared to C */ 2913 # define TV_YC_SKEW_MASK (7 << 12) 2914 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 2915 # define TV_ENC_SDP_FIX (1 << 11) 2916 /* 2917 * Enables a fix for the 915GM only. 2918 * 2919 * Not sure what it does. 2920 */ 2921 # define TV_ENC_C0_FIX (1 << 10) 2922 /* Bits that must be preserved by software */ 2923 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 2924 # define TV_FUSE_STATE_MASK (3 << 4) 2925 /* Read-only state that reports all features enabled */ 2926 # define TV_FUSE_STATE_ENABLED (0 << 4) 2927 /* Read-only state that reports that Macrovision is disabled in hardware*/ 2928 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 2929 /* Read-only state that reports that TV-out is disabled in hardware. */ 2930 # define TV_FUSE_STATE_DISABLED (2 << 4) 2931 /* Normal operation */ 2932 # define TV_TEST_MODE_NORMAL (0 << 0) 2933 /* Encoder test pattern 1 - combo pattern */ 2934 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 2935 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 2936 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 2937 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 2938 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 2939 /* Encoder test pattern 4 - random noise */ 2940 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 2941 /* Encoder test pattern 5 - linear color ramps */ 2942 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 2943 /* 2944 * This test mode forces the DACs to 50% of full output. 2945 * 2946 * This is used for load detection in combination with TVDAC_SENSE_MASK 2947 */ 2948 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 2949 # define TV_TEST_MODE_MASK (7 << 0) 2950 2951 #define TV_DAC _MMIO(0x68004) 2952 # define TV_DAC_SAVE 0x00ffff00 2953 /* 2954 * Reports that DAC state change logic has reported change (RO). 2955 * 2956 * This gets cleared when TV_DAC_STATE_EN is cleared 2957 */ 2958 # define TVDAC_STATE_CHG (1 << 31) 2959 # define TVDAC_SENSE_MASK (7 << 28) 2960 /* Reports that DAC A voltage is above the detect threshold */ 2961 # define TVDAC_A_SENSE (1 << 30) 2962 /* Reports that DAC B voltage is above the detect threshold */ 2963 # define TVDAC_B_SENSE (1 << 29) 2964 /* Reports that DAC C voltage is above the detect threshold */ 2965 # define TVDAC_C_SENSE (1 << 28) 2966 /* 2967 * Enables DAC state detection logic, for load-based TV detection. 2968 * 2969 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 2970 * to off, for load detection to work. 2971 */ 2972 # define TVDAC_STATE_CHG_EN (1 << 27) 2973 /* Sets the DAC A sense value to high */ 2974 # define TVDAC_A_SENSE_CTL (1 << 26) 2975 /* Sets the DAC B sense value to high */ 2976 # define TVDAC_B_SENSE_CTL (1 << 25) 2977 /* Sets the DAC C sense value to high */ 2978 # define TVDAC_C_SENSE_CTL (1 << 24) 2979 /* Overrides the ENC_ENABLE and DAC voltage levels */ 2980 # define DAC_CTL_OVERRIDE (1 << 7) 2981 /* Sets the slew rate. Must be preserved in software */ 2982 # define ENC_TVDAC_SLEW_FAST (1 << 6) 2983 # define DAC_A_1_3_V (0 << 4) 2984 # define DAC_A_1_1_V (1 << 4) 2985 # define DAC_A_0_7_V (2 << 4) 2986 # define DAC_A_MASK (3 << 4) 2987 # define DAC_B_1_3_V (0 << 2) 2988 # define DAC_B_1_1_V (1 << 2) 2989 # define DAC_B_0_7_V (2 << 2) 2990 # define DAC_B_MASK (3 << 2) 2991 # define DAC_C_1_3_V (0 << 0) 2992 # define DAC_C_1_1_V (1 << 0) 2993 # define DAC_C_0_7_V (2 << 0) 2994 # define DAC_C_MASK (3 << 0) 2995 2996 /* 2997 * CSC coefficients are stored in a floating point format with 9 bits of 2998 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 2999 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 3000 * -1 (0x3) being the only legal negative value. 3001 */ 3002 #define TV_CSC_Y _MMIO(0x68010) 3003 # define TV_RY_MASK 0x07ff0000 3004 # define TV_RY_SHIFT 16 3005 # define TV_GY_MASK 0x00000fff 3006 # define TV_GY_SHIFT 0 3007 3008 #define TV_CSC_Y2 _MMIO(0x68014) 3009 # define TV_BY_MASK 0x07ff0000 3010 # define TV_BY_SHIFT 16 3011 /* 3012 * Y attenuation for component video. 3013 * 3014 * Stored in 1.9 fixed point. 3015 */ 3016 # define TV_AY_MASK 0x000003ff 3017 # define TV_AY_SHIFT 0 3018 3019 #define TV_CSC_U _MMIO(0x68018) 3020 # define TV_RU_MASK 0x07ff0000 3021 # define TV_RU_SHIFT 16 3022 # define TV_GU_MASK 0x000007ff 3023 # define TV_GU_SHIFT 0 3024 3025 #define TV_CSC_U2 _MMIO(0x6801c) 3026 # define TV_BU_MASK 0x07ff0000 3027 # define TV_BU_SHIFT 16 3028 /* 3029 * U attenuation for component video. 3030 * 3031 * Stored in 1.9 fixed point. 3032 */ 3033 # define TV_AU_MASK 0x000003ff 3034 # define TV_AU_SHIFT 0 3035 3036 #define TV_CSC_V _MMIO(0x68020) 3037 # define TV_RV_MASK 0x0fff0000 3038 # define TV_RV_SHIFT 16 3039 # define TV_GV_MASK 0x000007ff 3040 # define TV_GV_SHIFT 0 3041 3042 #define TV_CSC_V2 _MMIO(0x68024) 3043 # define TV_BV_MASK 0x07ff0000 3044 # define TV_BV_SHIFT 16 3045 /* 3046 * V attenuation for component video. 3047 * 3048 * Stored in 1.9 fixed point. 3049 */ 3050 # define TV_AV_MASK 0x000007ff 3051 # define TV_AV_SHIFT 0 3052 3053 #define TV_CLR_KNOBS _MMIO(0x68028) 3054 /* 2s-complement brightness adjustment */ 3055 # define TV_BRIGHTNESS_MASK 0xff000000 3056 # define TV_BRIGHTNESS_SHIFT 24 3057 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 3058 # define TV_CONTRAST_MASK 0x00ff0000 3059 # define TV_CONTRAST_SHIFT 16 3060 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 3061 # define TV_SATURATION_MASK 0x0000ff00 3062 # define TV_SATURATION_SHIFT 8 3063 /* Hue adjustment, as an integer phase angle in degrees */ 3064 # define TV_HUE_MASK 0x000000ff 3065 # define TV_HUE_SHIFT 0 3066 3067 #define TV_CLR_LEVEL _MMIO(0x6802c) 3068 /* Controls the DAC level for black */ 3069 # define TV_BLACK_LEVEL_MASK 0x01ff0000 3070 # define TV_BLACK_LEVEL_SHIFT 16 3071 /* Controls the DAC level for blanking */ 3072 # define TV_BLANK_LEVEL_MASK 0x000001ff 3073 # define TV_BLANK_LEVEL_SHIFT 0 3074 3075 #define TV_H_CTL_1 _MMIO(0x68030) 3076 /* Number of pixels in the hsync. */ 3077 # define TV_HSYNC_END_MASK 0x1fff0000 3078 # define TV_HSYNC_END_SHIFT 16 3079 /* Total number of pixels minus one in the line (display and blanking). */ 3080 # define TV_HTOTAL_MASK 0x00001fff 3081 # define TV_HTOTAL_SHIFT 0 3082 3083 #define TV_H_CTL_2 _MMIO(0x68034) 3084 /* Enables the colorburst (needed for non-component color) */ 3085 # define TV_BURST_ENA (1 << 31) 3086 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 3087 # define TV_HBURST_START_SHIFT 16 3088 # define TV_HBURST_START_MASK 0x1fff0000 3089 /* Length of the colorburst */ 3090 # define TV_HBURST_LEN_SHIFT 0 3091 # define TV_HBURST_LEN_MASK 0x0001fff 3092 3093 #define TV_H_CTL_3 _MMIO(0x68038) 3094 /* End of hblank, measured in pixels minus one from start of hsync */ 3095 # define TV_HBLANK_END_SHIFT 16 3096 # define TV_HBLANK_END_MASK 0x1fff0000 3097 /* Start of hblank, measured in pixels minus one from start of hsync */ 3098 # define TV_HBLANK_START_SHIFT 0 3099 # define TV_HBLANK_START_MASK 0x0001fff 3100 3101 #define TV_V_CTL_1 _MMIO(0x6803c) 3102 /* XXX */ 3103 # define TV_NBR_END_SHIFT 16 3104 # define TV_NBR_END_MASK 0x07ff0000 3105 /* XXX */ 3106 # define TV_VI_END_F1_SHIFT 8 3107 # define TV_VI_END_F1_MASK 0x00003f00 3108 /* XXX */ 3109 # define TV_VI_END_F2_SHIFT 0 3110 # define TV_VI_END_F2_MASK 0x0000003f 3111 3112 #define TV_V_CTL_2 _MMIO(0x68040) 3113 /* Length of vsync, in half lines */ 3114 # define TV_VSYNC_LEN_MASK 0x07ff0000 3115 # define TV_VSYNC_LEN_SHIFT 16 3116 /* Offset of the start of vsync in field 1, measured in one less than the 3117 * number of half lines. 3118 */ 3119 # define TV_VSYNC_START_F1_MASK 0x00007f00 3120 # define TV_VSYNC_START_F1_SHIFT 8 3121 /* 3122 * Offset of the start of vsync in field 2, measured in one less than the 3123 * number of half lines. 3124 */ 3125 # define TV_VSYNC_START_F2_MASK 0x0000007f 3126 # define TV_VSYNC_START_F2_SHIFT 0 3127 3128 #define TV_V_CTL_3 _MMIO(0x68044) 3129 /* Enables generation of the equalization signal */ 3130 # define TV_EQUAL_ENA (1 << 31) 3131 /* Length of vsync, in half lines */ 3132 # define TV_VEQ_LEN_MASK 0x007f0000 3133 # define TV_VEQ_LEN_SHIFT 16 3134 /* Offset of the start of equalization in field 1, measured in one less than 3135 * the number of half lines. 3136 */ 3137 # define TV_VEQ_START_F1_MASK 0x0007f00 3138 # define TV_VEQ_START_F1_SHIFT 8 3139 /* 3140 * Offset of the start of equalization in field 2, measured in one less than 3141 * the number of half lines. 3142 */ 3143 # define TV_VEQ_START_F2_MASK 0x000007f 3144 # define TV_VEQ_START_F2_SHIFT 0 3145 3146 #define TV_V_CTL_4 _MMIO(0x68048) 3147 /* 3148 * Offset to start of vertical colorburst, measured in one less than the 3149 * number of lines from vertical start. 3150 */ 3151 # define TV_VBURST_START_F1_MASK 0x003f0000 3152 # define TV_VBURST_START_F1_SHIFT 16 3153 /* 3154 * Offset to the end of vertical colorburst, measured in one less than the 3155 * number of lines from the start of NBR. 3156 */ 3157 # define TV_VBURST_END_F1_MASK 0x000000ff 3158 # define TV_VBURST_END_F1_SHIFT 0 3159 3160 #define TV_V_CTL_5 _MMIO(0x6804c) 3161 /* 3162 * Offset to start of vertical colorburst, measured in one less than the 3163 * number of lines from vertical start. 3164 */ 3165 # define TV_VBURST_START_F2_MASK 0x003f0000 3166 # define TV_VBURST_START_F2_SHIFT 16 3167 /* 3168 * Offset to the end of vertical colorburst, measured in one less than the 3169 * number of lines from the start of NBR. 3170 */ 3171 # define TV_VBURST_END_F2_MASK 0x000000ff 3172 # define TV_VBURST_END_F2_SHIFT 0 3173 3174 #define TV_V_CTL_6 _MMIO(0x68050) 3175 /* 3176 * Offset to start of vertical colorburst, measured in one less than the 3177 * number of lines from vertical start. 3178 */ 3179 # define TV_VBURST_START_F3_MASK 0x003f0000 3180 # define TV_VBURST_START_F3_SHIFT 16 3181 /* 3182 * Offset to the end of vertical colorburst, measured in one less than the 3183 * number of lines from the start of NBR. 3184 */ 3185 # define TV_VBURST_END_F3_MASK 0x000000ff 3186 # define TV_VBURST_END_F3_SHIFT 0 3187 3188 #define TV_V_CTL_7 _MMIO(0x68054) 3189 /* 3190 * Offset to start of vertical colorburst, measured in one less than the 3191 * number of lines from vertical start. 3192 */ 3193 # define TV_VBURST_START_F4_MASK 0x003f0000 3194 # define TV_VBURST_START_F4_SHIFT 16 3195 /* 3196 * Offset to the end of vertical colorburst, measured in one less than the 3197 * number of lines from the start of NBR. 3198 */ 3199 # define TV_VBURST_END_F4_MASK 0x000000ff 3200 # define TV_VBURST_END_F4_SHIFT 0 3201 3202 #define TV_SC_CTL_1 _MMIO(0x68060) 3203 /* Turns on the first subcarrier phase generation DDA */ 3204 # define TV_SC_DDA1_EN (1 << 31) 3205 /* Turns on the first subcarrier phase generation DDA */ 3206 # define TV_SC_DDA2_EN (1 << 30) 3207 /* Turns on the first subcarrier phase generation DDA */ 3208 # define TV_SC_DDA3_EN (1 << 29) 3209 /* Sets the subcarrier DDA to reset frequency every other field */ 3210 # define TV_SC_RESET_EVERY_2 (0 << 24) 3211 /* Sets the subcarrier DDA to reset frequency every fourth field */ 3212 # define TV_SC_RESET_EVERY_4 (1 << 24) 3213 /* Sets the subcarrier DDA to reset frequency every eighth field */ 3214 # define TV_SC_RESET_EVERY_8 (2 << 24) 3215 /* Sets the subcarrier DDA to never reset the frequency */ 3216 # define TV_SC_RESET_NEVER (3 << 24) 3217 /* Sets the peak amplitude of the colorburst.*/ 3218 # define TV_BURST_LEVEL_MASK 0x00ff0000 3219 # define TV_BURST_LEVEL_SHIFT 16 3220 /* Sets the increment of the first subcarrier phase generation DDA */ 3221 # define TV_SCDDA1_INC_MASK 0x00000fff 3222 # define TV_SCDDA1_INC_SHIFT 0 3223 3224 #define TV_SC_CTL_2 _MMIO(0x68064) 3225 /* Sets the rollover for the second subcarrier phase generation DDA */ 3226 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 3227 # define TV_SCDDA2_SIZE_SHIFT 16 3228 /* Sets the increent of the second subcarrier phase generation DDA */ 3229 # define TV_SCDDA2_INC_MASK 0x00007fff 3230 # define TV_SCDDA2_INC_SHIFT 0 3231 3232 #define TV_SC_CTL_3 _MMIO(0x68068) 3233 /* Sets the rollover for the third subcarrier phase generation DDA */ 3234 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 3235 # define TV_SCDDA3_SIZE_SHIFT 16 3236 /* Sets the increent of the third subcarrier phase generation DDA */ 3237 # define TV_SCDDA3_INC_MASK 0x00007fff 3238 # define TV_SCDDA3_INC_SHIFT 0 3239 3240 #define TV_WIN_POS _MMIO(0x68070) 3241 /* X coordinate of the display from the start of horizontal active */ 3242 # define TV_XPOS_MASK 0x1fff0000 3243 # define TV_XPOS_SHIFT 16 3244 /* Y coordinate of the display from the start of vertical active (NBR) */ 3245 # define TV_YPOS_MASK 0x00000fff 3246 # define TV_YPOS_SHIFT 0 3247 3248 #define TV_WIN_SIZE _MMIO(0x68074) 3249 /* Horizontal size of the display window, measured in pixels*/ 3250 # define TV_XSIZE_MASK 0x1fff0000 3251 # define TV_XSIZE_SHIFT 16 3252 /* 3253 * Vertical size of the display window, measured in pixels. 3254 * 3255 * Must be even for interlaced modes. 3256 */ 3257 # define TV_YSIZE_MASK 0x00000fff 3258 # define TV_YSIZE_SHIFT 0 3259 3260 #define TV_FILTER_CTL_1 _MMIO(0x68080) 3261 /* 3262 * Enables automatic scaling calculation. 3263 * 3264 * If set, the rest of the registers are ignored, and the calculated values can 3265 * be read back from the register. 3266 */ 3267 # define TV_AUTO_SCALE (1 << 31) 3268 /* 3269 * Disables the vertical filter. 3270 * 3271 * This is required on modes more than 1024 pixels wide */ 3272 # define TV_V_FILTER_BYPASS (1 << 29) 3273 /* Enables adaptive vertical filtering */ 3274 # define TV_VADAPT (1 << 28) 3275 # define TV_VADAPT_MODE_MASK (3 << 26) 3276 /* Selects the least adaptive vertical filtering mode */ 3277 # define TV_VADAPT_MODE_LEAST (0 << 26) 3278 /* Selects the moderately adaptive vertical filtering mode */ 3279 # define TV_VADAPT_MODE_MODERATE (1 << 26) 3280 /* Selects the most adaptive vertical filtering mode */ 3281 # define TV_VADAPT_MODE_MOST (3 << 26) 3282 /* 3283 * Sets the horizontal scaling factor. 3284 * 3285 * This should be the fractional part of the horizontal scaling factor divided 3286 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 3287 * 3288 * (src width - 1) / ((oversample * dest width) - 1) 3289 */ 3290 # define TV_HSCALE_FRAC_MASK 0x00003fff 3291 # define TV_HSCALE_FRAC_SHIFT 0 3292 3293 #define TV_FILTER_CTL_2 _MMIO(0x68084) 3294 /* 3295 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3296 * 3297 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 3298 */ 3299 # define TV_VSCALE_INT_MASK 0x00038000 3300 # define TV_VSCALE_INT_SHIFT 15 3301 /* 3302 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3303 * 3304 * \sa TV_VSCALE_INT_MASK 3305 */ 3306 # define TV_VSCALE_FRAC_MASK 0x00007fff 3307 # define TV_VSCALE_FRAC_SHIFT 0 3308 3309 #define TV_FILTER_CTL_3 _MMIO(0x68088) 3310 /* 3311 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3312 * 3313 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 3314 * 3315 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3316 */ 3317 # define TV_VSCALE_IP_INT_MASK 0x00038000 3318 # define TV_VSCALE_IP_INT_SHIFT 15 3319 /* 3320 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3321 * 3322 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3323 * 3324 * \sa TV_VSCALE_IP_INT_MASK 3325 */ 3326 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 3327 # define TV_VSCALE_IP_FRAC_SHIFT 0 3328 3329 #define TV_CC_CONTROL _MMIO(0x68090) 3330 # define TV_CC_ENABLE (1 << 31) 3331 /* 3332 * Specifies which field to send the CC data in. 3333 * 3334 * CC data is usually sent in field 0. 3335 */ 3336 # define TV_CC_FID_MASK (1 << 27) 3337 # define TV_CC_FID_SHIFT 27 3338 /* Sets the horizontal position of the CC data. Usually 135. */ 3339 # define TV_CC_HOFF_MASK 0x03ff0000 3340 # define TV_CC_HOFF_SHIFT 16 3341 /* Sets the vertical position of the CC data. Usually 21 */ 3342 # define TV_CC_LINE_MASK 0x0000003f 3343 # define TV_CC_LINE_SHIFT 0 3344 3345 #define TV_CC_DATA _MMIO(0x68094) 3346 # define TV_CC_RDY (1 << 31) 3347 /* Second word of CC data to be transmitted. */ 3348 # define TV_CC_DATA_2_MASK 0x007f0000 3349 # define TV_CC_DATA_2_SHIFT 16 3350 /* First word of CC data to be transmitted. */ 3351 # define TV_CC_DATA_1_MASK 0x0000007f 3352 # define TV_CC_DATA_1_SHIFT 0 3353 3354 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 3355 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 3356 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 3357 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 3358 3359 /* Display Port */ 3360 #define DP_A _MMIO(0x64000) /* eDP */ 3361 #define DP_B _MMIO(0x64100) 3362 #define DP_C _MMIO(0x64200) 3363 #define DP_D _MMIO(0x64300) 3364 3365 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 3366 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 3367 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 3368 3369 #define DP_PORT_EN (1 << 31) 3370 #define DP_PIPE_SEL_SHIFT 30 3371 #define DP_PIPE_SEL_MASK (1 << 30) 3372 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 3373 #define DP_PIPE_SEL_SHIFT_IVB 29 3374 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 3375 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 3376 #define DP_PIPE_SEL_SHIFT_CHV 16 3377 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 3378 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 3379 3380 /* Link training mode - select a suitable mode for each stage */ 3381 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 3382 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 3383 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 3384 #define DP_LINK_TRAIN_OFF (3 << 28) 3385 #define DP_LINK_TRAIN_MASK (3 << 28) 3386 #define DP_LINK_TRAIN_SHIFT 28 3387 3388 /* CPT Link training mode */ 3389 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 3390 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 3391 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 3392 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 3393 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 3394 #define DP_LINK_TRAIN_SHIFT_CPT 8 3395 3396 /* Signal voltages. These are mostly controlled by the other end */ 3397 #define DP_VOLTAGE_0_4 (0 << 25) 3398 #define DP_VOLTAGE_0_6 (1 << 25) 3399 #define DP_VOLTAGE_0_8 (2 << 25) 3400 #define DP_VOLTAGE_1_2 (3 << 25) 3401 #define DP_VOLTAGE_MASK (7 << 25) 3402 #define DP_VOLTAGE_SHIFT 25 3403 3404 /* Signal pre-emphasis levels, like voltages, the other end tells us what 3405 * they want 3406 */ 3407 #define DP_PRE_EMPHASIS_0 (0 << 22) 3408 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 3409 #define DP_PRE_EMPHASIS_6 (2 << 22) 3410 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 3411 #define DP_PRE_EMPHASIS_MASK (7 << 22) 3412 #define DP_PRE_EMPHASIS_SHIFT 22 3413 3414 /* How many wires to use. I guess 3 was too hard */ 3415 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 3416 #define DP_PORT_WIDTH_MASK (7 << 19) 3417 #define DP_PORT_WIDTH_SHIFT 19 3418 3419 /* Mystic DPCD version 1.1 special mode */ 3420 #define DP_ENHANCED_FRAMING (1 << 18) 3421 3422 /* eDP */ 3423 #define DP_PLL_FREQ_270MHZ (0 << 16) 3424 #define DP_PLL_FREQ_162MHZ (1 << 16) 3425 #define DP_PLL_FREQ_MASK (3 << 16) 3426 3427 /* locked once port is enabled */ 3428 #define DP_PORT_REVERSAL (1 << 15) 3429 3430 /* eDP */ 3431 #define DP_PLL_ENABLE (1 << 14) 3432 3433 /* sends the clock on lane 15 of the PEG for debug */ 3434 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 3435 3436 #define DP_SCRAMBLING_DISABLE (1 << 12) 3437 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 3438 3439 /* limit RGB values to avoid confusing TVs */ 3440 #define DP_COLOR_RANGE_16_235 (1 << 8) 3441 3442 /* Turn on the audio link */ 3443 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 3444 3445 /* vs and hs sync polarity */ 3446 #define DP_SYNC_VS_HIGH (1 << 4) 3447 #define DP_SYNC_HS_HIGH (1 << 3) 3448 3449 /* A fantasy */ 3450 #define DP_DETECTED (1 << 2) 3451 3452 /* The aux channel provides a way to talk to the 3453 * signal sink for DDC etc. Max packet size supported 3454 * is 20 bytes in each direction, hence the 5 fixed 3455 * data registers 3456 */ 3457 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) 3458 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) 3459 3460 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) 3461 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) 3462 3463 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 3464 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 3465 3466 #define _XELPDP_USBC1_AUX_CH_CTL 0x16F210 3467 #define _XELPDP_USBC2_AUX_CH_CTL 0x16F410 3468 #define _XELPDP_USBC3_AUX_CH_CTL 0x16F610 3469 #define _XELPDP_USBC4_AUX_CH_CTL 0x16F810 3470 3471 #define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \ 3472 _DPA_AUX_CH_CTL, \ 3473 _DPB_AUX_CH_CTL, \ 3474 0, /* port/aux_ch C is non-existent */ \ 3475 _XELPDP_USBC1_AUX_CH_CTL, \ 3476 _XELPDP_USBC2_AUX_CH_CTL, \ 3477 _XELPDP_USBC3_AUX_CH_CTL, \ 3478 _XELPDP_USBC4_AUX_CH_CTL)) 3479 3480 #define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214 3481 #define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414 3482 #define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614 3483 #define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814 3484 3485 #define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \ 3486 _DPA_AUX_CH_DATA1, \ 3487 _DPB_AUX_CH_DATA1, \ 3488 0, /* port/aux_ch C is non-existent */ \ 3489 _XELPDP_USBC1_AUX_CH_DATA1, \ 3490 _XELPDP_USBC2_AUX_CH_DATA1, \ 3491 _XELPDP_USBC3_AUX_CH_DATA1, \ 3492 _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4) 3493 3494 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 3495 #define DP_AUX_CH_CTL_DONE (1 << 30) 3496 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 3497 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 3498 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 3499 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 3500 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 3501 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ 3502 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 3503 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 3504 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 3505 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 3506 #define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19) 3507 #define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18) 3508 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 3509 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 3510 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 3511 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 3512 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 3513 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 3514 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 3515 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 3516 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 3517 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 3518 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 3519 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 3520 #define DP_AUX_CH_CTL_TBT_IO (1 << 11) 3521 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 3522 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 3523 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 3524 3525 /* 3526 * Computing GMCH M and N values for the Display Port link 3527 * 3528 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 3529 * 3530 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 3531 * 3532 * The GMCH value is used internally 3533 * 3534 * bytes_per_pixel is the number of bytes coming out of the plane, 3535 * which is after the LUTs, so we want the bytes for our color format. 3536 * For our current usage, this is always 3, one byte for R, G and B. 3537 */ 3538 #define _PIPEA_DATA_M_G4X 0x70050 3539 #define _PIPEB_DATA_M_G4X 0x71050 3540 3541 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 3542 #define TU_SIZE_MASK REG_GENMASK(30, 25) 3543 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ 3544 3545 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) 3546 #define DATA_LINK_N_MAX (0x800000) 3547 3548 #define _PIPEA_DATA_N_G4X 0x70054 3549 #define _PIPEB_DATA_N_G4X 0x71054 3550 3551 /* 3552 * Computing Link M and N values for the Display Port link 3553 * 3554 * Link M / N = pixel_clock / ls_clk 3555 * 3556 * (the DP spec calls pixel_clock the 'strm_clk') 3557 * 3558 * The Link value is transmitted in the Main Stream 3559 * Attributes and VB-ID. 3560 */ 3561 3562 #define _PIPEA_LINK_M_G4X 0x70060 3563 #define _PIPEB_LINK_M_G4X 0x71060 3564 #define _PIPEA_LINK_N_G4X 0x70064 3565 #define _PIPEB_LINK_N_G4X 0x71064 3566 3567 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 3568 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 3569 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 3570 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 3571 3572 /* Display & cursor control */ 3573 3574 /* Pipe A */ 3575 #define _PIPEADSL 0x70000 3576 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ 3577 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) 3578 #define _PIPEACONF 0x70008 3579 #define PIPECONF_ENABLE REG_BIT(31) 3580 #define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ 3581 #define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */ 3582 #define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ 3583 #define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ 3584 #define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ 3585 #define PIPECONF_PIPE_LOCKED REG_BIT(25) 3586 #define PIPECONF_FORCE_BORDER REG_BIT(25) 3587 #define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ 3588 #define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ 3589 #define PIPECONF_GAMMA_MODE_8BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0) 3590 #define PIPECONF_GAMMA_MODE_10BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1) 3591 #define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ 3592 #define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ 3593 #define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ 3594 #define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ 3595 #define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0) 3596 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */ 3597 #define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */ 3598 #define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6) 3599 #define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */ 3600 /* 3601 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, 3602 * DBL=power saving pixel doubling, PF-ID* requires panel fitter 3603 */ 3604 #define PIPECONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ 3605 #define PIPECONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ 3606 #define PIPECONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0) 3607 #define PIPECONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1) 3608 #define PIPECONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3) 3609 #define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ 3610 #define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ 3611 #define PIPECONF_REFRESH_RATE_ALT_ILK REG_BIT(20) 3612 #define PIPECONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ 3613 #define PIPECONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(PIPECONF_MSA_TIMING_DELAY_MASK, (x)) 3614 #define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16) 3615 #define PIPECONF_REFRESH_RATE_ALT_VLV REG_BIT(14) 3616 #define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13) 3617 #define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ 3618 #define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ 3619 #define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ 3620 #define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ 3621 #define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ 3622 #define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ 3623 #define PIPECONF_BPC_8 REG_FIELD_PREP(PIPECONF_BPC_MASK, 0) 3624 #define PIPECONF_BPC_10 REG_FIELD_PREP(PIPECONF_BPC_MASK, 1) 3625 #define PIPECONF_BPC_6 REG_FIELD_PREP(PIPECONF_BPC_MASK, 2) 3626 #define PIPECONF_BPC_12 REG_FIELD_PREP(PIPECONF_BPC_MASK, 3) 3627 #define PIPECONF_DITHER_EN REG_BIT(4) 3628 #define PIPECONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) 3629 #define PIPECONF_DITHER_TYPE_SP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0) 3630 #define PIPECONF_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1) 3631 #define PIPECONF_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2) 3632 #define PIPECONF_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3) 3633 #define _PIPEASTAT 0x70024 3634 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 3635 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 3636 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 3637 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 3638 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 3639 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 3640 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 3641 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 3642 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 3643 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 3644 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 3645 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 3646 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 3647 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 3648 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 3649 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 3650 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 3651 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 3652 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 3653 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 3654 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 3655 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 3656 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 3657 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 3658 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 3659 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 3660 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 3661 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 3662 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 3663 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 3664 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 3665 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 3666 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 3667 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 3668 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 3669 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 3670 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 3671 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 3672 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 3673 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 3674 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 3675 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 3676 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 3677 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 3678 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 3679 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 3680 3681 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 3682 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 3683 3684 #define PIPE_A_OFFSET 0x70000 3685 #define PIPE_B_OFFSET 0x71000 3686 #define PIPE_C_OFFSET 0x72000 3687 #define PIPE_D_OFFSET 0x73000 3688 #define CHV_PIPE_C_OFFSET 0x74000 3689 /* 3690 * There's actually no pipe EDP. Some pipe registers have 3691 * simply shifted from the pipe to the transcoder, while 3692 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 3693 * to access such registers in transcoder EDP. 3694 */ 3695 #define PIPE_EDP_OFFSET 0x7f000 3696 3697 /* ICL DSI 0 and 1 */ 3698 #define PIPE_DSI0_OFFSET 0x7b000 3699 #define PIPE_DSI1_OFFSET 0x7b800 3700 3701 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 3702 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 3703 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 3704 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 3705 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 3706 3707 #define _PIPEAGCMAX 0x70010 3708 #define _PIPEBGCMAX 0x71010 3709 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) 3710 3711 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ 3712 #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A) 3713 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) 3714 3715 #define _PIPE_MISC_A 0x70030 3716 #define _PIPE_MISC_B 0x71030 3717 #define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ 3718 #define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ 3719 #define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ 3720 #define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) 3721 #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ 3722 /* 3723 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with 3724 * valid values of: 6, 8, 10 BPC. 3725 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: 3726 * 6, 8, 10, 12 BPC. 3727 */ 3728 #define PIPEMISC_BPC_MASK REG_GENMASK(7, 5) 3729 #define PIPEMISC_BPC_8 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0) 3730 #define PIPEMISC_BPC_10 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1) 3731 #define PIPEMISC_BPC_6 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2) 3732 #define PIPEMISC_BPC_12_ADLP REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */ 3733 #define PIPEMISC_DITHER_ENABLE REG_BIT(4) 3734 #define PIPEMISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) 3735 #define PIPEMISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0) 3736 #define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1) 3737 #define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2) 3738 #define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3) 3739 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 3740 3741 #define _PIPE_MISC2_A 0x7002C 3742 #define _PIPE_MISC2_B 0x7102C 3743 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) 3744 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) 3745 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) 3746 #define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A) 3747 3748 /* Skylake+ pipe bottom (background) color */ 3749 #define _SKL_BOTTOM_COLOR_A 0x70034 3750 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31) 3751 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30) 3752 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A) 3753 3754 #define _ICL_PIPE_A_STATUS 0x70058 3755 #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS) 3756 #define PIPE_STATUS_UNDERRUN REG_BIT(31) 3757 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) 3758 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) 3759 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26) 3760 3761 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 3762 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) 3763 #define PIPEB_HLINE_INT_EN REG_BIT(28) 3764 #define PIPEB_VBLANK_INT_EN REG_BIT(27) 3765 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) 3766 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) 3767 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) 3768 #define PIPE_PSR_INT_EN REG_BIT(22) 3769 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) 3770 #define PIPEA_HLINE_INT_EN REG_BIT(20) 3771 #define PIPEA_VBLANK_INT_EN REG_BIT(19) 3772 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) 3773 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) 3774 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) 3775 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) 3776 #define PIPEC_HLINE_INT_EN REG_BIT(12) 3777 #define PIPEC_VBLANK_INT_EN REG_BIT(11) 3778 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) 3779 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) 3780 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) 3781 3782 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 3783 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) 3784 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) 3785 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) 3786 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) 3787 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) 3788 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) 3789 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) 3790 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) 3791 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) 3792 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) 3793 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) 3794 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) 3795 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) 3796 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) 3797 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) 3798 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) 3799 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) 3800 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) 3801 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9) 3802 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8) 3803 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7) 3804 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6) 3805 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5) 3806 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) 3807 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3) 3808 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) 3809 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) 3810 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) 3811 3812 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 3813 #define DSPARB_CSTART_MASK (0x7f << 7) 3814 #define DSPARB_CSTART_SHIFT 7 3815 #define DSPARB_BSTART_MASK (0x7f) 3816 #define DSPARB_BSTART_SHIFT 0 3817 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 3818 #define DSPARB_AEND_SHIFT 0 3819 #define DSPARB_SPRITEA_SHIFT_VLV 0 3820 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 3821 #define DSPARB_SPRITEB_SHIFT_VLV 8 3822 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 3823 #define DSPARB_SPRITEC_SHIFT_VLV 16 3824 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 3825 #define DSPARB_SPRITED_SHIFT_VLV 24 3826 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 3827 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 3828 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 3829 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 3830 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 3831 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 3832 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 3833 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 3834 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 3835 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 3836 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 3837 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 3838 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 3839 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 3840 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 3841 #define DSPARB_SPRITEE_SHIFT_VLV 0 3842 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 3843 #define DSPARB_SPRITEF_SHIFT_VLV 8 3844 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 3845 3846 /* pnv/gen4/g4x/vlv/chv */ 3847 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 3848 #define DSPFW_SR_SHIFT 23 3849 #define DSPFW_SR_MASK (0x1ff << 23) 3850 #define DSPFW_CURSORB_SHIFT 16 3851 #define DSPFW_CURSORB_MASK (0x3f << 16) 3852 #define DSPFW_PLANEB_SHIFT 8 3853 #define DSPFW_PLANEB_MASK (0x7f << 8) 3854 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 3855 #define DSPFW_PLANEA_SHIFT 0 3856 #define DSPFW_PLANEA_MASK (0x7f << 0) 3857 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 3858 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 3859 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 3860 #define DSPFW_FBC_SR_SHIFT 28 3861 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 3862 #define DSPFW_FBC_HPLL_SR_SHIFT 24 3863 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 3864 #define DSPFW_SPRITEB_SHIFT (16) 3865 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 3866 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 3867 #define DSPFW_CURSORA_SHIFT 8 3868 #define DSPFW_CURSORA_MASK (0x3f << 8) 3869 #define DSPFW_PLANEC_OLD_SHIFT 0 3870 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 3871 #define DSPFW_SPRITEA_SHIFT 0 3872 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 3873 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 3874 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 3875 #define DSPFW_HPLL_SR_EN (1 << 31) 3876 #define PINEVIEW_SELF_REFRESH_EN (1 << 30) 3877 #define DSPFW_CURSOR_SR_SHIFT 24 3878 #define DSPFW_CURSOR_SR_MASK (0x3f << 24) 3879 #define DSPFW_HPLL_CURSOR_SHIFT 16 3880 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 3881 #define DSPFW_HPLL_SR_SHIFT 0 3882 #define DSPFW_HPLL_SR_MASK (0x1ff << 0) 3883 3884 /* vlv/chv */ 3885 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 3886 #define DSPFW_SPRITEB_WM1_SHIFT 16 3887 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 3888 #define DSPFW_CURSORA_WM1_SHIFT 8 3889 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 3890 #define DSPFW_SPRITEA_WM1_SHIFT 0 3891 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 3892 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 3893 #define DSPFW_PLANEB_WM1_SHIFT 24 3894 #define DSPFW_PLANEB_WM1_MASK (0xff << 24) 3895 #define DSPFW_PLANEA_WM1_SHIFT 16 3896 #define DSPFW_PLANEA_WM1_MASK (0xff << 16) 3897 #define DSPFW_CURSORB_WM1_SHIFT 8 3898 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 3899 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 3900 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 3901 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 3902 #define DSPFW_SR_WM1_SHIFT 0 3903 #define DSPFW_SR_WM1_MASK (0x1ff << 0) 3904 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 3905 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 3906 #define DSPFW_SPRITED_WM1_SHIFT 24 3907 #define DSPFW_SPRITED_WM1_MASK (0xff << 24) 3908 #define DSPFW_SPRITED_SHIFT 16 3909 #define DSPFW_SPRITED_MASK_VLV (0xff << 16) 3910 #define DSPFW_SPRITEC_WM1_SHIFT 8 3911 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 3912 #define DSPFW_SPRITEC_SHIFT 0 3913 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 3914 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 3915 #define DSPFW_SPRITEF_WM1_SHIFT 24 3916 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 3917 #define DSPFW_SPRITEF_SHIFT 16 3918 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 3919 #define DSPFW_SPRITEE_WM1_SHIFT 8 3920 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 3921 #define DSPFW_SPRITEE_SHIFT 0 3922 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 3923 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 3924 #define DSPFW_PLANEC_WM1_SHIFT 24 3925 #define DSPFW_PLANEC_WM1_MASK (0xff << 24) 3926 #define DSPFW_PLANEC_SHIFT 16 3927 #define DSPFW_PLANEC_MASK_VLV (0xff << 16) 3928 #define DSPFW_CURSORC_WM1_SHIFT 8 3929 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 3930 #define DSPFW_CURSORC_SHIFT 0 3931 #define DSPFW_CURSORC_MASK (0x3f << 0) 3932 3933 /* vlv/chv high order bits */ 3934 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 3935 #define DSPFW_SR_HI_SHIFT 24 3936 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 3937 #define DSPFW_SPRITEF_HI_SHIFT 23 3938 #define DSPFW_SPRITEF_HI_MASK (1 << 23) 3939 #define DSPFW_SPRITEE_HI_SHIFT 22 3940 #define DSPFW_SPRITEE_HI_MASK (1 << 22) 3941 #define DSPFW_PLANEC_HI_SHIFT 21 3942 #define DSPFW_PLANEC_HI_MASK (1 << 21) 3943 #define DSPFW_SPRITED_HI_SHIFT 20 3944 #define DSPFW_SPRITED_HI_MASK (1 << 20) 3945 #define DSPFW_SPRITEC_HI_SHIFT 16 3946 #define DSPFW_SPRITEC_HI_MASK (1 << 16) 3947 #define DSPFW_PLANEB_HI_SHIFT 12 3948 #define DSPFW_PLANEB_HI_MASK (1 << 12) 3949 #define DSPFW_SPRITEB_HI_SHIFT 8 3950 #define DSPFW_SPRITEB_HI_MASK (1 << 8) 3951 #define DSPFW_SPRITEA_HI_SHIFT 4 3952 #define DSPFW_SPRITEA_HI_MASK (1 << 4) 3953 #define DSPFW_PLANEA_HI_SHIFT 0 3954 #define DSPFW_PLANEA_HI_MASK (1 << 0) 3955 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 3956 #define DSPFW_SR_WM1_HI_SHIFT 24 3957 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 3958 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 3959 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 3960 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 3961 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 3962 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 3963 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 3964 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 3965 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 3966 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 3967 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 3968 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 3969 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 3970 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 3971 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 3972 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 3973 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 3974 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 3975 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 3976 3977 /* drain latency register values*/ 3978 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 3979 #define DDL_CURSOR_SHIFT 24 3980 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 3981 #define DDL_PLANE_SHIFT 0 3982 #define DDL_PRECISION_HIGH (1 << 7) 3983 #define DDL_PRECISION_LOW (0 << 7) 3984 #define DRAIN_LATENCY_MASK 0x7f 3985 3986 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 3987 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 3988 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 3989 3990 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 3991 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 3992 3993 /* FIFO watermark sizes etc */ 3994 #define G4X_FIFO_LINE_SIZE 64 3995 #define I915_FIFO_LINE_SIZE 64 3996 #define I830_FIFO_LINE_SIZE 32 3997 3998 #define VALLEYVIEW_FIFO_SIZE 255 3999 #define G4X_FIFO_SIZE 127 4000 #define I965_FIFO_SIZE 512 4001 #define I945_FIFO_SIZE 127 4002 #define I915_FIFO_SIZE 95 4003 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 4004 #define I830_FIFO_SIZE 95 4005 4006 #define VALLEYVIEW_MAX_WM 0xff 4007 #define G4X_MAX_WM 0x3f 4008 #define I915_MAX_WM 0x3f 4009 4010 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 4011 #define PINEVIEW_FIFO_LINE_SIZE 64 4012 #define PINEVIEW_MAX_WM 0x1ff 4013 #define PINEVIEW_DFT_WM 0x3f 4014 #define PINEVIEW_DFT_HPLLOFF_WM 0 4015 #define PINEVIEW_GUARD_WM 10 4016 #define PINEVIEW_CURSOR_FIFO 64 4017 #define PINEVIEW_CURSOR_MAX_WM 0x3f 4018 #define PINEVIEW_CURSOR_DFT_WM 0 4019 #define PINEVIEW_CURSOR_GUARD_WM 5 4020 4021 #define VALLEYVIEW_CURSOR_MAX_WM 64 4022 #define I965_CURSOR_FIFO 64 4023 #define I965_CURSOR_MAX_WM 32 4024 #define I965_CURSOR_DFT_WM 8 4025 4026 /* Watermark register definitions for SKL */ 4027 #define _CUR_WM_A_0 0x70140 4028 #define _CUR_WM_B_0 0x71140 4029 #define _CUR_WM_SAGV_A 0x70158 4030 #define _CUR_WM_SAGV_B 0x71158 4031 #define _CUR_WM_SAGV_TRANS_A 0x7015C 4032 #define _CUR_WM_SAGV_TRANS_B 0x7115C 4033 #define _CUR_WM_TRANS_A 0x70168 4034 #define _CUR_WM_TRANS_B 0x71168 4035 #define _PLANE_WM_1_A_0 0x70240 4036 #define _PLANE_WM_1_B_0 0x71240 4037 #define _PLANE_WM_2_A_0 0x70340 4038 #define _PLANE_WM_2_B_0 0x71340 4039 #define _PLANE_WM_SAGV_1_A 0x70258 4040 #define _PLANE_WM_SAGV_1_B 0x71258 4041 #define _PLANE_WM_SAGV_2_A 0x70358 4042 #define _PLANE_WM_SAGV_2_B 0x71358 4043 #define _PLANE_WM_SAGV_TRANS_1_A 0x7025C 4044 #define _PLANE_WM_SAGV_TRANS_1_B 0x7125C 4045 #define _PLANE_WM_SAGV_TRANS_2_A 0x7035C 4046 #define _PLANE_WM_SAGV_TRANS_2_B 0x7135C 4047 #define _PLANE_WM_TRANS_1_A 0x70268 4048 #define _PLANE_WM_TRANS_1_B 0x71268 4049 #define _PLANE_WM_TRANS_2_A 0x70368 4050 #define _PLANE_WM_TRANS_2_B 0x71368 4051 #define PLANE_WM_EN (1 << 31) 4052 #define PLANE_WM_IGNORE_LINES (1 << 30) 4053 #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) 4054 #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) 4055 4056 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 4057 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 4058 #define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) 4059 #define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) 4060 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) 4061 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 4062 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 4063 #define _PLANE_WM_BASE(pipe, plane) \ 4064 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 4065 #define PLANE_WM(pipe, plane, level) \ 4066 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 4067 #define _PLANE_WM_SAGV_1(pipe) \ 4068 _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) 4069 #define _PLANE_WM_SAGV_2(pipe) \ 4070 _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) 4071 #define PLANE_WM_SAGV(pipe, plane) \ 4072 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) 4073 #define _PLANE_WM_SAGV_TRANS_1(pipe) \ 4074 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) 4075 #define _PLANE_WM_SAGV_TRANS_2(pipe) \ 4076 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) 4077 #define PLANE_WM_SAGV_TRANS(pipe, plane) \ 4078 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe))) 4079 #define _PLANE_WM_TRANS_1(pipe) \ 4080 _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) 4081 #define _PLANE_WM_TRANS_2(pipe) \ 4082 _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) 4083 #define PLANE_WM_TRANS(pipe, plane) \ 4084 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 4085 4086 /* define the Watermark register on Ironlake */ 4087 #define _WM0_PIPEA_ILK 0x45100 4088 #define _WM0_PIPEB_ILK 0x45104 4089 #define _WM0_PIPEC_IVB 0x45200 4090 #define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \ 4091 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) 4092 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16) 4093 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8) 4094 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0) 4095 #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x)) 4096 #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x)) 4097 #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x)) 4098 #define WM1_LP_ILK _MMIO(0x45108) 4099 #define WM2_LP_ILK _MMIO(0x4510c) 4100 #define WM3_LP_ILK _MMIO(0x45110) 4101 #define WM_LP_ENABLE REG_BIT(31) 4102 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24) 4103 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19) 4104 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20) 4105 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8) 4106 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0) 4107 #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x)) 4108 #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x)) 4109 #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x)) 4110 #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x)) 4111 #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x)) 4112 #define WM1S_LP_ILK _MMIO(0x45120) 4113 #define WM2S_LP_IVB _MMIO(0x45124) 4114 #define WM3S_LP_IVB _MMIO(0x45128) 4115 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */ 4116 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0) 4117 #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x)) 4118 4119 /* 4120 * The two pipe frame counter registers are not synchronized, so 4121 * reading a stable value is somewhat tricky. The following code 4122 * should work: 4123 * 4124 * do { 4125 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4126 * PIPE_FRAME_HIGH_SHIFT; 4127 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 4128 * PIPE_FRAME_LOW_SHIFT); 4129 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4130 * PIPE_FRAME_HIGH_SHIFT); 4131 * } while (high1 != high2); 4132 * frame = (high1 << 8) | low1; 4133 */ 4134 #define _PIPEAFRAMEHIGH 0x70040 4135 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 4136 #define PIPE_FRAME_HIGH_SHIFT 0 4137 #define _PIPEAFRAMEPIXEL 0x70044 4138 #define PIPE_FRAME_LOW_MASK 0xff000000 4139 #define PIPE_FRAME_LOW_SHIFT 24 4140 #define PIPE_PIXEL_MASK 0x00ffffff 4141 #define PIPE_PIXEL_SHIFT 0 4142 /* GM45+ just has to be different */ 4143 #define _PIPEA_FRMCOUNT_G4X 0x70040 4144 #define _PIPEA_FLIPCOUNT_G4X 0x70044 4145 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 4146 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 4147 4148 /* Cursor A & B regs */ 4149 #define _CURACNTR 0x70080 4150 /* Old style CUR*CNTR flags (desktop 8xx) */ 4151 #define CURSOR_ENABLE REG_BIT(31) 4152 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) 4153 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) 4154 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ 4155 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) 4156 #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) 4157 #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) 4158 #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) 4159 #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) 4160 #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) 4161 /* New style CUR*CNTR flags */ 4162 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 4163 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ 4164 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) 4165 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) 4166 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) 4167 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 4168 #define MCURSOR_ROTATE_180 REG_BIT(15) 4169 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) 4170 #define MCURSOR_MODE_MASK 0x27 4171 #define MCURSOR_MODE_DISABLE 0x00 4172 #define MCURSOR_MODE_128_32B_AX 0x02 4173 #define MCURSOR_MODE_256_32B_AX 0x03 4174 #define MCURSOR_MODE_64_32B_AX 0x07 4175 #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) 4176 #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) 4177 #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) 4178 #define _CURABASE 0x70084 4179 #define _CURAPOS 0x70088 4180 #define CURSOR_POS_Y_SIGN REG_BIT(31) 4181 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) 4182 #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) 4183 #define CURSOR_POS_X_SIGN REG_BIT(15) 4184 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) 4185 #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) 4186 #define _CURASIZE 0x700a0 /* 845/865 */ 4187 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) 4188 #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) 4189 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) 4190 #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) 4191 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 4192 #define CUR_FBC_EN REG_BIT(31) 4193 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) 4194 #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) 4195 #define _CURASURFLIVE 0x700ac /* g4x+ */ 4196 #define _CURBCNTR 0x700c0 4197 #define _CURBBASE 0x700c4 4198 #define _CURBPOS 0x700c8 4199 4200 #define _CURBCNTR_IVB 0x71080 4201 #define _CURBBASE_IVB 0x71084 4202 #define _CURBPOS_IVB 0x71088 4203 4204 #define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR) 4205 #define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE) 4206 #define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS) 4207 #define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE) 4208 #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A) 4209 #define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE) 4210 4211 #define CURSOR_A_OFFSET 0x70080 4212 #define CURSOR_B_OFFSET 0x700c0 4213 #define CHV_CURSOR_C_OFFSET 0x700e0 4214 #define IVB_CURSOR_B_OFFSET 0x71080 4215 #define IVB_CURSOR_C_OFFSET 0x72080 4216 #define TGL_CURSOR_D_OFFSET 0x73080 4217 4218 /* Display A control */ 4219 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ 4220 #define _DSPACNTR 0x70180 4221 #define DISP_ENABLE REG_BIT(31) 4222 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) 4223 #define DISP_FORMAT_MASK REG_GENMASK(29, 26) 4224 #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) 4225 #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) 4226 #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) 4227 #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) 4228 #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) 4229 #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) 4230 #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) 4231 #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) 4232 #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) 4233 #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) 4234 #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) 4235 #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) 4236 #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) 4237 #define DISP_STEREO_ENABLE REG_BIT(25) 4238 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 4239 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) 4240 #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) 4241 #define DISP_SRC_KEY_ENABLE REG_BIT(22) 4242 #define DISP_LINE_DOUBLE REG_BIT(20) 4243 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) 4244 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ 4245 #define DISP_ROTATE_180 REG_BIT(15) 4246 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ 4247 #define DISP_TILED REG_BIT(10) 4248 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ 4249 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ 4250 #define _DSPAADDR 0x70184 4251 #define _DSPASTRIDE 0x70188 4252 #define _DSPAPOS 0x7018C /* reserved */ 4253 #define DISP_POS_Y_MASK REG_GENMASK(31, 16) 4254 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) 4255 #define DISP_POS_X_MASK REG_GENMASK(15, 0) 4256 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) 4257 #define _DSPASIZE 0x70190 4258 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) 4259 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) 4260 #define DISP_WIDTH_MASK REG_GENMASK(15, 0) 4261 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) 4262 #define _DSPASURF 0x7019C /* 965+ only */ 4263 #define DISP_ADDR_MASK REG_GENMASK(31, 12) 4264 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 4265 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) 4266 #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) 4267 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) 4268 #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) 4269 #define _DSPAOFFSET 0x701A4 /* HSW */ 4270 #define _DSPASURFLIVE 0x701AC 4271 #define _DSPAGAMC 0x701E0 4272 4273 #define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV) 4274 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 4275 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 4276 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 4277 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 4278 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 4279 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 4280 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 4281 #define DSPLINOFF(plane) DSPADDR(plane) 4282 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 4283 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 4284 #define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ 4285 4286 /* CHV pipe B blender and primary plane */ 4287 #define _CHV_BLEND_A 0x60a00 4288 #define CHV_BLEND_MASK REG_GENMASK(31, 30) 4289 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) 4290 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) 4291 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) 4292 #define _CHV_CANVAS_A 0x60a04 4293 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) 4294 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) 4295 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) 4296 #define _PRIMPOS_A 0x60a08 4297 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) 4298 #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) 4299 #define PRIM_POS_X_MASK REG_GENMASK(15, 0) 4300 #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) 4301 #define _PRIMSIZE_A 0x60a0c 4302 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) 4303 #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) 4304 #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) 4305 #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) 4306 #define _PRIMCNSTALPHA_A 0x60a10 4307 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) 4308 #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) 4309 #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) 4310 4311 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 4312 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 4313 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 4314 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 4315 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 4316 4317 /* Display/Sprite base address macros */ 4318 #define DISP_BASEADDR_MASK (0xfffff000) 4319 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 4320 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 4321 4322 /* 4323 * VBIOS flags 4324 * gen2: 4325 * [00:06] alm,mgm 4326 * [10:16] all 4327 * [30:32] alm,mgm 4328 * gen3+: 4329 * [00:0f] all 4330 * [10:1f] all 4331 * [30:32] all 4332 */ 4333 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 4334 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 4335 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 4336 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 4337 4338 /* Pipe B */ 4339 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) 4340 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) 4341 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) 4342 #define _PIPEBFRAMEHIGH 0x71040 4343 #define _PIPEBFRAMEPIXEL 0x71044 4344 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) 4345 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) 4346 4347 4348 /* Display B control */ 4349 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) 4350 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) 4351 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) 4352 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) 4353 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) 4354 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) 4355 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) 4356 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) 4357 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 4358 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 4359 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) 4360 4361 /* ICL DSI 0 and 1 */ 4362 #define _PIPEDSI0CONF 0x7b008 4363 #define _PIPEDSI1CONF 0x7b808 4364 4365 /* Sprite A control */ 4366 #define _DVSACNTR 0x72180 4367 #define DVS_ENABLE REG_BIT(31) 4368 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) 4369 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) 4370 #define DVS_FORMAT_MASK REG_GENMASK(26, 25) 4371 #define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0) 4372 #define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1) 4373 #define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2) 4374 #define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3) 4375 #define DVS_PIPE_CSC_ENABLE REG_BIT(24) 4376 #define DVS_SOURCE_KEY REG_BIT(22) 4377 #define DVS_RGB_ORDER_XBGR REG_BIT(20) 4378 #define DVS_YUV_FORMAT_BT709 REG_BIT(18) 4379 #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16) 4380 #define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0) 4381 #define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1) 4382 #define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2) 4383 #define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3) 4384 #define DVS_ROTATE_180 REG_BIT(15) 4385 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) 4386 #define DVS_TILED REG_BIT(10) 4387 #define DVS_DEST_KEY REG_BIT(2) 4388 #define _DVSALINOFF 0x72184 4389 #define _DVSASTRIDE 0x72188 4390 #define _DVSAPOS 0x7218c 4391 #define DVS_POS_Y_MASK REG_GENMASK(31, 16) 4392 #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) 4393 #define DVS_POS_X_MASK REG_GENMASK(15, 0) 4394 #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) 4395 #define _DVSASIZE 0x72190 4396 #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) 4397 #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) 4398 #define DVS_WIDTH_MASK REG_GENMASK(15, 0) 4399 #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) 4400 #define _DVSAKEYVAL 0x72194 4401 #define _DVSAKEYMSK 0x72198 4402 #define _DVSASURF 0x7219c 4403 #define DVS_ADDR_MASK REG_GENMASK(31, 12) 4404 #define _DVSAKEYMAXVAL 0x721a0 4405 #define _DVSATILEOFF 0x721a4 4406 #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) 4407 #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) 4408 #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) 4409 #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) 4410 #define _DVSASURFLIVE 0x721ac 4411 #define _DVSAGAMC_G4X 0x721e0 /* g4x */ 4412 #define _DVSASCALE 0x72204 4413 #define DVS_SCALE_ENABLE REG_BIT(31) 4414 #define DVS_FILTER_MASK REG_GENMASK(30, 29) 4415 #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) 4416 #define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1) 4417 #define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2) 4418 #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 4419 #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27) 4420 #define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16) 4421 #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) 4422 #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 4423 #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) 4424 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ 4425 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ 4426 4427 #define _DVSBCNTR 0x73180 4428 #define _DVSBLINOFF 0x73184 4429 #define _DVSBSTRIDE 0x73188 4430 #define _DVSBPOS 0x7318c 4431 #define _DVSBSIZE 0x73190 4432 #define _DVSBKEYVAL 0x73194 4433 #define _DVSBKEYMSK 0x73198 4434 #define _DVSBSURF 0x7319c 4435 #define _DVSBKEYMAXVAL 0x731a0 4436 #define _DVSBTILEOFF 0x731a4 4437 #define _DVSBSURFLIVE 0x731ac 4438 #define _DVSBGAMC_G4X 0x731e0 /* g4x */ 4439 #define _DVSBSCALE 0x73204 4440 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ 4441 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ 4442 4443 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 4444 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 4445 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 4446 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 4447 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 4448 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 4449 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 4450 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 4451 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 4452 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 4453 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 4454 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 4455 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ 4456 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ 4457 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ 4458 4459 #define _SPRA_CTL 0x70280 4460 #define SPRITE_ENABLE REG_BIT(31) 4461 #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30) 4462 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4463 #define SPRITE_FORMAT_MASK REG_GENMASK(27, 25) 4464 #define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0) 4465 #define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1) 4466 #define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2) 4467 #define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3) 4468 #define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4) 4469 #define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */ 4470 #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24) 4471 #define SPRITE_SOURCE_KEY REG_BIT(22) 4472 #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */ 4473 #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19) 4474 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */ 4475 #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16) 4476 #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0) 4477 #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1) 4478 #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2) 4479 #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3) 4480 #define SPRITE_ROTATE_180 REG_BIT(15) 4481 #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14) 4482 #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13) 4483 #define SPRITE_TILED REG_BIT(10) 4484 #define SPRITE_DEST_KEY REG_BIT(2) 4485 #define _SPRA_LINOFF 0x70284 4486 #define _SPRA_STRIDE 0x70288 4487 #define _SPRA_POS 0x7028c 4488 #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16) 4489 #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y)) 4490 #define SPRITE_POS_X_MASK REG_GENMASK(15, 0) 4491 #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x)) 4492 #define _SPRA_SIZE 0x70290 4493 #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16) 4494 #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h)) 4495 #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0) 4496 #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w)) 4497 #define _SPRA_KEYVAL 0x70294 4498 #define _SPRA_KEYMSK 0x70298 4499 #define _SPRA_SURF 0x7029c 4500 #define SPRITE_ADDR_MASK REG_GENMASK(31, 12) 4501 #define _SPRA_KEYMAX 0x702a0 4502 #define _SPRA_TILEOFF 0x702a4 4503 #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) 4504 #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) 4505 #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) 4506 #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) 4507 #define _SPRA_OFFSET 0x702a4 4508 #define _SPRA_SURFLIVE 0x702ac 4509 #define _SPRA_SCALE 0x70304 4510 #define SPRITE_SCALE_ENABLE REG_BIT(31) 4511 #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) 4512 #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0) 4513 #define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1) 4514 #define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2) 4515 #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 4516 #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27) 4517 #define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16) 4518 #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w)) 4519 #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 4520 #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h)) 4521 #define _SPRA_GAMC 0x70400 4522 #define _SPRA_GAMC16 0x70440 4523 #define _SPRA_GAMC17 0x7044c 4524 4525 #define _SPRB_CTL 0x71280 4526 #define _SPRB_LINOFF 0x71284 4527 #define _SPRB_STRIDE 0x71288 4528 #define _SPRB_POS 0x7128c 4529 #define _SPRB_SIZE 0x71290 4530 #define _SPRB_KEYVAL 0x71294 4531 #define _SPRB_KEYMSK 0x71298 4532 #define _SPRB_SURF 0x7129c 4533 #define _SPRB_KEYMAX 0x712a0 4534 #define _SPRB_TILEOFF 0x712a4 4535 #define _SPRB_OFFSET 0x712a4 4536 #define _SPRB_SURFLIVE 0x712ac 4537 #define _SPRB_SCALE 0x71304 4538 #define _SPRB_GAMC 0x71400 4539 #define _SPRB_GAMC16 0x71440 4540 #define _SPRB_GAMC17 0x7144c 4541 4542 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 4543 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 4544 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 4545 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 4546 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 4547 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 4548 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 4549 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 4550 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 4551 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 4552 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 4553 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 4554 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ 4555 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ 4556 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ 4557 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 4558 4559 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 4560 #define SP_ENABLE REG_BIT(31) 4561 #define SP_PIPE_GAMMA_ENABLE REG_BIT(30) 4562 #define SP_FORMAT_MASK REG_GENMASK(29, 26) 4563 #define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0) 4564 #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2) 4565 #define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5) 4566 #define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6) 4567 #define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7) 4568 #define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8) 4569 #define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9) 4570 #define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */ 4571 #define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */ 4572 #define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14) 4573 #define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15) 4574 #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */ 4575 #define SP_SOURCE_KEY REG_BIT(22) 4576 #define SP_YUV_FORMAT_BT709 REG_BIT(18) 4577 #define SP_YUV_ORDER_MASK REG_GENMASK(17, 16) 4578 #define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0) 4579 #define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1) 4580 #define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2) 4581 #define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3) 4582 #define SP_ROTATE_180 REG_BIT(15) 4583 #define SP_TILED REG_BIT(10) 4584 #define SP_MIRROR REG_BIT(8) /* CHV pipe B */ 4585 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 4586 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 4587 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 4588 #define SP_POS_Y_MASK REG_GENMASK(31, 16) 4589 #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y)) 4590 #define SP_POS_X_MASK REG_GENMASK(15, 0) 4591 #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x)) 4592 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 4593 #define SP_HEIGHT_MASK REG_GENMASK(31, 16) 4594 #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h)) 4595 #define SP_WIDTH_MASK REG_GENMASK(15, 0) 4596 #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w)) 4597 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 4598 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 4599 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 4600 #define SP_ADDR_MASK REG_GENMASK(31, 12) 4601 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 4602 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 4603 #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16) 4604 #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y)) 4605 #define SP_OFFSET_X_MASK REG_GENMASK(15, 0) 4606 #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x)) 4607 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 4608 #define SP_CONST_ALPHA_ENABLE REG_BIT(31) 4609 #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0) 4610 #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha)) 4611 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) 4612 #define SP_CONTRAST_MASK REG_GENMASK(26, 18) 4613 #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */ 4614 #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0) 4615 #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */ 4616 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) 4617 #define SP_SH_SIN_MASK REG_GENMASK(26, 16) 4618 #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */ 4619 #define SP_SH_COS_MASK REG_GENMASK(9, 0) 4620 #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */ 4621 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) 4622 4623 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 4624 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 4625 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 4626 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 4627 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 4628 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 4629 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 4630 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 4631 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 4632 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 4633 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 4634 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) 4635 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) 4636 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) 4637 4638 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 4639 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 4640 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 4641 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) 4642 4643 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 4644 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 4645 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 4646 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 4647 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 4648 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 4649 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 4650 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 4651 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 4652 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 4653 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 4654 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) 4655 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) 4656 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ 4657 4658 /* 4659 * CHV pipe B sprite CSC 4660 * 4661 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 4662 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 4663 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 4664 */ 4665 #define _MMIO_CHV_SPCSC(plane_id, reg) \ 4666 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 4667 4668 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 4669 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 4670 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 4671 #define SPCSC_OOFF_MASK REG_GENMASK(26, 16) 4672 #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */ 4673 #define SPCSC_IOFF_MASK REG_GENMASK(10, 0) 4674 #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */ 4675 4676 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 4677 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 4678 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 4679 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 4680 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 4681 #define SPCSC_C1_MASK REG_GENMASK(30, 16) 4682 #define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */ 4683 #define SPCSC_C0_MASK REG_GENMASK(14, 0) 4684 #define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */ 4685 4686 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 4687 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 4688 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 4689 #define SPCSC_IMAX_MASK REG_GENMASK(26, 16) 4690 #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */ 4691 #define SPCSC_IMIN_MASK REG_GENMASK(10, 0) 4692 #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */ 4693 4694 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 4695 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 4696 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 4697 #define SPCSC_OMAX_MASK REG_GENMASK(25, 16) 4698 #define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */ 4699 #define SPCSC_OMIN_MASK REG_GENMASK(9, 0) 4700 #define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */ 4701 4702 /* Skylake plane registers */ 4703 4704 #define _PLANE_CTL_1_A 0x70180 4705 #define _PLANE_CTL_2_A 0x70280 4706 #define _PLANE_CTL_3_A 0x70380 4707 #define PLANE_CTL_ENABLE REG_BIT(31) 4708 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 4709 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ 4710 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ 4711 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4712 /* 4713 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 4714 * expanded to include bit 23 as well. However, the shift-24 based values 4715 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 4716 */ 4717 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ 4718 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ 4719 #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) 4720 #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) 4721 #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) 4722 #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) 4723 #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) 4724 #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) 4725 #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) 4726 #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) 4727 #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) 4728 #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) 4729 #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) 4730 #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) 4731 #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) 4732 #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) 4733 #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) 4734 #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) 4735 #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) 4736 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ 4737 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) 4738 #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) 4739 #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) 4740 #define PLANE_CTL_ORDER_RGBX REG_BIT(20) 4741 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) 4742 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) 4743 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) 4744 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) 4745 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) 4746 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) 4747 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) 4748 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) 4749 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) 4750 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ 4751 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ 4752 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) 4753 #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) 4754 #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) 4755 #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) 4756 #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 4757 #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 4758 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9) 4759 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) 4760 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ 4761 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ 4762 #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) 4763 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) 4764 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) 4765 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) 4766 #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) 4767 #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) 4768 #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) 4769 #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) 4770 #define _PLANE_STRIDE_1_A 0x70188 4771 #define _PLANE_STRIDE_2_A 0x70288 4772 #define _PLANE_STRIDE_3_A 0x70388 4773 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) 4774 #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) 4775 #define _PLANE_POS_1_A 0x7018c 4776 #define _PLANE_POS_2_A 0x7028c 4777 #define _PLANE_POS_3_A 0x7038c 4778 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) 4779 #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) 4780 #define PLANE_POS_X_MASK REG_GENMASK(15, 0) 4781 #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) 4782 #define _PLANE_SIZE_1_A 0x70190 4783 #define _PLANE_SIZE_2_A 0x70290 4784 #define _PLANE_SIZE_3_A 0x70390 4785 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) 4786 #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) 4787 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) 4788 #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) 4789 #define _PLANE_SURF_1_A 0x7019c 4790 #define _PLANE_SURF_2_A 0x7029c 4791 #define _PLANE_SURF_3_A 0x7039c 4792 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) 4793 #define PLANE_SURF_DECRYPT REG_BIT(2) 4794 #define _PLANE_OFFSET_1_A 0x701a4 4795 #define _PLANE_OFFSET_2_A 0x702a4 4796 #define _PLANE_OFFSET_3_A 0x703a4 4797 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) 4798 #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) 4799 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) 4800 #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) 4801 #define _PLANE_KEYVAL_1_A 0x70194 4802 #define _PLANE_KEYVAL_2_A 0x70294 4803 #define _PLANE_KEYMSK_1_A 0x70198 4804 #define _PLANE_KEYMSK_2_A 0x70298 4805 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31) 4806 #define _PLANE_KEYMAX_1_A 0x701a0 4807 #define _PLANE_KEYMAX_2_A 0x702a0 4808 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) 4809 #define _PLANE_CC_VAL_1_A 0x701b4 4810 #define _PLANE_CC_VAL_2_A 0x702b4 4811 #define _PLANE_AUX_DIST_1_A 0x701c0 4812 #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) 4813 #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) 4814 #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) 4815 #define _PLANE_AUX_DIST_2_A 0x702c0 4816 #define _PLANE_AUX_OFFSET_1_A 0x701c4 4817 #define _PLANE_AUX_OFFSET_2_A 0x702c4 4818 #define _PLANE_CUS_CTL_1_A 0x701c8 4819 #define _PLANE_CUS_CTL_2_A 0x702c8 4820 #define PLANE_CUS_ENABLE REG_BIT(31) 4821 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) 4822 #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 4823 #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 4824 #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 4825 #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 4826 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) 4827 #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) 4828 #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) 4829 #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) 4830 #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) 4831 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) 4832 #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) 4833 #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) 4834 #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) 4835 #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) 4836 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 4837 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 4838 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 4839 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ 4840 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4841 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ 4842 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ 4843 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ 4844 #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) 4845 #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) 4846 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) 4847 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) 4848 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) 4849 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) 4850 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) 4851 #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) 4852 #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) 4853 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) 4854 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) 4855 #define _PLANE_BUF_CFG_1_A 0x7027c 4856 #define _PLANE_BUF_CFG_2_A 0x7037c 4857 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 4858 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 4859 4860 #define _PLANE_CC_VAL_1_B 0x711b4 4861 #define _PLANE_CC_VAL_2_B 0x712b4 4862 #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) 4863 #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) 4864 #define PLANE_CC_VAL(pipe, plane, dw) \ 4865 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) 4866 4867 /* Input CSC Register Definitions */ 4868 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 4869 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 4870 4871 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 4872 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 4873 4874 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ 4875 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ 4876 _PLANE_INPUT_CSC_RY_GY_1_B) 4877 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ 4878 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 4879 _PLANE_INPUT_CSC_RY_GY_2_B) 4880 4881 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ 4882 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ 4883 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) 4884 4885 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 4886 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 4887 4888 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 4889 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 4890 4891 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ 4892 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ 4893 _PLANE_INPUT_CSC_PREOFF_HI_1_B) 4894 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ 4895 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ 4896 _PLANE_INPUT_CSC_PREOFF_HI_2_B) 4897 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ 4898 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ 4899 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) 4900 4901 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 4902 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 4903 4904 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 4905 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 4906 4907 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ 4908 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ 4909 _PLANE_INPUT_CSC_POSTOFF_HI_1_B) 4910 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ 4911 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ 4912 _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 4913 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ 4914 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ 4915 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) 4916 4917 #define _PLANE_CTL_1_B 0x71180 4918 #define _PLANE_CTL_2_B 0x71280 4919 #define _PLANE_CTL_3_B 0x71380 4920 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 4921 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 4922 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 4923 #define PLANE_CTL(pipe, plane) \ 4924 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 4925 4926 #define _PLANE_STRIDE_1_B 0x71188 4927 #define _PLANE_STRIDE_2_B 0x71288 4928 #define _PLANE_STRIDE_3_B 0x71388 4929 #define _PLANE_STRIDE_1(pipe) \ 4930 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 4931 #define _PLANE_STRIDE_2(pipe) \ 4932 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 4933 #define _PLANE_STRIDE_3(pipe) \ 4934 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 4935 #define PLANE_STRIDE(pipe, plane) \ 4936 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 4937 4938 #define _PLANE_POS_1_B 0x7118c 4939 #define _PLANE_POS_2_B 0x7128c 4940 #define _PLANE_POS_3_B 0x7138c 4941 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 4942 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 4943 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 4944 #define PLANE_POS(pipe, plane) \ 4945 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 4946 4947 #define _PLANE_SIZE_1_B 0x71190 4948 #define _PLANE_SIZE_2_B 0x71290 4949 #define _PLANE_SIZE_3_B 0x71390 4950 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 4951 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 4952 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 4953 #define PLANE_SIZE(pipe, plane) \ 4954 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 4955 4956 #define _PLANE_SURF_1_B 0x7119c 4957 #define _PLANE_SURF_2_B 0x7129c 4958 #define _PLANE_SURF_3_B 0x7139c 4959 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 4960 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 4961 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 4962 #define PLANE_SURF(pipe, plane) \ 4963 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 4964 4965 #define _PLANE_OFFSET_1_B 0x711a4 4966 #define _PLANE_OFFSET_2_B 0x712a4 4967 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 4968 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 4969 #define PLANE_OFFSET(pipe, plane) \ 4970 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 4971 4972 #define _PLANE_KEYVAL_1_B 0x71194 4973 #define _PLANE_KEYVAL_2_B 0x71294 4974 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 4975 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 4976 #define PLANE_KEYVAL(pipe, plane) \ 4977 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 4978 4979 #define _PLANE_KEYMSK_1_B 0x71198 4980 #define _PLANE_KEYMSK_2_B 0x71298 4981 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 4982 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 4983 #define PLANE_KEYMSK(pipe, plane) \ 4984 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 4985 4986 #define _PLANE_KEYMAX_1_B 0x711a0 4987 #define _PLANE_KEYMAX_2_B 0x712a0 4988 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 4989 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 4990 #define PLANE_KEYMAX(pipe, plane) \ 4991 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 4992 4993 #define _PLANE_BUF_CFG_1_B 0x7127c 4994 #define _PLANE_BUF_CFG_2_B 0x7137c 4995 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ 4996 #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) 4997 #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) 4998 #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) 4999 #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) 5000 #define _PLANE_BUF_CFG_1(pipe) \ 5001 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 5002 #define _PLANE_BUF_CFG_2(pipe) \ 5003 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 5004 #define PLANE_BUF_CFG(pipe, plane) \ 5005 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 5006 5007 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 5008 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 5009 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 5010 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 5011 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 5012 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 5013 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 5014 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 5015 5016 #define _PLANE_AUX_DIST_1_B 0x711c0 5017 #define _PLANE_AUX_DIST_2_B 0x712c0 5018 #define _PLANE_AUX_DIST_1(pipe) \ 5019 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 5020 #define _PLANE_AUX_DIST_2(pipe) \ 5021 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 5022 #define PLANE_AUX_DIST(pipe, plane) \ 5023 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 5024 5025 #define _PLANE_AUX_OFFSET_1_B 0x711c4 5026 #define _PLANE_AUX_OFFSET_2_B 0x712c4 5027 #define _PLANE_AUX_OFFSET_1(pipe) \ 5028 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 5029 #define _PLANE_AUX_OFFSET_2(pipe) \ 5030 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 5031 #define PLANE_AUX_OFFSET(pipe, plane) \ 5032 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 5033 5034 #define _PLANE_CUS_CTL_1_B 0x711c8 5035 #define _PLANE_CUS_CTL_2_B 0x712c8 5036 #define _PLANE_CUS_CTL_1(pipe) \ 5037 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) 5038 #define _PLANE_CUS_CTL_2(pipe) \ 5039 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 5040 #define PLANE_CUS_CTL(pipe, plane) \ 5041 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) 5042 5043 #define _PLANE_COLOR_CTL_1_B 0x711CC 5044 #define _PLANE_COLOR_CTL_2_B 0x712CC 5045 #define _PLANE_COLOR_CTL_3_B 0x713CC 5046 #define _PLANE_COLOR_CTL_1(pipe) \ 5047 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 5048 #define _PLANE_COLOR_CTL_2(pipe) \ 5049 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 5050 #define PLANE_COLOR_CTL(pipe, plane) \ 5051 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 5052 5053 #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 5054 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 5055 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 5056 #define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 5057 #define _SEL_FETCH_PLANE_BASE_5_A 0x70920 5058 #define _SEL_FETCH_PLANE_BASE_6_A 0x70940 5059 #define _SEL_FETCH_PLANE_BASE_7_A 0x70960 5060 #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 5061 #define _SEL_FETCH_PLANE_BASE_1_B 0x71890 5062 5063 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ 5064 _SEL_FETCH_PLANE_BASE_1_A, \ 5065 _SEL_FETCH_PLANE_BASE_2_A, \ 5066 _SEL_FETCH_PLANE_BASE_3_A, \ 5067 _SEL_FETCH_PLANE_BASE_4_A, \ 5068 _SEL_FETCH_PLANE_BASE_5_A, \ 5069 _SEL_FETCH_PLANE_BASE_6_A, \ 5070 _SEL_FETCH_PLANE_BASE_7_A, \ 5071 _SEL_FETCH_PLANE_BASE_CUR_A) 5072 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) 5073 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ 5074 _SEL_FETCH_PLANE_BASE_1_A + \ 5075 _SEL_FETCH_PLANE_BASE_A(plane)) 5076 5077 #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 5078 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5079 _SEL_FETCH_PLANE_CTL_1_A - \ 5080 _SEL_FETCH_PLANE_BASE_1_A) 5081 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) 5082 5083 #define _SEL_FETCH_PLANE_POS_1_A 0x70894 5084 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5085 _SEL_FETCH_PLANE_POS_1_A - \ 5086 _SEL_FETCH_PLANE_BASE_1_A) 5087 5088 #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 5089 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5090 _SEL_FETCH_PLANE_SIZE_1_A - \ 5091 _SEL_FETCH_PLANE_BASE_1_A) 5092 5093 #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C 5094 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5095 _SEL_FETCH_PLANE_OFFSET_1_A - \ 5096 _SEL_FETCH_PLANE_BASE_1_A) 5097 5098 /* SKL new cursor registers */ 5099 #define _CUR_BUF_CFG_A 0x7017c 5100 #define _CUR_BUF_CFG_B 0x7117c 5101 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 5102 5103 /* VBIOS regs */ 5104 #define VGACNTRL _MMIO(0x71400) 5105 # define VGA_DISP_DISABLE (1 << 31) 5106 # define VGA_2X_MODE (1 << 30) 5107 # define VGA_PIPE_B_SELECT (1 << 29) 5108 5109 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 5110 5111 /* Ironlake */ 5112 5113 #define CPU_VGACNTRL _MMIO(0x41000) 5114 5115 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 5116 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 5117 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 5118 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 5119 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 5120 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 5121 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 5122 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 5123 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 5124 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 5125 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 5126 5127 /* refresh rate hardware control */ 5128 #define RR_HW_CTL _MMIO(0x45300) 5129 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 5130 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 5131 5132 #define FDI_PLL_BIOS_0 _MMIO(0x46000) 5133 #define FDI_PLL_FB_CLOCK_MASK 0xff 5134 #define FDI_PLL_BIOS_1 _MMIO(0x46004) 5135 #define FDI_PLL_BIOS_2 _MMIO(0x46008) 5136 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 5137 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 5138 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 5139 5140 #define PCH_3DCGDIS0 _MMIO(0x46020) 5141 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 5142 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 5143 5144 #define PCH_3DCGDIS1 _MMIO(0x46024) 5145 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 5146 5147 #define FDI_PLL_FREQ_CTL _MMIO(0x46030) 5148 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24) 5149 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 5150 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 5151 5152 5153 #define _PIPEA_DATA_M1 0x60030 5154 #define _PIPEA_DATA_N1 0x60034 5155 #define _PIPEA_DATA_M2 0x60038 5156 #define _PIPEA_DATA_N2 0x6003c 5157 #define _PIPEA_LINK_M1 0x60040 5158 #define _PIPEA_LINK_N1 0x60044 5159 #define _PIPEA_LINK_M2 0x60048 5160 #define _PIPEA_LINK_N2 0x6004c 5161 5162 /* PIPEB timing regs are same start from 0x61000 */ 5163 5164 #define _PIPEB_DATA_M1 0x61030 5165 #define _PIPEB_DATA_N1 0x61034 5166 #define _PIPEB_DATA_M2 0x61038 5167 #define _PIPEB_DATA_N2 0x6103c 5168 #define _PIPEB_LINK_M1 0x61040 5169 #define _PIPEB_LINK_N1 0x61044 5170 #define _PIPEB_LINK_M2 0x61048 5171 #define _PIPEB_LINK_N2 0x6104c 5172 5173 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 5174 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 5175 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 5176 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 5177 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 5178 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 5179 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 5180 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 5181 5182 /* CPU panel fitter */ 5183 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 5184 #define _PFA_CTL_1 0x68080 5185 #define _PFB_CTL_1 0x68880 5186 #define PF_ENABLE (1 << 31) 5187 #define PF_PIPE_SEL_MASK_IVB (3 << 29) 5188 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29) 5189 #define PF_FILTER_MASK (3 << 23) 5190 #define PF_FILTER_PROGRAMMED (0 << 23) 5191 #define PF_FILTER_MED_3x3 (1 << 23) 5192 #define PF_FILTER_EDGE_ENHANCE (2 << 23) 5193 #define PF_FILTER_EDGE_SOFTEN (3 << 23) 5194 #define _PFA_WIN_SZ 0x68074 5195 #define _PFB_WIN_SZ 0x68874 5196 #define _PFA_WIN_POS 0x68070 5197 #define _PFB_WIN_POS 0x68870 5198 #define _PFA_VSCALE 0x68084 5199 #define _PFB_VSCALE 0x68884 5200 #define _PFA_HSCALE 0x68090 5201 #define _PFB_HSCALE 0x68890 5202 5203 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 5204 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 5205 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 5206 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 5207 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 5208 5209 #define _PSA_CTL 0x68180 5210 #define _PSB_CTL 0x68980 5211 #define PS_ENABLE (1 << 31) 5212 #define _PSA_WIN_SZ 0x68174 5213 #define _PSB_WIN_SZ 0x68974 5214 #define _PSA_WIN_POS 0x68170 5215 #define _PSB_WIN_POS 0x68970 5216 5217 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 5218 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 5219 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 5220 5221 /* 5222 * Skylake scalers 5223 */ 5224 #define _PS_1A_CTRL 0x68180 5225 #define _PS_2A_CTRL 0x68280 5226 #define _PS_1B_CTRL 0x68980 5227 #define _PS_2B_CTRL 0x68A80 5228 #define _PS_1C_CTRL 0x69180 5229 #define PS_SCALER_EN (1 << 31) 5230 #define SKL_PS_SCALER_MODE_MASK (3 << 28) 5231 #define SKL_PS_SCALER_MODE_DYN (0 << 28) 5232 #define SKL_PS_SCALER_MODE_HQ (1 << 28) 5233 #define SKL_PS_SCALER_MODE_NV12 (2 << 28) 5234 #define PS_SCALER_MODE_PLANAR (1 << 29) 5235 #define PS_SCALER_MODE_NORMAL (0 << 29) 5236 #define PS_PLANE_SEL_MASK (7 << 25) 5237 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 5238 #define PS_FILTER_MASK (3 << 23) 5239 #define PS_FILTER_MEDIUM (0 << 23) 5240 #define PS_FILTER_PROGRAMMED (1 << 23) 5241 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 5242 #define PS_FILTER_BILINEAR (3 << 23) 5243 #define PS_VERT3TAP (1 << 21) 5244 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 5245 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 5246 #define PS_PWRUP_PROGRESS (1 << 17) 5247 #define PS_V_FILTER_BYPASS (1 << 8) 5248 #define PS_VADAPT_EN (1 << 7) 5249 #define PS_VADAPT_MODE_MASK (3 << 5) 5250 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 5251 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 5252 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 5253 #define PS_PLANE_Y_SEL_MASK (7 << 5) 5254 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5) 5255 #define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4) 5256 #define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3) 5257 #define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2) 5258 #define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1) 5259 5260 #define _PS_PWR_GATE_1A 0x68160 5261 #define _PS_PWR_GATE_2A 0x68260 5262 #define _PS_PWR_GATE_1B 0x68960 5263 #define _PS_PWR_GATE_2B 0x68A60 5264 #define _PS_PWR_GATE_1C 0x69160 5265 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 5266 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 5267 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 5268 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 5269 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 5270 #define PS_PWR_GATE_SLPEN_8 0 5271 #define PS_PWR_GATE_SLPEN_16 1 5272 #define PS_PWR_GATE_SLPEN_24 2 5273 #define PS_PWR_GATE_SLPEN_32 3 5274 5275 #define _PS_WIN_POS_1A 0x68170 5276 #define _PS_WIN_POS_2A 0x68270 5277 #define _PS_WIN_POS_1B 0x68970 5278 #define _PS_WIN_POS_2B 0x68A70 5279 #define _PS_WIN_POS_1C 0x69170 5280 5281 #define _PS_WIN_SZ_1A 0x68174 5282 #define _PS_WIN_SZ_2A 0x68274 5283 #define _PS_WIN_SZ_1B 0x68974 5284 #define _PS_WIN_SZ_2B 0x68A74 5285 #define _PS_WIN_SZ_1C 0x69174 5286 5287 #define _PS_VSCALE_1A 0x68184 5288 #define _PS_VSCALE_2A 0x68284 5289 #define _PS_VSCALE_1B 0x68984 5290 #define _PS_VSCALE_2B 0x68A84 5291 #define _PS_VSCALE_1C 0x69184 5292 5293 #define _PS_HSCALE_1A 0x68190 5294 #define _PS_HSCALE_2A 0x68290 5295 #define _PS_HSCALE_1B 0x68990 5296 #define _PS_HSCALE_2B 0x68A90 5297 #define _PS_HSCALE_1C 0x69190 5298 5299 #define _PS_VPHASE_1A 0x68188 5300 #define _PS_VPHASE_2A 0x68288 5301 #define _PS_VPHASE_1B 0x68988 5302 #define _PS_VPHASE_2B 0x68A88 5303 #define _PS_VPHASE_1C 0x69188 5304 #define PS_Y_PHASE(x) ((x) << 16) 5305 #define PS_UV_RGB_PHASE(x) ((x) << 0) 5306 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 5307 #define PS_PHASE_TRIP (1 << 0) 5308 5309 #define _PS_HPHASE_1A 0x68194 5310 #define _PS_HPHASE_2A 0x68294 5311 #define _PS_HPHASE_1B 0x68994 5312 #define _PS_HPHASE_2B 0x68A94 5313 #define _PS_HPHASE_1C 0x69194 5314 5315 #define _PS_ECC_STAT_1A 0x681D0 5316 #define _PS_ECC_STAT_2A 0x682D0 5317 #define _PS_ECC_STAT_1B 0x689D0 5318 #define _PS_ECC_STAT_2B 0x68AD0 5319 #define _PS_ECC_STAT_1C 0x691D0 5320 5321 #define _PS_COEF_SET0_INDEX_1A 0x68198 5322 #define _PS_COEF_SET0_INDEX_2A 0x68298 5323 #define _PS_COEF_SET0_INDEX_1B 0x68998 5324 #define _PS_COEF_SET0_INDEX_2B 0x68A98 5325 #define PS_COEE_INDEX_AUTO_INC (1 << 10) 5326 5327 #define _PS_COEF_SET0_DATA_1A 0x6819C 5328 #define _PS_COEF_SET0_DATA_2A 0x6829C 5329 #define _PS_COEF_SET0_DATA_1B 0x6899C 5330 #define _PS_COEF_SET0_DATA_2B 0x68A9C 5331 5332 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 5333 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 5334 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 5335 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 5336 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 5337 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 5338 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 5339 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 5340 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 5341 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 5342 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 5343 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 5344 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 5345 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5346 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 5347 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 5348 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5349 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 5350 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 5351 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5352 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 5353 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 5354 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5355 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 5356 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 5357 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 5358 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 5359 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 5360 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 5361 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ 5362 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) 5363 5364 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 5365 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ 5366 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) 5367 /* legacy palette */ 5368 #define _LGC_PALETTE_A 0x4a000 5369 #define _LGC_PALETTE_B 0x4a800 5370 #define LGC_PALETTE_RED_MASK REG_GENMASK(23, 16) 5371 #define LGC_PALETTE_GREEN_MASK REG_GENMASK(15, 8) 5372 #define LGC_PALETTE_BLUE_MASK REG_GENMASK(7, 0) 5373 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 5374 5375 /* ilk/snb precision palette */ 5376 #define _PREC_PALETTE_A 0x4b000 5377 #define _PREC_PALETTE_B 0x4c000 5378 #define PREC_PALETTE_RED_MASK REG_GENMASK(29, 20) 5379 #define PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10) 5380 #define PREC_PALETTE_BLUE_MASK REG_GENMASK(9, 0) 5381 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) 5382 5383 #define _PREC_PIPEAGCMAX 0x4d000 5384 #define _PREC_PIPEBGCMAX 0x4d010 5385 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) 5386 5387 #define _GAMMA_MODE_A 0x4a480 5388 #define _GAMMA_MODE_B 0x4ac80 5389 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 5390 #define PRE_CSC_GAMMA_ENABLE (1 << 31) 5391 #define POST_CSC_GAMMA_ENABLE (1 << 30) 5392 #define GAMMA_MODE_MODE_MASK (3 << 0) 5393 #define GAMMA_MODE_MODE_8BIT (0 << 0) 5394 #define GAMMA_MODE_MODE_10BIT (1 << 0) 5395 #define GAMMA_MODE_MODE_12BIT (2 << 0) 5396 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ 5397 #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ 5398 5399 /* Display Internal Timeout Register */ 5400 #define RM_TIMEOUT _MMIO(0x42060) 5401 #define MMIO_TIMEOUT_US(us) ((us) << 0) 5402 5403 /* interrupts */ 5404 #define DE_MASTER_IRQ_CONTROL (1 << 31) 5405 #define DE_SPRITEB_FLIP_DONE (1 << 29) 5406 #define DE_SPRITEA_FLIP_DONE (1 << 28) 5407 #define DE_PLANEB_FLIP_DONE (1 << 27) 5408 #define DE_PLANEA_FLIP_DONE (1 << 26) 5409 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 5410 #define DE_PCU_EVENT (1 << 25) 5411 #define DE_GTT_FAULT (1 << 24) 5412 #define DE_POISON (1 << 23) 5413 #define DE_PERFORM_COUNTER (1 << 22) 5414 #define DE_PCH_EVENT (1 << 21) 5415 #define DE_AUX_CHANNEL_A (1 << 20) 5416 #define DE_DP_A_HOTPLUG (1 << 19) 5417 #define DE_GSE (1 << 18) 5418 #define DE_PIPEB_VBLANK (1 << 15) 5419 #define DE_PIPEB_EVEN_FIELD (1 << 14) 5420 #define DE_PIPEB_ODD_FIELD (1 << 13) 5421 #define DE_PIPEB_LINE_COMPARE (1 << 12) 5422 #define DE_PIPEB_VSYNC (1 << 11) 5423 #define DE_PIPEB_CRC_DONE (1 << 10) 5424 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 5425 #define DE_PIPEA_VBLANK (1 << 7) 5426 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 5427 #define DE_PIPEA_EVEN_FIELD (1 << 6) 5428 #define DE_PIPEA_ODD_FIELD (1 << 5) 5429 #define DE_PIPEA_LINE_COMPARE (1 << 4) 5430 #define DE_PIPEA_VSYNC (1 << 3) 5431 #define DE_PIPEA_CRC_DONE (1 << 2) 5432 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 5433 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 5434 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 5435 5436 /* More Ivybridge lolz */ 5437 #define DE_ERR_INT_IVB (1 << 30) 5438 #define DE_GSE_IVB (1 << 29) 5439 #define DE_PCH_EVENT_IVB (1 << 28) 5440 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 5441 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 5442 #define DE_EDP_PSR_INT_HSW (1 << 19) 5443 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 5444 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 5445 #define DE_PIPEC_VBLANK_IVB (1 << 10) 5446 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 5447 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 5448 #define DE_PIPEB_VBLANK_IVB (1 << 5) 5449 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 5450 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 5451 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 5452 #define DE_PIPEA_VBLANK_IVB (1 << 0) 5453 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 5454 5455 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 5456 #define MASTER_INTERRUPT_ENABLE (1 << 31) 5457 5458 #define DEISR _MMIO(0x44000) 5459 #define DEIMR _MMIO(0x44004) 5460 #define DEIIR _MMIO(0x44008) 5461 #define DEIER _MMIO(0x4400c) 5462 5463 #define GTISR _MMIO(0x44010) 5464 #define GTIMR _MMIO(0x44014) 5465 #define GTIIR _MMIO(0x44018) 5466 #define GTIER _MMIO(0x4401c) 5467 5468 #define GEN8_MASTER_IRQ _MMIO(0x44200) 5469 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 5470 #define GEN8_PCU_IRQ (1 << 30) 5471 #define GEN8_DE_PCH_IRQ (1 << 23) 5472 #define GEN8_DE_MISC_IRQ (1 << 22) 5473 #define GEN8_DE_PORT_IRQ (1 << 20) 5474 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 5475 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 5476 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 5477 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 5478 #define GEN8_GT_VECS_IRQ (1 << 6) 5479 #define GEN8_GT_GUC_IRQ (1 << 5) 5480 #define GEN8_GT_PM_IRQ (1 << 4) 5481 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 5482 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 5483 #define GEN8_GT_BCS_IRQ (1 << 1) 5484 #define GEN8_GT_RCS_IRQ (1 << 0) 5485 5486 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) 5487 5488 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 5489 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 5490 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 5491 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 5492 5493 #define GEN8_RCS_IRQ_SHIFT 0 5494 #define GEN8_BCS_IRQ_SHIFT 16 5495 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 5496 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 5497 #define GEN8_VECS_IRQ_SHIFT 0 5498 #define GEN8_WD_IRQ_SHIFT 16 5499 5500 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 5501 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 5502 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 5503 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 5504 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 5505 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 5506 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 5507 #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22) 5508 #define XELPD_PIPE_HARD_UNDERRUN (1 << 21) 5509 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 5510 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 5511 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 5512 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 5513 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 5514 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 5515 #define GEN8_PIPE_VSYNC (1 << 1) 5516 #define GEN8_PIPE_VBLANK (1 << 0) 5517 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 5518 #define GEN11_PIPE_PLANE7_FAULT (1 << 22) 5519 #define GEN11_PIPE_PLANE6_FAULT (1 << 21) 5520 #define GEN11_PIPE_PLANE5_FAULT (1 << 20) 5521 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 5522 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 5523 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 5524 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 5525 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 5526 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 5527 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 5528 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 5529 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 5530 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 5531 (GEN8_PIPE_CURSOR_FAULT | \ 5532 GEN8_PIPE_SPRITE_FAULT | \ 5533 GEN8_PIPE_PRIMARY_FAULT) 5534 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 5535 (GEN9_PIPE_CURSOR_FAULT | \ 5536 GEN9_PIPE_PLANE4_FAULT | \ 5537 GEN9_PIPE_PLANE3_FAULT | \ 5538 GEN9_PIPE_PLANE2_FAULT | \ 5539 GEN9_PIPE_PLANE1_FAULT) 5540 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ 5541 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 5542 GEN11_PIPE_PLANE7_FAULT | \ 5543 GEN11_PIPE_PLANE6_FAULT | \ 5544 GEN11_PIPE_PLANE5_FAULT) 5545 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ 5546 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 5547 GEN11_PIPE_PLANE5_FAULT) 5548 5549 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) 5550 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) 5551 5552 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 5553 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 5554 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 5555 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 5556 #define DSI1_NON_TE (1 << 31) 5557 #define DSI0_NON_TE (1 << 30) 5558 #define ICL_AUX_CHANNEL_E (1 << 29) 5559 #define ICL_AUX_CHANNEL_F (1 << 28) 5560 #define GEN9_AUX_CHANNEL_D (1 << 27) 5561 #define GEN9_AUX_CHANNEL_C (1 << 26) 5562 #define GEN9_AUX_CHANNEL_B (1 << 25) 5563 #define DSI1_TE (1 << 24) 5564 #define DSI0_TE (1 << 23) 5565 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) 5566 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ 5567 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ 5568 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) 5569 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) 5570 #define BXT_DE_PORT_GMBUS (1 << 1) 5571 #define GEN8_AUX_CHANNEL_A (1 << 0) 5572 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) 5573 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) 5574 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) 5575 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12) 5576 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) 5577 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) 5578 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) 5579 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) 5580 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2) 5581 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) 5582 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) 5583 5584 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 5585 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 5586 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 5587 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 5588 #define GEN8_DE_MISC_GSE (1 << 27) 5589 #define GEN8_DE_EDP_PSR (1 << 19) 5590 5591 #define GEN8_PCU_ISR _MMIO(0x444e0) 5592 #define GEN8_PCU_IMR _MMIO(0x444e4) 5593 #define GEN8_PCU_IIR _MMIO(0x444e8) 5594 #define GEN8_PCU_IER _MMIO(0x444ec) 5595 5596 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 5597 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 5598 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 5599 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 5600 #define GEN11_GU_MISC_GSE (1 << 27) 5601 5602 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 5603 #define GEN11_MASTER_IRQ (1 << 31) 5604 #define GEN11_PCU_IRQ (1 << 30) 5605 #define GEN11_GU_MISC_IRQ (1 << 29) 5606 #define GEN11_DISPLAY_IRQ (1 << 16) 5607 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 5608 #define GEN11_GT_DW1_IRQ (1 << 1) 5609 #define GEN11_GT_DW0_IRQ (1 << 0) 5610 5611 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) 5612 #define DG1_MSTR_IRQ REG_BIT(31) 5613 #define DG1_MSTR_TILE(t) REG_BIT(t) 5614 5615 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 5616 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 5617 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 5618 #define GEN11_DE_PCH_IRQ (1 << 23) 5619 #define GEN11_DE_MISC_IRQ (1 << 22) 5620 #define GEN11_DE_HPD_IRQ (1 << 21) 5621 #define GEN11_DE_PORT_IRQ (1 << 20) 5622 #define GEN11_DE_PIPE_C (1 << 18) 5623 #define GEN11_DE_PIPE_B (1 << 17) 5624 #define GEN11_DE_PIPE_A (1 << 16) 5625 5626 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 5627 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 5628 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 5629 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 5630 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 5631 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ 5632 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ 5633 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ 5634 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ 5635 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ 5636 GEN11_TC_HOTPLUG(HPD_PORT_TC1)) 5637 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 5638 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ 5639 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ 5640 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ 5641 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ 5642 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ 5643 GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) 5644 5645 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 5646 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 5647 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 5648 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 5649 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 5650 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) 5651 5652 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 5653 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 5654 #define ILK_ELPIN_409_SELECT (1 << 25) 5655 #define ILK_DPARB_GATE (1 << 22) 5656 #define ILK_VSDPFD_FULL (1 << 21) 5657 #define FUSE_STRAP _MMIO(0x42014) 5658 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 5659 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 5660 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 5661 #define IVB_PIPE_C_DISABLE (1 << 28) 5662 #define ILK_HDCP_DISABLE (1 << 25) 5663 #define ILK_eDP_A_DISABLE (1 << 24) 5664 #define HSW_CDCLK_LIMIT (1 << 24) 5665 #define ILK_DESKTOP (1 << 23) 5666 #define HSW_CPU_SSC_ENABLE (1 << 21) 5667 5668 #define FUSE_STRAP3 _MMIO(0x42020) 5669 #define HSW_REF_CLK_SELECT (1 << 1) 5670 5671 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 5672 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 5673 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 5674 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 5675 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 5676 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 5677 5678 #define IVB_CHICKEN3 _MMIO(0x4200c) 5679 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 5680 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 5681 5682 #define CHICKEN_PAR1_1 _MMIO(0x42080) 5683 #define IGNORE_KVMR_PIPE_A REG_BIT(23) 5684 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) 5685 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16) 5686 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) 5687 #define DPA_MASK_VBLANK_SRD (1 << 15) 5688 #define FORCE_ARB_IDLE_PLANES (1 << 14) 5689 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 5690 #define IGNORE_PSR2_HW_TRACKING (1 << 1) 5691 5692 #define CHICKEN_PAR2_1 _MMIO(0x42090) 5693 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 5694 5695 #define CHICKEN_MISC_2 _MMIO(0x42084) 5696 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) 5697 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) 5698 #define GLK_CL2_PWR_DOWN (1 << 12) 5699 #define GLK_CL1_PWR_DOWN (1 << 11) 5700 #define GLK_CL0_PWR_DOWN (1 << 10) 5701 5702 #define CHICKEN_MISC_4 _MMIO(0x4208c) 5703 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) 5704 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) 5705 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) 5706 5707 #define _CHICKEN_PIPESL_1_A 0x420b0 5708 #define _CHICKEN_PIPESL_1_B 0x420b4 5709 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 5710 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 5711 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 5712 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 5713 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 5714 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 5715 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 5716 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 5717 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 5718 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 5719 #define HSW_FBCQ_DIS (1 << 22) 5720 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 5721 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) 5722 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) 5723 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) 5724 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) 5725 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) 5726 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 5727 5728 #define _CHICKEN_TRANS_A 0x420c0 5729 #define _CHICKEN_TRANS_B 0x420c4 5730 #define _CHICKEN_TRANS_C 0x420c8 5731 #define _CHICKEN_TRANS_EDP 0x420cc 5732 #define _CHICKEN_TRANS_D 0x420d8 5733 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 5734 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 5735 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 5736 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ 5737 [TRANSCODER_C] = _CHICKEN_TRANS_C, \ 5738 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 5739 5740 #define _MTL_CHICKEN_TRANS_A 0x604e0 5741 #define _MTL_CHICKEN_TRANS_B 0x614e0 5742 #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ 5743 _MTL_CHICKEN_TRANS_A, \ 5744 _MTL_CHICKEN_TRANS_B) 5745 5746 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 5747 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) 5748 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ 5749 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) 5750 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) 5751 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) 5752 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) 5753 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ 5754 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ 5755 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) 5756 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) 5757 5758 #define DISP_ARB_CTL _MMIO(0x45000) 5759 #define DISP_FBC_MEMORY_WAKE (1 << 31) 5760 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13) 5761 #define DISP_FBC_WM_DIS (1 << 15) 5762 #define DISP_ARB_CTL2 _MMIO(0x45004) 5763 #define DISP_DATA_PARTITION_5_6 (1 << 6) 5764 #define DISP_IPC_ENABLE (1 << 3) 5765 5766 /* 5767 * The below are numbered starting from "S1" on gen11/gen12, but starting 5768 * with display 13, the bspec switches to a 0-based numbering scheme 5769 * (although the addresses stay the same so new S0 = old S1, new S1 = old S2). 5770 * We'll just use the 0-based numbering here for all platforms since it's the 5771 * way things will be named by the hardware team going forward, plus it's more 5772 * consistent with how most of the rest of our registers are named. 5773 */ 5774 #define _DBUF_CTL_S0 0x45008 5775 #define _DBUF_CTL_S1 0x44FE8 5776 #define _DBUF_CTL_S2 0x44300 5777 #define _DBUF_CTL_S3 0x44304 5778 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \ 5779 _DBUF_CTL_S0, \ 5780 _DBUF_CTL_S1, \ 5781 _DBUF_CTL_S2, \ 5782 _DBUF_CTL_S3)) 5783 #define DBUF_POWER_REQUEST REG_BIT(31) 5784 #define DBUF_POWER_STATE REG_BIT(30) 5785 #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19) 5786 #define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x) 5787 #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */ 5788 #define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */ 5789 5790 #define GEN7_MSG_CTL _MMIO(0x45010) 5791 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 5792 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 5793 5794 #define _BW_BUDDY0_CTL 0x45130 5795 #define _BW_BUDDY1_CTL 0x45140 5796 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ 5797 _BW_BUDDY0_CTL, \ 5798 _BW_BUDDY1_CTL)) 5799 #define BW_BUDDY_DISABLE REG_BIT(31) 5800 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) 5801 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) 5802 5803 #define _BW_BUDDY0_PAGE_MASK 0x45134 5804 #define _BW_BUDDY1_PAGE_MASK 0x45144 5805 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ 5806 _BW_BUDDY0_PAGE_MASK, \ 5807 _BW_BUDDY1_PAGE_MASK)) 5808 5809 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 5810 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) 5811 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) 5812 5813 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 5814 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 5815 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 5816 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 5817 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 5818 #define ICL_DELAY_PMRSP REG_BIT(22) 5819 #define DISABLE_FLR_SRC REG_BIT(15) 5820 #define MASK_WAKEMEM REG_BIT(13) 5821 #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 5822 5823 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) 5824 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) 5825 #define DCPR_MASK_LPMODE REG_BIT(26) 5826 #define DCPR_SEND_RESP_IMM REG_BIT(25) 5827 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) 5828 5829 #define SKL_DFSM _MMIO(0x51000) 5830 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) 5831 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) 5832 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 5833 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 5834 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 5835 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 5836 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 5837 #define ICL_DFSM_DMC_DISABLE (1 << 23) 5838 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 5839 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 5840 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 5841 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) 5842 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) 5843 5844 #define SKL_DSSM _MMIO(0x51004) 5845 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 5846 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 5847 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 5848 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 5849 5850 /*GEN11 chicken */ 5851 #define _PIPEA_CHICKEN 0x70038 5852 #define _PIPEB_CHICKEN 0x71038 5853 #define _PIPEC_CHICKEN 0x72038 5854 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 5855 _PIPEB_CHICKEN) 5856 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) 5857 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) 5858 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) 5859 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) 5860 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) 5861 5862 /* PCH */ 5863 5864 #define PCH_DISPLAY_BASE 0xc0000u 5865 5866 /* south display engine interrupt: IBX */ 5867 #define SDE_AUDIO_POWER_D (1 << 27) 5868 #define SDE_AUDIO_POWER_C (1 << 26) 5869 #define SDE_AUDIO_POWER_B (1 << 25) 5870 #define SDE_AUDIO_POWER_SHIFT (25) 5871 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 5872 #define SDE_GMBUS (1 << 24) 5873 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 5874 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 5875 #define SDE_AUDIO_HDCP_MASK (3 << 22) 5876 #define SDE_AUDIO_TRANSB (1 << 21) 5877 #define SDE_AUDIO_TRANSA (1 << 20) 5878 #define SDE_AUDIO_TRANS_MASK (3 << 20) 5879 #define SDE_POISON (1 << 19) 5880 /* 18 reserved */ 5881 #define SDE_FDI_RXB (1 << 17) 5882 #define SDE_FDI_RXA (1 << 16) 5883 #define SDE_FDI_MASK (3 << 16) 5884 #define SDE_AUXD (1 << 15) 5885 #define SDE_AUXC (1 << 14) 5886 #define SDE_AUXB (1 << 13) 5887 #define SDE_AUX_MASK (7 << 13) 5888 /* 12 reserved */ 5889 #define SDE_CRT_HOTPLUG (1 << 11) 5890 #define SDE_PORTD_HOTPLUG (1 << 10) 5891 #define SDE_PORTC_HOTPLUG (1 << 9) 5892 #define SDE_PORTB_HOTPLUG (1 << 8) 5893 #define SDE_SDVOB_HOTPLUG (1 << 6) 5894 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 5895 SDE_SDVOB_HOTPLUG | \ 5896 SDE_PORTB_HOTPLUG | \ 5897 SDE_PORTC_HOTPLUG | \ 5898 SDE_PORTD_HOTPLUG) 5899 #define SDE_TRANSB_CRC_DONE (1 << 5) 5900 #define SDE_TRANSB_CRC_ERR (1 << 4) 5901 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 5902 #define SDE_TRANSA_CRC_DONE (1 << 2) 5903 #define SDE_TRANSA_CRC_ERR (1 << 1) 5904 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 5905 #define SDE_TRANS_MASK (0x3f) 5906 5907 /* south display engine interrupt: CPT - CNP */ 5908 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 5909 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 5910 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 5911 #define SDE_AUDIO_POWER_SHIFT_CPT 29 5912 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 5913 #define SDE_AUXD_CPT (1 << 27) 5914 #define SDE_AUXC_CPT (1 << 26) 5915 #define SDE_AUXB_CPT (1 << 25) 5916 #define SDE_AUX_MASK_CPT (7 << 25) 5917 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 5918 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 5919 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 5920 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 5921 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 5922 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 5923 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 5924 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 5925 SDE_SDVOB_HOTPLUG_CPT | \ 5926 SDE_PORTD_HOTPLUG_CPT | \ 5927 SDE_PORTC_HOTPLUG_CPT | \ 5928 SDE_PORTB_HOTPLUG_CPT) 5929 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 5930 SDE_PORTD_HOTPLUG_CPT | \ 5931 SDE_PORTC_HOTPLUG_CPT | \ 5932 SDE_PORTB_HOTPLUG_CPT | \ 5933 SDE_PORTA_HOTPLUG_SPT) 5934 #define SDE_GMBUS_CPT (1 << 17) 5935 #define SDE_ERROR_CPT (1 << 16) 5936 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 5937 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 5938 #define SDE_FDI_RXC_CPT (1 << 8) 5939 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 5940 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 5941 #define SDE_FDI_RXB_CPT (1 << 4) 5942 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 5943 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 5944 #define SDE_FDI_RXA_CPT (1 << 0) 5945 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 5946 SDE_AUDIO_CP_REQ_B_CPT | \ 5947 SDE_AUDIO_CP_REQ_A_CPT) 5948 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 5949 SDE_AUDIO_CP_CHG_B_CPT | \ 5950 SDE_AUDIO_CP_CHG_A_CPT) 5951 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 5952 SDE_FDI_RXB_CPT | \ 5953 SDE_FDI_RXA_CPT) 5954 5955 /* south display engine interrupt: ICP/TGP */ 5956 #define SDE_GMBUS_ICP (1 << 23) 5957 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) 5958 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */ 5959 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) 5960 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ 5961 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ 5962 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ 5963 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) 5964 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ 5965 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ 5966 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ 5967 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ 5968 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ 5969 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) 5970 5971 #define SDEISR _MMIO(0xc4000) 5972 #define SDEIMR _MMIO(0xc4004) 5973 #define SDEIIR _MMIO(0xc4008) 5974 #define SDEIER _MMIO(0xc400c) 5975 5976 #define SERR_INT _MMIO(0xc4040) 5977 #define SERR_INT_POISON (1 << 31) 5978 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 5979 5980 /* digital port hotplug */ 5981 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 5982 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 5983 #define BXT_DDIA_HPD_INVERT (1 << 27) 5984 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 5985 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 5986 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 5987 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 5988 #define PORTD_HOTPLUG_ENABLE (1 << 20) 5989 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 5990 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 5991 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 5992 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 5993 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 5994 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 5995 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 5996 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 5997 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 5998 #define PORTC_HOTPLUG_ENABLE (1 << 12) 5999 #define BXT_DDIC_HPD_INVERT (1 << 11) 6000 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 6001 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 6002 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 6003 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 6004 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 6005 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 6006 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 6007 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 6008 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 6009 #define PORTB_HOTPLUG_ENABLE (1 << 4) 6010 #define BXT_DDIB_HPD_INVERT (1 << 3) 6011 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 6012 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 6013 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 6014 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 6015 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 6016 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 6017 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 6018 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 6019 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 6020 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 6021 BXT_DDIB_HPD_INVERT | \ 6022 BXT_DDIC_HPD_INVERT) 6023 6024 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 6025 #define PORTE_HOTPLUG_ENABLE (1 << 4) 6026 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 6027 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 6028 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 6029 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 6030 6031 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 6032 * functionality covered in PCH_PORT_HOTPLUG is split into 6033 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 6034 */ 6035 6036 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 6037 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6038 #define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6039 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6040 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6041 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6042 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6043 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6044 6045 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 6046 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 6047 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 6048 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 6049 6050 #define SHPD_FILTER_CNT _MMIO(0xc4038) 6051 #define SHPD_FILTER_CNT_500_ADJ 0x001D9 6052 6053 #define _PCH_DPLL_A 0xc6014 6054 #define _PCH_DPLL_B 0xc6018 6055 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 6056 6057 #define _PCH_FPA0 0xc6040 6058 #define FP_CB_TUNE (0x3 << 22) 6059 #define _PCH_FPA1 0xc6044 6060 #define _PCH_FPB0 0xc6048 6061 #define _PCH_FPB1 0xc604c 6062 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 6063 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 6064 6065 #define PCH_DPLL_TEST _MMIO(0xc606c) 6066 6067 #define PCH_DREF_CONTROL _MMIO(0xC6200) 6068 #define DREF_CONTROL_MASK 0x7fc3 6069 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 6070 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 6071 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 6072 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 6073 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 6074 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 6075 #define DREF_SSC_SOURCE_MASK (3 << 11) 6076 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 6077 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 6078 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 6079 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 6080 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 6081 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 6082 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 6083 #define DREF_SSC4_DOWNSPREAD (0 << 6) 6084 #define DREF_SSC4_CENTERSPREAD (1 << 6) 6085 #define DREF_SSC1_DISABLE (0 << 1) 6086 #define DREF_SSC1_ENABLE (1 << 1) 6087 #define DREF_SSC4_DISABLE (0) 6088 #define DREF_SSC4_ENABLE (1) 6089 6090 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 6091 #define FDL_TP1_TIMER_SHIFT 12 6092 #define FDL_TP1_TIMER_MASK (3 << 12) 6093 #define FDL_TP2_TIMER_SHIFT 10 6094 #define FDL_TP2_TIMER_MASK (3 << 10) 6095 #define RAWCLK_FREQ_MASK 0x3ff 6096 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 6097 #define CNP_RAWCLK_DIV(div) ((div) << 16) 6098 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 6099 #define CNP_RAWCLK_DEN(den) ((den) << 26) 6100 #define ICP_RAWCLK_NUM(num) ((num) << 11) 6101 6102 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 6103 6104 #define PCH_SSC4_PARMS _MMIO(0xc6210) 6105 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 6106 6107 #define PCH_DPLL_SEL _MMIO(0xc7000) 6108 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 6109 #define TRANS_DPLLA_SEL(pipe) 0 6110 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 6111 6112 /* transcoder */ 6113 6114 #define _PCH_TRANS_HTOTAL_A 0xe0000 6115 #define TRANS_HTOTAL_SHIFT 16 6116 #define TRANS_HACTIVE_SHIFT 0 6117 #define _PCH_TRANS_HBLANK_A 0xe0004 6118 #define TRANS_HBLANK_END_SHIFT 16 6119 #define TRANS_HBLANK_START_SHIFT 0 6120 #define _PCH_TRANS_HSYNC_A 0xe0008 6121 #define TRANS_HSYNC_END_SHIFT 16 6122 #define TRANS_HSYNC_START_SHIFT 0 6123 #define _PCH_TRANS_VTOTAL_A 0xe000c 6124 #define TRANS_VTOTAL_SHIFT 16 6125 #define TRANS_VACTIVE_SHIFT 0 6126 #define _PCH_TRANS_VBLANK_A 0xe0010 6127 #define TRANS_VBLANK_END_SHIFT 16 6128 #define TRANS_VBLANK_START_SHIFT 0 6129 #define _PCH_TRANS_VSYNC_A 0xe0014 6130 #define TRANS_VSYNC_END_SHIFT 16 6131 #define TRANS_VSYNC_START_SHIFT 0 6132 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 6133 6134 #define _PCH_TRANSA_DATA_M1 0xe0030 6135 #define _PCH_TRANSA_DATA_N1 0xe0034 6136 #define _PCH_TRANSA_DATA_M2 0xe0038 6137 #define _PCH_TRANSA_DATA_N2 0xe003c 6138 #define _PCH_TRANSA_LINK_M1 0xe0040 6139 #define _PCH_TRANSA_LINK_N1 0xe0044 6140 #define _PCH_TRANSA_LINK_M2 0xe0048 6141 #define _PCH_TRANSA_LINK_N2 0xe004c 6142 6143 /* Per-transcoder DIP controls (PCH) */ 6144 #define _VIDEO_DIP_CTL_A 0xe0200 6145 #define _VIDEO_DIP_DATA_A 0xe0208 6146 #define _VIDEO_DIP_GCP_A 0xe0210 6147 #define GCP_COLOR_INDICATION (1 << 2) 6148 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 6149 #define GCP_AV_MUTE (1 << 0) 6150 6151 #define _VIDEO_DIP_CTL_B 0xe1200 6152 #define _VIDEO_DIP_DATA_B 0xe1208 6153 #define _VIDEO_DIP_GCP_B 0xe1210 6154 6155 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 6156 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 6157 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 6158 6159 /* Per-transcoder DIP controls (VLV) */ 6160 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 6161 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 6162 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 6163 6164 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 6165 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 6166 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 6167 6168 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 6169 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 6170 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 6171 6172 #define VLV_TVIDEO_DIP_CTL(pipe) \ 6173 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 6174 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 6175 #define VLV_TVIDEO_DIP_DATA(pipe) \ 6176 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 6177 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 6178 #define VLV_TVIDEO_DIP_GCP(pipe) \ 6179 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 6180 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 6181 6182 /* Haswell DIP controls */ 6183 6184 #define _HSW_VIDEO_DIP_CTL_A 0x60200 6185 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 6186 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 6187 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 6188 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 6189 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 6190 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 6191 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 6192 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 6193 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 6194 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 6195 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 6196 #define _HSW_VIDEO_DIP_GCP_A 0x60210 6197 6198 #define _HSW_VIDEO_DIP_CTL_B 0x61200 6199 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 6200 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 6201 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 6202 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 6203 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 6204 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 6205 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 6206 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 6207 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 6208 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 6209 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 6210 #define _HSW_VIDEO_DIP_GCP_B 0x61210 6211 6212 /* Icelake PPS_DATA and _ECC DIP Registers. 6213 * These are available for transcoders B,C and eDP. 6214 * Adding the _A so as to reuse the _MMIO_TRANS2 6215 * definition, with which it offsets to the right location. 6216 */ 6217 6218 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 6219 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 6220 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 6221 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 6222 6223 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 6224 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 6225 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 6226 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 6227 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 6228 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 6229 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 6230 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 6231 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 6232 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 6233 6234 #define _HSW_STEREO_3D_CTL_A 0x70020 6235 #define S3D_ENABLE (1 << 31) 6236 #define _HSW_STEREO_3D_CTL_B 0x71020 6237 6238 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 6239 6240 #define _PCH_TRANS_HTOTAL_B 0xe1000 6241 #define _PCH_TRANS_HBLANK_B 0xe1004 6242 #define _PCH_TRANS_HSYNC_B 0xe1008 6243 #define _PCH_TRANS_VTOTAL_B 0xe100c 6244 #define _PCH_TRANS_VBLANK_B 0xe1010 6245 #define _PCH_TRANS_VSYNC_B 0xe1014 6246 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 6247 6248 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 6249 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 6250 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 6251 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 6252 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 6253 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 6254 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 6255 6256 #define _PCH_TRANSB_DATA_M1 0xe1030 6257 #define _PCH_TRANSB_DATA_N1 0xe1034 6258 #define _PCH_TRANSB_DATA_M2 0xe1038 6259 #define _PCH_TRANSB_DATA_N2 0xe103c 6260 #define _PCH_TRANSB_LINK_M1 0xe1040 6261 #define _PCH_TRANSB_LINK_N1 0xe1044 6262 #define _PCH_TRANSB_LINK_M2 0xe1048 6263 #define _PCH_TRANSB_LINK_N2 0xe104c 6264 6265 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 6266 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 6267 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 6268 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 6269 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 6270 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 6271 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 6272 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 6273 6274 #define _PCH_TRANSACONF 0xf0008 6275 #define _PCH_TRANSBCONF 0xf1008 6276 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 6277 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 6278 #define TRANS_ENABLE REG_BIT(31) 6279 #define TRANS_STATE_ENABLE REG_BIT(30) 6280 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ 6281 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ 6282 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) 6283 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) 6284 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ 6285 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) 6286 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ 6287 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) 6288 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) 6289 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) 6290 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) 6291 #define _TRANSA_CHICKEN1 0xf0060 6292 #define _TRANSB_CHICKEN1 0xf1060 6293 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 6294 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10) 6295 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4) 6296 #define _TRANSA_CHICKEN2 0xf0064 6297 #define _TRANSB_CHICKEN2 0xf1064 6298 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 6299 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31) 6300 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29) 6301 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27) 6302 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */ 6303 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26) 6304 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25) 6305 6306 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 6307 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 6308 #define FDIA_PHASE_SYNC_SHIFT_EN 18 6309 #define INVERT_DDID_HPD (1 << 18) 6310 #define INVERT_DDIC_HPD (1 << 17) 6311 #define INVERT_DDIB_HPD (1 << 16) 6312 #define INVERT_DDIA_HPD (1 << 15) 6313 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 6314 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 6315 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 6316 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 6317 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 6318 #define SBCLK_RUN_REFCLK_DIS (1 << 7) 6319 #define SPT_PWM_GRANULARITY (1 << 0) 6320 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 6321 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 6322 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 6323 #define LPT_PWM_GRANULARITY (1 << 5) 6324 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 6325 6326 #define _FDI_RXA_CHICKEN 0xc200c 6327 #define _FDI_RXB_CHICKEN 0xc2010 6328 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 6329 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 6330 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 6331 6332 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 6333 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 6334 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 6335 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 6336 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 6337 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 6338 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 6339 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 6340 6341 /* CPU: FDI_TX */ 6342 #define _FDI_TXA_CTL 0x60100 6343 #define _FDI_TXB_CTL 0x61100 6344 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 6345 #define FDI_TX_DISABLE (0 << 31) 6346 #define FDI_TX_ENABLE (1 << 31) 6347 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 6348 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 6349 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 6350 #define FDI_LINK_TRAIN_NONE (3 << 28) 6351 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 6352 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 6353 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 6354 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 6355 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 6356 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 6357 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 6358 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 6359 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 6360 SNB has different settings. */ 6361 /* SNB A-stepping */ 6362 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 6363 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 6364 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 6365 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 6366 /* SNB B-stepping */ 6367 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22) 6368 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 6369 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 6370 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 6371 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 6372 #define FDI_DP_PORT_WIDTH_SHIFT 19 6373 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 6374 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 6375 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 6376 /* Ironlake: hardwired to 1 */ 6377 #define FDI_TX_PLL_ENABLE (1 << 14) 6378 6379 /* Ivybridge has different bits for lolz */ 6380 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 6381 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 6382 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 6383 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 6384 6385 /* both Tx and Rx */ 6386 #define FDI_COMPOSITE_SYNC (1 << 11) 6387 #define FDI_LINK_TRAIN_AUTO (1 << 10) 6388 #define FDI_SCRAMBLING_ENABLE (0 << 7) 6389 #define FDI_SCRAMBLING_DISABLE (1 << 7) 6390 6391 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 6392 #define _FDI_RXA_CTL 0xf000c 6393 #define _FDI_RXB_CTL 0xf100c 6394 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 6395 #define FDI_RX_ENABLE (1 << 31) 6396 /* train, dp width same as FDI_TX */ 6397 #define FDI_FS_ERRC_ENABLE (1 << 27) 6398 #define FDI_FE_ERRC_ENABLE (1 << 26) 6399 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16) 6400 #define FDI_8BPC (0 << 16) 6401 #define FDI_10BPC (1 << 16) 6402 #define FDI_6BPC (2 << 16) 6403 #define FDI_12BPC (3 << 16) 6404 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15) 6405 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14) 6406 #define FDI_RX_PLL_ENABLE (1 << 13) 6407 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11) 6408 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10) 6409 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9) 6410 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8) 6411 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 6412 #define FDI_PCDCLK (1 << 4) 6413 /* CPT */ 6414 #define FDI_AUTO_TRAINING (1 << 10) 6415 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 6416 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 6417 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 6418 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 6419 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 6420 6421 #define _FDI_RXA_MISC 0xf0010 6422 #define _FDI_RXB_MISC 0xf1010 6423 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 6424 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 6425 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 6426 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 6427 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 6428 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 6429 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 6430 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 6431 6432 #define _FDI_RXA_TUSIZE1 0xf0030 6433 #define _FDI_RXA_TUSIZE2 0xf0038 6434 #define _FDI_RXB_TUSIZE1 0xf1030 6435 #define _FDI_RXB_TUSIZE2 0xf1038 6436 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 6437 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 6438 6439 /* FDI_RX interrupt register format */ 6440 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 6441 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */ 6442 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */ 6443 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 6444 #define FDI_RX_FS_CODE_ERR (1 << 6) 6445 #define FDI_RX_FE_CODE_ERR (1 << 5) 6446 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 6447 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 6448 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 6449 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 6450 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 6451 6452 #define _FDI_RXA_IIR 0xf0014 6453 #define _FDI_RXA_IMR 0xf0018 6454 #define _FDI_RXB_IIR 0xf1014 6455 #define _FDI_RXB_IMR 0xf1018 6456 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 6457 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 6458 6459 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 6460 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 6461 6462 #define PCH_LVDS _MMIO(0xe1180) 6463 #define LVDS_DETECTED (1 << 1) 6464 6465 #define _PCH_DP_B 0xe4100 6466 #define PCH_DP_B _MMIO(_PCH_DP_B) 6467 #define _PCH_DPB_AUX_CH_CTL 0xe4110 6468 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 6469 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 6470 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 6471 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 6472 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 6473 6474 #define _PCH_DP_C 0xe4200 6475 #define PCH_DP_C _MMIO(_PCH_DP_C) 6476 #define _PCH_DPC_AUX_CH_CTL 0xe4210 6477 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 6478 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 6479 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 6480 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 6481 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 6482 6483 #define _PCH_DP_D 0xe4300 6484 #define PCH_DP_D _MMIO(_PCH_DP_D) 6485 #define _PCH_DPD_AUX_CH_CTL 0xe4310 6486 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 6487 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 6488 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 6489 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 6490 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 6491 6492 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 6493 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 6494 6495 /* CPT */ 6496 #define _TRANS_DP_CTL_A 0xe0300 6497 #define _TRANS_DP_CTL_B 0xe1300 6498 #define _TRANS_DP_CTL_C 0xe2300 6499 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 6500 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) 6501 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) 6502 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) 6503 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) 6504 #define TRANS_DP_AUDIO_ONLY REG_BIT(26) 6505 #define TRANS_DP_ENH_FRAMING REG_BIT(18) 6506 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) 6507 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) 6508 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) 6509 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) 6510 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) 6511 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) 6512 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) 6513 6514 #define _TRANS_DP2_CTL_A 0x600a0 6515 #define _TRANS_DP2_CTL_B 0x610a0 6516 #define _TRANS_DP2_CTL_C 0x620a0 6517 #define _TRANS_DP2_CTL_D 0x630a0 6518 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) 6519 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) 6520 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) 6521 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) 6522 6523 #define _TRANS_DP2_VFREQHIGH_A 0x600a4 6524 #define _TRANS_DP2_VFREQHIGH_B 0x610a4 6525 #define _TRANS_DP2_VFREQHIGH_C 0x620a4 6526 #define _TRANS_DP2_VFREQHIGH_D 0x630a4 6527 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) 6528 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) 6529 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) 6530 6531 #define _TRANS_DP2_VFREQLOW_A 0x600a8 6532 #define _TRANS_DP2_VFREQLOW_B 0x610a8 6533 #define _TRANS_DP2_VFREQLOW_C 0x620a8 6534 #define _TRANS_DP2_VFREQLOW_D 0x630a8 6535 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) 6536 6537 /* SNB eDP training params */ 6538 /* SNB A-stepping */ 6539 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 6540 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 6541 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 6542 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 6543 /* SNB B-stepping */ 6544 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 6545 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 6546 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 6547 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 6548 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 6549 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 6550 6551 /* IVB */ 6552 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 6553 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 6554 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 6555 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 6556 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 6557 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 6558 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 6559 6560 /* legacy values */ 6561 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 6562 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 6563 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 6564 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 6565 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 6566 6567 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 6568 6569 #define VLV_PMWGICZ _MMIO(0x1300a4) 6570 6571 #define HSW_EDRAM_CAP _MMIO(0x120010) 6572 #define EDRAM_ENABLED 0x1 6573 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 6574 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 6575 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 6576 6577 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 6578 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 6579 #define PIXEL_OVERLAP_CNT_SHIFT 30 6580 6581 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 6582 #define GEN6_PCODE_READY (1 << 31) 6583 #define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16) 6584 #define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8) 6585 #define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0) 6586 #define GEN6_PCODE_ERROR_MASK 0xFF 6587 #define GEN6_PCODE_SUCCESS 0x0 6588 #define GEN6_PCODE_ILLEGAL_CMD 0x1 6589 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 6590 #define GEN6_PCODE_TIMEOUT 0x3 6591 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 6592 #define GEN7_PCODE_TIMEOUT 0x2 6593 #define GEN7_PCODE_ILLEGAL_DATA 0x3 6594 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 6595 #define GEN11_PCODE_LOCKED 0x6 6596 #define GEN11_PCODE_REJECTED 0x11 6597 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 6598 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 6599 #define GEN6_PCODE_READ_RC6VIDS 0x5 6600 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 6601 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 6602 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 6603 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 6604 #define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24) 6605 #define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16) 6606 #define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8) 6607 #define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0) 6608 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 6609 #define SKL_PCODE_CDCLK_CONTROL 0x7 6610 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 6611 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 6612 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 6613 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 6614 #define GEN6_READ_OC_PARAMS 0xc 6615 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 6616 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 6617 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 6618 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8)) 6619 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe 6620 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0) 6621 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0) 6622 #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1) 6623 #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2) 6624 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2) 6625 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0) 6626 #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1) 6627 #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2) 6628 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0) 6629 #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x)) 6630 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8) 6631 #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x)) 6632 #define GEN6_PCODE_READ_D_COMP 0x10 6633 #define GEN6_PCODE_WRITE_D_COMP 0x11 6634 #define ICL_PCODE_EXIT_TCCOLD 0x12 6635 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 6636 #define DISPLAY_IPS_CONTROL 0x19 6637 #define TGL_PCODE_TCCOLD 0x26 6638 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) 6639 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 6640 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) 6641 /* See also IPS_CTL */ 6642 #define IPS_PCODE_CONTROL (1 << 30) 6643 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 6644 #define GEN9_PCODE_SAGV_CONTROL 0x21 6645 #define GEN9_SAGV_DISABLE 0x0 6646 #define GEN9_SAGV_IS_DISABLED 0x1 6647 #define GEN9_SAGV_ENABLE 0x3 6648 #define DG1_PCODE_STATUS 0x7E 6649 #define DG1_UNCORE_GET_INIT_STATUS 0x0 6650 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 6651 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 6652 #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */ 6653 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */ 6654 #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 6655 #define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1 6656 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */ 6657 /* XEHP_PCODE_FREQUENCY_CONFIG param2 */ 6658 #define PCODE_MBOX_DOMAIN_NONE 0x0 6659 #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3 6660 #define GEN6_PCODE_DATA _MMIO(0x138128) 6661 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 6662 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 6663 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 6664 6665 /* IVYBRIDGE DPF */ 6666 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 6667 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 6668 #define GEN7_PARITY_ERROR_VALID (1 << 13) 6669 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 6670 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 6671 #define GEN7_PARITY_ERROR_ROW(reg) \ 6672 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 6673 #define GEN7_PARITY_ERROR_BANK(reg) \ 6674 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 6675 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 6676 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 6677 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 6678 6679 /* These are the 4 32-bit write offset registers for each stream 6680 * output buffer. It determines the offset from the 6681 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 6682 */ 6683 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 6684 6685 /* 6686 * HSW - ICL power wells 6687 * 6688 * Platforms have up to 3 power well control register sets, each set 6689 * controlling up to 16 power wells via a request/status HW flag tuple: 6690 * - main (HSW_PWR_WELL_CTL[1-4]) 6691 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 6692 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 6693 * Each control register set consists of up to 4 registers used by different 6694 * sources that can request a power well to be enabled: 6695 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 6696 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 6697 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 6698 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 6699 */ 6700 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 6701 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 6702 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 6703 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 6704 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 6705 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 6706 6707 /* HSW/BDW power well */ 6708 #define HSW_PW_CTL_IDX_GLOBAL 15 6709 6710 /* SKL/BXT/GLK power wells */ 6711 #define SKL_PW_CTL_IDX_PW_2 15 6712 #define SKL_PW_CTL_IDX_PW_1 14 6713 #define GLK_PW_CTL_IDX_AUX_C 10 6714 #define GLK_PW_CTL_IDX_AUX_B 9 6715 #define GLK_PW_CTL_IDX_AUX_A 8 6716 #define SKL_PW_CTL_IDX_DDI_D 4 6717 #define SKL_PW_CTL_IDX_DDI_C 3 6718 #define SKL_PW_CTL_IDX_DDI_B 2 6719 #define SKL_PW_CTL_IDX_DDI_A_E 1 6720 #define GLK_PW_CTL_IDX_DDI_A 1 6721 #define SKL_PW_CTL_IDX_MISC_IO 0 6722 6723 /* ICL/TGL - power wells */ 6724 #define TGL_PW_CTL_IDX_PW_5 4 6725 #define ICL_PW_CTL_IDX_PW_4 3 6726 #define ICL_PW_CTL_IDX_PW_3 2 6727 #define ICL_PW_CTL_IDX_PW_2 1 6728 #define ICL_PW_CTL_IDX_PW_1 0 6729 6730 /* XE_LPD - power wells */ 6731 #define XELPD_PW_CTL_IDX_PW_D 8 6732 #define XELPD_PW_CTL_IDX_PW_C 7 6733 #define XELPD_PW_CTL_IDX_PW_B 6 6734 #define XELPD_PW_CTL_IDX_PW_A 5 6735 6736 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 6737 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 6738 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 6739 #define TGL_PW_CTL_IDX_AUX_TBT6 14 6740 #define TGL_PW_CTL_IDX_AUX_TBT5 13 6741 #define TGL_PW_CTL_IDX_AUX_TBT4 12 6742 #define ICL_PW_CTL_IDX_AUX_TBT4 11 6743 #define TGL_PW_CTL_IDX_AUX_TBT3 11 6744 #define ICL_PW_CTL_IDX_AUX_TBT3 10 6745 #define TGL_PW_CTL_IDX_AUX_TBT2 10 6746 #define ICL_PW_CTL_IDX_AUX_TBT2 9 6747 #define TGL_PW_CTL_IDX_AUX_TBT1 9 6748 #define ICL_PW_CTL_IDX_AUX_TBT1 8 6749 #define TGL_PW_CTL_IDX_AUX_TC6 8 6750 #define XELPD_PW_CTL_IDX_AUX_E 8 6751 #define TGL_PW_CTL_IDX_AUX_TC5 7 6752 #define XELPD_PW_CTL_IDX_AUX_D 7 6753 #define TGL_PW_CTL_IDX_AUX_TC4 6 6754 #define ICL_PW_CTL_IDX_AUX_F 5 6755 #define TGL_PW_CTL_IDX_AUX_TC3 5 6756 #define ICL_PW_CTL_IDX_AUX_E 4 6757 #define TGL_PW_CTL_IDX_AUX_TC2 4 6758 #define ICL_PW_CTL_IDX_AUX_D 3 6759 #define TGL_PW_CTL_IDX_AUX_TC1 3 6760 #define ICL_PW_CTL_IDX_AUX_C 2 6761 #define ICL_PW_CTL_IDX_AUX_B 1 6762 #define ICL_PW_CTL_IDX_AUX_A 0 6763 6764 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 6765 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 6766 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 6767 #define XELPD_PW_CTL_IDX_DDI_E 8 6768 #define TGL_PW_CTL_IDX_DDI_TC6 8 6769 #define XELPD_PW_CTL_IDX_DDI_D 7 6770 #define TGL_PW_CTL_IDX_DDI_TC5 7 6771 #define TGL_PW_CTL_IDX_DDI_TC4 6 6772 #define ICL_PW_CTL_IDX_DDI_F 5 6773 #define TGL_PW_CTL_IDX_DDI_TC3 5 6774 #define ICL_PW_CTL_IDX_DDI_E 4 6775 #define TGL_PW_CTL_IDX_DDI_TC2 4 6776 #define ICL_PW_CTL_IDX_DDI_D 3 6777 #define TGL_PW_CTL_IDX_DDI_TC1 3 6778 #define ICL_PW_CTL_IDX_DDI_C 2 6779 #define ICL_PW_CTL_IDX_DDI_B 1 6780 #define ICL_PW_CTL_IDX_DDI_A 0 6781 6782 /* HSW - power well misc debug registers */ 6783 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 6784 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 6785 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 6786 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 6787 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 6788 6789 /* SKL Fuse Status */ 6790 enum skl_power_gate { 6791 SKL_PG0, 6792 SKL_PG1, 6793 SKL_PG2, 6794 ICL_PG3, 6795 ICL_PG4, 6796 }; 6797 6798 #define SKL_FUSE_STATUS _MMIO(0x42000) 6799 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 6800 /* 6801 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 6802 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 6803 */ 6804 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 6805 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 6806 /* 6807 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 6808 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 6809 */ 6810 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 6811 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 6812 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 6813 6814 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) 6815 #define _ICL_AUX_ANAOVRD1_A 0x162398 6816 #define _ICL_AUX_ANAOVRD1_B 0x6C398 6817 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ 6818 _ICL_AUX_ANAOVRD1_A, \ 6819 _ICL_AUX_ANAOVRD1_B)) 6820 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) 6821 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) 6822 6823 /* Per-pipe DDI Function Control */ 6824 #define _TRANS_DDI_FUNC_CTL_A 0x60400 6825 #define _TRANS_DDI_FUNC_CTL_B 0x61400 6826 #define _TRANS_DDI_FUNC_CTL_C 0x62400 6827 #define _TRANS_DDI_FUNC_CTL_D 0x63400 6828 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 6829 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 6830 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 6831 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 6832 6833 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 6834 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 6835 #define TRANS_DDI_PORT_SHIFT 28 6836 #define TGL_TRANS_DDI_PORT_SHIFT 27 6837 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) 6838 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) 6839 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 6840 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) 6841 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 6842 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 6843 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 6844 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 6845 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 6846 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) 6847 #define TRANS_DDI_BPC_MASK (7 << 20) 6848 #define TRANS_DDI_BPC_8 (0 << 20) 6849 #define TRANS_DDI_BPC_10 (1 << 20) 6850 #define TRANS_DDI_BPC_6 (2 << 20) 6851 #define TRANS_DDI_BPC_12 (3 << 20) 6852 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) 6853 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) 6854 #define TRANS_DDI_PVSYNC (1 << 17) 6855 #define TRANS_DDI_PHSYNC (1 << 16) 6856 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) 6857 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 6858 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 6859 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 6860 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 6861 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 6862 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) 6863 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) 6864 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ 6865 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) 6866 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 6867 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 6868 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 6869 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 6870 #define TRANS_DDI_HDCP_SELECT REG_BIT(5) 6871 #define TRANS_DDI_BFI_ENABLE (1 << 4) 6872 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 6873 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 6874 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 6875 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 6876 | TRANS_DDI_HDMI_SCRAMBLING) 6877 6878 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 6879 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 6880 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 6881 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 6882 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 6883 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 6884 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A) 6885 #define PORT_SYNC_MODE_ENABLE REG_BIT(4) 6886 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) 6887 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) 6888 6889 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) 6890 #define DISABLE_DPT_CLK_GATING REG_BIT(1) 6891 6892 /* DisplayPort Transport Control */ 6893 #define _DP_TP_CTL_A 0x64040 6894 #define _DP_TP_CTL_B 0x64140 6895 #define _TGL_DP_TP_CTL_A 0x60540 6896 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 6897 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A) 6898 #define DP_TP_CTL_ENABLE (1 << 31) 6899 #define DP_TP_CTL_FEC_ENABLE (1 << 30) 6900 #define DP_TP_CTL_MODE_SST (0 << 27) 6901 #define DP_TP_CTL_MODE_MST (1 << 27) 6902 #define DP_TP_CTL_FORCE_ACT (1 << 25) 6903 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 6904 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 6905 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 6906 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 6907 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 6908 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 6909 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 6910 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 6911 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 6912 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 6913 6914 /* DisplayPort Transport Status */ 6915 #define _DP_TP_STATUS_A 0x64044 6916 #define _DP_TP_STATUS_B 0x64144 6917 #define _TGL_DP_TP_STATUS_A 0x60544 6918 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 6919 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A) 6920 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 6921 #define DP_TP_STATUS_IDLE_DONE (1 << 25) 6922 #define DP_TP_STATUS_ACT_SENT (1 << 24) 6923 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 6924 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 6925 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 6926 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 6927 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 6928 6929 /* DDI Buffer Control */ 6930 #define _DDI_BUF_CTL_A 0x64000 6931 #define _DDI_BUF_CTL_B 0x64100 6932 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 6933 #define DDI_BUF_CTL_ENABLE (1 << 31) 6934 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 6935 #define DDI_BUF_EMP_MASK (0xf << 24) 6936 #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) 6937 #define DDI_BUF_PORT_REVERSAL (1 << 16) 6938 #define DDI_BUF_IS_IDLE (1 << 7) 6939 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) 6940 #define DDI_A_4_LANES (1 << 4) 6941 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 6942 #define DDI_PORT_WIDTH_MASK (7 << 1) 6943 #define DDI_PORT_WIDTH_SHIFT 1 6944 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 6945 6946 /* DDI Buffer Translations */ 6947 #define _DDI_BUF_TRANS_A 0x64E00 6948 #define _DDI_BUF_TRANS_B 0x64E60 6949 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 6950 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 6951 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 6952 6953 /* DDI DP Compliance Control */ 6954 #define _DDI_DP_COMP_CTL_A 0x605F0 6955 #define _DDI_DP_COMP_CTL_B 0x615F0 6956 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) 6957 #define DDI_DP_COMP_CTL_ENABLE (1 << 31) 6958 #define DDI_DP_COMP_CTL_D10_2 (0 << 28) 6959 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) 6960 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) 6961 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) 6962 #define DDI_DP_COMP_CTL_HBR2 (4 << 28) 6963 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) 6964 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) 6965 6966 /* DDI DP Compliance Pattern */ 6967 #define _DDI_DP_COMP_PAT_A 0x605F4 6968 #define _DDI_DP_COMP_PAT_B 0x615F4 6969 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) 6970 6971 /* Sideband Interface (SBI) is programmed indirectly, via 6972 * SBI_ADDR, which contains the register offset; and SBI_DATA, 6973 * which contains the payload */ 6974 #define SBI_ADDR _MMIO(0xC6000) 6975 #define SBI_DATA _MMIO(0xC6004) 6976 #define SBI_CTL_STAT _MMIO(0xC6008) 6977 #define SBI_CTL_DEST_ICLK (0x0 << 16) 6978 #define SBI_CTL_DEST_MPHY (0x1 << 16) 6979 #define SBI_CTL_OP_IORD (0x2 << 8) 6980 #define SBI_CTL_OP_IOWR (0x3 << 8) 6981 #define SBI_CTL_OP_CRRD (0x6 << 8) 6982 #define SBI_CTL_OP_CRWR (0x7 << 8) 6983 #define SBI_RESPONSE_FAIL (0x1 << 1) 6984 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 6985 #define SBI_BUSY (0x1 << 0) 6986 #define SBI_READY (0x0 << 0) 6987 6988 /* SBI offsets */ 6989 #define SBI_SSCDIVINTPHASE 0x0200 6990 #define SBI_SSCDIVINTPHASE6 0x0600 6991 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 6992 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 6993 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 6994 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 6995 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 6996 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 6997 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 6998 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 6999 #define SBI_SSCDITHPHASE 0x0204 7000 #define SBI_SSCCTL 0x020c 7001 #define SBI_SSCCTL6 0x060C 7002 #define SBI_SSCCTL_PATHALT (1 << 3) 7003 #define SBI_SSCCTL_DISABLE (1 << 0) 7004 #define SBI_SSCAUXDIV6 0x0610 7005 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 7006 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 7007 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 7008 #define SBI_DBUFF0 0x2a00 7009 #define SBI_GEN0 0x1f00 7010 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 7011 7012 /* LPT PIXCLK_GATE */ 7013 #define PIXCLK_GATE _MMIO(0xC6020) 7014 #define PIXCLK_GATE_UNGATE (1 << 0) 7015 #define PIXCLK_GATE_GATE (0 << 0) 7016 7017 /* SPLL */ 7018 #define SPLL_CTL _MMIO(0x46020) 7019 #define SPLL_PLL_ENABLE (1 << 31) 7020 #define SPLL_REF_BCLK (0 << 28) 7021 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 7022 #define SPLL_REF_NON_SSC_HSW (2 << 28) 7023 #define SPLL_REF_PCH_SSC_BDW (2 << 28) 7024 #define SPLL_REF_LCPLL (3 << 28) 7025 #define SPLL_REF_MASK (3 << 28) 7026 #define SPLL_FREQ_810MHz (0 << 26) 7027 #define SPLL_FREQ_1350MHz (1 << 26) 7028 #define SPLL_FREQ_2700MHz (2 << 26) 7029 #define SPLL_FREQ_MASK (3 << 26) 7030 7031 /* WRPLL */ 7032 #define _WRPLL_CTL1 0x46040 7033 #define _WRPLL_CTL2 0x46060 7034 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 7035 #define WRPLL_PLL_ENABLE (1 << 31) 7036 #define WRPLL_REF_BCLK (0 << 28) 7037 #define WRPLL_REF_PCH_SSC (1 << 28) 7038 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 7039 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 7040 #define WRPLL_REF_LCPLL (3 << 28) 7041 #define WRPLL_REF_MASK (3 << 28) 7042 /* WRPLL divider programming */ 7043 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 7044 #define WRPLL_DIVIDER_REF_MASK (0xff) 7045 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 7046 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 7047 #define WRPLL_DIVIDER_POST_SHIFT 8 7048 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 7049 #define WRPLL_DIVIDER_FB_SHIFT 16 7050 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 7051 7052 /* Port clock selection */ 7053 #define _PORT_CLK_SEL_A 0x46100 7054 #define _PORT_CLK_SEL_B 0x46104 7055 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 7056 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) 7057 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) 7058 #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) 7059 #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) 7060 #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) 7061 #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) 7062 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) 7063 #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) 7064 #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) 7065 7066 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 7067 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 7068 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) 7069 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) 7070 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) 7071 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) 7072 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) 7073 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) 7074 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) 7075 7076 /* Transcoder clock selection */ 7077 #define _TRANS_CLK_SEL_A 0x46140 7078 #define _TRANS_CLK_SEL_B 0x46144 7079 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 7080 /* For each transcoder, we need to select the corresponding port clock */ 7081 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 7082 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 7083 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) 7084 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) 7085 7086 7087 #define CDCLK_FREQ _MMIO(0x46200) 7088 7089 #define _TRANSA_MSA_MISC 0x60410 7090 #define _TRANSB_MSA_MISC 0x61410 7091 #define _TRANSC_MSA_MISC 0x62410 7092 #define _TRANS_EDP_MSA_MISC 0x6f410 7093 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 7094 /* See DP_MSA_MISC_* for the bit definitions */ 7095 7096 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C 7097 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C 7098 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C 7099 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C 7100 #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY) 7101 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) 7102 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) 7103 7104 /* LCPLL Control */ 7105 #define LCPLL_CTL _MMIO(0x130040) 7106 #define LCPLL_PLL_DISABLE (1 << 31) 7107 #define LCPLL_PLL_LOCK (1 << 30) 7108 #define LCPLL_REF_NON_SSC (0 << 28) 7109 #define LCPLL_REF_BCLK (2 << 28) 7110 #define LCPLL_REF_PCH_SSC (3 << 28) 7111 #define LCPLL_REF_MASK (3 << 28) 7112 #define LCPLL_CLK_FREQ_MASK (3 << 26) 7113 #define LCPLL_CLK_FREQ_450 (0 << 26) 7114 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 7115 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 7116 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 7117 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 7118 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 7119 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 7120 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 7121 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 7122 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 7123 7124 /* 7125 * SKL Clocks 7126 */ 7127 7128 /* CDCLK_CTL */ 7129 #define CDCLK_CTL _MMIO(0x46000) 7130 #define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26) 7131 #define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0) 7132 #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1) 7133 #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2) 7134 #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3) 7135 #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22) 7136 #define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0) 7137 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1) 7138 #define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2) 7139 #define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3) 7140 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 7141 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 7142 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 7143 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) 7144 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 7145 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) 7146 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE 7147 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 7148 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 7149 7150 /* CDCLK_SQUASH_CTL */ 7151 #define CDCLK_SQUASH_CTL _MMIO(0x46008) 7152 #define CDCLK_SQUASH_ENABLE REG_BIT(31) 7153 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) 7154 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) 7155 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) 7156 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) 7157 7158 /* LCPLL_CTL */ 7159 #define LCPLL1_CTL _MMIO(0x46010) 7160 #define LCPLL2_CTL _MMIO(0x46014) 7161 #define LCPLL_PLL_ENABLE (1 << 31) 7162 7163 /* DPLL control1 */ 7164 #define DPLL_CTRL1 _MMIO(0x6C058) 7165 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 7166 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 7167 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 7168 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 7169 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 7170 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 7171 #define DPLL_CTRL1_LINK_RATE_2700 0 7172 #define DPLL_CTRL1_LINK_RATE_1350 1 7173 #define DPLL_CTRL1_LINK_RATE_810 2 7174 #define DPLL_CTRL1_LINK_RATE_1620 3 7175 #define DPLL_CTRL1_LINK_RATE_1080 4 7176 #define DPLL_CTRL1_LINK_RATE_2160 5 7177 7178 /* DPLL control2 */ 7179 #define DPLL_CTRL2 _MMIO(0x6C05C) 7180 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 7181 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 7182 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 7183 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 7184 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 7185 7186 /* DPLL Status */ 7187 #define DPLL_STATUS _MMIO(0x6C060) 7188 #define DPLL_LOCK(id) (1 << ((id) * 8)) 7189 7190 /* DPLL cfg */ 7191 #define _DPLL1_CFGCR1 0x6C040 7192 #define _DPLL2_CFGCR1 0x6C048 7193 #define _DPLL3_CFGCR1 0x6C050 7194 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 7195 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 7196 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 7197 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 7198 7199 #define _DPLL1_CFGCR2 0x6C044 7200 #define _DPLL2_CFGCR2 0x6C04C 7201 #define _DPLL3_CFGCR2 0x6C054 7202 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 7203 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 7204 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 7205 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 7206 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 7207 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 7208 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 7209 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 7210 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 7211 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 7212 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 7213 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 7214 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 7215 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 7216 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 7217 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) 7218 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 7219 7220 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 7221 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 7222 7223 /* ICL Clocks */ 7224 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) 7225 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) 7226 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) 7227 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ 7228 (tc_port) + 12 : \ 7229 (tc_port) - TC_PORT_4 + 21)) 7230 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) 7231 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7232 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7233 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) 7234 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ 7235 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7236 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ 7237 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7238 7239 /* 7240 * DG1 Clocks 7241 * First registers controls the first A and B, while the second register 7242 * controls the phy C and D. The bits on these registers are the 7243 * same, but refer to different phys 7244 */ 7245 #define _DG1_DPCLKA_CFGCR0 0x164280 7246 #define _DG1_DPCLKA1_CFGCR0 0x16C280 7247 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) 7248 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) 7249 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ 7250 _DG1_DPCLKA_CFGCR0, \ 7251 _DG1_DPCLKA1_CFGCR0) 7252 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) 7253 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) 7254 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7255 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7256 7257 /* ADLS Clocks */ 7258 #define _ADLS_DPCLKA_CFGCR0 0x164280 7259 #define _ADLS_DPCLKA_CFGCR1 0x1642BC 7260 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ 7261 _ADLS_DPCLKA_CFGCR0, \ 7262 _ADLS_DPCLKA_CFGCR1) 7263 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) 7264 /* ADLS DPCLKA_CFGCR0 DDI mask */ 7265 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) 7266 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) 7267 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) 7268 /* ADLS DPCLKA_CFGCR1 DDI mask */ 7269 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) 7270 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) 7271 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ 7272 ADLS_DPCLKA_DDIA_SEL_MASK, \ 7273 ADLS_DPCLKA_DDIB_SEL_MASK, \ 7274 ADLS_DPCLKA_DDII_SEL_MASK, \ 7275 ADLS_DPCLKA_DDIJ_SEL_MASK, \ 7276 ADLS_DPCLKA_DDIK_SEL_MASK) 7277 7278 /* ICL PLL */ 7279 #define DPLL0_ENABLE 0x46010 7280 #define DPLL1_ENABLE 0x46014 7281 #define _ADLS_DPLL2_ENABLE 0x46018 7282 #define _ADLS_DPLL3_ENABLE 0x46030 7283 #define PLL_ENABLE (1 << 31) 7284 #define PLL_LOCK (1 << 30) 7285 #define PLL_POWER_ENABLE (1 << 27) 7286 #define PLL_POWER_STATE (1 << 26) 7287 #define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7288 _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE) 7289 7290 #define _DG2_PLL3_ENABLE 0x4601C 7291 7292 #define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7293 _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE) 7294 7295 #define TBT_PLL_ENABLE _MMIO(0x46020) 7296 7297 #define _MG_PLL1_ENABLE 0x46030 7298 #define _MG_PLL2_ENABLE 0x46034 7299 #define _MG_PLL3_ENABLE 0x46038 7300 #define _MG_PLL4_ENABLE 0x4603C 7301 /* Bits are the same as DPLL0_ENABLE */ 7302 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 7303 _MG_PLL2_ENABLE) 7304 7305 /* DG1 PLL */ 7306 #define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7307 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE) 7308 7309 /* ADL-P Type C PLL */ 7310 #define PORTTC1_PLL_ENABLE 0x46038 7311 #define PORTTC2_PLL_ENABLE 0x46040 7312 7313 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ 7314 PORTTC1_PLL_ENABLE, \ 7315 PORTTC2_PLL_ENABLE) 7316 7317 #define _ICL_DPLL0_CFGCR0 0x164000 7318 #define _ICL_DPLL1_CFGCR0 0x164080 7319 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 7320 _ICL_DPLL1_CFGCR0) 7321 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 7322 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 7323 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 7324 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 7325 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 7326 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 7327 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 7328 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 7329 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 7330 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 7331 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 7332 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 7333 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 7334 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 7335 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 7336 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 7337 7338 #define _ICL_DPLL0_CFGCR1 0x164004 7339 #define _ICL_DPLL1_CFGCR1 0x164084 7340 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 7341 _ICL_DPLL1_CFGCR1) 7342 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 7343 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 7344 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 7345 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 7346 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 7347 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 7348 #define DPLL_CFGCR1_KDIV_SHIFT (6) 7349 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 7350 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 7351 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 7352 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 7353 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 7354 #define DPLL_CFGCR1_PDIV_SHIFT (2) 7355 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 7356 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 7357 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 7358 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 7359 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 7360 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 7361 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 7362 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) 7363 7364 #define _TGL_DPLL0_CFGCR0 0x164284 7365 #define _TGL_DPLL1_CFGCR0 0x16428C 7366 #define _TGL_TBTPLL_CFGCR0 0x16429C 7367 #define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7368 _TGL_DPLL1_CFGCR0, \ 7369 _TGL_TBTPLL_CFGCR0) 7370 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ 7371 _TGL_DPLL1_CFGCR0) 7372 7373 #define _TGL_DPLL0_DIV0 0x164B00 7374 #define _TGL_DPLL1_DIV0 0x164C00 7375 #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0) 7376 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) 7377 #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val)) 7378 7379 #define _TGL_DPLL0_CFGCR1 0x164288 7380 #define _TGL_DPLL1_CFGCR1 0x164290 7381 #define _TGL_TBTPLL_CFGCR1 0x1642A0 7382 #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7383 _TGL_DPLL1_CFGCR1, \ 7384 _TGL_TBTPLL_CFGCR1) 7385 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ 7386 _TGL_DPLL1_CFGCR1) 7387 7388 #define _DG1_DPLL2_CFGCR0 0x16C284 7389 #define _DG1_DPLL3_CFGCR0 0x16C28C 7390 #define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7391 _TGL_DPLL1_CFGCR0, \ 7392 _DG1_DPLL2_CFGCR0, \ 7393 _DG1_DPLL3_CFGCR0) 7394 7395 #define _DG1_DPLL2_CFGCR1 0x16C288 7396 #define _DG1_DPLL3_CFGCR1 0x16C290 7397 #define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7398 _TGL_DPLL1_CFGCR1, \ 7399 _DG1_DPLL2_CFGCR1, \ 7400 _DG1_DPLL3_CFGCR1) 7401 7402 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ 7403 #define _ADLS_DPLL3_CFGCR0 0x1642C0 7404 #define _ADLS_DPLL4_CFGCR0 0x164294 7405 #define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7406 _TGL_DPLL1_CFGCR0, \ 7407 _ADLS_DPLL4_CFGCR0, \ 7408 _ADLS_DPLL3_CFGCR0) 7409 7410 #define _ADLS_DPLL3_CFGCR1 0x1642C4 7411 #define _ADLS_DPLL4_CFGCR1 0x164298 7412 #define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7413 _TGL_DPLL1_CFGCR1, \ 7414 _ADLS_DPLL4_CFGCR1, \ 7415 _ADLS_DPLL3_CFGCR1) 7416 7417 #define _DKL_PHY1_BASE 0x168000 7418 #define _DKL_PHY2_BASE 0x169000 7419 #define _DKL_PHY3_BASE 0x16A000 7420 #define _DKL_PHY4_BASE 0x16B000 7421 #define _DKL_PHY5_BASE 0x16C000 7422 #define _DKL_PHY6_BASE 0x16D000 7423 7424 #define DKL_REG_TC_PORT(__reg) \ 7425 (TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE)) 7426 7427 /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ 7428 #define _DKL_PCS_DW5 0x14 7429 #define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7430 _DKL_PHY2_BASE) + \ 7431 _DKL_PCS_DW5) 7432 #define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11) 7433 7434 #define _DKL_PLL_DIV0 0x200 7435 #define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) 7436 #define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val)) 7437 #define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16) 7438 #define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16) 7439 #define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12) 7440 #define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12) 7441 #define DKL_PLL_DIV0_FBPREDIV_SHIFT (8) 7442 #define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT) 7443 #define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT) 7444 #define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0) 7445 #define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0) 7446 #define DKL_PLL_DIV0_MASK (DKL_PLL_DIV0_INTEG_COEFF_MASK | \ 7447 DKL_PLL_DIV0_PROP_COEFF_MASK | \ 7448 DKL_PLL_DIV0_FBPREDIV_MASK | \ 7449 DKL_PLL_DIV0_FBDIV_INT_MASK) 7450 #define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7451 _DKL_PHY2_BASE) + \ 7452 _DKL_PLL_DIV0) 7453 7454 #define _DKL_PLL_DIV1 0x204 7455 #define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16) 7456 #define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16) 7457 #define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0) 7458 #define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0) 7459 #define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7460 _DKL_PHY2_BASE) + \ 7461 _DKL_PLL_DIV1) 7462 7463 #define _DKL_PLL_SSC 0x210 7464 #define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29) 7465 #define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29) 7466 #define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16) 7467 #define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16) 7468 #define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11) 7469 #define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11) 7470 #define DKL_PLL_SSC_EN (1 << 9) 7471 #define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7472 _DKL_PHY2_BASE) + \ 7473 _DKL_PLL_SSC) 7474 7475 #define _DKL_PLL_BIAS 0x214 7476 #define DKL_PLL_BIAS_FRAC_EN_H (1 << 30) 7477 #define DKL_PLL_BIAS_FBDIV_SHIFT (8) 7478 #define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT) 7479 #define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT) 7480 #define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7481 _DKL_PHY2_BASE) + \ 7482 _DKL_PLL_BIAS) 7483 7484 #define _DKL_PLL_TDC_COLDST_BIAS 0x218 7485 #define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8) 7486 #define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8) 7487 #define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0) 7488 #define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0) 7489 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \ 7490 _DKL_PHY1_BASE, \ 7491 _DKL_PHY2_BASE) + \ 7492 _DKL_PLL_TDC_COLDST_BIAS) 7493 7494 #define _DKL_REFCLKIN_CTL 0x12C 7495 /* Bits are the same as MG_REFCLKIN_CTL */ 7496 #define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \ 7497 _DKL_PHY1_BASE, \ 7498 _DKL_PHY2_BASE) + \ 7499 _DKL_REFCLKIN_CTL) 7500 7501 #define _DKL_CLKTOP2_HSCLKCTL 0xD4 7502 /* Bits are the same as MG_CLKTOP2_HSCLKCTL */ 7503 #define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \ 7504 _DKL_PHY1_BASE, \ 7505 _DKL_PHY2_BASE) + \ 7506 _DKL_CLKTOP2_HSCLKCTL) 7507 7508 #define _DKL_CLKTOP2_CORECLKCTL1 0xD8 7509 /* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */ 7510 #define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \ 7511 _DKL_PHY1_BASE, \ 7512 _DKL_PHY2_BASE) + \ 7513 _DKL_CLKTOP2_CORECLKCTL1) 7514 7515 #define _DKL_TX_DPCNTL0 0x2C0 7516 #define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13) 7517 #define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13) 7518 #define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8) 7519 #define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8) 7520 #define DKL_TX_VSWING_CONTROL(x) ((x) << 0) 7521 #define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0) 7522 #define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \ 7523 _DKL_PHY1_BASE, \ 7524 _DKL_PHY2_BASE) + \ 7525 _DKL_TX_DPCNTL0) 7526 7527 #define _DKL_TX_DPCNTL1 0x2C4 7528 /* Bits are the same as DKL_TX_DPCNTRL0 */ 7529 #define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \ 7530 _DKL_PHY1_BASE, \ 7531 _DKL_PHY2_BASE) + \ 7532 _DKL_TX_DPCNTL1) 7533 7534 #define _DKL_TX_DPCNTL2 0x2C8 7535 #define DKL_TX_DP20BITMODE REG_BIT(2) 7536 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3) 7537 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val)) 7538 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5) 7539 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val)) 7540 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ 7541 _DKL_PHY1_BASE, \ 7542 _DKL_PHY2_BASE) + \ 7543 _DKL_TX_DPCNTL2) 7544 7545 #define _DKL_TX_FW_CALIB 0x2F8 7546 #define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7) 7547 #define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \ 7548 _DKL_PHY1_BASE, \ 7549 _DKL_PHY2_BASE) + \ 7550 _DKL_TX_FW_CALIB) 7551 7552 #define _DKL_TX_PMD_LANE_SUS 0xD00 7553 #define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \ 7554 _DKL_PHY1_BASE, \ 7555 _DKL_PHY2_BASE) + \ 7556 _DKL_TX_PMD_LANE_SUS) 7557 7558 #define _DKL_TX_DW17 0xDC4 7559 #define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \ 7560 _DKL_PHY1_BASE, \ 7561 _DKL_PHY2_BASE) + \ 7562 _DKL_TX_DW17) 7563 7564 #define _DKL_TX_DW18 0xDC8 7565 #define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \ 7566 _DKL_PHY1_BASE, \ 7567 _DKL_PHY2_BASE) + \ 7568 _DKL_TX_DW18) 7569 7570 #define _DKL_DP_MODE 0xA0 7571 #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \ 7572 _DKL_PHY1_BASE, \ 7573 _DKL_PHY2_BASE) + \ 7574 _DKL_DP_MODE) 7575 7576 #define _DKL_CMN_UC_DW27 0x36C 7577 #define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15) 7578 #define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \ 7579 _DKL_PHY1_BASE, \ 7580 _DKL_PHY2_BASE) + \ 7581 _DKL_CMN_UC_DW27) 7582 7583 /* 7584 * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than 7585 * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0 7586 * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address 7587 * bits that point the 4KB window into the full PHY register space. 7588 */ 7589 #define _HIP_INDEX_REG0 0x1010A0 7590 #define _HIP_INDEX_REG1 0x1010A4 7591 #define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \ 7592 : _HIP_INDEX_REG1) 7593 #define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4)) 7594 #define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port)) 7595 7596 /* BXT display engine PLL */ 7597 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 7598 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 7599 #define BXT_DE_PLL_RATIO_MASK 0xff 7600 7601 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 7602 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 7603 #define BXT_DE_PLL_LOCK (1 << 30) 7604 #define BXT_DE_PLL_FREQ_REQ (1 << 23) 7605 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) 7606 #define ICL_CDCLK_PLL_RATIO(x) (x) 7607 #define ICL_CDCLK_PLL_RATIO_MASK 0xff 7608 7609 /* GEN9 DC */ 7610 #define DC_STATE_EN _MMIO(0x45504) 7611 #define DC_STATE_DISABLE 0 7612 #define DC_STATE_EN_DC3CO REG_BIT(30) 7613 #define DC_STATE_DC3CO_STATUS REG_BIT(29) 7614 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 7615 #define DC_STATE_EN_DC9 (1 << 3) 7616 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 7617 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 7618 7619 #define DC_STATE_DEBUG _MMIO(0x45520) 7620 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 7621 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 7622 7623 #define D_COMP_BDW _MMIO(0x138144) 7624 7625 /* Pipe WM_LINETIME - watermark line time */ 7626 #define _WM_LINETIME_A 0x45270 7627 #define _WM_LINETIME_B 0x45274 7628 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) 7629 #define HSW_LINETIME_MASK REG_GENMASK(8, 0) 7630 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) 7631 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) 7632 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) 7633 7634 /* SFUSE_STRAP */ 7635 #define SFUSE_STRAP _MMIO(0xc2014) 7636 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 7637 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 7638 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 7639 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 7640 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 7641 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 7642 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 7643 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 7644 7645 #define WM_MISC _MMIO(0x45260) 7646 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 7647 7648 #define WM_DBG _MMIO(0x45280) 7649 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 7650 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 7651 #define WM_DBG_DISALLOW_SPRITE (1 << 2) 7652 7653 /* pipe CSC */ 7654 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 7655 #define _PIPE_A_CSC_COEFF_BY 0x49014 7656 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 7657 #define _PIPE_A_CSC_COEFF_BU 0x4901c 7658 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 7659 #define _PIPE_A_CSC_COEFF_BV 0x49024 7660 7661 #define _PIPE_A_CSC_MODE 0x49028 7662 #define ICL_CSC_ENABLE (1 << 31) /* icl+ */ 7663 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */ 7664 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */ 7665 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */ 7666 #define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */ 7667 7668 #define _PIPE_A_CSC_PREOFF_HI 0x49030 7669 #define _PIPE_A_CSC_PREOFF_ME 0x49034 7670 #define _PIPE_A_CSC_PREOFF_LO 0x49038 7671 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 7672 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 7673 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 7674 7675 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 7676 #define _PIPE_B_CSC_COEFF_BY 0x49114 7677 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 7678 #define _PIPE_B_CSC_COEFF_BU 0x4911c 7679 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 7680 #define _PIPE_B_CSC_COEFF_BV 0x49124 7681 #define _PIPE_B_CSC_MODE 0x49128 7682 #define _PIPE_B_CSC_PREOFF_HI 0x49130 7683 #define _PIPE_B_CSC_PREOFF_ME 0x49134 7684 #define _PIPE_B_CSC_PREOFF_LO 0x49138 7685 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 7686 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 7687 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 7688 7689 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 7690 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 7691 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 7692 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 7693 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 7694 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 7695 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 7696 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 7697 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 7698 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 7699 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 7700 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 7701 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 7702 7703 /* Pipe Output CSC */ 7704 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050 7705 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054 7706 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058 7707 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c 7708 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060 7709 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064 7710 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068 7711 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c 7712 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070 7713 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074 7714 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078 7715 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c 7716 7717 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150 7718 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154 7719 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158 7720 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c 7721 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160 7722 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164 7723 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168 7724 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c 7725 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170 7726 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174 7727 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178 7728 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c 7729 7730 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\ 7731 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\ 7732 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY) 7733 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \ 7734 _PIPE_A_OUTPUT_CSC_COEFF_BY, \ 7735 _PIPE_B_OUTPUT_CSC_COEFF_BY) 7736 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \ 7737 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \ 7738 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU) 7739 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \ 7740 _PIPE_A_OUTPUT_CSC_COEFF_BU, \ 7741 _PIPE_B_OUTPUT_CSC_COEFF_BU) 7742 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \ 7743 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \ 7744 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV) 7745 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \ 7746 _PIPE_A_OUTPUT_CSC_COEFF_BV, \ 7747 _PIPE_B_OUTPUT_CSC_COEFF_BV) 7748 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \ 7749 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \ 7750 _PIPE_B_OUTPUT_CSC_PREOFF_HI) 7751 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \ 7752 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \ 7753 _PIPE_B_OUTPUT_CSC_PREOFF_ME) 7754 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \ 7755 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \ 7756 _PIPE_B_OUTPUT_CSC_PREOFF_LO) 7757 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \ 7758 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \ 7759 _PIPE_B_OUTPUT_CSC_POSTOFF_HI) 7760 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \ 7761 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \ 7762 _PIPE_B_OUTPUT_CSC_POSTOFF_ME) 7763 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \ 7764 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \ 7765 _PIPE_B_OUTPUT_CSC_POSTOFF_LO) 7766 7767 /* pipe degamma/gamma LUTs on IVB+ */ 7768 #define _PAL_PREC_INDEX_A 0x4A400 7769 #define _PAL_PREC_INDEX_B 0x4AC00 7770 #define _PAL_PREC_INDEX_C 0x4B400 7771 #define PAL_PREC_10_12_BIT (0 << 31) 7772 #define PAL_PREC_SPLIT_MODE (1 << 31) 7773 #define PAL_PREC_AUTO_INCREMENT (1 << 15) 7774 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0) 7775 #define PAL_PREC_INDEX_VALUE(x) ((x) << 0) 7776 #define _PAL_PREC_DATA_A 0x4A404 7777 #define _PAL_PREC_DATA_B 0x4AC04 7778 #define _PAL_PREC_DATA_C 0x4B404 7779 #define _PAL_PREC_GC_MAX_A 0x4A410 7780 #define _PAL_PREC_GC_MAX_B 0x4AC10 7781 #define _PAL_PREC_GC_MAX_C 0x4B410 7782 #define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20) 7783 #define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10) 7784 #define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0) 7785 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 7786 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 7787 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 7788 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 7789 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 7790 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 7791 7792 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 7793 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 7794 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) 7795 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) 7796 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) 7797 7798 #define _PRE_CSC_GAMC_INDEX_A 0x4A484 7799 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 7800 #define _PRE_CSC_GAMC_INDEX_C 0x4B484 7801 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10) 7802 #define _PRE_CSC_GAMC_DATA_A 0x4A488 7803 #define _PRE_CSC_GAMC_DATA_B 0x4AC88 7804 #define _PRE_CSC_GAMC_DATA_C 0x4B488 7805 7806 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 7807 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 7808 7809 /* ICL Multi segmented gamma */ 7810 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 7811 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 7812 #define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15) 7813 #define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0) 7814 7815 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C 7816 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C 7817 #define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24) 7818 #define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20) 7819 #define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14) 7820 #define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10) 7821 #define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4) 7822 #define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0) 7823 7824 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ 7825 _PAL_PREC_MULTI_SEG_INDEX_A, \ 7826 _PAL_PREC_MULTI_SEG_INDEX_B) 7827 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ 7828 _PAL_PREC_MULTI_SEG_DATA_A, \ 7829 _PAL_PREC_MULTI_SEG_DATA_B) 7830 7831 #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) 7832 7833 /* Plane CSC Registers */ 7834 #define _PLANE_CSC_RY_GY_1_A 0x70210 7835 #define _PLANE_CSC_RY_GY_2_A 0x70310 7836 7837 #define _PLANE_CSC_RY_GY_1_B 0x71210 7838 #define _PLANE_CSC_RY_GY_2_B 0x71310 7839 7840 #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ 7841 _PLANE_CSC_RY_GY_1_B) 7842 #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 7843 _PLANE_INPUT_CSC_RY_GY_2_B) 7844 #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ 7845 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ 7846 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) 7847 7848 #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 7849 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 7850 7851 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 7852 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 7853 7854 #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ 7855 _PLANE_CSC_PREOFF_HI_1_B) 7856 #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ 7857 _PLANE_CSC_PREOFF_HI_2_B) 7858 #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ 7859 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ 7860 (index) * 4) 7861 7862 #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 7863 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 7864 7865 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 7866 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 7867 7868 #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ 7869 _PLANE_CSC_POSTOFF_HI_1_B) 7870 #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ 7871 _PLANE_CSC_POSTOFF_HI_2_B) 7872 #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ 7873 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ 7874 (index) * 4) 7875 7876 /* pipe CSC & degamma/gamma LUTs on CHV */ 7877 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 7878 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 7879 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 7880 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 7881 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 7882 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 7883 #define CGM_PIPE_DEGAMMA_RED_MASK REG_GENMASK(13, 0) 7884 #define CGM_PIPE_DEGAMMA_GREEN_MASK REG_GENMASK(29, 16) 7885 #define CGM_PIPE_DEGAMMA_BLUE_MASK REG_GENMASK(13, 0) 7886 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 7887 #define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0) 7888 #define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16) 7889 #define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0) 7890 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 7891 #define CGM_PIPE_MODE_GAMMA (1 << 2) 7892 #define CGM_PIPE_MODE_CSC (1 << 1) 7893 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 7894 7895 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 7896 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 7897 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 7898 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 7899 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 7900 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 7901 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 7902 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 7903 7904 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 7905 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 7906 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 7907 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 7908 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 7909 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 7910 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 7911 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 7912 7913 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 7914 #define GEN4_TIMESTAMP _MMIO(0x2358) 7915 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 7916 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 7917 7918 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 7919 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 7920 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 7921 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 7922 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 7923 7924 #define _PIPE_FRMTMSTMP_A 0x70048 7925 #define PIPE_FRMTMSTMP(pipe) \ 7926 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A) 7927 7928 /* Display Stream Splitter Control */ 7929 #define DSS_CTL1 _MMIO(0x67400) 7930 #define SPLITTER_ENABLE (1 << 31) 7931 #define JOINER_ENABLE (1 << 30) 7932 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24) 7933 #define DUAL_LINK_MODE_FRONTBACK (0 << 24) 7934 #define OVERLAP_PIXELS_MASK (0xf << 16) 7935 #define OVERLAP_PIXELS(pixels) ((pixels) << 16) 7936 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 7937 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 7938 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 7939 7940 #define DSS_CTL2 _MMIO(0x67404) 7941 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 7942 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 7943 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 7944 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 7945 7946 #define _ICL_PIPE_DSS_CTL1_PB 0x78200 7947 #define _ICL_PIPE_DSS_CTL1_PC 0x78400 7948 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7949 _ICL_PIPE_DSS_CTL1_PB, \ 7950 _ICL_PIPE_DSS_CTL1_PC) 7951 #define BIG_JOINER_ENABLE (1 << 29) 7952 #define MASTER_BIG_JOINER_ENABLE (1 << 28) 7953 #define VGA_CENTERING_ENABLE (1 << 27) 7954 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) 7955 #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) 7956 #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) 7957 #define UNCOMPRESSED_JOINER_MASTER (1 << 21) 7958 #define UNCOMPRESSED_JOINER_SLAVE (1 << 20) 7959 7960 #define _ICL_PIPE_DSS_CTL2_PB 0x78204 7961 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 7962 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7963 _ICL_PIPE_DSS_CTL2_PB, \ 7964 _ICL_PIPE_DSS_CTL2_PC) 7965 7966 #define GEN12_GSMBASE _MMIO(0x108100) 7967 #define GEN12_DSMBASE _MMIO(0x1080C0) 7968 7969 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) 7970 #define SGSI_SIDECLK_DIS REG_BIT(17) 7971 #define SGGI_DIS REG_BIT(15) 7972 #define SGR_DIS REG_BIT(13) 7973 7974 #define _ICL_PHY_MISC_A 0x64C00 7975 #define _ICL_PHY_MISC_B 0x64C04 7976 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */ 7977 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B) 7978 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ 7979 ICL_PHY_MISC(port)) 7980 #define ICL_PHY_MISC_MUX_DDID (1 << 28) 7981 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 7982 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) 7983 7984 /* Icelake Display Stream Compression Registers */ 7985 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) 7986 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) 7987 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 7988 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 7989 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 7990 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 7991 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7992 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 7993 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 7994 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 7995 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 7996 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 7997 #define DSC_ALT_ICH_SEL (1 << 20) 7998 #define DSC_VBR_ENABLE (1 << 19) 7999 #define DSC_422_ENABLE (1 << 18) 8000 #define DSC_COLOR_SPACE_CONVERSION (1 << 17) 8001 #define DSC_BLOCK_PREDICTION (1 << 16) 8002 #define DSC_LINE_BUF_DEPTH_SHIFT 12 8003 #define DSC_BPC_SHIFT 8 8004 #define DSC_VER_MIN_SHIFT 4 8005 #define DSC_VER_MAJ (0x1 << 0) 8006 8007 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204) 8008 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04) 8009 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274 8010 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374 8011 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474 8012 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574 8013 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8014 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \ 8015 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC) 8016 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8017 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \ 8018 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC) 8019 #define DSC_BPP(bpp) ((bpp) << 0) 8020 8021 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208) 8022 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08) 8023 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278 8024 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378 8025 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478 8026 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578 8027 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8028 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \ 8029 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC) 8030 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8031 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \ 8032 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC) 8033 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16) 8034 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0) 8035 8036 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C) 8037 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C) 8038 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C 8039 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C 8040 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C 8041 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C 8042 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8043 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \ 8044 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC) 8045 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8046 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \ 8047 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC) 8048 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16) 8049 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0) 8050 8051 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210) 8052 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10) 8053 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280 8054 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380 8055 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480 8056 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580 8057 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8058 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 8059 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC) 8060 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8061 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \ 8062 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC) 8063 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 8064 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) 8065 8066 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214) 8067 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14) 8068 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284 8069 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384 8070 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484 8071 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584 8072 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8073 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \ 8074 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC) 8075 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8076 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \ 8077 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 8078 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16) 8079 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0) 8080 8081 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218) 8082 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18) 8083 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288 8084 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388 8085 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488 8086 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588 8087 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8088 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \ 8089 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC) 8090 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8091 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \ 8092 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC) 8093 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24) 8094 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16) 8095 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8) 8096 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0) 8097 8098 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C) 8099 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C) 8100 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C 8101 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C 8102 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C 8103 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C 8104 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8105 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \ 8106 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC) 8107 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8108 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \ 8109 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC) 8110 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16) 8111 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0) 8112 8113 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220) 8114 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20) 8115 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290 8116 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390 8117 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490 8118 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590 8119 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8120 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \ 8121 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC) 8122 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8123 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \ 8124 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC) 8125 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) 8126 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0) 8127 8128 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224) 8129 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24) 8130 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294 8131 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394 8132 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494 8133 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594 8134 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8135 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \ 8136 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC) 8137 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8138 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \ 8139 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC) 8140 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16) 8141 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0) 8142 8143 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228) 8144 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28) 8145 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298 8146 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398 8147 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498 8148 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598 8149 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8150 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \ 8151 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC) 8152 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8153 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \ 8154 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC) 8155 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20) 8156 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16) 8157 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8) 8158 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0) 8159 8160 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C) 8161 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C) 8162 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C 8163 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C 8164 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C 8165 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C 8166 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8167 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \ 8168 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC) 8169 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8170 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \ 8171 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC) 8172 8173 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260) 8174 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60) 8175 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0 8176 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0 8177 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0 8178 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0 8179 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8180 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \ 8181 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC) 8182 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8183 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \ 8184 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC) 8185 8186 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264) 8187 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64) 8188 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4 8189 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4 8190 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4 8191 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4 8192 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8193 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \ 8194 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC) 8195 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8196 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \ 8197 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC) 8198 8199 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268) 8200 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68) 8201 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8 8202 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8 8203 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8 8204 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8 8205 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8206 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \ 8207 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC) 8208 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8209 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \ 8210 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC) 8211 8212 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C) 8213 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C) 8214 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC 8215 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC 8216 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC 8217 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC 8218 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8219 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \ 8220 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC) 8221 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8222 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \ 8223 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC) 8224 8225 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270) 8226 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70) 8227 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0 8228 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0 8229 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0 8230 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0 8231 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8232 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \ 8233 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC) 8234 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8235 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 8236 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 8237 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) 8238 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 8239 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) 8240 8241 /* Icelake Rate Control Buffer Threshold Registers */ 8242 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 8243 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) 8244 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) 8245 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) 8246 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) 8247 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) 8248 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) 8249 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) 8250 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) 8251 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) 8252 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) 8253 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) 8254 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8255 _ICL_DSC0_RC_BUF_THRESH_0_PB, \ 8256 _ICL_DSC0_RC_BUF_THRESH_0_PC) 8257 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8258 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ 8259 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) 8260 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8261 _ICL_DSC1_RC_BUF_THRESH_0_PB, \ 8262 _ICL_DSC1_RC_BUF_THRESH_0_PC) 8263 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8264 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ 8265 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) 8266 8267 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) 8268 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) 8269 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) 8270 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) 8271 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) 8272 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) 8273 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) 8274 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) 8275 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) 8276 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) 8277 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) 8278 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) 8279 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8280 _ICL_DSC0_RC_BUF_THRESH_1_PB, \ 8281 _ICL_DSC0_RC_BUF_THRESH_1_PC) 8282 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8283 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ 8284 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) 8285 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8286 _ICL_DSC1_RC_BUF_THRESH_1_PB, \ 8287 _ICL_DSC1_RC_BUF_THRESH_1_PC) 8288 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8289 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 8290 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 8291 8292 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) 8293 #define MODULAR_FIA_MASK (1 << 4) 8294 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) 8295 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) 8296 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) 8297 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) 8298 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) 8299 8300 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) 8301 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) 8302 8303 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) 8304 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) 8305 8306 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) 8307 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) 8308 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) 8309 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) 8310 8311 #define _TCSS_DDI_STATUS_1 0x161500 8312 #define _TCSS_DDI_STATUS_2 0x161504 8313 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ 8314 _TCSS_DDI_STATUS_1, \ 8315 _TCSS_DDI_STATUS_2)) 8316 #define TCSS_DDI_STATUS_READY REG_BIT(2) 8317 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) 8318 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) 8319 8320 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) 8321 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) 8322 #define PRIMARY_SPI_REGIONID _MMIO(0x102084) 8323 #define SPI_STATIC_REGIONS _MMIO(0x102090) 8324 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) 8325 #define OROM_OFFSET _MMIO(0x1020c0) 8326 #define OROM_OFFSET_MASK REG_GENMASK(20, 16) 8327 8328 /* This register controls the Display State Buffer (DSB) engines. */ 8329 #define _DSBSL_INSTANCE_BASE 0x70B00 8330 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ 8331 (pipe) * 0x1000 + (id) * 0x100) 8332 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) 8333 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) 8334 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) 8335 #define DSB_ENABLE (1 << 31) 8336 #define DSB_STATUS (1 << 0) 8337 8338 #define CLKREQ_POLICY _MMIO(0x101038) 8339 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) 8340 8341 #define CLKGATE_DIS_MISC _MMIO(0x46534) 8342 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) 8343 8344 #define GEN12_CULLBIT1 _MMIO(0x6100) 8345 #define GEN12_CULLBIT2 _MMIO(0x7030) 8346 #define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC) 8347 8348 #define MTL_LATENCY_LP0_LP1 _MMIO(0x45780) 8349 #define MTL_LATENCY_LP2_LP3 _MMIO(0x45784) 8350 #define MTL_LATENCY_LP4_LP5 _MMIO(0x45788) 8351 #define MTL_LATENCY_LEVEL_EVEN_MASK REG_GENMASK(12, 0) 8352 #define MTL_LATENCY_LEVEL_ODD_MASK REG_GENMASK(28, 16) 8353 8354 #define MTL_LATENCY_SAGV _MMIO(0x4578b) 8355 #define MTL_LATENCY_QCLK_SAGV REG_GENMASK(12, 0) 8356 8357 #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) 8358 #define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8) 8359 #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) 8360 #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) 8361 8362 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(0x45710 + (point) * 2) 8363 #define MTL_TRCD_MASK REG_GENMASK(31, 24) 8364 #define MTL_TRP_MASK REG_GENMASK(23, 16) 8365 #define MTL_DCLK_MASK REG_GENMASK(15, 0) 8366 8367 #define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(0x45714 + (point) * 2) 8368 #define MTL_TRAS_MASK REG_GENMASK(16, 8) 8369 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0) 8370 8371 #endif /* _I915_REG_H_ */ 8372