1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * Exynos SROMC register definitions 7 */ 8 9 #ifndef __EXYNOS_SROM_H 10 #define __EXYNOS_SROM_H __FILE__ 11 12 #define EXYNOS_SROMREG(x) (x) 13 14 #define EXYNOS_SROM_BW EXYNOS_SROMREG(0x0) 15 #define EXYNOS_SROM_BC0 EXYNOS_SROMREG(0x4) 16 #define EXYNOS_SROM_BC1 EXYNOS_SROMREG(0x8) 17 #define EXYNOS_SROM_BC2 EXYNOS_SROMREG(0xc) 18 #define EXYNOS_SROM_BC3 EXYNOS_SROMREG(0x10) 19 #define EXYNOS_SROM_BC4 EXYNOS_SROMREG(0x14) 20 #define EXYNOS_SROM_BC5 EXYNOS_SROMREG(0x18) 21 22 /* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ 23 24 #define EXYNOS_SROM_BW__DATAWIDTH__SHIFT 0 25 #define EXYNOS_SROM_BW__ADDRMODE__SHIFT 1 26 #define EXYNOS_SROM_BW__WAITENABLE__SHIFT 2 27 #define EXYNOS_SROM_BW__BYTEENABLE__SHIFT 3 28 29 #define EXYNOS_SROM_BW__CS_MASK 0xf 30 31 #define EXYNOS_SROM_BW__NCS0__SHIFT 0 32 #define EXYNOS_SROM_BW__NCS1__SHIFT 4 33 #define EXYNOS_SROM_BW__NCS2__SHIFT 8 34 #define EXYNOS_SROM_BW__NCS3__SHIFT 12 35 #define EXYNOS_SROM_BW__NCS4__SHIFT 16 36 #define EXYNOS_SROM_BW__NCS5__SHIFT 20 37 38 /* applies to same to BCS0 - BCS3 */ 39 40 #define EXYNOS_SROM_BCX__PMC__SHIFT 0 41 #define EXYNOS_SROM_BCX__TACP__SHIFT 4 42 #define EXYNOS_SROM_BCX__TCAH__SHIFT 8 43 #define EXYNOS_SROM_BCX__TCOH__SHIFT 12 44 #define EXYNOS_SROM_BCX__TACC__SHIFT 16 45 #define EXYNOS_SROM_BCX__TCOS__SHIFT 24 46 #define EXYNOS_SROM_BCX__TACS__SHIFT 28 47 48 #endif /* __EXYNOS_SROM_H */ 49