1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2020 SiFive 4 */ 5 6 #include <linux/bits.h> 7 8 /* The bit field of immediate value in I-type instruction */ 9 #define I_IMM_SIGN_OPOFF 31 10 #define I_IMM_11_0_OPOFF 20 11 #define I_IMM_SIGN_OFF 12 12 #define I_IMM_11_0_OFF 0 13 #define I_IMM_11_0_MASK GENMASK(11, 0) 14 15 /* The bit field of immediate value in J-type instruction */ 16 #define J_IMM_SIGN_OPOFF 31 17 #define J_IMM_10_1_OPOFF 21 18 #define J_IMM_11_OPOFF 20 19 #define J_IMM_19_12_OPOFF 12 20 #define J_IMM_SIGN_OFF 20 21 #define J_IMM_10_1_OFF 1 22 #define J_IMM_11_OFF 11 23 #define J_IMM_19_12_OFF 12 24 #define J_IMM_10_1_MASK GENMASK(9, 0) 25 #define J_IMM_11_MASK GENMASK(0, 0) 26 #define J_IMM_19_12_MASK GENMASK(7, 0) 27 28 /* The bit field of immediate value in B-type instruction */ 29 #define B_IMM_SIGN_OPOFF 31 30 #define B_IMM_10_5_OPOFF 25 31 #define B_IMM_4_1_OPOFF 8 32 #define B_IMM_11_OPOFF 7 33 #define B_IMM_SIGN_OFF 12 34 #define B_IMM_10_5_OFF 5 35 #define B_IMM_4_1_OFF 1 36 #define B_IMM_11_OFF 11 37 #define B_IMM_10_5_MASK GENMASK(5, 0) 38 #define B_IMM_4_1_MASK GENMASK(3, 0) 39 #define B_IMM_11_MASK GENMASK(0, 0) 40 41 /* The register offset in RVG instruction */ 42 #define RVG_RS1_OPOFF 15 43 #define RVG_RS2_OPOFF 20 44 #define RVG_RD_OPOFF 7 45 46 /* The bit field of immediate value in RVC J instruction */ 47 #define RVC_J_IMM_SIGN_OPOFF 12 48 #define RVC_J_IMM_4_OPOFF 11 49 #define RVC_J_IMM_9_8_OPOFF 9 50 #define RVC_J_IMM_10_OPOFF 8 51 #define RVC_J_IMM_6_OPOFF 7 52 #define RVC_J_IMM_7_OPOFF 6 53 #define RVC_J_IMM_3_1_OPOFF 3 54 #define RVC_J_IMM_5_OPOFF 2 55 #define RVC_J_IMM_SIGN_OFF 11 56 #define RVC_J_IMM_4_OFF 4 57 #define RVC_J_IMM_9_8_OFF 8 58 #define RVC_J_IMM_10_OFF 10 59 #define RVC_J_IMM_6_OFF 6 60 #define RVC_J_IMM_7_OFF 7 61 #define RVC_J_IMM_3_1_OFF 1 62 #define RVC_J_IMM_5_OFF 5 63 #define RVC_J_IMM_4_MASK GENMASK(0, 0) 64 #define RVC_J_IMM_9_8_MASK GENMASK(1, 0) 65 #define RVC_J_IMM_10_MASK GENMASK(0, 0) 66 #define RVC_J_IMM_6_MASK GENMASK(0, 0) 67 #define RVC_J_IMM_7_MASK GENMASK(0, 0) 68 #define RVC_J_IMM_3_1_MASK GENMASK(2, 0) 69 #define RVC_J_IMM_5_MASK GENMASK(0, 0) 70 71 /* The bit field of immediate value in RVC B instruction */ 72 #define RVC_B_IMM_SIGN_OPOFF 12 73 #define RVC_B_IMM_4_3_OPOFF 10 74 #define RVC_B_IMM_7_6_OPOFF 5 75 #define RVC_B_IMM_2_1_OPOFF 3 76 #define RVC_B_IMM_5_OPOFF 2 77 #define RVC_B_IMM_SIGN_OFF 8 78 #define RVC_B_IMM_4_3_OFF 3 79 #define RVC_B_IMM_7_6_OFF 6 80 #define RVC_B_IMM_2_1_OFF 1 81 #define RVC_B_IMM_5_OFF 5 82 #define RVC_B_IMM_4_3_MASK GENMASK(1, 0) 83 #define RVC_B_IMM_7_6_MASK GENMASK(1, 0) 84 #define RVC_B_IMM_2_1_MASK GENMASK(1, 0) 85 #define RVC_B_IMM_5_MASK GENMASK(0, 0) 86 87 /* The register offset in RVC op=C0 instruction */ 88 #define RVC_C0_RS1_OPOFF 7 89 #define RVC_C0_RS2_OPOFF 2 90 #define RVC_C0_RD_OPOFF 2 91 92 /* The register offset in RVC op=C1 instruction */ 93 #define RVC_C1_RS1_OPOFF 7 94 #define RVC_C1_RS2_OPOFF 2 95 #define RVC_C1_RD_OPOFF 7 96 97 /* The register offset in RVC op=C2 instruction */ 98 #define RVC_C2_RS1_OPOFF 7 99 #define RVC_C2_RS2_OPOFF 2 100 #define RVC_C2_RD_OPOFF 7 101 102 /* parts of opcode for RVG*/ 103 #define OPCODE_BRANCH 0x63 104 #define OPCODE_JALR 0x67 105 #define OPCODE_JAL 0x6f 106 #define OPCODE_SYSTEM 0x73 107 108 /* parts of opcode for RVC*/ 109 #define OPCODE_C_0 0x0 110 #define OPCODE_C_1 0x1 111 #define OPCODE_C_2 0x2 112 113 /* parts of funct3 code for I, M, A extension*/ 114 #define FUNCT3_JALR 0x0 115 #define FUNCT3_BEQ 0x0 116 #define FUNCT3_BNE 0x1000 117 #define FUNCT3_BLT 0x4000 118 #define FUNCT3_BGE 0x5000 119 #define FUNCT3_BLTU 0x6000 120 #define FUNCT3_BGEU 0x7000 121 122 /* parts of funct3 code for C extension*/ 123 #define FUNCT3_C_BEQZ 0xc000 124 #define FUNCT3_C_BNEZ 0xe000 125 #define FUNCT3_C_J 0xa000 126 #define FUNCT3_C_JAL 0x2000 127 #define FUNCT4_C_JR 0x8000 128 #define FUNCT4_C_JALR 0xf000 129 130 #define FUNCT12_SRET 0x10200000 131 132 #define MATCH_JALR (FUNCT3_JALR | OPCODE_JALR) 133 #define MATCH_JAL (OPCODE_JAL) 134 #define MATCH_BEQ (FUNCT3_BEQ | OPCODE_BRANCH) 135 #define MATCH_BNE (FUNCT3_BNE | OPCODE_BRANCH) 136 #define MATCH_BLT (FUNCT3_BLT | OPCODE_BRANCH) 137 #define MATCH_BGE (FUNCT3_BGE | OPCODE_BRANCH) 138 #define MATCH_BLTU (FUNCT3_BLTU | OPCODE_BRANCH) 139 #define MATCH_BGEU (FUNCT3_BGEU | OPCODE_BRANCH) 140 #define MATCH_SRET (FUNCT12_SRET | OPCODE_SYSTEM) 141 #define MATCH_C_BEQZ (FUNCT3_C_BEQZ | OPCODE_C_1) 142 #define MATCH_C_BNEZ (FUNCT3_C_BNEZ | OPCODE_C_1) 143 #define MATCH_C_J (FUNCT3_C_J | OPCODE_C_1) 144 #define MATCH_C_JAL (FUNCT3_C_JAL | OPCODE_C_1) 145 #define MATCH_C_JR (FUNCT4_C_JR | OPCODE_C_2) 146 #define MATCH_C_JALR (FUNCT4_C_JALR | OPCODE_C_2) 147 148 #define MASK_JALR 0x707f 149 #define MASK_JAL 0x7f 150 #define MASK_C_JALR 0xf07f 151 #define MASK_C_JR 0xf07f 152 #define MASK_C_JAL 0xe003 153 #define MASK_C_J 0xe003 154 #define MASK_BEQ 0x707f 155 #define MASK_BNE 0x707f 156 #define MASK_BLT 0x707f 157 #define MASK_BGE 0x707f 158 #define MASK_BLTU 0x707f 159 #define MASK_BGEU 0x707f 160 #define MASK_C_BEQZ 0xe003 161 #define MASK_C_BNEZ 0xe003 162 #define MASK_SRET 0xffffffff 163 164 #define __INSN_LENGTH_MASK _UL(0x3) 165 #define __INSN_LENGTH_GE_32 _UL(0x3) 166 #define __INSN_OPCODE_MASK _UL(0x7F) 167 #define __INSN_BRANCH_OPCODE _UL(OPCODE_BRANCH) 168 169 /* Define a series of is_XXX_insn functions to check if the value INSN 170 * is an instance of instruction XXX. 171 */ 172 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \ 173 static inline bool is_ ## INSN_NAME ## _insn(long insn) \ 174 { \ 175 return (insn & (INSN_MASK)) == (INSN_MATCH); \ 176 } 177 178 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) 179 #define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1)) 180 #define RV_X(X, s, mask) (((X) >> (s)) & (mask)) 181 #define RVC_X(X, s, mask) RV_X(X, s, mask) 182 183 #define EXTRACT_JTYPE_IMM(x) \ 184 ({typeof(x) x_ = (x); \ 185 (RV_X(x_, J_IMM_10_1_OPOFF, J_IMM_10_1_MASK) << J_IMM_10_1_OFF) | \ 186 (RV_X(x_, J_IMM_11_OPOFF, J_IMM_11_MASK) << J_IMM_11_OFF) | \ 187 (RV_X(x_, J_IMM_19_12_OPOFF, J_IMM_19_12_MASK) << J_IMM_19_12_OFF) | \ 188 (RV_IMM_SIGN(x_) << J_IMM_SIGN_OFF); }) 189 190 #define EXTRACT_ITYPE_IMM(x) \ 191 ({typeof(x) x_ = (x); \ 192 (RV_X(x_, I_IMM_11_0_OPOFF, I_IMM_11_0_MASK)) | \ 193 (RV_IMM_SIGN(x_) << I_IMM_SIGN_OFF); }) 194 195 #define EXTRACT_BTYPE_IMM(x) \ 196 ({typeof(x) x_ = (x); \ 197 (RV_X(x_, B_IMM_4_1_OPOFF, B_IMM_4_1_MASK) << B_IMM_4_1_OFF) | \ 198 (RV_X(x_, B_IMM_10_5_OPOFF, B_IMM_10_5_MASK) << B_IMM_10_5_OFF) | \ 199 (RV_X(x_, B_IMM_11_OPOFF, B_IMM_11_MASK) << B_IMM_11_OFF) | \ 200 (RV_IMM_SIGN(x_) << B_IMM_SIGN_OFF); }) 201 202 #define EXTRACT_RVC_J_IMM(x) \ 203 ({typeof(x) x_ = (x); \ 204 (RVC_X(x_, RVC_J_IMM_3_1_OPOFF, RVC_J_IMM_3_1_MASK) << RVC_J_IMM_3_1_OFF) | \ 205 (RVC_X(x_, RVC_J_IMM_4_OPOFF, RVC_J_IMM_4_MASK) << RVC_J_IMM_4_OFF) | \ 206 (RVC_X(x_, RVC_J_IMM_5_OPOFF, RVC_J_IMM_5_MASK) << RVC_J_IMM_5_OFF) | \ 207 (RVC_X(x_, RVC_J_IMM_6_OPOFF, RVC_J_IMM_6_MASK) << RVC_J_IMM_6_OFF) | \ 208 (RVC_X(x_, RVC_J_IMM_7_OPOFF, RVC_J_IMM_7_MASK) << RVC_J_IMM_7_OFF) | \ 209 (RVC_X(x_, RVC_J_IMM_9_8_OPOFF, RVC_J_IMM_9_8_MASK) << RVC_J_IMM_9_8_OFF) | \ 210 (RVC_X(x_, RVC_J_IMM_10_OPOFF, RVC_J_IMM_10_MASK) << RVC_J_IMM_10_OFF) | \ 211 (RVC_IMM_SIGN(x_) << RVC_J_IMM_SIGN_OFF); }) 212 213 #define EXTRACT_RVC_B_IMM(x) \ 214 ({typeof(x) x_ = (x); \ 215 (RVC_X(x_, RVC_B_IMM_2_1_OPOFF, RVC_B_IMM_2_1_MASK) << RVC_B_IMM_2_1_OFF) | \ 216 (RVC_X(x_, RVC_B_IMM_4_3_OPOFF, RVC_B_IMM_4_3_MASK) << RVC_B_IMM_4_3_OFF) | \ 217 (RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) << RVC_B_IMM_5_OFF) | \ 218 (RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \ 219 (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); }) 220