1 /*
2  *  Copyright 2004-2009 Analog Devices Inc.
3  *                 2001 Lineo, Inc
4  *                        Tony Kou
5  *                 1993 Hamish Macdonald
6  *
7  * Licensed under the GPL-2
8  */
9 
10 #ifndef _BFIN_TRAPS_H
11 #define _BFIN_TRAPS_H
12 
13 #define VEC_SYS		(0)
14 #define VEC_EXCPT01	(1)
15 #define VEC_EXCPT02	(2)
16 #define VEC_EXCPT03	(3)
17 #define VEC_EXCPT04	(4)
18 #define VEC_EXCPT05	(5)
19 #define VEC_EXCPT06	(6)
20 #define VEC_EXCPT07	(7)
21 #define VEC_EXCPT08	(8)
22 #define VEC_EXCPT09	(9)
23 #define VEC_EXCPT10	(10)
24 #define VEC_EXCPT11	(11)
25 #define VEC_EXCPT12	(12)
26 #define VEC_EXCPT13	(13)
27 #define VEC_EXCPT14	(14)
28 #define VEC_EXCPT15	(15)
29 #define VEC_STEP	(16)
30 #define VEC_OVFLOW	(17)
31 #define VEC_UNDEF_I	(33)
32 #define VEC_ILGAL_I	(34)
33 #define VEC_CPLB_VL	(35)
34 #define VEC_MISALI_D	(36)
35 #define VEC_UNCOV	(37)
36 #define VEC_CPLB_M	(38)
37 #define VEC_CPLB_MHIT	(39)
38 #define VEC_WATCH	(40)
39 #define VEC_ISTRU_VL	(41)	/*ADSP-BF535 only (MH) */
40 #define VEC_MISALI_I	(42)
41 #define VEC_CPLB_I_VL	(43)
42 #define VEC_CPLB_I_M	(44)
43 #define VEC_CPLB_I_MHIT	(45)
44 #define VEC_ILL_RES	(46)	/* including unvalid supervisor mode insn */
45 /* The hardware reserves (63) for future use - we use it to tell our
46  * normal exception handling code we have a hardware error
47  */
48 #define VEC_HWERR	(63)
49 
50 #ifndef __ASSEMBLY__
51 
52 #define HWC_x2(level) \
53 	"System MMR Error\n" \
54 	level " - An error occurred due to an invalid access to an System MMR location\n" \
55 	level "   Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
56 	level "   or a 16-bit register is accessed with a 32-bit instruction.\n"
57 #define HWC_x3(level) \
58 	"External Memory Addressing Error\n"
59 #define EXC_0x04(level) \
60 	"Unimplmented exception occurred\n" \
61 	level " - Maybe you forgot to install a custom exception handler?\n"
62 #define HWC_x12(level) \
63 	"Performance Monitor Overflow\n"
64 #define HWC_x18(level) \
65 	"RAISE 5 instruction\n" \
66 	level "    Software issued a RAISE 5 instruction to invoke the Hardware\n"
67 #define HWC_default(level) \
68 	 "Reserved\n"
69 #define EXC_0x03(level) \
70 	"Application stack overflow\n" \
71 	level " - Please increase the stack size of the application using elf2flt -s option,\n" \
72 	level "   and/or reduce the stack use of the application.\n"
73 #define EXC_0x10(level) \
74 	"Single step\n" \
75 	level " - When the processor is in single step mode, every instruction\n" \
76 	level "   generates an exception. Primarily used for debugging.\n"
77 #define EXC_0x11(level) \
78 	"Exception caused by a trace buffer full condition\n" \
79 	level " - The processor takes this exception when the trace\n" \
80 	level "   buffer overflows (only when enabled by the Trace Unit Control register).\n"
81 #define EXC_0x21(level) \
82 	"Undefined instruction\n" \
83 	level " - May be used to emulate instructions that are not defined for\n" \
84 	level "   a particular processor implementation.\n"
85 #define EXC_0x22(level) \
86 	"Illegal instruction combination\n" \
87 	level " - See section for multi-issue rules in the Blackfin\n" \
88 	level "   Processor Instruction Set Reference.\n"
89 #define EXC_0x23(level) \
90 	"Data access CPLB protection violation\n" \
91 	level " - Attempted read or write to Supervisor resource,\n" \
92 	level "   or illegal data memory access. \n"
93 #define EXC_0x24(level) \
94 	"Data access misaligned address violation\n" \
95 	level " - Attempted misaligned data memory or data cache access.\n"
96 #define EXC_0x25(level) \
97 	"Unrecoverable event\n" \
98 	level " - For example, an exception generated while processing a previous exception.\n"
99 #define EXC_0x26(level) \
100 	"Data access CPLB miss\n" \
101 	level " - Used by the MMU to signal a CPLB miss on a data access.\n"
102 #define EXC_0x27(level) \
103 	"Data access multiple CPLB hits\n" \
104 	level " - More than one CPLB entry matches data fetch address.\n"
105 #define EXC_0x28(level) \
106 	"Program Sequencer Exception caused by an emulation watchpoint match\n" \
107 	level " - There is a watchpoint match, and one of the EMUSW\n" \
108 	level "   bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
109 #define EXC_0x2A(level) \
110 	"Instruction fetch misaligned address violation\n" \
111 	level " - Attempted misaligned instruction cache fetch.\n"
112 #define EXC_0x2B(level) \
113 	"CPLB protection violation\n" \
114 	level " - Illegal instruction fetch access (memory protection violation).\n"
115 #define EXC_0x2C(level) \
116 	"Instruction fetch CPLB miss\n" \
117 	level " - CPLB miss on an instruction fetch.\n"
118 #define EXC_0x2D(level) \
119 	"Instruction fetch multiple CPLB hits\n" \
120 	level " - More than one CPLB entry matches instruction fetch address.\n"
121 #define EXC_0x2E(level) \
122 	"Illegal use of supervisor resource\n" \
123 	level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
124 	level "   Supervisor resources are registers and instructions that are reserved\n" \
125 	level "   for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
126 	level "   only instructions.\n"
127 
128 #endif				/* __ASSEMBLY__ */
129 #endif				/* _BFIN_TRAPS_H */
130