1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ASM_ESR_H
8 #define __ASM_ESR_H
9
10 #include <asm/memory.h>
11 #include <asm/sysreg.h>
12
13 #define ESR_ELx_EC_UNKNOWN (0x00)
14 #define ESR_ELx_EC_WFx (0x01)
15 /* Unallocated EC: 0x02 */
16 #define ESR_ELx_EC_CP15_32 (0x03)
17 #define ESR_ELx_EC_CP15_64 (0x04)
18 #define ESR_ELx_EC_CP14_MR (0x05)
19 #define ESR_ELx_EC_CP14_LS (0x06)
20 #define ESR_ELx_EC_FP_ASIMD (0x07)
21 #define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */
22 #define ESR_ELx_EC_PAC (0x09) /* EL2 and above */
23 /* Unallocated EC: 0x0A - 0x0B */
24 #define ESR_ELx_EC_CP14_64 (0x0C)
25 #define ESR_ELx_EC_BTI (0x0D)
26 #define ESR_ELx_EC_ILL (0x0E)
27 /* Unallocated EC: 0x0F - 0x10 */
28 #define ESR_ELx_EC_SVC32 (0x11)
29 #define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */
30 #define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */
31 /* Unallocated EC: 0x14 */
32 #define ESR_ELx_EC_SVC64 (0x15)
33 #define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */
34 #define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
35 #define ESR_ELx_EC_SYS64 (0x18)
36 #define ESR_ELx_EC_SVE (0x19)
37 #define ESR_ELx_EC_ERET (0x1a) /* EL2 only */
38 /* Unallocated EC: 0x1B */
39 #define ESR_ELx_EC_FPAC (0x1C) /* EL1 and above */
40 #define ESR_ELx_EC_SME (0x1D)
41 /* Unallocated EC: 0x1E */
42 #define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
43 #define ESR_ELx_EC_IABT_LOW (0x20)
44 #define ESR_ELx_EC_IABT_CUR (0x21)
45 #define ESR_ELx_EC_PC_ALIGN (0x22)
46 /* Unallocated EC: 0x23 */
47 #define ESR_ELx_EC_DABT_LOW (0x24)
48 #define ESR_ELx_EC_DABT_CUR (0x25)
49 #define ESR_ELx_EC_SP_ALIGN (0x26)
50 #define ESR_ELx_EC_MOPS (0x27)
51 #define ESR_ELx_EC_FP_EXC32 (0x28)
52 /* Unallocated EC: 0x29 - 0x2B */
53 #define ESR_ELx_EC_FP_EXC64 (0x2C)
54 /* Unallocated EC: 0x2D - 0x2E */
55 #define ESR_ELx_EC_SERROR (0x2F)
56 #define ESR_ELx_EC_BREAKPT_LOW (0x30)
57 #define ESR_ELx_EC_BREAKPT_CUR (0x31)
58 #define ESR_ELx_EC_SOFTSTP_LOW (0x32)
59 #define ESR_ELx_EC_SOFTSTP_CUR (0x33)
60 #define ESR_ELx_EC_WATCHPT_LOW (0x34)
61 #define ESR_ELx_EC_WATCHPT_CUR (0x35)
62 /* Unallocated EC: 0x36 - 0x37 */
63 #define ESR_ELx_EC_BKPT32 (0x38)
64 /* Unallocated EC: 0x39 */
65 #define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */
66 /* Unallocated EC: 0x3B */
67 #define ESR_ELx_EC_BRK64 (0x3C)
68 /* Unallocated EC: 0x3D - 0x3F */
69 #define ESR_ELx_EC_MAX (0x3F)
70
71 #define ESR_ELx_EC_SHIFT (26)
72 #define ESR_ELx_EC_WIDTH (6)
73 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
74 #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
75
76 #define ESR_ELx_IL_SHIFT (25)
77 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
78 #define ESR_ELx_ISS_MASK (GENMASK(24, 0))
79 #define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK)
80 #define ESR_ELx_ISS2_SHIFT (32)
81 #define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32))
82 #define ESR_ELx_ISS2(esr) (((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT)
83
84 /* ISS field definitions shared by different classes */
85 #define ESR_ELx_WNR_SHIFT (6)
86 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
87
88 /* Asynchronous Error Type */
89 #define ESR_ELx_IDS_SHIFT (24)
90 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
91 #define ESR_ELx_AET_SHIFT (10)
92 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
93
94 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
95 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
96 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
97 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
98 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
99
100 /* Shared ISS field definitions for Data/Instruction aborts */
101 #define ESR_ELx_SET_SHIFT (11)
102 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
103 #define ESR_ELx_FnV_SHIFT (10)
104 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
105 #define ESR_ELx_EA_SHIFT (9)
106 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
107 #define ESR_ELx_S1PTW_SHIFT (7)
108 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
109
110 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
111 #define ESR_ELx_FSC (0x3F)
112 #define ESR_ELx_FSC_TYPE (0x3C)
113 #define ESR_ELx_FSC_LEVEL (0x03)
114 #define ESR_ELx_FSC_EXTABT (0x10)
115 #define ESR_ELx_FSC_MTE (0x11)
116 #define ESR_ELx_FSC_SERROR (0x11)
117 #define ESR_ELx_FSC_ACCESS (0x08)
118 #define ESR_ELx_FSC_FAULT (0x04)
119 #define ESR_ELx_FSC_PERM (0x0C)
120 #define ESR_ELx_FSC_SEA_TTW0 (0x14)
121 #define ESR_ELx_FSC_SEA_TTW1 (0x15)
122 #define ESR_ELx_FSC_SEA_TTW2 (0x16)
123 #define ESR_ELx_FSC_SEA_TTW3 (0x17)
124 #define ESR_ELx_FSC_SECC (0x18)
125 #define ESR_ELx_FSC_SECC_TTW0 (0x1c)
126 #define ESR_ELx_FSC_SECC_TTW1 (0x1d)
127 #define ESR_ELx_FSC_SECC_TTW2 (0x1e)
128 #define ESR_ELx_FSC_SECC_TTW3 (0x1f)
129
130 /* ISS field definitions for Data Aborts */
131 #define ESR_ELx_ISV_SHIFT (24)
132 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
133 #define ESR_ELx_SAS_SHIFT (22)
134 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
135 #define ESR_ELx_SSE_SHIFT (21)
136 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
137 #define ESR_ELx_SRT_SHIFT (16)
138 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
139 #define ESR_ELx_SF_SHIFT (15)
140 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
141 #define ESR_ELx_AR_SHIFT (14)
142 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
143 #define ESR_ELx_CM_SHIFT (8)
144 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
145
146 /* ISS2 field definitions for Data Aborts */
147 #define ESR_ELx_TnD_SHIFT (10)
148 #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT)
149 #define ESR_ELx_TagAccess_SHIFT (9)
150 #define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT)
151 #define ESR_ELx_GCS_SHIFT (8)
152 #define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT)
153 #define ESR_ELx_Overlay_SHIFT (6)
154 #define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT)
155 #define ESR_ELx_DirtyBit_SHIFT (5)
156 #define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT)
157 #define ESR_ELx_Xs_SHIFT (0)
158 #define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0))
159
160 /* ISS field definitions for exceptions taken in to Hyp */
161 #define ESR_ELx_CV (UL(1) << 24)
162 #define ESR_ELx_COND_SHIFT (20)
163 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
164 #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
165 #define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
166 #define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
167 #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
168 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
169 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
170 #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
171
172 #define DISR_EL1_IDS (UL(1) << 24)
173 /*
174 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
175 * different things in the future...
176 */
177 #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
178
179 /* ESR value templates for specific events */
180 #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \
181 (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT))
182 #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \
183 ESR_ELx_WFx_ISS_WFI)
184
185 /* BRK instruction trap from AArch64 state */
186 #define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff
187
188 /* ISS field definitions for System instruction traps */
189 #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22
190 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
191 #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
192 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1
193 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
194
195 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5
196 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
197 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
198 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
199 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
200 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
201 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
202 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
203 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
204 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
205 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
206 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
207 #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
208 ESR_ELx_SYS64_ISS_OP1_MASK | \
209 ESR_ELx_SYS64_ISS_OP2_MASK | \
210 ESR_ELx_SYS64_ISS_CRN_MASK | \
211 ESR_ELx_SYS64_ISS_CRM_MASK)
212 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
213 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
214 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
215 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
216 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
217 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
218
219 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \
220 ESR_ELx_SYS64_ISS_DIR_MASK)
221 #define ESR_ELx_SYS64_ISS_RT(esr) \
222 (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
223 /*
224 * User space cache operations have the following sysreg encoding
225 * in System instructions.
226 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
227 */
228 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
229 #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13
230 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12
231 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
232 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
233 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5
234
235 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
236 ESR_ELx_SYS64_ISS_OP1_MASK | \
237 ESR_ELx_SYS64_ISS_OP2_MASK | \
238 ESR_ELx_SYS64_ISS_CRN_MASK | \
239 ESR_ELx_SYS64_ISS_DIR_MASK)
240 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
241 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
242 ESR_ELx_SYS64_ISS_DIR_WRITE)
243 /*
244 * User space MRS operations which are supported for emulation
245 * have the following sysreg encoding in System instructions.
246 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
247 */
248 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
249 ESR_ELx_SYS64_ISS_OP1_MASK | \
250 ESR_ELx_SYS64_ISS_CRN_MASK | \
251 ESR_ELx_SYS64_ISS_DIR_MASK)
252 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
253 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
254 ESR_ELx_SYS64_ISS_DIR_READ)
255
256 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
257 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \
258 ESR_ELx_SYS64_ISS_DIR_READ)
259
260 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
261 ESR_ELx_SYS64_ISS_DIR_READ)
262
263 #define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
264 ESR_ELx_SYS64_ISS_DIR_READ)
265
266 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
267 ESR_ELx_SYS64_ISS_DIR_READ)
268
269 #define esr_sys64_to_sysreg(e) \
270 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
271 ESR_ELx_SYS64_ISS_OP0_SHIFT), \
272 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
273 ESR_ELx_SYS64_ISS_OP1_SHIFT), \
274 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
275 ESR_ELx_SYS64_ISS_CRN_SHIFT), \
276 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
277 ESR_ELx_SYS64_ISS_CRM_SHIFT), \
278 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
279 ESR_ELx_SYS64_ISS_OP2_SHIFT))
280
281 #define esr_cp15_to_sysreg(e) \
282 sys_reg(3, \
283 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
284 ESR_ELx_SYS64_ISS_OP1_SHIFT), \
285 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
286 ESR_ELx_SYS64_ISS_CRN_SHIFT), \
287 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
288 ESR_ELx_SYS64_ISS_CRM_SHIFT), \
289 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
290 ESR_ELx_SYS64_ISS_OP2_SHIFT))
291
292 /* ISS field definitions for ERET/ERETAA/ERETAB trapping */
293 #define ESR_ELx_ERET_ISS_ERET 0x2
294 #define ESR_ELx_ERET_ISS_ERETA 0x1
295
296 /*
297 * ISS field definitions for floating-point exception traps
298 * (FP_EXC_32/FP_EXC_64).
299 *
300 * (The FPEXC_* constants are used instead for common bits.)
301 */
302
303 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
304
305 /*
306 * ISS field definitions for CP15 accesses
307 */
308 #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1
309 #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1
310 #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0
311
312 #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5
313 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
314 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1
315 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
316 #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10
317 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
318 #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14
319 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
320 #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17
321 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
322
323 #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \
324 ESR_ELx_CP15_32_ISS_OP2_MASK | \
325 ESR_ELx_CP15_32_ISS_CRN_MASK | \
326 ESR_ELx_CP15_32_ISS_CRM_MASK | \
327 ESR_ELx_CP15_32_ISS_DIR_MASK)
328 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
329 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
330 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
331 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
332 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
333
334 #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1
335 #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1
336 #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0
337
338 #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5
339 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
340
341 #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10
342 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
343
344 #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16
345 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
346 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1
347 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
348
349 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
350 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
351 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
352
353 #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \
354 ESR_ELx_CP15_64_ISS_CRM_MASK | \
355 ESR_ELx_CP15_64_ISS_DIR_MASK)
356
357 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
358 ESR_ELx_CP15_64_ISS_DIR_READ)
359
360 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
361 ESR_ELx_CP15_64_ISS_DIR_READ)
362
363 #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
364 ESR_ELx_CP15_32_ISS_DIR_READ)
365
366 /*
367 * ISS values for SME traps
368 */
369
370 #define ESR_ELx_SME_ISS_SME_DISABLED 0
371 #define ESR_ELx_SME_ISS_ILL 1
372 #define ESR_ELx_SME_ISS_SM_DISABLED 2
373 #define ESR_ELx_SME_ISS_ZA_DISABLED 3
374 #define ESR_ELx_SME_ISS_ZT_DISABLED 4
375
376 /* ISS field definitions for MOPS exceptions */
377 #define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24)
378 #define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18)
379 #define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17)
380 #define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16)
381 #define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10)
382 #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
383 #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)
384
385 #ifndef __ASSEMBLY__
386 #include <asm/types.h>
387
esr_is_data_abort(unsigned long esr)388 static inline bool esr_is_data_abort(unsigned long esr)
389 {
390 const unsigned long ec = ESR_ELx_EC(esr);
391
392 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
393 }
394
395 const char *esr_get_class_string(unsigned long esr);
396 #endif /* __ASSEMBLY */
397
398 #endif /* __ASM_ESR_H */
399