1 /*
2  *  arch/cris/arch-v32/kernel/kgdb.c
3  *
4  *  CRIS v32 version by Orjan Friberg, Axis Communications AB.
5  *
6  *  S390 version
7  *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
8  *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9  *
10  *  Originally written by Glenn Engel, Lake Stevens Instrument Division
11  *
12  *  Contributed by HP Systems
13  *
14  *  Modified for SPARC by Stu Grossman, Cygnus Support.
15  *
16  *  Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
17  *  Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
18  *
19  *  Copyright (C) 1995 Andreas Busse
20  */
21 
22 /* FIXME: Check the documentation. */
23 
24 /*
25  *  kgdb usage notes:
26  *  -----------------
27  *
28  * If you select CONFIG_ETRAX_KGDB in the configuration, the kernel will be
29  * built with different gcc flags: "-g" is added to get debug infos, and
30  * "-fomit-frame-pointer" is omitted to make debugging easier. Since the
31  * resulting kernel will be quite big (approx. > 7 MB), it will be stripped
32  * before compresion. Such a kernel will behave just as usually, except if
33  * given a "debug=<device>" command line option. (Only serial devices are
34  * allowed for <device>, i.e. no printers or the like; possible values are
35  * machine depedend and are the same as for the usual debug device, the one
36  * for logging kernel messages.) If that option is given and the device can be
37  * initialized, the kernel will connect to the remote gdb in trap_init(). The
38  * serial parameters are fixed to 8N1 and 115200 bps, for easyness of
39  * implementation.
40  *
41  * To start a debugging session, start that gdb with the debugging kernel
42  * image (the one with the symbols, vmlinux.debug) named on the command line.
43  * This file will be used by gdb to get symbol and debugging infos about the
44  * kernel. Next, select remote debug mode by
45  *    target remote <device>
46  * where <device> is the name of the serial device over which the debugged
47  * machine is connected. Maybe you have to adjust the baud rate by
48  *    set remotebaud <rate>
49  * or also other parameters with stty:
50  *    shell stty ... </dev/...
51  * If the kernel to debug has already booted, it waited for gdb and now
52  * connects, and you'll see a breakpoint being reported. If the kernel isn't
53  * running yet, start it now. The order of gdb and the kernel doesn't matter.
54  * Another thing worth knowing about in the getting-started phase is how to
55  * debug the remote protocol itself. This is activated with
56  *    set remotedebug 1
57  * gdb will then print out each packet sent or received. You'll also get some
58  * messages about the gdb stub on the console of the debugged machine.
59  *
60  * If all that works, you can use lots of the usual debugging techniques on
61  * the kernel, e.g. inspecting and changing variables/memory, setting
62  * breakpoints, single stepping and so on. It's also possible to interrupt the
63  * debugged kernel by pressing C-c in gdb. Have fun! :-)
64  *
65  * The gdb stub is entered (and thus the remote gdb gets control) in the
66  * following situations:
67  *
68  *  - If breakpoint() is called. This is just after kgdb initialization, or if
69  *    a breakpoint() call has been put somewhere into the kernel source.
70  *    (Breakpoints can of course also be set the usual way in gdb.)
71  *    In eLinux, we call breakpoint() in init/main.c after IRQ initialization.
72  *
73  *  - If there is a kernel exception, i.e. bad_super_trap() or die_if_kernel()
74  *    are entered. All the CPU exceptions are mapped to (more or less..., see
75  *    the hard_trap_info array below) appropriate signal, which are reported
76  *    to gdb. die_if_kernel() is usually called after some kind of access
77  *    error and thus is reported as SIGSEGV.
78  *
79  *  - When panic() is called. This is reported as SIGABRT.
80  *
81  *  - If C-c is received over the serial line, which is treated as
82  *    SIGINT.
83  *
84  * Of course, all these signals are just faked for gdb, since there is no
85  * signal concept as such for the kernel. It also isn't possible --obviously--
86  * to set signal handlers from inside gdb, or restart the kernel with a
87  * signal.
88  *
89  * Current limitations:
90  *
91  *  - While the kernel is stopped, interrupts are disabled for safety reasons
92  *    (i.e., variables not changing magically or the like). But this also
93  *    means that the clock isn't running anymore, and that interrupts from the
94  *    hardware may get lost/not be served in time. This can cause some device
95  *    errors...
96  *
97  *  - When single-stepping, only one instruction of the current thread is
98  *    executed, but interrupts are allowed for that time and will be serviced
99  *    if pending. Be prepared for that.
100  *
101  *  - All debugging happens in kernel virtual address space. There's no way to
102  *    access physical memory not mapped in kernel space, or to access user
103  *    space. A way to work around this is using get_user_long & Co. in gdb
104  *    expressions, but only for the current process.
105  *
106  *  - Interrupting the kernel only works if interrupts are currently allowed,
107  *    and the interrupt of the serial line isn't blocked by some other means
108  *    (IPL too high, disabled, ...)
109  *
110  *  - The gdb stub is currently not reentrant, i.e. errors that happen therein
111  *    (e.g. accessing invalid memory) may not be caught correctly. This could
112  *    be removed in future by introducing a stack of struct registers.
113  *
114  */
115 
116 /*
117  *  To enable debugger support, two things need to happen.  One, a
118  *  call to kgdb_init() is necessary in order to allow any breakpoints
119  *  or error conditions to be properly intercepted and reported to gdb.
120  *  Two, a breakpoint needs to be generated to begin communication.  This
121  *  is most easily accomplished by a call to breakpoint().
122  *
123  *    The following gdb commands are supported:
124  *
125  * command          function                               Return value
126  *
127  *    g             return the value of the CPU registers  hex data or ENN
128  *    G             set the value of the CPU registers     OK or ENN
129  *
130  *    mAA..AA,LLLL  Read LLLL bytes at address AA..AA      hex data or ENN
131  *    MAA..AA,LLLL: Write LLLL bytes at address AA.AA      OK or ENN
132  *
133  *    c             Resume at current address              SNN   ( signal NN)
134  *    cAA..AA       Continue at address AA..AA             SNN
135  *
136  *    s             Step one instruction                   SNN
137  *    sAA..AA       Step one instruction from AA..AA       SNN
138  *
139  *    k             kill
140  *
141  *    ?             What was the last sigval ?             SNN   (signal NN)
142  *
143  *    bBB..BB	    Set baud rate to BB..BB		   OK or BNN, then sets
144  *							   baud rate
145  *
146  * All commands and responses are sent with a packet which includes a
147  * checksum.  A packet consists of
148  *
149  * $<packet info>#<checksum>.
150  *
151  * where
152  * <packet info> :: <characters representing the command or response>
153  * <checksum>    :: < two hex digits computed as modulo 256 sum of <packetinfo>>
154  *
155  * When a packet is received, it is first acknowledged with either '+' or '-'.
156  * '+' indicates a successful transfer.  '-' indicates a failed transfer.
157  *
158  * Example:
159  *
160  * Host:                  Reply:
161  * $m0,10#2a               +$00010203040506070809101112131415#42
162  *
163  */
164 
165 
166 #include <linux/string.h>
167 #include <linux/signal.h>
168 #include <linux/kernel.h>
169 #include <linux/delay.h>
170 #include <linux/linkage.h>
171 #include <linux/reboot.h>
172 
173 #include <asm/setup.h>
174 #include <asm/ptrace.h>
175 
176 #include <asm/irq.h>
177 #include <hwregs/reg_map.h>
178 #include <hwregs/reg_rdwr.h>
179 #include <hwregs/intr_vect_defs.h>
180 #include <hwregs/ser_defs.h>
181 
182 /* From entry.S. */
183 extern void gdb_handle_exception(void);
184 /* From kgdb_asm.S. */
185 extern void kgdb_handle_exception(void);
186 
187 static int kgdb_started = 0;
188 
189 /********************************* Register image ****************************/
190 
191 typedef
192 struct register_image
193 {
194 	                      /* Offset */
195 	unsigned int   r0;    /* 0x00 */
196 	unsigned int   r1;    /* 0x04 */
197 	unsigned int   r2;    /* 0x08 */
198 	unsigned int   r3;    /* 0x0C */
199 	unsigned int   r4;    /* 0x10 */
200 	unsigned int   r5;    /* 0x14 */
201 	unsigned int   r6;    /* 0x18 */
202 	unsigned int   r7;    /* 0x1C */
203 	unsigned int   r8;    /* 0x20; Frame pointer (if any) */
204 	unsigned int   r9;    /* 0x24 */
205 	unsigned int   r10;   /* 0x28 */
206 	unsigned int   r11;   /* 0x2C */
207 	unsigned int   r12;   /* 0x30 */
208 	unsigned int   r13;   /* 0x34 */
209 	unsigned int   sp;    /* 0x38; R14, Stack pointer */
210 	unsigned int   acr;   /* 0x3C; R15, Address calculation register. */
211 
212 	unsigned char  bz;    /* 0x40; P0, 8-bit zero register */
213 	unsigned char  vr;    /* 0x41; P1, Version register (8-bit) */
214 	unsigned int   pid;   /* 0x42; P2, Process ID */
215 	unsigned char  srs;   /* 0x46; P3, Support register select (8-bit) */
216         unsigned short wz;    /* 0x47; P4, 16-bit zero register */
217 	unsigned int   exs;   /* 0x49; P5, Exception status */
218 	unsigned int   eda;   /* 0x4D; P6, Exception data address */
219 	unsigned int   mof;   /* 0x51; P7, Multiply overflow register */
220 	unsigned int   dz;    /* 0x55; P8, 32-bit zero register */
221 	unsigned int   ebp;   /* 0x59; P9, Exception base pointer */
222 	unsigned int   erp;   /* 0x5D; P10, Exception return pointer. Contains the PC we are interested in. */
223 	unsigned int   srp;   /* 0x61; P11, Subroutine return pointer */
224 	unsigned int   nrp;   /* 0x65; P12, NMI return pointer */
225 	unsigned int   ccs;   /* 0x69; P13, Condition code stack */
226 	unsigned int   usp;   /* 0x6D; P14, User mode stack pointer */
227 	unsigned int   spc;   /* 0x71; P15, Single step PC */
228 	unsigned int   pc;    /* 0x75; Pseudo register (for the most part set to ERP). */
229 
230 } registers;
231 
232 typedef
233 struct bp_register_image
234 {
235 	/* Support register bank 0. */
236 	unsigned int   s0_0;
237 	unsigned int   s1_0;
238 	unsigned int   s2_0;
239 	unsigned int   s3_0;
240 	unsigned int   s4_0;
241 	unsigned int   s5_0;
242 	unsigned int   s6_0;
243 	unsigned int   s7_0;
244 	unsigned int   s8_0;
245 	unsigned int   s9_0;
246 	unsigned int   s10_0;
247 	unsigned int   s11_0;
248 	unsigned int   s12_0;
249 	unsigned int   s13_0;
250 	unsigned int   s14_0;
251 	unsigned int   s15_0;
252 
253 	/* Support register bank 1. */
254 	unsigned int   s0_1;
255 	unsigned int   s1_1;
256 	unsigned int   s2_1;
257 	unsigned int   s3_1;
258 	unsigned int   s4_1;
259 	unsigned int   s5_1;
260 	unsigned int   s6_1;
261 	unsigned int   s7_1;
262 	unsigned int   s8_1;
263 	unsigned int   s9_1;
264 	unsigned int   s10_1;
265 	unsigned int   s11_1;
266 	unsigned int   s12_1;
267 	unsigned int   s13_1;
268 	unsigned int   s14_1;
269 	unsigned int   s15_1;
270 
271 	/* Support register bank 2. */
272 	unsigned int   s0_2;
273 	unsigned int   s1_2;
274 	unsigned int   s2_2;
275 	unsigned int   s3_2;
276 	unsigned int   s4_2;
277 	unsigned int   s5_2;
278 	unsigned int   s6_2;
279 	unsigned int   s7_2;
280 	unsigned int   s8_2;
281 	unsigned int   s9_2;
282 	unsigned int   s10_2;
283 	unsigned int   s11_2;
284 	unsigned int   s12_2;
285 	unsigned int   s13_2;
286 	unsigned int   s14_2;
287 	unsigned int   s15_2;
288 
289 	/* Support register bank 3. */
290 	unsigned int   s0_3; /* BP_CTRL */
291 	unsigned int   s1_3; /* BP_I0_START */
292 	unsigned int   s2_3; /* BP_I0_END */
293 	unsigned int   s3_3; /* BP_D0_START */
294 	unsigned int   s4_3; /* BP_D0_END */
295 	unsigned int   s5_3; /* BP_D1_START */
296 	unsigned int   s6_3; /* BP_D1_END */
297 	unsigned int   s7_3; /* BP_D2_START */
298 	unsigned int   s8_3; /* BP_D2_END */
299 	unsigned int   s9_3; /* BP_D3_START */
300 	unsigned int   s10_3; /* BP_D3_END */
301 	unsigned int   s11_3; /* BP_D4_START */
302 	unsigned int   s12_3; /* BP_D4_END */
303 	unsigned int   s13_3; /* BP_D5_START */
304 	unsigned int   s14_3; /* BP_D5_END */
305 	unsigned int   s15_3; /* BP_RESERVED */
306 
307 } support_registers;
308 
309 enum register_name
310 {
311 	R0,  R1,  R2,  R3,
312 	R4,  R5,  R6,  R7,
313 	R8,  R9,  R10, R11,
314 	R12, R13, SP,  ACR,
315 
316 	BZ,  VR,  PID, SRS,
317 	WZ,  EXS, EDA, MOF,
318 	DZ,  EBP, ERP, SRP,
319 	NRP, CCS, USP, SPC,
320 	PC,
321 
322 	S0,  S1,  S2,  S3,
323 	S4,  S5,  S6,  S7,
324 	S8,  S9,  S10, S11,
325 	S12, S13, S14, S15
326 
327 };
328 
329 /* The register sizes of the registers in register_name. An unimplemented register
330    is designated by size 0 in this array. */
331 static int register_size[] =
332 {
333 	4, 4, 4, 4,
334 	4, 4, 4, 4,
335 	4, 4, 4, 4,
336 	4, 4, 4, 4,
337 
338 	1, 1, 4, 1,
339 	2, 4, 4, 4,
340 	4, 4, 4, 4,
341 	4, 4, 4, 4,
342 
343 	4,
344 
345 	4, 4, 4, 4,
346 	4, 4, 4, 4,
347 	4, 4, 4, 4,
348 	4, 4, 4
349 
350 };
351 
352 /* Contains the register image of the kernel.
353    (Global so that they can be reached from assembler code.) */
354 registers reg;
355 support_registers sreg;
356 
357 /************** Prototypes for local library functions ***********************/
358 
359 /* Copy of strcpy from libc. */
360 static char *gdb_cris_strcpy(char *s1, const char *s2);
361 
362 /* Copy of strlen from libc. */
363 static int gdb_cris_strlen(const char *s);
364 
365 /* Copy of memchr from libc. */
366 static void *gdb_cris_memchr(const void *s, int c, int n);
367 
368 /* Copy of strtol from libc. Does only support base 16. */
369 static int gdb_cris_strtol(const char *s, char **endptr, int base);
370 
371 /********************** Prototypes for local functions. **********************/
372 
373 /* Write a value to a specified register regno in the register image
374    of the current thread. */
375 static int write_register(int regno, char *val);
376 
377 /* Read a value from a specified register in the register image. Returns the
378    status of the read operation. The register value is returned in valptr. */
379 static int read_register(char regno, unsigned int *valptr);
380 
381 /* Serial port, reads one character. ETRAX 100 specific. from debugport.c */
382 int getDebugChar(void);
383 
384 #ifdef CONFIG_ETRAX_VCS_SIM
getDebugChar(void)385 int getDebugChar(void)
386 {
387   return socketread();
388 }
389 #endif
390 
391 /* Serial port, writes one character. ETRAX 100 specific. from debugport.c */
392 void putDebugChar(int val);
393 
394 #ifdef CONFIG_ETRAX_VCS_SIM
putDebugChar(int val)395 void putDebugChar(int val)
396 {
397   socketwrite((char *)&val, 1);
398 }
399 #endif
400 
401 /* Returns the integer equivalent of a hexadecimal character. */
402 static int hex(char ch);
403 
404 /* Convert the memory, pointed to by mem into hexadecimal representation.
405    Put the result in buf, and return a pointer to the last character
406    in buf (null). */
407 static char *mem2hex(char *buf, unsigned char *mem, int count);
408 
409 /* Convert the array, in hexadecimal representation, pointed to by buf into
410    binary representation. Put the result in mem, and return a pointer to
411    the character after the last byte written. */
412 static unsigned char *hex2mem(unsigned char *mem, char *buf, int count);
413 
414 /* Put the content of the array, in binary representation, pointed to by buf
415    into memory pointed to by mem, and return a pointer to
416    the character after the last byte written. */
417 static unsigned char *bin2mem(unsigned char *mem, unsigned char *buf, int count);
418 
419 /* Await the sequence $<data>#<checksum> and store <data> in the array buffer
420    returned. */
421 static void getpacket(char *buffer);
422 
423 /* Send $<data>#<checksum> from the <data> in the array buffer. */
424 static void putpacket(char *buffer);
425 
426 /* Build and send a response packet in order to inform the host the
427    stub is stopped. */
428 static void stub_is_stopped(int sigval);
429 
430 /* All expected commands are sent from remote.c. Send a response according
431    to the description in remote.c. Not static since it needs to be reached
432    from assembler code. */
433 void handle_exception(int sigval);
434 
435 /* Performs a complete re-start from scratch. ETRAX specific. */
436 static void kill_restart(void);
437 
438 /******************** Prototypes for global functions. ***********************/
439 
440 /* The string str is prepended with the GDB printout token and sent. */
441 void putDebugString(const unsigned char *str, int len);
442 
443 /* A static breakpoint to be used at startup. */
444 void breakpoint(void);
445 
446 /* Avoid warning as the internal_stack is not used in the C-code. */
447 #define USEDVAR(name)    { if (name) { ; } }
448 #define USEDFUN(name) { void (*pf)(void) = (void *)name; USEDVAR(pf) }
449 
450 /********************************** Packet I/O ******************************/
451 /* BUFMAX defines the maximum number of characters in
452    inbound/outbound buffers */
453 /* FIXME: How do we know it's enough? */
454 #define BUFMAX 512
455 
456 /* Run-length encoding maximum length. Send 64 at most. */
457 #define RUNLENMAX 64
458 
459 /* The inbound/outbound buffers used in packet I/O */
460 static char input_buffer[BUFMAX];
461 static char output_buffer[BUFMAX];
462 
463 /* Error and warning messages. */
464 enum error_type
465 {
466 	SUCCESS, E01, E02, E03, E04, E05, E06,
467 };
468 
469 static char *error_message[] =
470 {
471 	"",
472 	"E01 Set current or general thread - H[c,g] - internal error.",
473 	"E02 Change register content - P - cannot change read-only register.",
474 	"E03 Thread is not alive.", /* T, not used. */
475 	"E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.",
476 	"E05 Change register content - P - the register is not implemented..",
477 	"E06 Change memory content - M - internal error.",
478 };
479 
480 /********************************** Breakpoint *******************************/
481 /* Use an internal stack in the breakpoint and interrupt response routines.
482    FIXME: How do we know the size of this stack is enough?
483    Global so it can be reached from assembler code. */
484 #define INTERNAL_STACK_SIZE 1024
485 char internal_stack[INTERNAL_STACK_SIZE];
486 
487 /* Due to the breakpoint return pointer, a state variable is needed to keep
488    track of whether it is a static (compiled) or dynamic (gdb-invoked)
489    breakpoint to be handled. A static breakpoint uses the content of register
490    ERP as it is whereas a dynamic breakpoint requires subtraction with 2
491    in order to execute the instruction. The first breakpoint is static; all
492    following are assumed to be dynamic. */
493 static int dynamic_bp = 0;
494 
495 /********************************* String library ****************************/
496 /* Single-step over library functions creates trap loops. */
497 
498 /* Copy char s2[] to s1[]. */
499 static char*
gdb_cris_strcpy(char * s1,const char * s2)500 gdb_cris_strcpy(char *s1, const char *s2)
501 {
502 	char *s = s1;
503 
504 	for (s = s1; (*s++ = *s2++) != '\0'; )
505 		;
506 	return s1;
507 }
508 
509 /* Find length of s[]. */
510 static int
gdb_cris_strlen(const char * s)511 gdb_cris_strlen(const char *s)
512 {
513 	const char *sc;
514 
515 	for (sc = s; *sc != '\0'; sc++)
516 		;
517 	return (sc - s);
518 }
519 
520 /* Find first occurrence of c in s[n]. */
521 static void*
gdb_cris_memchr(const void * s,int c,int n)522 gdb_cris_memchr(const void *s, int c, int n)
523 {
524 	const unsigned char uc = c;
525 	const unsigned char *su;
526 
527 	for (su = s; 0 < n; ++su, --n)
528 		if (*su == uc)
529 			return (void *)su;
530 	return NULL;
531 }
532 /******************************* Standard library ****************************/
533 /* Single-step over library functions creates trap loops. */
534 /* Convert string to long. */
535 static int
gdb_cris_strtol(const char * s,char ** endptr,int base)536 gdb_cris_strtol(const char *s, char **endptr, int base)
537 {
538 	char *s1;
539 	char *sd;
540 	int x = 0;
541 
542 	for (s1 = (char*)s; (sd = gdb_cris_memchr(hex_asc, *s1, base)) != NULL; ++s1)
543 		x = x * base + (sd - hex_asc);
544 
545         if (endptr) {
546                 /* Unconverted suffix is stored in endptr unless endptr is NULL. */
547                 *endptr = s1;
548         }
549 
550 	return x;
551 }
552 
553 /********************************* Register image ****************************/
554 
555 /* Write a value to a specified register in the register image of the current
556    thread. Returns status code SUCCESS, E02 or E05. */
557 static int
write_register(int regno,char * val)558 write_register(int regno, char *val)
559 {
560 	int status = SUCCESS;
561 
562         if (regno >= R0 && regno <= ACR) {
563 		/* Consecutive 32-bit registers. */
564 		hex2mem((unsigned char *)&reg.r0 + (regno - R0) * sizeof(unsigned int),
565 			val, sizeof(unsigned int));
566 
567 	} else if (regno == BZ || regno == VR || regno == WZ || regno == DZ) {
568 		/* Read-only registers. */
569 		status = E02;
570 
571 	} else if (regno == PID) {
572 		/* 32-bit register. (Even though we already checked SRS and WZ, we cannot
573 		   combine this with the EXS - SPC write since SRS and WZ have different size.) */
574 		hex2mem((unsigned char *)&reg.pid, val, sizeof(unsigned int));
575 
576 	} else if (regno == SRS) {
577 		/* 8-bit register. */
578 		hex2mem((unsigned char *)&reg.srs, val, sizeof(unsigned char));
579 
580 	} else if (regno >= EXS && regno <= SPC) {
581 		/* Consecutive 32-bit registers. */
582 		hex2mem((unsigned char *)&reg.exs + (regno - EXS) * sizeof(unsigned int),
583 			 val, sizeof(unsigned int));
584 
585        } else if (regno == PC) {
586                /* Pseudo-register. Treat as read-only. */
587                status = E02;
588 
589        } else if (regno >= S0 && regno <= S15) {
590                /* 32-bit registers. */
591                hex2mem((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int), val, sizeof(unsigned int));
592 	} else {
593 		/* Non-existing register. */
594 		status = E05;
595 	}
596 	return status;
597 }
598 
599 /* Read a value from a specified register in the register image. Returns the
600    value in the register or -1 for non-implemented registers. */
601 static int
read_register(char regno,unsigned int * valptr)602 read_register(char regno, unsigned int *valptr)
603 {
604 	int status = SUCCESS;
605 
606 	/* We read the zero registers from the register struct (instead of just returning 0)
607 	   to catch errors. */
608 
609 	if (regno >= R0 && regno <= ACR) {
610 		/* Consecutive 32-bit registers. */
611 		*valptr = *(unsigned int *)((char *)&reg.r0 + (regno - R0) * sizeof(unsigned int));
612 
613 	} else if (regno == BZ || regno == VR) {
614 		/* Consecutive 8-bit registers. */
615 		*valptr = (unsigned int)(*(unsigned char *)
616                                          ((char *)&reg.bz + (regno - BZ) * sizeof(char)));
617 
618 	} else if (regno == PID) {
619 		/* 32-bit register. */
620 		*valptr =  *(unsigned int *)((char *)&reg.pid);
621 
622 	} else if (regno == SRS) {
623 		/* 8-bit register. */
624 		*valptr = (unsigned int)(*(unsigned char *)((char *)&reg.srs));
625 
626 	} else if (regno == WZ) {
627 		/* 16-bit register. */
628 		*valptr = (unsigned int)(*(unsigned short *)(char *)&reg.wz);
629 
630 	} else if (regno >= EXS && regno <= PC) {
631 		/* Consecutive 32-bit registers. */
632 		*valptr = *(unsigned int *)((char *)&reg.exs + (regno - EXS) * sizeof(unsigned int));
633 
634 	} else if (regno >= S0 && regno <= S15) {
635 		/* Consecutive 32-bit registers, located elsewhere. */
636 		*valptr = *(unsigned int *)((char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int));
637 
638 	} else {
639 		/* Non-existing register. */
640 		status = E05;
641 	}
642 	return status;
643 
644 }
645 
646 /********************************** Packet I/O ******************************/
647 /* Returns the integer equivalent of a hexadecimal character. */
648 static int
hex(char ch)649 hex(char ch)
650 {
651 	if ((ch >= 'a') && (ch <= 'f'))
652 		return (ch - 'a' + 10);
653 	if ((ch >= '0') && (ch <= '9'))
654 		return (ch - '0');
655 	if ((ch >= 'A') && (ch <= 'F'))
656 		return (ch - 'A' + 10);
657 	return -1;
658 }
659 
660 /* Convert the memory, pointed to by mem into hexadecimal representation.
661    Put the result in buf, and return a pointer to the last character
662    in buf (null). */
663 
664 static char *
mem2hex(char * buf,unsigned char * mem,int count)665 mem2hex(char *buf, unsigned char *mem, int count)
666 {
667 	int i;
668 	int ch;
669 
670         if (mem == NULL) {
671 		/* Invalid address, caught by 'm' packet handler. */
672                 for (i = 0; i < count; i++) {
673                         *buf++ = '0';
674                         *buf++ = '0';
675                 }
676         } else {
677                 /* Valid mem address. */
678 		for (i = 0; i < count; i++) {
679 			ch = *mem++;
680 			buf = hex_byte_pack(buf, ch);
681 		}
682         }
683         /* Terminate properly. */
684 	*buf = '\0';
685 	return buf;
686 }
687 
688 /* Same as mem2hex, but puts it in network byte order. */
689 static char *
mem2hex_nbo(char * buf,unsigned char * mem,int count)690 mem2hex_nbo(char *buf, unsigned char *mem, int count)
691 {
692 	int i;
693 	int ch;
694 
695 	mem += count - 1;
696 	for (i = 0; i < count; i++) {
697 		ch = *mem--;
698 		buf = hex_byte_pack(buf, ch);
699         }
700 
701         /* Terminate properly. */
702 	*buf = '\0';
703 	return buf;
704 }
705 
706 /* Convert the array, in hexadecimal representation, pointed to by buf into
707    binary representation. Put the result in mem, and return a pointer to
708    the character after the last byte written. */
709 static unsigned char*
hex2mem(unsigned char * mem,char * buf,int count)710 hex2mem(unsigned char *mem, char *buf, int count)
711 {
712 	int i;
713 	unsigned char ch;
714 	for (i = 0; i < count; i++) {
715 		ch = hex (*buf++) << 4;
716 		ch = ch + hex (*buf++);
717 		*mem++ = ch;
718 	}
719 	return mem;
720 }
721 
722 /* Put the content of the array, in binary representation, pointed to by buf
723    into memory pointed to by mem, and return a pointer to the character after
724    the last byte written.
725    Gdb will escape $, #, and the escape char (0x7d). */
726 static unsigned char*
bin2mem(unsigned char * mem,unsigned char * buf,int count)727 bin2mem(unsigned char *mem, unsigned char *buf, int count)
728 {
729 	int i;
730 	unsigned char *next;
731 	for (i = 0; i < count; i++) {
732 		/* Check for any escaped characters. Be paranoid and
733 		   only unescape chars that should be escaped. */
734 		if (*buf == 0x7d) {
735 			next = buf + 1;
736 			if (*next == 0x3 || *next == 0x4 || *next == 0x5D) {
737 				 /* #, $, ESC */
738 				buf++;
739 				*buf += 0x20;
740 			}
741 		}
742 		*mem++ = *buf++;
743 	}
744 	return mem;
745 }
746 
747 /* Await the sequence $<data>#<checksum> and store <data> in the array buffer
748    returned. */
749 static void
getpacket(char * buffer)750 getpacket(char *buffer)
751 {
752 	unsigned char checksum;
753 	unsigned char xmitcsum;
754 	int i;
755 	int count;
756 	char ch;
757 
758 	do {
759 		while((ch = getDebugChar ()) != '$')
760 			/* Wait for the start character $ and ignore all other characters */;
761 		checksum = 0;
762 		xmitcsum = -1;
763 		count = 0;
764 		/* Read until a # or the end of the buffer is reached */
765 		while (count < BUFMAX) {
766 			ch = getDebugChar();
767 			if (ch == '#')
768 				break;
769 			checksum = checksum + ch;
770 			buffer[count] = ch;
771 			count = count + 1;
772 		}
773 
774 		if (count >= BUFMAX)
775 			continue;
776 
777 		buffer[count] = 0;
778 
779 		if (ch == '#') {
780 			xmitcsum = hex(getDebugChar()) << 4;
781 			xmitcsum += hex(getDebugChar());
782 			if (checksum != xmitcsum) {
783 				/* Wrong checksum */
784 				putDebugChar('-');
785 			} else {
786 				/* Correct checksum */
787 				putDebugChar('+');
788 				/* If sequence characters are received, reply with them */
789 				if (buffer[2] == ':') {
790 					putDebugChar(buffer[0]);
791 					putDebugChar(buffer[1]);
792 					/* Remove the sequence characters from the buffer */
793 					count = gdb_cris_strlen(buffer);
794 					for (i = 3; i <= count; i++)
795 						buffer[i - 3] = buffer[i];
796 				}
797 			}
798 		}
799 	} while (checksum != xmitcsum);
800 }
801 
802 /* Send $<data>#<checksum> from the <data> in the array buffer. */
803 
804 static void
putpacket(char * buffer)805 putpacket(char *buffer)
806 {
807 	int checksum;
808 	int runlen;
809 	int encode;
810 
811 	do {
812 		char *src = buffer;
813 		putDebugChar('$');
814 		checksum = 0;
815 		while (*src) {
816 			/* Do run length encoding */
817 			putDebugChar(*src);
818 			checksum += *src;
819 			runlen = 0;
820 			while (runlen < RUNLENMAX && *src == src[runlen]) {
821 				runlen++;
822 			}
823 			if (runlen > 3) {
824 				/* Got a useful amount */
825 				putDebugChar ('*');
826 				checksum += '*';
827 				encode = runlen + ' ' - 4;
828 				putDebugChar(encode);
829 				checksum += encode;
830 				src += runlen;
831 			} else {
832 				src++;
833 			}
834 		}
835 		putDebugChar('#');
836 		putDebugChar(hex_asc_hi(checksum));
837 		putDebugChar(hex_asc_lo(checksum));
838 	} while(kgdb_started && (getDebugChar() != '+'));
839 }
840 
841 /* The string str is prepended with the GDB printout token and sent. Required
842    in traditional implementations. */
843 void
putDebugString(const unsigned char * str,int len)844 putDebugString(const unsigned char *str, int len)
845 {
846 	/* Move SPC forward if we are single-stepping. */
847 	asm("spchere:");
848 	asm("move $spc, $r10");
849 	asm("cmp.d spchere, $r10");
850 	asm("bne nosstep");
851 	asm("nop");
852 	asm("move.d spccont, $r10");
853 	asm("move $r10, $spc");
854 	asm("nosstep:");
855 
856         output_buffer[0] = 'O';
857         mem2hex(&output_buffer[1], (unsigned char *)str, len);
858         putpacket(output_buffer);
859 
860 	asm("spccont:");
861 }
862 
863 /********************************** Handle exceptions ************************/
864 /* Build and send a response packet in order to inform the host the
865    stub is stopped. TAAn...:r...;n...:r...;n...:r...;
866                     AA = signal number
867                     n... = register number (hex)
868                     r... = register contents
869                     n... = `thread'
870                     r... = thread process ID.  This is a hex integer.
871                     n... = other string not starting with valid hex digit.
872                     gdb should ignore this n,r pair and go on to the next.
873                     This way we can extend the protocol. */
874 static void
stub_is_stopped(int sigval)875 stub_is_stopped(int sigval)
876 {
877 	char *ptr = output_buffer;
878 	unsigned int reg_cont;
879 
880 	/* Send trap type (converted to signal) */
881 
882 	*ptr++ = 'T';
883 	ptr = hex_byte_pack(ptr, sigval);
884 
885 	if (((reg.exs & 0xff00) >> 8) == 0xc) {
886 
887 		/* Some kind of hardware watchpoint triggered. Find which one
888 		   and determine its type (read/write/access).  */
889 		int S, bp, trig_bits = 0, rw_bits = 0;
890 		int trig_mask = 0;
891 		unsigned int *bp_d_regs = &sreg.s3_3;
892 		/* In a lot of cases, the stopped data address will simply be EDA.
893 		   In some cases, we adjust it to match the watched data range.
894 		   (We don't want to change the actual EDA though). */
895 		unsigned int stopped_data_address;
896 		/* The S field of EXS. */
897 		S = (reg.exs & 0xffff0000) >> 16;
898 
899 		if (S & 1) {
900 			/* Instruction watchpoint. */
901 			/* FIXME: Check against, and possibly adjust reported EDA. */
902 		} else {
903 			/* Data watchpoint.  Find the one that triggered. */
904 			for (bp = 0; bp < 6; bp++) {
905 
906 				/* Dx_RD, Dx_WR in the S field of EXS for this BP. */
907 				int bitpos_trig = 1 + bp * 2;
908 				/* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
909 				int bitpos_config = 2 + bp * 4;
910 
911 				/* Get read/write trig bits for this BP. */
912 				trig_bits = (S & (3 << bitpos_trig)) >> bitpos_trig;
913 
914 				/* Read/write config bits for this BP. */
915 				rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
916 				if (trig_bits) {
917 					/* Sanity check: the BP shouldn't trigger for accesses
918 					   that it isn't configured for. */
919 					if ((rw_bits == 0x1 && trig_bits != 0x1) ||
920 					    (rw_bits == 0x2 && trig_bits != 0x2))
921 						panic("Invalid r/w trigging for this BP");
922 
923 					/* Mark this BP as trigged for future reference. */
924 					trig_mask |= (1 << bp);
925 
926 					if (reg.eda >= bp_d_regs[bp * 2] &&
927 					    reg.eda <= bp_d_regs[bp * 2 + 1]) {
928 						/* EDA within range for this BP; it must be the one
929 						   we're looking for. */
930 						stopped_data_address = reg.eda;
931 						break;
932 					}
933 				}
934 			}
935 			if (bp < 6) {
936 				/* Found a trigged BP with EDA within its configured data range. */
937 			} else if (trig_mask) {
938 				/* Something triggered, but EDA doesn't match any BP's range. */
939 				for (bp = 0; bp < 6; bp++) {
940 					/* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
941 					int bitpos_config = 2 + bp * 4;
942 
943 					/* Read/write config bits for this BP (needed later). */
944 					rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
945 
946 					if (trig_mask & (1 << bp)) {
947 						/* EDA within 31 bytes of the configured start address? */
948 						if (reg.eda + 31 >= bp_d_regs[bp * 2]) {
949 							/* Changing the reported address to match
950 							   the start address of the first applicable BP. */
951 							stopped_data_address = bp_d_regs[bp * 2];
952 							break;
953 						} else {
954 							/* We continue since we might find another useful BP. */
955 							printk("EDA doesn't match trigged BP's range");
956 						}
957 					}
958 				}
959 			}
960 
961 			/* No match yet? */
962 			BUG_ON(bp >= 6);
963 			/* Note that we report the type according to what the BP is configured
964 			   for (otherwise we'd never report an 'awatch'), not according to how
965 			   it trigged. We did check that the trigged bits match what the BP is
966 			   configured for though. */
967 			if (rw_bits == 0x1) {
968 				/* read */
969 				strncpy(ptr, "rwatch", 6);
970 				ptr += 6;
971 			} else if (rw_bits == 0x2) {
972 				/* write */
973 				strncpy(ptr, "watch", 5);
974 				ptr += 5;
975 			} else if (rw_bits == 0x3) {
976 				/* access */
977 				strncpy(ptr, "awatch", 6);
978 				ptr += 6;
979 			} else {
980 				panic("Invalid r/w bits for this BP.");
981 			}
982 
983 			*ptr++ = ':';
984 			/* Note that we don't read_register(EDA, ...) */
985 			ptr = mem2hex_nbo(ptr, (unsigned char *)&stopped_data_address, register_size[EDA]);
986 			*ptr++ = ';';
987 		}
988 	}
989 	/* Only send PC, frame and stack pointer. */
990 	read_register(PC, &reg_cont);
991 	ptr = hex_byte_pack(ptr, PC);
992 	*ptr++ = ':';
993 	ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[PC]);
994 	*ptr++ = ';';
995 
996 	read_register(R8, &reg_cont);
997 	ptr = hex_byte_pack(ptr, R8);
998 	*ptr++ = ':';
999 	ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[R8]);
1000 	*ptr++ = ';';
1001 
1002 	read_register(SP, &reg_cont);
1003 	ptr = hex_byte_pack(ptr, SP);
1004 	*ptr++ = ':';
1005 	ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[SP]);
1006 	*ptr++ = ';';
1007 
1008 	/* Send ERP as well; this will save us an entire register fetch in some cases. */
1009         read_register(ERP, &reg_cont);
1010 	ptr = hex_byte_pack(ptr, ERP);
1011         *ptr++ = ':';
1012         ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[ERP]);
1013         *ptr++ = ';';
1014 
1015 	/* null-terminate and send it off */
1016 	*ptr = 0;
1017 	putpacket(output_buffer);
1018 }
1019 
1020 /* Returns the size of an instruction that has a delay slot. */
1021 
insn_size(unsigned long pc)1022 int insn_size(unsigned long pc)
1023 {
1024 	unsigned short opcode = *(unsigned short *)pc;
1025 	int size = 0;
1026 
1027 	switch ((opcode & 0x0f00) >> 8) {
1028 	case 0x0:
1029 	case 0x9:
1030 	case 0xb:
1031 		size = 2;
1032 		break;
1033 	case 0xe:
1034 	case 0xf:
1035 		size = 6;
1036 		break;
1037 	case 0xd:
1038 		/* Could be 4 or 6; check more bits. */
1039 		if ((opcode & 0xff) == 0xff)
1040 			size = 4;
1041 		else
1042 			size = 6;
1043 		break;
1044 	default:
1045 		panic("Couldn't find size of opcode 0x%x at 0x%lx\n", opcode, pc);
1046 	}
1047 
1048 	return size;
1049 }
1050 
register_fixup(int sigval)1051 void register_fixup(int sigval)
1052 {
1053 	/* Compensate for ACR push at the beginning of exception handler. */
1054 	reg.sp += 4;
1055 
1056 	/* Standard case. */
1057 	reg.pc = reg.erp;
1058 	if (reg.erp & 0x1) {
1059 		/* Delay slot bit set.  Report as stopped on proper instruction.  */
1060 		if (reg.spc) {
1061 			/* Rely on SPC if set. */
1062 			reg.pc = reg.spc;
1063 		} else {
1064 			/* Calculate the PC from the size of the instruction
1065 			   that the delay slot we're in belongs to. */
1066 			reg.pc += insn_size(reg.erp & ~1) - 1 ;
1067 		}
1068 	}
1069 
1070 	if ((reg.exs & 0x3) == 0x0) {
1071 		/* Bits 1 - 0 indicate the type of memory operation performed
1072 		   by the interrupted instruction. 0 means no memory operation,
1073 		   and EDA is undefined in that case. We zero it to avoid confusion. */
1074 		reg.eda = 0;
1075 	}
1076 
1077 	if (sigval == SIGTRAP) {
1078 		/* Break 8, single step or hardware breakpoint exception. */
1079 
1080 		/* Check IDX field of EXS. */
1081 		if (((reg.exs & 0xff00) >> 8) == 0x18) {
1082 
1083 			/* Break 8. */
1084 
1085                         /* Static (compiled) breakpoints must return to the next instruction
1086 			   in order to avoid infinite loops (default value of ERP). Dynamic
1087 			   (gdb-invoked) must subtract the size of the break instruction from
1088 			   the ERP so that the instruction that was originally in the break
1089 			   instruction's place will be run when we return from the exception. */
1090 			if (!dynamic_bp) {
1091 				/* Assuming that all breakpoints are dynamic from now on. */
1092 				dynamic_bp = 1;
1093 			} else {
1094 
1095 				/* Only if not in a delay slot. */
1096 				if (!(reg.erp & 0x1)) {
1097 					reg.erp -= 2;
1098 					reg.pc -= 2;
1099 				}
1100 			}
1101 
1102 		} else if (((reg.exs & 0xff00) >> 8) == 0x3) {
1103 			/* Single step. */
1104 			/* Don't fiddle with S1. */
1105 
1106 		} else if (((reg.exs & 0xff00) >> 8) == 0xc) {
1107 
1108 			/* Hardware watchpoint exception. */
1109 
1110 			/* SPC has been updated so that we will get a single step exception
1111 			   when we return, but we don't want that. */
1112 			reg.spc = 0;
1113 
1114 			/* Don't fiddle with S1. */
1115 		}
1116 
1117 	} else if (sigval == SIGINT) {
1118 		/* Nothing special. */
1119 	}
1120 }
1121 
insert_watchpoint(char type,int addr,int len)1122 static void insert_watchpoint(char type, int addr, int len)
1123 {
1124 	/* Breakpoint/watchpoint types (GDB terminology):
1125 	   0 = memory breakpoint for instructions
1126 	   (not supported; done via memory write instead)
1127 	   1 = hardware breakpoint for instructions (supported)
1128 	   2 = write watchpoint (supported)
1129 	   3 = read watchpoint (supported)
1130 	   4 = access watchpoint (supported) */
1131 
1132 	if (type < '1' || type > '4') {
1133 		output_buffer[0] = 0;
1134 		return;
1135 	}
1136 
1137 	/* Read watchpoints are set as access watchpoints, because of GDB's
1138 	   inability to deal with pure read watchpoints. */
1139 	if (type == '3')
1140 		type = '4';
1141 
1142 	if (type == '1') {
1143 		/* Hardware (instruction) breakpoint. */
1144 		/* Bit 0 in BP_CTRL holds the configuration for I0. */
1145 		if (sreg.s0_3 & 0x1) {
1146 			/* Already in use. */
1147 			gdb_cris_strcpy(output_buffer, error_message[E04]);
1148 			return;
1149 		}
1150 		/* Configure. */
1151 		sreg.s1_3 = addr;
1152 		sreg.s2_3 = (addr + len - 1);
1153 		sreg.s0_3 |= 1;
1154 	} else {
1155 		int bp;
1156 		unsigned int *bp_d_regs = &sreg.s3_3;
1157 
1158 		/* The watchpoint allocation scheme is the simplest possible.
1159 		   For example, if a region is watched for read and
1160 		   a write watch is requested, a new watchpoint will
1161 		   be used. Also, if a watch for a region that is already
1162 		   covered by one or more existing watchpoints, a new
1163 		   watchpoint will be used. */
1164 
1165 		/* First, find a free data watchpoint. */
1166 		for (bp = 0; bp < 6; bp++) {
1167 			/* Each data watchpoint's control registers occupy 2 bits
1168 			   (hence the 3), starting at bit 2 for D0 (hence the 2)
1169 			   with 4 bits between for each watchpoint (yes, the 4). */
1170 			if (!(sreg.s0_3 & (0x3 << (2 + (bp * 4))))) {
1171 				break;
1172 			}
1173 		}
1174 
1175 		if (bp > 5) {
1176 			/* We're out of watchpoints. */
1177 			gdb_cris_strcpy(output_buffer, error_message[E04]);
1178 			return;
1179 		}
1180 
1181 		/* Configure the control register first. */
1182 		if (type == '3' || type == '4') {
1183 			/* Trigger on read. */
1184 			sreg.s0_3 |= (1 << (2 + bp * 4));
1185 		}
1186 		if (type == '2' || type == '4') {
1187 			/* Trigger on write. */
1188 			sreg.s0_3 |= (2 << (2 + bp * 4));
1189 		}
1190 
1191 		/* Ugly pointer arithmetics to configure the watched range. */
1192 		bp_d_regs[bp * 2] = addr;
1193 		bp_d_regs[bp * 2 + 1] = (addr + len - 1);
1194 	}
1195 
1196 	/* Set the S1 flag to enable watchpoints. */
1197 	reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
1198 	gdb_cris_strcpy(output_buffer, "OK");
1199 }
1200 
remove_watchpoint(char type,int addr,int len)1201 static void remove_watchpoint(char type, int addr, int len)
1202 {
1203 	/* Breakpoint/watchpoint types:
1204 	   0 = memory breakpoint for instructions
1205 	   (not supported; done via memory write instead)
1206 	   1 = hardware breakpoint for instructions (supported)
1207 	   2 = write watchpoint (supported)
1208 	   3 = read watchpoint (supported)
1209 	   4 = access watchpoint (supported) */
1210 	if (type < '1' || type > '4') {
1211 		output_buffer[0] = 0;
1212 		return;
1213 	}
1214 
1215 	/* Read watchpoints are set as access watchpoints, because of GDB's
1216 	   inability to deal with pure read watchpoints. */
1217 	if (type == '3')
1218 		type = '4';
1219 
1220 	if (type == '1') {
1221 		/* Hardware breakpoint. */
1222 		/* Bit 0 in BP_CTRL holds the configuration for I0. */
1223 		if (!(sreg.s0_3 & 0x1)) {
1224 			/* Not in use. */
1225 			gdb_cris_strcpy(output_buffer, error_message[E04]);
1226 			return;
1227 		}
1228 		/* Deconfigure. */
1229 		sreg.s1_3 = 0;
1230 		sreg.s2_3 = 0;
1231 		sreg.s0_3 &= ~1;
1232 	} else {
1233 		int bp;
1234 		unsigned int *bp_d_regs = &sreg.s3_3;
1235 		/* Try to find a watchpoint that is configured for the
1236 		   specified range, then check that read/write also matches. */
1237 
1238 		/* Ugly pointer arithmetic, since I cannot rely on a
1239 		   single switch (addr) as there may be several watchpoints with
1240 		   the same start address for example. */
1241 
1242 		for (bp = 0; bp < 6; bp++) {
1243 			if (bp_d_regs[bp * 2] == addr &&
1244 			    bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
1245 				/* Matching range. */
1246 				int bitpos = 2 + bp * 4;
1247 				int rw_bits;
1248 
1249 				/* Read/write bits for this BP. */
1250 				rw_bits = (sreg.s0_3 & (0x3 << bitpos)) >> bitpos;
1251 
1252 				if ((type == '3' && rw_bits == 0x1) ||
1253 				    (type == '2' && rw_bits == 0x2) ||
1254 				    (type == '4' && rw_bits == 0x3)) {
1255 					/* Read/write matched. */
1256 					break;
1257 				}
1258 			}
1259 		}
1260 
1261 		if (bp > 5) {
1262 			/* No watchpoint matched. */
1263 			gdb_cris_strcpy(output_buffer, error_message[E04]);
1264 			return;
1265 		}
1266 
1267 		/* Found a matching watchpoint. Now, deconfigure it by
1268 		   both disabling read/write in bp_ctrl and zeroing its
1269 		   start/end addresses. */
1270 		sreg.s0_3 &= ~(3 << (2 + (bp * 4)));
1271 		bp_d_regs[bp * 2] = 0;
1272 		bp_d_regs[bp * 2 + 1] = 0;
1273 	}
1274 
1275 	/* Note that we don't clear the S1 flag here. It's done when continuing.  */
1276 	gdb_cris_strcpy(output_buffer, "OK");
1277 }
1278 
1279 
1280 
1281 /* All expected commands are sent from remote.c. Send a response according
1282    to the description in remote.c. */
1283 void
handle_exception(int sigval)1284 handle_exception(int sigval)
1285 {
1286 	/* Avoid warning of not used. */
1287 
1288 	USEDFUN(handle_exception);
1289 	USEDVAR(internal_stack[0]);
1290 
1291 	register_fixup(sigval);
1292 
1293 	/* Send response. */
1294 	stub_is_stopped(sigval);
1295 
1296 	for (;;) {
1297 		output_buffer[0] = '\0';
1298 		getpacket(input_buffer);
1299 		switch (input_buffer[0]) {
1300 			case 'g':
1301 				/* Read registers: g
1302 				   Success: Each byte of register data is described by two hex digits.
1303 				   Registers are in the internal order for GDB, and the bytes
1304 				   in a register  are in the same order the machine uses.
1305 				   Failure: void. */
1306 			{
1307 				char *buf;
1308 				/* General and special registers. */
1309 				buf = mem2hex(output_buffer, (char *)&reg, sizeof(registers));
1310 				/* Support registers. */
1311 				/* -1 because of the null termination that mem2hex adds. */
1312 				mem2hex(buf,
1313 					(char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
1314 					16 * sizeof(unsigned int));
1315 				break;
1316 			}
1317 			case 'G':
1318 				/* Write registers. GXX..XX
1319 				   Each byte of register data  is described by two hex digits.
1320 				   Success: OK
1321 				   Failure: void. */
1322 				/* General and special registers. */
1323 				hex2mem((char *)&reg, &input_buffer[1], sizeof(registers));
1324 				/* Support registers. */
1325 				hex2mem((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
1326 					&input_buffer[1] + sizeof(registers),
1327 					16 * sizeof(unsigned int));
1328 				gdb_cris_strcpy(output_buffer, "OK");
1329 				break;
1330 
1331 			case 'P':
1332 				/* Write register. Pn...=r...
1333 				   Write register n..., hex value without 0x, with value r...,
1334 				   which contains a hex value without 0x and two hex digits
1335 				   for each byte in the register (target byte order). P1f=11223344 means
1336 				   set register 31 to 44332211.
1337 				   Success: OK
1338 				   Failure: E02, E05 */
1339 				{
1340 					char *suffix;
1341 					int regno = gdb_cris_strtol(&input_buffer[1], &suffix, 16);
1342 					int status;
1343 
1344 					status = write_register(regno, suffix+1);
1345 
1346 					switch (status) {
1347 						case E02:
1348 							/* Do not support read-only registers. */
1349 							gdb_cris_strcpy(output_buffer, error_message[E02]);
1350 							break;
1351 						case E05:
1352 							/* Do not support non-existing registers. */
1353 							gdb_cris_strcpy(output_buffer, error_message[E05]);
1354 							break;
1355 						default:
1356 							/* Valid register number. */
1357 							gdb_cris_strcpy(output_buffer, "OK");
1358 							break;
1359 					}
1360 				}
1361 				break;
1362 
1363 			case 'm':
1364 				/* Read from memory. mAA..AA,LLLL
1365 				   AA..AA is the address and LLLL is the length.
1366 				   Success: XX..XX is the memory content.  Can be fewer bytes than
1367 				   requested if only part of the data may be read. m6000120a,6c means
1368 				   retrieve 108 byte from base address 6000120a.
1369 				   Failure: void. */
1370 				{
1371                                         char *suffix;
1372 					unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
1373                                                                                                &suffix, 16);
1374 					int len = gdb_cris_strtol(suffix+1, 0, 16);
1375 
1376 					/* Bogus read (i.e. outside the kernel's
1377 					   segment)? . */
1378 					if (!((unsigned int)addr >= 0xc0000000 &&
1379 					      (unsigned int)addr < 0xd0000000))
1380 						addr = NULL;
1381 
1382                                         mem2hex(output_buffer, addr, len);
1383                                 }
1384 				break;
1385 
1386 			case 'X':
1387 				/* Write to memory. XAA..AA,LLLL:XX..XX
1388 				   AA..AA is the start address,  LLLL is the number of bytes, and
1389 				   XX..XX is the binary data.
1390 				   Success: OK
1391 				   Failure: void. */
1392 			case 'M':
1393 				/* Write to memory. MAA..AA,LLLL:XX..XX
1394 				   AA..AA is the start address,  LLLL is the number of bytes, and
1395 				   XX..XX is the hexadecimal data.
1396 				   Success: OK
1397 				   Failure: void. */
1398 				{
1399 					char *lenptr;
1400 					char *dataptr;
1401 					unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
1402 										      &lenptr, 16);
1403 					int len = gdb_cris_strtol(lenptr+1, &dataptr, 16);
1404 					if (*lenptr == ',' && *dataptr == ':') {
1405 						if (input_buffer[0] == 'M') {
1406 							hex2mem(addr, dataptr + 1, len);
1407 						} else /* X */ {
1408 							bin2mem(addr, dataptr + 1, len);
1409 						}
1410 						gdb_cris_strcpy(output_buffer, "OK");
1411 					}
1412 					else {
1413 						gdb_cris_strcpy(output_buffer, error_message[E06]);
1414 					}
1415 				}
1416 				break;
1417 
1418 			case 'c':
1419 				/* Continue execution. cAA..AA
1420 				   AA..AA is the address where execution is resumed. If AA..AA is
1421 				   omitted, resume at the present address.
1422 				   Success: return to the executing thread.
1423 				   Failure: will never know. */
1424 
1425 				if (input_buffer[1] != '\0') {
1426 					/* FIXME: Doesn't handle address argument. */
1427 					gdb_cris_strcpy(output_buffer, error_message[E04]);
1428 					break;
1429 				}
1430 
1431 				/* Before continuing, make sure everything is set up correctly. */
1432 
1433 				/* Set the SPC to some unlikely value.  */
1434 				reg.spc = 0;
1435 				/* Set the S1 flag to 0 unless some watchpoint is enabled (since setting
1436 				   S1 to 0 would also disable watchpoints). (Note that bits 26-31 in BP_CTRL
1437 				   are reserved, so don't check against those). */
1438 				if ((sreg.s0_3 & 0x3fff) == 0) {
1439 					reg.ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT));
1440 				}
1441 
1442 				return;
1443 
1444 			case 's':
1445 				/* Step. sAA..AA
1446 				   AA..AA is the address where execution is resumed. If AA..AA is
1447 				   omitted, resume at the present address. Success: return to the
1448 				   executing thread. Failure: will never know. */
1449 
1450 				if (input_buffer[1] != '\0') {
1451 					/* FIXME: Doesn't handle address argument. */
1452 					gdb_cris_strcpy(output_buffer, error_message[E04]);
1453 					break;
1454 				}
1455 
1456 				/* Set the SPC to PC, which is where we'll return
1457 				   (deduced previously). */
1458 				reg.spc = reg.pc;
1459 
1460 				/* Set the S1 (first stacked, not current) flag, which will
1461 				   kick into action when we rfe. */
1462 				reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
1463 				return;
1464 
1465                        case 'Z':
1466 
1467                                /* Insert breakpoint or watchpoint, Ztype,addr,length.
1468                                   Remote protocol says: A remote target shall return an empty string
1469                                   for an unrecognized breakpoint or watchpoint packet type. */
1470                                {
1471                                        char *lenptr;
1472                                        char *dataptr;
1473                                        int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
1474                                        int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
1475                                        char type = input_buffer[1];
1476 
1477 				       insert_watchpoint(type, addr, len);
1478                                        break;
1479                                }
1480 
1481                        case 'z':
1482                                /* Remove breakpoint or watchpoint, Ztype,addr,length.
1483                                   Remote protocol says: A remote target shall return an empty string
1484                                   for an unrecognized breakpoint or watchpoint packet type. */
1485                                {
1486                                        char *lenptr;
1487                                        char *dataptr;
1488                                        int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
1489                                        int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
1490                                        char type = input_buffer[1];
1491 
1492                                        remove_watchpoint(type, addr, len);
1493                                        break;
1494                                }
1495 
1496 
1497 			case '?':
1498 				/* The last signal which caused a stop. ?
1499 				   Success: SAA, where AA is the signal number.
1500 				   Failure: void. */
1501 				output_buffer[0] = 'S';
1502 				output_buffer[1] = hex_asc_hi(sigval);
1503 				output_buffer[2] = hex_asc_lo(sigval);
1504 				output_buffer[3] = 0;
1505 				break;
1506 
1507 			case 'D':
1508 				/* Detach from host. D
1509 				   Success: OK, and return to the executing thread.
1510 				   Failure: will never know */
1511 				putpacket("OK");
1512 				return;
1513 
1514 			case 'k':
1515 			case 'r':
1516 				/* kill request or reset request.
1517 				   Success: restart of target.
1518 				   Failure: will never know. */
1519 				kill_restart();
1520 				break;
1521 
1522 			case 'C':
1523 			case 'S':
1524 			case '!':
1525 			case 'R':
1526 			case 'd':
1527 				/* Continue with signal sig. Csig;AA..AA
1528 				   Step with signal sig. Ssig;AA..AA
1529 				   Use the extended remote protocol. !
1530 				   Restart the target system. R0
1531 				   Toggle debug flag. d
1532 				   Search backwards. tAA:PP,MM
1533 				   Not supported: E04 */
1534 
1535 				/* FIXME: What's the difference between not supported
1536 				   and ignored (below)? */
1537 				gdb_cris_strcpy(output_buffer, error_message[E04]);
1538 				break;
1539 
1540 			default:
1541 				/* The stub should ignore other request and send an empty
1542 				   response ($#<checksum>). This way we can extend the protocol and GDB
1543 				   can tell whether the stub it is talking to uses the old or the new. */
1544 				output_buffer[0] = 0;
1545 				break;
1546 		}
1547 		putpacket(output_buffer);
1548 	}
1549 }
1550 
1551 void
kgdb_init(void)1552 kgdb_init(void)
1553 {
1554 	reg_intr_vect_rw_mask intr_mask;
1555 	reg_ser_rw_intr_mask ser_intr_mask;
1556 
1557 	/* Configure the kgdb serial port. */
1558 #if defined(CONFIG_ETRAX_KGDB_PORT0)
1559 	/* Note: no shortcut registered (not handled by multiple_interrupt).
1560 	   See entry.S.  */
1561 	set_exception_vector(SER0_INTR_VECT, kgdb_handle_exception);
1562 	/* Enable the ser irq in the global config. */
1563 	intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1564 	intr_mask.ser0 = 1;
1565 	REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1566 
1567 	ser_intr_mask = REG_RD(ser, regi_ser0, rw_intr_mask);
1568 	ser_intr_mask.dav = regk_ser_yes;
1569 	REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask);
1570 #elif defined(CONFIG_ETRAX_KGDB_PORT1)
1571 	/* Note: no shortcut registered (not handled by multiple_interrupt).
1572 	   See entry.S.  */
1573 	set_exception_vector(SER1_INTR_VECT, kgdb_handle_exception);
1574 	/* Enable the ser irq in the global config. */
1575 	intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1576 	intr_mask.ser1 = 1;
1577 	REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1578 
1579 	ser_intr_mask = REG_RD(ser, regi_ser1, rw_intr_mask);
1580 	ser_intr_mask.dav = regk_ser_yes;
1581 	REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask);
1582 #elif defined(CONFIG_ETRAX_KGDB_PORT2)
1583 	/* Note: no shortcut registered (not handled by multiple_interrupt).
1584 	   See entry.S.  */
1585 	set_exception_vector(SER2_INTR_VECT, kgdb_handle_exception);
1586 	/* Enable the ser irq in the global config. */
1587 	intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1588 	intr_mask.ser2 = 1;
1589 	REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1590 
1591 	ser_intr_mask = REG_RD(ser, regi_ser2, rw_intr_mask);
1592 	ser_intr_mask.dav = regk_ser_yes;
1593 	REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask);
1594 #elif defined(CONFIG_ETRAX_KGDB_PORT3)
1595 	/* Note: no shortcut registered (not handled by multiple_interrupt).
1596 	   See entry.S.  */
1597 	set_exception_vector(SER3_INTR_VECT, kgdb_handle_exception);
1598 	/* Enable the ser irq in the global config. */
1599 	intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
1600 	intr_mask.ser3 = 1;
1601 	REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
1602 
1603 	ser_intr_mask = REG_RD(ser, regi_ser3, rw_intr_mask);
1604 	ser_intr_mask.dav = regk_ser_yes;
1605 	REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask);
1606 #endif
1607 
1608 }
1609 /* Performs a complete re-start from scratch. */
1610 static void
kill_restart(void)1611 kill_restart(void)
1612 {
1613 	machine_restart("");
1614 }
1615 
1616 /* Use this static breakpoint in the start-up only. */
1617 
1618 void
breakpoint(void)1619 breakpoint(void)
1620 {
1621 	kgdb_started = 1;
1622 	dynamic_bp = 0;     /* This is a static, not a dynamic breakpoint. */
1623 	__asm__ volatile ("break 8"); /* Jump to kgdb_handle_breakpoint. */
1624 }
1625 
1626 /****************************** End of file **********************************/
1627