1 /*
2 * Enhanced Host Controller Interface (EHCI) driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
6 * Copyright (c) 2000-2004 by David Brownell
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/dmapool.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/vmalloc.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/ktime.h>
35 #include <linux/list.h>
36 #include <linux/interrupt.h>
37 #include <linux/usb.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/moduleparam.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/debugfs.h>
42 #include <linux/slab.h>
43 #include <linux/uaccess.h>
44
45 #include <asm/byteorder.h>
46 #include <asm/io.h>
47 #include <asm/irq.h>
48 #include <asm/unaligned.h>
49
50 #if defined(CONFIG_PPC_PS3)
51 #include <asm/firmware.h>
52 #endif
53
54 /*-------------------------------------------------------------------------*/
55
56 /*
57 * EHCI hc_driver implementation ... experimental, incomplete.
58 * Based on the final 1.0 register interface specification.
59 *
60 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
61 * First was PCMCIA, like ISA; then CardBus, which is PCI.
62 * Next comes "CardBay", using USB 2.0 signals.
63 *
64 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
65 * Special thanks to Intel and VIA for providing host controllers to
66 * test this driver on, and Cypress (including In-System Design) for
67 * providing early devices for those host controllers to talk to!
68 */
69
70 #define DRIVER_AUTHOR "David Brownell"
71 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
72
73 static const char hcd_name [] = "ehci_hcd";
74
75
76 #undef VERBOSE_DEBUG
77 #undef EHCI_URB_TRACE
78
79 #ifdef DEBUG
80 #define EHCI_STATS
81 #endif
82
83 /* magic numbers that can affect system performance */
84 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
85 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
86 #define EHCI_TUNE_RL_TT 0
87 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
88 #define EHCI_TUNE_MULT_TT 1
89 /*
90 * Some drivers think it's safe to schedule isochronous transfers more than
91 * 256 ms into the future (partly as a result of an old bug in the scheduling
92 * code). In an attempt to avoid trouble, we will use a minimum scheduling
93 * length of 512 frames instead of 256.
94 */
95 #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
96
97 #define EHCI_IAA_MSECS 10 /* arbitrary */
98 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
99 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
100 #define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1)
101 /* 5-ms async qh unlink delay */
102
103 /* Initial IRQ latency: faster than hw default */
104 static int log2_irq_thresh = 0; // 0 to 6
105 module_param (log2_irq_thresh, int, S_IRUGO);
106 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
107
108 /* initial park setting: slower than hw default */
109 static unsigned park = 0;
110 module_param (park, uint, S_IRUGO);
111 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
112
113 /* for flakey hardware, ignore overcurrent indicators */
114 static bool ignore_oc = 0;
115 module_param (ignore_oc, bool, S_IRUGO);
116 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
117
118 /* for link power management(LPM) feature */
119 static unsigned int hird;
120 module_param(hird, int, S_IRUGO);
121 MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us");
122
123 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
124
125 /*-------------------------------------------------------------------------*/
126
127 #include "ehci.h"
128 #include "ehci-dbg.c"
129 #include "pci-quirks.h"
130
131 /*-------------------------------------------------------------------------*/
132
133 static void
timer_action(struct ehci_hcd * ehci,enum ehci_timer_action action)134 timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
135 {
136 /* Don't override timeouts which shrink or (later) disable
137 * the async ring; just the I/O watchdog. Note that if a
138 * SHRINK were pending, OFF would never be requested.
139 */
140 if (timer_pending(&ehci->watchdog)
141 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
142 & ehci->actions))
143 return;
144
145 if (!test_and_set_bit(action, &ehci->actions)) {
146 unsigned long t;
147
148 switch (action) {
149 case TIMER_IO_WATCHDOG:
150 if (!ehci->need_io_watchdog)
151 return;
152 t = EHCI_IO_JIFFIES;
153 break;
154 case TIMER_ASYNC_OFF:
155 t = EHCI_ASYNC_JIFFIES;
156 break;
157 /* case TIMER_ASYNC_SHRINK: */
158 default:
159 t = EHCI_SHRINK_JIFFIES;
160 break;
161 }
162 mod_timer(&ehci->watchdog, t + jiffies);
163 }
164 }
165
166 /*-------------------------------------------------------------------------*/
167
168 /*
169 * handshake - spin reading hc until handshake completes or fails
170 * @ptr: address of hc register to be read
171 * @mask: bits to look at in result of read
172 * @done: value of those bits when handshake succeeds
173 * @usec: timeout in microseconds
174 *
175 * Returns negative errno, or zero on success
176 *
177 * Success happens when the "mask" bits have the specified value (hardware
178 * handshake done). There are two failure modes: "usec" have passed (major
179 * hardware flakeout), or the register reads as all-ones (hardware removed).
180 *
181 * That last failure should_only happen in cases like physical cardbus eject
182 * before driver shutdown. But it also seems to be caused by bugs in cardbus
183 * bridge shutdown: shutting down the bridge before the devices using it.
184 */
handshake(struct ehci_hcd * ehci,void __iomem * ptr,u32 mask,u32 done,int usec)185 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
186 u32 mask, u32 done, int usec)
187 {
188 u32 result;
189
190 do {
191 result = ehci_readl(ehci, ptr);
192 if (result == ~(u32)0) /* card removed */
193 return -ENODEV;
194 result &= mask;
195 if (result == done)
196 return 0;
197 udelay (1);
198 usec--;
199 } while (usec > 0);
200 return -ETIMEDOUT;
201 }
202
203 /* check TDI/ARC silicon is in host mode */
tdi_in_host_mode(struct ehci_hcd * ehci)204 static int tdi_in_host_mode (struct ehci_hcd *ehci)
205 {
206 u32 __iomem *reg_ptr;
207 u32 tmp;
208
209 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
210 tmp = ehci_readl(ehci, reg_ptr);
211 return (tmp & 3) == USBMODE_CM_HC;
212 }
213
214 /* force HC to halt state from unknown (EHCI spec section 2.3) */
ehci_halt(struct ehci_hcd * ehci)215 static int ehci_halt (struct ehci_hcd *ehci)
216 {
217 u32 temp = ehci_readl(ehci, &ehci->regs->status);
218
219 /* disable any irqs left enabled by previous code */
220 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
221
222 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) {
223 return 0;
224 }
225
226 if ((temp & STS_HALT) != 0)
227 return 0;
228
229 temp = ehci_readl(ehci, &ehci->regs->command);
230 temp &= ~CMD_RUN;
231 ehci_writel(ehci, temp, &ehci->regs->command);
232 return handshake (ehci, &ehci->regs->status,
233 STS_HALT, STS_HALT, 16 * 125);
234 }
235
236 #if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_PPC_PS3)
237
238 /*
239 * The EHCI controller of the Cell Super Companion Chip used in the
240 * PS3 will stop the root hub after all root hub ports are suspended.
241 * When in this condition handshake will return -ETIMEDOUT. The
242 * STS_HLT bit will not be set, so inspection of the frame index is
243 * used here to test for the condition. If the condition is found
244 * return success to allow the USB suspend to complete.
245 */
246
handshake_for_broken_root_hub(struct ehci_hcd * ehci,void __iomem * ptr,u32 mask,u32 done,int usec)247 static int handshake_for_broken_root_hub(struct ehci_hcd *ehci,
248 void __iomem *ptr, u32 mask, u32 done,
249 int usec)
250 {
251 unsigned int old_index;
252 int error;
253
254 if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
255 return -ETIMEDOUT;
256
257 old_index = ehci_read_frame_index(ehci);
258
259 error = handshake(ehci, ptr, mask, done, usec);
260
261 if (error == -ETIMEDOUT && ehci_read_frame_index(ehci) == old_index)
262 return 0;
263
264 return error;
265 }
266
267 #else
268
handshake_for_broken_root_hub(struct ehci_hcd * ehci,void __iomem * ptr,u32 mask,u32 done,int usec)269 static int handshake_for_broken_root_hub(struct ehci_hcd *ehci,
270 void __iomem *ptr, u32 mask, u32 done,
271 int usec)
272 {
273 return -ETIMEDOUT;
274 }
275
276 #endif
277
handshake_on_error_set_halt(struct ehci_hcd * ehci,void __iomem * ptr,u32 mask,u32 done,int usec)278 static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
279 u32 mask, u32 done, int usec)
280 {
281 int error;
282
283 error = handshake(ehci, ptr, mask, done, usec);
284 if (error == -ETIMEDOUT)
285 error = handshake_for_broken_root_hub(ehci, ptr, mask, done,
286 usec);
287
288 if (error) {
289 ehci_halt(ehci);
290 ehci->rh_state = EHCI_RH_HALTED;
291 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n",
292 ptr, mask, done, error);
293 }
294
295 return error;
296 }
297
298 /* put TDI/ARC silicon into EHCI mode */
tdi_reset(struct ehci_hcd * ehci)299 static void tdi_reset (struct ehci_hcd *ehci)
300 {
301 u32 __iomem *reg_ptr;
302 u32 tmp;
303
304 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
305 tmp = ehci_readl(ehci, reg_ptr);
306 tmp |= USBMODE_CM_HC;
307 /* The default byte access to MMR space is LE after
308 * controller reset. Set the required endian mode
309 * for transfer buffers to match the host microprocessor
310 */
311 if (ehci_big_endian_mmio(ehci))
312 tmp |= USBMODE_BE;
313 ehci_writel(ehci, tmp, reg_ptr);
314 }
315
316 /* reset a non-running (STS_HALT == 1) controller */
ehci_reset(struct ehci_hcd * ehci)317 static int ehci_reset (struct ehci_hcd *ehci)
318 {
319 int retval;
320 u32 command = ehci_readl(ehci, &ehci->regs->command);
321
322 /* If the EHCI debug controller is active, special care must be
323 * taken before and after a host controller reset */
324 if (ehci->debug && !dbgp_reset_prep())
325 ehci->debug = NULL;
326
327 command |= CMD_RESET;
328 dbg_cmd (ehci, "reset", command);
329 ehci_writel(ehci, command, &ehci->regs->command);
330 ehci->rh_state = EHCI_RH_HALTED;
331 ehci->next_statechange = jiffies;
332 retval = handshake (ehci, &ehci->regs->command,
333 CMD_RESET, 0, 250 * 1000);
334
335 if (ehci->has_hostpc) {
336 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
337 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX));
338 ehci_writel(ehci, TXFIFO_DEFAULT,
339 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));
340 }
341 if (retval)
342 return retval;
343
344 if (ehci_is_TDI(ehci))
345 tdi_reset (ehci);
346
347 if (ehci->debug)
348 dbgp_external_startup();
349
350 ehci->port_c_suspend = ehci->suspended_ports =
351 ehci->resuming_ports = 0;
352 return retval;
353 }
354
355 /* idle the controller (from running) */
ehci_quiesce(struct ehci_hcd * ehci)356 static void ehci_quiesce (struct ehci_hcd *ehci)
357 {
358 u32 temp;
359
360 #ifdef DEBUG
361 if (ehci->rh_state != EHCI_RH_RUNNING)
362 BUG ();
363 #endif
364
365 /* wait for any schedule enables/disables to take effect */
366 temp = ehci_readl(ehci, &ehci->regs->command) << 10;
367 temp &= STS_ASS | STS_PSS;
368 if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
369 STS_ASS | STS_PSS, temp, 16 * 125))
370 return;
371
372 /* then disable anything that's still active */
373 temp = ehci_readl(ehci, &ehci->regs->command);
374 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
375 ehci_writel(ehci, temp, &ehci->regs->command);
376
377 /* hardware can take 16 microframes to turn off ... */
378 handshake_on_error_set_halt(ehci, &ehci->regs->status,
379 STS_ASS | STS_PSS, 0, 16 * 125);
380 }
381
382 /*-------------------------------------------------------------------------*/
383
384 static void end_unlink_async(struct ehci_hcd *ehci);
385 static void ehci_work(struct ehci_hcd *ehci);
386
387 #include "ehci-hub.c"
388 #include "ehci-lpm.c"
389 #include "ehci-mem.c"
390 #include "ehci-q.c"
391 #include "ehci-sched.c"
392 #include "ehci-sysfs.c"
393
394 /*-------------------------------------------------------------------------*/
395
ehci_iaa_watchdog(unsigned long param)396 static void ehci_iaa_watchdog(unsigned long param)
397 {
398 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
399 unsigned long flags;
400
401 spin_lock_irqsave (&ehci->lock, flags);
402
403 /* Lost IAA irqs wedge things badly; seen first with a vt8235.
404 * So we need this watchdog, but must protect it against both
405 * (a) SMP races against real IAA firing and retriggering, and
406 * (b) clean HC shutdown, when IAA watchdog was pending.
407 */
408 if (ehci->reclaim
409 && !timer_pending(&ehci->iaa_watchdog)
410 && ehci->rh_state == EHCI_RH_RUNNING) {
411 u32 cmd, status;
412
413 /* If we get here, IAA is *REALLY* late. It's barely
414 * conceivable that the system is so busy that CMD_IAAD
415 * is still legitimately set, so let's be sure it's
416 * clear before we read STS_IAA. (The HC should clear
417 * CMD_IAAD when it sets STS_IAA.)
418 */
419 cmd = ehci_readl(ehci, &ehci->regs->command);
420 if (cmd & CMD_IAAD)
421 ehci_writel(ehci, cmd & ~CMD_IAAD,
422 &ehci->regs->command);
423
424 /* If IAA is set here it either legitimately triggered
425 * before we cleared IAAD above (but _way_ late, so we'll
426 * still count it as lost) ... or a silicon erratum:
427 * - VIA seems to set IAA without triggering the IRQ;
428 * - IAAD potentially cleared without setting IAA.
429 */
430 status = ehci_readl(ehci, &ehci->regs->status);
431 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
432 COUNT (ehci->stats.lost_iaa);
433 ehci_writel(ehci, STS_IAA, &ehci->regs->status);
434 }
435
436 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
437 status, cmd);
438 end_unlink_async(ehci);
439 }
440
441 spin_unlock_irqrestore(&ehci->lock, flags);
442 }
443
ehci_watchdog(unsigned long param)444 static void ehci_watchdog(unsigned long param)
445 {
446 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
447 unsigned long flags;
448
449 spin_lock_irqsave(&ehci->lock, flags);
450
451 /* stop async processing after it's idled a bit */
452 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
453 start_unlink_async (ehci, ehci->async);
454
455 /* ehci could run by timer, without IRQs ... */
456 ehci_work (ehci);
457
458 spin_unlock_irqrestore (&ehci->lock, flags);
459 }
460
461 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
462 * The firmware seems to think that powering off is a wakeup event!
463 * This routine turns off remote wakeup and everything else, on all ports.
464 */
ehci_turn_off_all_ports(struct ehci_hcd * ehci)465 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
466 {
467 int port = HCS_N_PORTS(ehci->hcs_params);
468
469 while (port--)
470 ehci_writel(ehci, PORT_RWC_BITS,
471 &ehci->regs->port_status[port]);
472 }
473
474 /*
475 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
476 * Should be called with ehci->lock held.
477 */
ehci_silence_controller(struct ehci_hcd * ehci)478 static void ehci_silence_controller(struct ehci_hcd *ehci)
479 {
480 ehci_halt(ehci);
481 ehci_turn_off_all_ports(ehci);
482
483 /* make BIOS/etc use companion controller during reboot */
484 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
485
486 /* unblock posted writes */
487 ehci_readl(ehci, &ehci->regs->configured_flag);
488 }
489
490 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
491 * This forcibly disables dma and IRQs, helping kexec and other cases
492 * where the next system software may expect clean state.
493 */
ehci_shutdown(struct usb_hcd * hcd)494 static void ehci_shutdown(struct usb_hcd *hcd)
495 {
496 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
497
498 del_timer_sync(&ehci->watchdog);
499 del_timer_sync(&ehci->iaa_watchdog);
500
501 spin_lock_irq(&ehci->lock);
502 ehci_silence_controller(ehci);
503 spin_unlock_irq(&ehci->lock);
504 }
505
ehci_port_power(struct ehci_hcd * ehci,int is_on)506 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
507 {
508 unsigned port;
509
510 if (!HCS_PPC (ehci->hcs_params))
511 return;
512
513 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
514 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
515 (void) ehci_hub_control(ehci_to_hcd(ehci),
516 is_on ? SetPortFeature : ClearPortFeature,
517 USB_PORT_FEAT_POWER,
518 port--, NULL, 0);
519 /* Flush those writes */
520 ehci_readl(ehci, &ehci->regs->command);
521 msleep(20);
522 }
523
524 /*-------------------------------------------------------------------------*/
525
526 /*
527 * ehci_work is called from some interrupts, timers, and so on.
528 * it calls driver completion functions, after dropping ehci->lock.
529 */
ehci_work(struct ehci_hcd * ehci)530 static void ehci_work (struct ehci_hcd *ehci)
531 {
532 timer_action_done (ehci, TIMER_IO_WATCHDOG);
533
534 /* another CPU may drop ehci->lock during a schedule scan while
535 * it reports urb completions. this flag guards against bogus
536 * attempts at re-entrant schedule scanning.
537 */
538 if (ehci->scanning)
539 return;
540 ehci->scanning = 1;
541 scan_async (ehci);
542 if (ehci->next_uframe != -1)
543 scan_periodic (ehci);
544 ehci->scanning = 0;
545
546 /* the IO watchdog guards against hardware or driver bugs that
547 * misplace IRQs, and should let us run completely without IRQs.
548 * such lossage has been observed on both VT6202 and VT8235.
549 */
550 if (ehci->rh_state == EHCI_RH_RUNNING &&
551 (ehci->async->qh_next.ptr != NULL ||
552 ehci->periodic_sched != 0))
553 timer_action (ehci, TIMER_IO_WATCHDOG);
554 }
555
556 /*
557 * Called when the ehci_hcd module is removed.
558 */
ehci_stop(struct usb_hcd * hcd)559 static void ehci_stop (struct usb_hcd *hcd)
560 {
561 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
562
563 ehci_dbg (ehci, "stop\n");
564
565 /* no more interrupts ... */
566 del_timer_sync (&ehci->watchdog);
567 del_timer_sync(&ehci->iaa_watchdog);
568
569 spin_lock_irq(&ehci->lock);
570 if (ehci->rh_state == EHCI_RH_RUNNING)
571 ehci_quiesce (ehci);
572
573 ehci_silence_controller(ehci);
574 ehci_reset (ehci);
575 spin_unlock_irq(&ehci->lock);
576
577 remove_sysfs_files(ehci);
578 remove_debug_files (ehci);
579
580 /* root hub is shut down separately (first, when possible) */
581 spin_lock_irq (&ehci->lock);
582 if (ehci->async)
583 ehci_work (ehci);
584 spin_unlock_irq (&ehci->lock);
585 ehci_mem_cleanup (ehci);
586
587 if (ehci->amd_pll_fix == 1)
588 usb_amd_dev_put();
589
590 #ifdef EHCI_STATS
591 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
592 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
593 ehci->stats.lost_iaa);
594 ehci_dbg (ehci, "complete %ld unlink %ld\n",
595 ehci->stats.complete, ehci->stats.unlink);
596 #endif
597
598 dbg_status (ehci, "ehci_stop completed",
599 ehci_readl(ehci, &ehci->regs->status));
600 }
601
602 /* one-time init, only for memory state */
ehci_init(struct usb_hcd * hcd)603 static int ehci_init(struct usb_hcd *hcd)
604 {
605 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
606 u32 temp;
607 int retval;
608 u32 hcc_params;
609 struct ehci_qh_hw *hw;
610
611 spin_lock_init(&ehci->lock);
612
613 /*
614 * keep io watchdog by default, those good HCDs could turn off it later
615 */
616 ehci->need_io_watchdog = 1;
617 init_timer(&ehci->watchdog);
618 ehci->watchdog.function = ehci_watchdog;
619 ehci->watchdog.data = (unsigned long) ehci;
620
621 init_timer(&ehci->iaa_watchdog);
622 ehci->iaa_watchdog.function = ehci_iaa_watchdog;
623 ehci->iaa_watchdog.data = (unsigned long) ehci;
624
625 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
626
627 /*
628 * by default set standard 80% (== 100 usec/uframe) max periodic
629 * bandwidth as required by USB 2.0
630 */
631 ehci->uframe_periodic_max = 100;
632
633 /*
634 * hw default: 1K periodic list heads, one per frame.
635 * periodic_size can shrink by USBCMD update if hcc_params allows.
636 */
637 ehci->periodic_size = DEFAULT_I_TDPS;
638 INIT_LIST_HEAD(&ehci->cached_itd_list);
639 INIT_LIST_HEAD(&ehci->cached_sitd_list);
640
641 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
642 /* periodic schedule size can be smaller than default */
643 switch (EHCI_TUNE_FLS) {
644 case 0: ehci->periodic_size = 1024; break;
645 case 1: ehci->periodic_size = 512; break;
646 case 2: ehci->periodic_size = 256; break;
647 default: BUG();
648 }
649 }
650 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
651 return retval;
652
653 /* controllers may cache some of the periodic schedule ... */
654 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
655 ehci->i_thresh = 2 + 8;
656 else // N microframes cached
657 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
658
659 ehci->reclaim = NULL;
660 ehci->next_uframe = -1;
661 ehci->clock_frame = -1;
662
663 /*
664 * dedicate a qh for the async ring head, since we couldn't unlink
665 * a 'real' qh without stopping the async schedule [4.8]. use it
666 * as the 'reclamation list head' too.
667 * its dummy is used in hw_alt_next of many tds, to prevent the qh
668 * from automatically advancing to the next td after short reads.
669 */
670 ehci->async->qh_next.qh = NULL;
671 hw = ehci->async->hw;
672 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
673 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
674 #if defined(CONFIG_PPC_PS3)
675 hw->hw_info1 |= cpu_to_hc32(ehci, (1 << 7)); /* I = 1 */
676 #endif
677 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
678 hw->hw_qtd_next = EHCI_LIST_END(ehci);
679 ehci->async->qh_state = QH_STATE_LINKED;
680 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
681
682 /* clear interrupt enables, set irq latency */
683 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
684 log2_irq_thresh = 0;
685 temp = 1 << (16 + log2_irq_thresh);
686 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
687 ehci->has_ppcd = 1;
688 ehci_dbg(ehci, "enable per-port change event\n");
689 temp |= CMD_PPCEE;
690 }
691 if (HCC_CANPARK(hcc_params)) {
692 /* HW default park == 3, on hardware that supports it (like
693 * NVidia and ALI silicon), maximizes throughput on the async
694 * schedule by avoiding QH fetches between transfers.
695 *
696 * With fast usb storage devices and NForce2, "park" seems to
697 * make problems: throughput reduction (!), data errors...
698 */
699 if (park) {
700 park = min(park, (unsigned) 3);
701 temp |= CMD_PARK;
702 temp |= park << 8;
703 }
704 ehci_dbg(ehci, "park %d\n", park);
705 }
706 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
707 /* periodic schedule size can be smaller than default */
708 temp &= ~(3 << 2);
709 temp |= (EHCI_TUNE_FLS << 2);
710 }
711 if (HCC_LPM(hcc_params)) {
712 /* support link power management EHCI 1.1 addendum */
713 ehci_dbg(ehci, "support lpm\n");
714 ehci->has_lpm = 1;
715 if (hird > 0xf) {
716 ehci_dbg(ehci, "hird %d invalid, use default 0",
717 hird);
718 hird = 0;
719 }
720 temp |= hird << 24;
721 }
722 ehci->command = temp;
723
724 /* Accept arbitrarily long scatter-gather lists */
725 if (!(hcd->driver->flags & HCD_LOCAL_MEM))
726 hcd->self.sg_tablesize = ~0;
727 return 0;
728 }
729
730 /* start HC running; it's halted, ehci_init() has been run (once) */
ehci_run(struct usb_hcd * hcd)731 static int ehci_run (struct usb_hcd *hcd)
732 {
733 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
734 u32 temp;
735 u32 hcc_params;
736
737 hcd->uses_new_polling = 1;
738
739 /* EHCI spec section 4.1 */
740
741 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
742 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
743
744 /*
745 * hcc_params controls whether ehci->regs->segment must (!!!)
746 * be used; it constrains QH/ITD/SITD and QTD locations.
747 * pci_pool consistent memory always uses segment zero.
748 * streaming mappings for I/O buffers, like pci_map_single(),
749 * can return segments above 4GB, if the device allows.
750 *
751 * NOTE: the dma mask is visible through dma_supported(), so
752 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
753 * Scsi_Host.highmem_io, and so forth. It's readonly to all
754 * host side drivers though.
755 */
756 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
757 if (HCC_64BIT_ADDR(hcc_params)) {
758 ehci_writel(ehci, 0, &ehci->regs->segment);
759 #if 0
760 // this is deeply broken on almost all architectures
761 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
762 ehci_info(ehci, "enabled 64bit DMA\n");
763 #endif
764 }
765
766
767 // Philips, Intel, and maybe others need CMD_RUN before the
768 // root hub will detect new devices (why?); NEC doesn't
769 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
770 ehci->command |= CMD_RUN;
771 ehci_writel(ehci, ehci->command, &ehci->regs->command);
772 dbg_cmd (ehci, "init", ehci->command);
773
774 /*
775 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
776 * are explicitly handed to companion controller(s), so no TT is
777 * involved with the root hub. (Except where one is integrated,
778 * and there's no companion controller unless maybe for USB OTG.)
779 *
780 * Turning on the CF flag will transfer ownership of all ports
781 * from the companions to the EHCI controller. If any of the
782 * companions are in the middle of a port reset at the time, it
783 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
784 * guarantees that no resets are in progress. After we set CF,
785 * a short delay lets the hardware catch up; new resets shouldn't
786 * be started before the port switching actions could complete.
787 */
788 down_write(&ehci_cf_port_reset_rwsem);
789 ehci->rh_state = EHCI_RH_RUNNING;
790 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
791 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
792 msleep(5);
793 up_write(&ehci_cf_port_reset_rwsem);
794 ehci->last_periodic_enable = ktime_get_real();
795
796 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
797 ehci_info (ehci,
798 "USB %x.%x started, EHCI %x.%02x%s\n",
799 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
800 temp >> 8, temp & 0xff,
801 ignore_oc ? ", overcurrent ignored" : "");
802
803 ehci_writel(ehci, INTR_MASK,
804 &ehci->regs->intr_enable); /* Turn On Interrupts */
805
806 /* GRR this is run-once init(), being done every time the HC starts.
807 * So long as they're part of class devices, we can't do it init()
808 * since the class device isn't created that early.
809 */
810 create_debug_files(ehci);
811 create_sysfs_files(ehci);
812
813 return 0;
814 }
815
ehci_setup(struct usb_hcd * hcd)816 static int __maybe_unused ehci_setup (struct usb_hcd *hcd)
817 {
818 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
819 int retval;
820
821 ehci->regs = (void __iomem *)ehci->caps +
822 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
823 dbg_hcs_params(ehci, "reset");
824 dbg_hcc_params(ehci, "reset");
825
826 /* cache this readonly data; minimize chip reads */
827 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
828
829 ehci->sbrn = HCD_USB2;
830
831 retval = ehci_halt(ehci);
832 if (retval)
833 return retval;
834
835 /* data structure init */
836 retval = ehci_init(hcd);
837 if (retval)
838 return retval;
839
840 ehci_reset(ehci);
841
842 return 0;
843 }
844
845 /*-------------------------------------------------------------------------*/
846
ehci_irq(struct usb_hcd * hcd)847 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
848 {
849 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
850 u32 status, masked_status, pcd_status = 0, cmd;
851 int bh;
852
853 spin_lock (&ehci->lock);
854
855 status = ehci_readl(ehci, &ehci->regs->status);
856
857 /* e.g. cardbus physical eject */
858 if (status == ~(u32) 0) {
859 ehci_dbg (ehci, "device removed\n");
860 goto dead;
861 }
862
863 /*
864 * We don't use STS_FLR, but some controllers don't like it to
865 * remain on, so mask it out along with the other status bits.
866 */
867 masked_status = status & (INTR_MASK | STS_FLR);
868
869 /* Shared IRQ? */
870 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
871 spin_unlock(&ehci->lock);
872 return IRQ_NONE;
873 }
874
875 /* clear (just) interrupts */
876 ehci_writel(ehci, masked_status, &ehci->regs->status);
877 cmd = ehci_readl(ehci, &ehci->regs->command);
878 bh = 0;
879
880 #ifdef VERBOSE_DEBUG
881 /* unrequested/ignored: Frame List Rollover */
882 dbg_status (ehci, "irq", status);
883 #endif
884
885 /* INT, ERR, and IAA interrupt rates can be throttled */
886
887 /* normal [4.15.1.2] or error [4.15.1.1] completion */
888 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
889 if (likely ((status & STS_ERR) == 0))
890 COUNT (ehci->stats.normal);
891 else
892 COUNT (ehci->stats.error);
893 bh = 1;
894 }
895
896 /* complete the unlinking of some qh [4.15.2.3] */
897 if (status & STS_IAA) {
898 /* guard against (alleged) silicon errata */
899 if (cmd & CMD_IAAD) {
900 ehci_writel(ehci, cmd & ~CMD_IAAD,
901 &ehci->regs->command);
902 ehci_dbg(ehci, "IAA with IAAD still set?\n");
903 }
904 if (ehci->reclaim) {
905 COUNT(ehci->stats.reclaim);
906 end_unlink_async(ehci);
907 } else
908 ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
909 }
910
911 /* remote wakeup [4.3.1] */
912 if (status & STS_PCD) {
913 unsigned i = HCS_N_PORTS (ehci->hcs_params);
914 u32 ppcd = 0;
915
916 /* kick root hub later */
917 pcd_status = status;
918
919 /* resume root hub? */
920 if (ehci->rh_state == EHCI_RH_SUSPENDED)
921 usb_hcd_resume_root_hub(hcd);
922
923 /* get per-port change detect bits */
924 if (ehci->has_ppcd)
925 ppcd = status >> 16;
926
927 while (i--) {
928 int pstatus;
929
930 /* leverage per-port change bits feature */
931 if (ehci->has_ppcd && !(ppcd & (1 << i)))
932 continue;
933 pstatus = ehci_readl(ehci,
934 &ehci->regs->port_status[i]);
935
936 if (pstatus & PORT_OWNER)
937 continue;
938 if (!(test_bit(i, &ehci->suspended_ports) &&
939 ((pstatus & PORT_RESUME) ||
940 !(pstatus & PORT_SUSPEND)) &&
941 (pstatus & PORT_PE) &&
942 ehci->reset_done[i] == 0))
943 continue;
944
945 /* start 20 msec resume signaling from this port,
946 * and make khubd collect PORT_STAT_C_SUSPEND to
947 * stop that signaling. Use 5 ms extra for safety,
948 * like usb_port_resume() does.
949 */
950 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
951 set_bit(i, &ehci->resuming_ports);
952 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
953 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
954 }
955 }
956
957 /* PCI errors [4.15.2.4] */
958 if (unlikely ((status & STS_FATAL) != 0)) {
959 ehci_err(ehci, "fatal error\n");
960 dbg_cmd(ehci, "fatal", cmd);
961 dbg_status(ehci, "fatal", status);
962 ehci_halt(ehci);
963 dead:
964 ehci_reset(ehci);
965 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
966 usb_hc_died(hcd);
967 /* generic layer kills/unlinks all urbs, then
968 * uses ehci_stop to clean up the rest
969 */
970 bh = 1;
971 }
972
973 if (bh)
974 ehci_work (ehci);
975 spin_unlock (&ehci->lock);
976 if (pcd_status)
977 usb_hcd_poll_rh_status(hcd);
978 return IRQ_HANDLED;
979 }
980
981 /*-------------------------------------------------------------------------*/
982
983 /*
984 * non-error returns are a promise to giveback() the urb later
985 * we drop ownership so next owner (or urb unlink) can get it
986 *
987 * urb + dev is in hcd.self.controller.urb_list
988 * we're queueing TDs onto software and hardware lists
989 *
990 * hcd-specific init for hcpriv hasn't been done yet
991 *
992 * NOTE: control, bulk, and interrupt share the same code to append TDs
993 * to a (possibly active) QH, and the same QH scanning code.
994 */
ehci_urb_enqueue(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)995 static int ehci_urb_enqueue (
996 struct usb_hcd *hcd,
997 struct urb *urb,
998 gfp_t mem_flags
999 ) {
1000 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1001 struct list_head qtd_list;
1002
1003 INIT_LIST_HEAD (&qtd_list);
1004
1005 switch (usb_pipetype (urb->pipe)) {
1006 case PIPE_CONTROL:
1007 /* qh_completions() code doesn't handle all the fault cases
1008 * in multi-TD control transfers. Even 1KB is rare anyway.
1009 */
1010 if (urb->transfer_buffer_length > (16 * 1024))
1011 return -EMSGSIZE;
1012 /* FALLTHROUGH */
1013 /* case PIPE_BULK: */
1014 default:
1015 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1016 return -ENOMEM;
1017 return submit_async(ehci, urb, &qtd_list, mem_flags);
1018
1019 case PIPE_INTERRUPT:
1020 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1021 return -ENOMEM;
1022 return intr_submit(ehci, urb, &qtd_list, mem_flags);
1023
1024 case PIPE_ISOCHRONOUS:
1025 if (urb->dev->speed == USB_SPEED_HIGH)
1026 return itd_submit (ehci, urb, mem_flags);
1027 else
1028 return sitd_submit (ehci, urb, mem_flags);
1029 }
1030 }
1031
unlink_async(struct ehci_hcd * ehci,struct ehci_qh * qh)1032 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
1033 {
1034 /* failfast */
1035 if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim)
1036 end_unlink_async(ehci);
1037
1038 /* If the QH isn't linked then there's nothing we can do
1039 * unless we were called during a giveback, in which case
1040 * qh_completions() has to deal with it.
1041 */
1042 if (qh->qh_state != QH_STATE_LINKED) {
1043 if (qh->qh_state == QH_STATE_COMPLETING)
1044 qh->needs_rescan = 1;
1045 return;
1046 }
1047
1048 /* defer till later if busy */
1049 if (ehci->reclaim) {
1050 struct ehci_qh *last;
1051
1052 for (last = ehci->reclaim;
1053 last->reclaim;
1054 last = last->reclaim)
1055 continue;
1056 qh->qh_state = QH_STATE_UNLINK_WAIT;
1057 last->reclaim = qh;
1058
1059 /* start IAA cycle */
1060 } else
1061 start_unlink_async (ehci, qh);
1062 }
1063
1064 /* remove from hardware lists
1065 * completions normally happen asynchronously
1066 */
1067
ehci_urb_dequeue(struct usb_hcd * hcd,struct urb * urb,int status)1068 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1069 {
1070 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1071 struct ehci_qh *qh;
1072 unsigned long flags;
1073 int rc;
1074
1075 spin_lock_irqsave (&ehci->lock, flags);
1076 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
1077 if (rc)
1078 goto done;
1079
1080 switch (usb_pipetype (urb->pipe)) {
1081 // case PIPE_CONTROL:
1082 // case PIPE_BULK:
1083 default:
1084 qh = (struct ehci_qh *) urb->hcpriv;
1085 if (!qh)
1086 break;
1087 switch (qh->qh_state) {
1088 case QH_STATE_LINKED:
1089 case QH_STATE_COMPLETING:
1090 unlink_async(ehci, qh);
1091 break;
1092 case QH_STATE_UNLINK:
1093 case QH_STATE_UNLINK_WAIT:
1094 /* already started */
1095 break;
1096 case QH_STATE_IDLE:
1097 /* QH might be waiting for a Clear-TT-Buffer */
1098 qh_completions(ehci, qh);
1099 break;
1100 }
1101 break;
1102
1103 case PIPE_INTERRUPT:
1104 qh = (struct ehci_qh *) urb->hcpriv;
1105 if (!qh)
1106 break;
1107 switch (qh->qh_state) {
1108 case QH_STATE_LINKED:
1109 case QH_STATE_COMPLETING:
1110 intr_deschedule (ehci, qh);
1111 break;
1112 case QH_STATE_IDLE:
1113 qh_completions (ehci, qh);
1114 break;
1115 default:
1116 ehci_dbg (ehci, "bogus qh %p state %d\n",
1117 qh, qh->qh_state);
1118 goto done;
1119 }
1120 break;
1121
1122 case PIPE_ISOCHRONOUS:
1123 // itd or sitd ...
1124
1125 // wait till next completion, do it then.
1126 // completion irqs can wait up to 1024 msec,
1127 break;
1128 }
1129 done:
1130 spin_unlock_irqrestore (&ehci->lock, flags);
1131 return rc;
1132 }
1133
1134 /*-------------------------------------------------------------------------*/
1135
1136 // bulk qh holds the data toggle
1137
1138 static void
ehci_endpoint_disable(struct usb_hcd * hcd,struct usb_host_endpoint * ep)1139 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1140 {
1141 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1142 unsigned long flags;
1143 struct ehci_qh *qh, *tmp;
1144
1145 /* ASSERT: any requests/urbs are being unlinked */
1146 /* ASSERT: nobody can be submitting urbs for this any more */
1147
1148 rescan:
1149 spin_lock_irqsave (&ehci->lock, flags);
1150 qh = ep->hcpriv;
1151 if (!qh)
1152 goto done;
1153
1154 /* endpoints can be iso streams. for now, we don't
1155 * accelerate iso completions ... so spin a while.
1156 */
1157 if (qh->hw == NULL) {
1158 ehci_vdbg (ehci, "iso delay\n");
1159 goto idle_timeout;
1160 }
1161
1162 if (ehci->rh_state != EHCI_RH_RUNNING)
1163 qh->qh_state = QH_STATE_IDLE;
1164 switch (qh->qh_state) {
1165 case QH_STATE_LINKED:
1166 case QH_STATE_COMPLETING:
1167 for (tmp = ehci->async->qh_next.qh;
1168 tmp && tmp != qh;
1169 tmp = tmp->qh_next.qh)
1170 continue;
1171 /* periodic qh self-unlinks on empty, and a COMPLETING qh
1172 * may already be unlinked.
1173 */
1174 if (tmp)
1175 unlink_async(ehci, qh);
1176 /* FALL THROUGH */
1177 case QH_STATE_UNLINK: /* wait for hw to finish? */
1178 case QH_STATE_UNLINK_WAIT:
1179 idle_timeout:
1180 spin_unlock_irqrestore (&ehci->lock, flags);
1181 schedule_timeout_uninterruptible(1);
1182 goto rescan;
1183 case QH_STATE_IDLE: /* fully unlinked */
1184 if (qh->clearing_tt)
1185 goto idle_timeout;
1186 if (list_empty (&qh->qtd_list)) {
1187 qh_put (qh);
1188 break;
1189 }
1190 /* else FALL THROUGH */
1191 default:
1192 /* caller was supposed to have unlinked any requests;
1193 * that's not our job. just leak this memory.
1194 */
1195 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1196 qh, ep->desc.bEndpointAddress, qh->qh_state,
1197 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1198 break;
1199 }
1200 ep->hcpriv = NULL;
1201 done:
1202 spin_unlock_irqrestore (&ehci->lock, flags);
1203 }
1204
1205 static void
ehci_endpoint_reset(struct usb_hcd * hcd,struct usb_host_endpoint * ep)1206 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1207 {
1208 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1209 struct ehci_qh *qh;
1210 int eptype = usb_endpoint_type(&ep->desc);
1211 int epnum = usb_endpoint_num(&ep->desc);
1212 int is_out = usb_endpoint_dir_out(&ep->desc);
1213 unsigned long flags;
1214
1215 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1216 return;
1217
1218 spin_lock_irqsave(&ehci->lock, flags);
1219 qh = ep->hcpriv;
1220
1221 /* For Bulk and Interrupt endpoints we maintain the toggle state
1222 * in the hardware; the toggle bits in udev aren't used at all.
1223 * When an endpoint is reset by usb_clear_halt() we must reset
1224 * the toggle bit in the QH.
1225 */
1226 if (qh) {
1227 usb_settoggle(qh->dev, epnum, is_out, 0);
1228 if (!list_empty(&qh->qtd_list)) {
1229 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1230 } else if (qh->qh_state == QH_STATE_LINKED ||
1231 qh->qh_state == QH_STATE_COMPLETING) {
1232
1233 /* The toggle value in the QH can't be updated
1234 * while the QH is active. Unlink it now;
1235 * re-linking will call qh_refresh().
1236 */
1237 if (eptype == USB_ENDPOINT_XFER_BULK)
1238 unlink_async(ehci, qh);
1239 else
1240 intr_deschedule(ehci, qh);
1241 }
1242 }
1243 spin_unlock_irqrestore(&ehci->lock, flags);
1244 }
1245
ehci_get_frame(struct usb_hcd * hcd)1246 static int ehci_get_frame (struct usb_hcd *hcd)
1247 {
1248 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1249 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
1250 }
1251
1252 /*-------------------------------------------------------------------------*/
1253
1254 MODULE_DESCRIPTION(DRIVER_DESC);
1255 MODULE_AUTHOR (DRIVER_AUTHOR);
1256 MODULE_LICENSE ("GPL");
1257
1258 #ifdef CONFIG_PCI
1259 #include "ehci-pci.c"
1260 #define PCI_DRIVER ehci_pci_driver
1261 #endif
1262
1263 #ifdef CONFIG_USB_EHCI_FSL
1264 #include "ehci-fsl.c"
1265 #define PLATFORM_DRIVER ehci_fsl_driver
1266 #endif
1267
1268 #ifdef CONFIG_USB_EHCI_MXC
1269 #include "ehci-mxc.c"
1270 #define PLATFORM_DRIVER ehci_mxc_driver
1271 #endif
1272
1273 #ifdef CONFIG_USB_EHCI_SH
1274 #include "ehci-sh.c"
1275 #define PLATFORM_DRIVER ehci_hcd_sh_driver
1276 #endif
1277
1278 #ifdef CONFIG_MIPS_ALCHEMY
1279 #include "ehci-au1xxx.c"
1280 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1281 #endif
1282
1283 #ifdef CONFIG_USB_EHCI_HCD_OMAP
1284 #include "ehci-omap.c"
1285 #define PLATFORM_DRIVER ehci_hcd_omap_driver
1286 #endif
1287
1288 #ifdef CONFIG_PPC_PS3
1289 #include "ehci-ps3.c"
1290 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1291 #endif
1292
1293 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1294 #include "ehci-ppc-of.c"
1295 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1296 #endif
1297
1298 #ifdef CONFIG_XPS_USB_HCD_XILINX
1299 #include "ehci-xilinx-of.c"
1300 #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
1301 #endif
1302
1303 #ifdef CONFIG_PLAT_ORION
1304 #include "ehci-orion.c"
1305 #define PLATFORM_DRIVER ehci_orion_driver
1306 #endif
1307
1308 #ifdef CONFIG_ARCH_IXP4XX
1309 #include "ehci-ixp4xx.c"
1310 #define PLATFORM_DRIVER ixp4xx_ehci_driver
1311 #endif
1312
1313 #ifdef CONFIG_USB_W90X900_EHCI
1314 #include "ehci-w90x900.c"
1315 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1316 #endif
1317
1318 #ifdef CONFIG_ARCH_AT91
1319 #include "ehci-atmel.c"
1320 #define PLATFORM_DRIVER ehci_atmel_driver
1321 #endif
1322
1323 #ifdef CONFIG_USB_OCTEON_EHCI
1324 #include "ehci-octeon.c"
1325 #define PLATFORM_DRIVER ehci_octeon_driver
1326 #endif
1327
1328 #ifdef CONFIG_USB_CNS3XXX_EHCI
1329 #include "ehci-cns3xxx.c"
1330 #define PLATFORM_DRIVER cns3xxx_ehci_driver
1331 #endif
1332
1333 #ifdef CONFIG_ARCH_VT8500
1334 #include "ehci-vt8500.c"
1335 #define PLATFORM_DRIVER vt8500_ehci_driver
1336 #endif
1337
1338 #ifdef CONFIG_PLAT_SPEAR
1339 #include "ehci-spear.c"
1340 #define PLATFORM_DRIVER spear_ehci_hcd_driver
1341 #endif
1342
1343 #ifdef CONFIG_USB_EHCI_MSM
1344 #include "ehci-msm.c"
1345 #define PLATFORM_DRIVER ehci_msm_driver
1346 #endif
1347
1348 #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1349 #include "ehci-pmcmsp.c"
1350 #define PLATFORM_DRIVER ehci_hcd_msp_driver
1351 #endif
1352
1353 #ifdef CONFIG_USB_EHCI_TEGRA
1354 #include "ehci-tegra.c"
1355 #define PLATFORM_DRIVER tegra_ehci_driver
1356 #endif
1357
1358 #ifdef CONFIG_USB_EHCI_S5P
1359 #include "ehci-s5p.c"
1360 #define PLATFORM_DRIVER s5p_ehci_driver
1361 #endif
1362
1363 #ifdef CONFIG_SPARC_LEON
1364 #include "ehci-grlib.c"
1365 #define PLATFORM_DRIVER ehci_grlib_driver
1366 #endif
1367
1368 #ifdef CONFIG_CPU_XLR
1369 #include "ehci-xls.c"
1370 #define PLATFORM_DRIVER ehci_xls_driver
1371 #endif
1372
1373 #ifdef CONFIG_USB_EHCI_MV
1374 #include "ehci-mv.c"
1375 #define PLATFORM_DRIVER ehci_mv_driver
1376 #endif
1377
1378 #ifdef CONFIG_MACH_LOONGSON1
1379 #include "ehci-ls1x.c"
1380 #define PLATFORM_DRIVER ehci_ls1x_driver
1381 #endif
1382
1383 #ifdef CONFIG_USB_EHCI_HCD_PLATFORM
1384 #include "ehci-platform.c"
1385 #define PLATFORM_DRIVER ehci_platform_driver
1386 #endif
1387
1388 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1389 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
1390 !defined(XILINX_OF_PLATFORM_DRIVER)
1391 #error "missing bus glue for ehci-hcd"
1392 #endif
1393
ehci_hcd_init(void)1394 static int __init ehci_hcd_init(void)
1395 {
1396 int retval = 0;
1397
1398 if (usb_disabled())
1399 return -ENODEV;
1400
1401 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1402 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1403 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1404 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1405 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1406 " before uhci_hcd and ohci_hcd, not after\n");
1407
1408 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1409 hcd_name,
1410 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1411 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1412
1413 #ifdef DEBUG
1414 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1415 if (!ehci_debug_root) {
1416 retval = -ENOENT;
1417 goto err_debug;
1418 }
1419 #endif
1420
1421 #ifdef PLATFORM_DRIVER
1422 retval = platform_driver_register(&PLATFORM_DRIVER);
1423 if (retval < 0)
1424 goto clean0;
1425 #endif
1426
1427 #ifdef PCI_DRIVER
1428 retval = pci_register_driver(&PCI_DRIVER);
1429 if (retval < 0)
1430 goto clean1;
1431 #endif
1432
1433 #ifdef PS3_SYSTEM_BUS_DRIVER
1434 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1435 if (retval < 0)
1436 goto clean2;
1437 #endif
1438
1439 #ifdef OF_PLATFORM_DRIVER
1440 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1441 if (retval < 0)
1442 goto clean3;
1443 #endif
1444
1445 #ifdef XILINX_OF_PLATFORM_DRIVER
1446 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
1447 if (retval < 0)
1448 goto clean4;
1449 #endif
1450 return retval;
1451
1452 #ifdef XILINX_OF_PLATFORM_DRIVER
1453 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
1454 clean4:
1455 #endif
1456 #ifdef OF_PLATFORM_DRIVER
1457 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1458 clean3:
1459 #endif
1460 #ifdef PS3_SYSTEM_BUS_DRIVER
1461 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1462 clean2:
1463 #endif
1464 #ifdef PCI_DRIVER
1465 pci_unregister_driver(&PCI_DRIVER);
1466 clean1:
1467 #endif
1468 #ifdef PLATFORM_DRIVER
1469 platform_driver_unregister(&PLATFORM_DRIVER);
1470 clean0:
1471 #endif
1472 #ifdef DEBUG
1473 debugfs_remove(ehci_debug_root);
1474 ehci_debug_root = NULL;
1475 err_debug:
1476 #endif
1477 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1478 return retval;
1479 }
1480 module_init(ehci_hcd_init);
1481
ehci_hcd_cleanup(void)1482 static void __exit ehci_hcd_cleanup(void)
1483 {
1484 #ifdef XILINX_OF_PLATFORM_DRIVER
1485 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
1486 #endif
1487 #ifdef OF_PLATFORM_DRIVER
1488 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1489 #endif
1490 #ifdef PLATFORM_DRIVER
1491 platform_driver_unregister(&PLATFORM_DRIVER);
1492 #endif
1493 #ifdef PCI_DRIVER
1494 pci_unregister_driver(&PCI_DRIVER);
1495 #endif
1496 #ifdef PS3_SYSTEM_BUS_DRIVER
1497 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1498 #endif
1499 #ifdef DEBUG
1500 debugfs_remove(ehci_debug_root);
1501 #endif
1502 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1503 }
1504 module_exit(ehci_hcd_cleanup);
1505
1506