1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 22 * USA 23 * 24 * The full GNU General Public License is included in this distribution 25 * in the file called LICENSE.GPL. 26 * 27 * Contact Information: 28 * Intel Linux Wireless <ilw@linux.intel.com> 29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 30 * 31 * BSD LICENSE 32 * 33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 40 * * Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * * Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in 44 * the documentation and/or other materials provided with the 45 * distribution. 46 * * Neither the name Intel Corporation nor the names of its 47 * contributors may be used to endorse or promote products derived 48 * from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 *****************************************************************************/ 62 63 #ifndef __iwl_eeprom_h__ 64 #define __iwl_eeprom_h__ 65 66 #include <net/mac80211.h> 67 68 struct iwl_priv; 69 struct iwl_shared; 70 struct iwl_trans; 71 72 /* 73 * EEPROM access time values: 74 * 75 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG. 76 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). 77 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. 78 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. 79 */ 80 #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ 81 82 #define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */ 83 #define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ 84 85 86 /* 87 * Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags. 88 * 89 * IBSS and/or AP operation is allowed *only* on those channels with 90 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because 91 * RADAR detection is not supported by the 4965 driver, but is a 92 * requirement for establishing a new network for legal operation on channels 93 * requiring RADAR detection or restricting ACTIVE scanning. 94 * 95 * NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels. 96 * It only indicates that 20 MHz channel use is supported; HT40 channel 97 * usage is indicated by a separate set of regulatory flags for each 98 * HT40 channel pair. 99 * 100 * NOTE: Using a channel inappropriately will result in a uCode error! 101 */ 102 #define IWL_NUM_TX_CALIB_GROUPS 5 103 enum { 104 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ 105 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ 106 /* Bit 2 Reserved */ 107 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ 108 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ 109 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ 110 /* Bit 6 Reserved (was Narrow Channel) */ 111 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ 112 }; 113 114 /* SKU Capabilities */ 115 #define EEPROM_SKU_CAP_BAND_24GHZ (1 << 4) 116 #define EEPROM_SKU_CAP_BAND_52GHZ (1 << 5) 117 #define EEPROM_SKU_CAP_11N_ENABLE (1 << 6) 118 #define EEPROM_SKU_CAP_AMT_ENABLE (1 << 7) 119 #define EEPROM_SKU_CAP_IPAN_ENABLE (1 << 8) 120 121 /* *regulatory* channel data format in eeprom, one for each channel. 122 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */ 123 struct iwl_eeprom_channel { 124 u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */ 125 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */ 126 } __packed; 127 128 enum iwl_eeprom_enhanced_txpwr_flags { 129 IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0), 130 IWL_EEPROM_ENH_TXP_FL_BAND_52G = BIT(1), 131 IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2), 132 IWL_EEPROM_ENH_TXP_FL_40MHZ = BIT(3), 133 IWL_EEPROM_ENH_TXP_FL_HT_AP = BIT(4), 134 IWL_EEPROM_ENH_TXP_FL_RES1 = BIT(5), 135 IWL_EEPROM_ENH_TXP_FL_RES2 = BIT(6), 136 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE = BIT(7), 137 }; 138 139 /** 140 * iwl_eeprom_enhanced_txpwr structure 141 * This structure presents the enhanced regulatory tx power limit layout 142 * in eeprom image 143 * Enhanced regulatory tx power portion of eeprom image can be broken down 144 * into individual structures; each one is 8 bytes in size and contain the 145 * following information 146 * @flags: entry flags 147 * @channel: channel number 148 * @chain_a_max_pwr: chain a max power in 1/2 dBm 149 * @chain_b_max_pwr: chain b max power in 1/2 dBm 150 * @chain_c_max_pwr: chain c max power in 1/2 dBm 151 * @delta_20_in_40: 20-in-40 deltas (hi/lo) 152 * @mimo2_max_pwr: mimo2 max power in 1/2 dBm 153 * @mimo3_max_pwr: mimo3 max power in 1/2 dBm 154 * 155 */ 156 struct iwl_eeprom_enhanced_txpwr { 157 u8 flags; 158 u8 channel; 159 s8 chain_a_max; 160 s8 chain_b_max; 161 s8 chain_c_max; 162 u8 delta_20_in_40; 163 s8 mimo2_max; 164 s8 mimo3_max; 165 } __packed; 166 167 /* calibration */ 168 struct iwl_eeprom_calib_hdr { 169 u8 version; 170 u8 pa_type; 171 __le16 voltage; 172 } __packed; 173 174 #define EEPROM_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION) 175 #define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL) 176 177 /* temperature */ 178 #define EEPROM_KELVIN_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL) 179 #define EEPROM_RAW_TEMPERATURE ((2*0x12B) | EEPROM_CALIB_ALL) 180 181 182 /* agn links */ 183 #define EEPROM_LINK_HOST (2*0x64) 184 #define EEPROM_LINK_GENERAL (2*0x65) 185 #define EEPROM_LINK_REGULATORY (2*0x66) 186 #define EEPROM_LINK_CALIBRATION (2*0x67) 187 #define EEPROM_LINK_PROCESS_ADJST (2*0x68) 188 #define EEPROM_LINK_OTHERS (2*0x69) 189 #define EEPROM_LINK_TXP_LIMIT (2*0x6a) 190 #define EEPROM_LINK_TXP_LIMIT_SIZE (2*0x6b) 191 192 /* agn regulatory - indirect access */ 193 #define EEPROM_REG_BAND_1_CHANNELS ((0x08)\ 194 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 28 bytes */ 195 #define EEPROM_REG_BAND_2_CHANNELS ((0x26)\ 196 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 26 bytes */ 197 #define EEPROM_REG_BAND_3_CHANNELS ((0x42)\ 198 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 24 bytes */ 199 #define EEPROM_REG_BAND_4_CHANNELS ((0x5C)\ 200 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */ 201 #define EEPROM_REG_BAND_5_CHANNELS ((0x74)\ 202 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 12 bytes */ 203 #define EEPROM_REG_BAND_24_HT40_CHANNELS ((0x82)\ 204 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */ 205 #define EEPROM_REG_BAND_52_HT40_CHANNELS ((0x92)\ 206 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */ 207 208 /* 6000 regulatory - indirect access */ 209 #define EEPROM_6000_REG_BAND_24_HT40_CHANNELS ((0x80)\ 210 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */ 211 212 /* 5000 Specific */ 213 #define EEPROM_5000_TX_POWER_VERSION (4) 214 #define EEPROM_5000_EEPROM_VERSION (0x11A) 215 216 /* 5050 Specific */ 217 #define EEPROM_5050_TX_POWER_VERSION (4) 218 #define EEPROM_5050_EEPROM_VERSION (0x21E) 219 220 /* 1000 Specific */ 221 #define EEPROM_1000_TX_POWER_VERSION (4) 222 #define EEPROM_1000_EEPROM_VERSION (0x15C) 223 224 /* 6x00 Specific */ 225 #define EEPROM_6000_TX_POWER_VERSION (4) 226 #define EEPROM_6000_EEPROM_VERSION (0x423) 227 228 /* 6x50 Specific */ 229 #define EEPROM_6050_TX_POWER_VERSION (4) 230 #define EEPROM_6050_EEPROM_VERSION (0x532) 231 232 /* 6150 Specific */ 233 #define EEPROM_6150_TX_POWER_VERSION (6) 234 #define EEPROM_6150_EEPROM_VERSION (0x553) 235 236 /* 6x05 Specific */ 237 #define EEPROM_6005_TX_POWER_VERSION (6) 238 #define EEPROM_6005_EEPROM_VERSION (0x709) 239 240 /* 6x30 Specific */ 241 #define EEPROM_6030_TX_POWER_VERSION (6) 242 #define EEPROM_6030_EEPROM_VERSION (0x709) 243 244 /* 2x00 Specific */ 245 #define EEPROM_2000_TX_POWER_VERSION (6) 246 #define EEPROM_2000_EEPROM_VERSION (0x805) 247 248 /* 6x35 Specific */ 249 #define EEPROM_6035_TX_POWER_VERSION (6) 250 #define EEPROM_6035_EEPROM_VERSION (0x753) 251 252 253 /* OTP */ 254 /* lower blocks contain EEPROM image and calibration data */ 255 #define OTP_LOW_IMAGE_SIZE (2 * 512 * sizeof(u16)) /* 2 KB */ 256 /* high blocks contain PAPD data */ 257 #define OTP_HIGH_IMAGE_SIZE_6x00 (6 * 512 * sizeof(u16)) /* 6 KB */ 258 #define OTP_HIGH_IMAGE_SIZE_1000 (0x200 * sizeof(u16)) /* 1024 bytes */ 259 #define OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */ 260 #define OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */ 261 #define OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */ 262 #define OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */ 263 264 /* 2.4 GHz */ 265 extern const u8 iwl_eeprom_band_1[14]; 266 267 #define ADDRESS_MSK 0x0000FFFF 268 #define INDIRECT_TYPE_MSK 0x000F0000 269 #define INDIRECT_HOST 0x00010000 270 #define INDIRECT_GENERAL 0x00020000 271 #define INDIRECT_REGULATORY 0x00030000 272 #define INDIRECT_CALIBRATION 0x00040000 273 #define INDIRECT_PROCESS_ADJST 0x00050000 274 #define INDIRECT_OTHERS 0x00060000 275 #define INDIRECT_TXP_LIMIT 0x00070000 276 #define INDIRECT_TXP_LIMIT_SIZE 0x00080000 277 #define INDIRECT_ADDRESS 0x00100000 278 279 /* General */ 280 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ 281 #define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */ 282 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ 283 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ 284 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ 285 #define EEPROM_VERSION (2*0x44) /* 2 bytes */ 286 #define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */ 287 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ 288 #define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */ 289 #define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */ 290 291 /* The following masks are to be applied on EEPROM_RADIO_CONFIG */ 292 #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */ 293 #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ 294 #define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ 295 #define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ 296 #define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ 297 #define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ 298 299 #define EEPROM_RF_CONFIG_TYPE_MAX 0x3 300 301 #define EEPROM_REGULATORY_BAND_NO_HT40 (0) 302 303 struct iwl_eeprom_ops { 304 const u32 regulatory_bands[7]; 305 bool enhanced_txpower; 306 }; 307 308 309 int iwl_eeprom_init(struct iwl_trans *trans, u32 hw_rev); 310 void iwl_eeprom_free(struct iwl_shared *shrd); 311 int iwl_eeprom_check_version(struct iwl_priv *priv); 312 int iwl_eeprom_init_hw_params(struct iwl_priv *priv); 313 const u8 *iwl_eeprom_query_addr(const struct iwl_shared *shrd, size_t offset); 314 u16 iwl_eeprom_query16(const struct iwl_shared *shrd, size_t offset); 315 int iwl_init_channel_map(struct iwl_priv *priv); 316 void iwl_free_channel_map(struct iwl_priv *priv); 317 const struct iwl_channel_info *iwl_get_channel_info( 318 const struct iwl_priv *priv, 319 enum ieee80211_band band, u16 channel); 320 void iwl_rf_config(struct iwl_priv *priv); 321 322 #endif /* __iwl_eeprom_h__ */ 323