1 /********************************************************************** 2 * Defines for the Tachyon Fibre Channel Controller and the Interphase 3 * (i)chip TPI. 4 *********************************************************************/ 5 6 #ifndef _TACH_H 7 #define _TACH_H 8 9 #define MY_PAGE_SIZE 4096 10 #define REPLICATE 0xFF 11 #define MAX_NODES 127 12 #define BROADCAST 0xFFFFFF 13 #define BROADCAST_ADDR 0xFFFFFFFFFFFF 14 #define LOGIN_COMPLETED 2 15 #define LOGIN_ATTEMPTED 1 16 #define LOGIN_NOT_ATTEMPTED 0 17 #define TRUE 1 18 #define FALSE 0 19 20 #define TACHYON_LIMIT 0x01EF 21 #define TACHYON_OFFSET 0x200 22 23 /* Offsets to the (i) chip */ 24 #define ICHIP_HW_CONTROL_REG_OFF (0x080 - TACHYON_OFFSET) 25 #define ICHIP_HW_STATUS_REG_OFF (0x084 - TACHYON_OFFSET) 26 #define ICHIP_HW_ADDR_MASK_REG_OFF (0x090 - TACHYON_OFFSET) 27 28 /* (i)chip Hardware Control Register defines */ 29 #define ICHIP_HCR_RESET 0x01 30 #define ICHIP_HCR_DERESET 0x0 31 #define ICHIP_HCR_ENABLE_INTA 0x0000003E 32 #define ICHIP_HCR_ENABLE_INTB 0x003E0000 33 #define ICHIP_HCR_IWDATA_FIFO 0x800000 34 35 /* (i)chip Hardware Status Register defines */ 36 #define ICHIP_HSR_INT_LATCH 0x02 37 38 /* (i)chip Hardware Address Mask Register defines */ 39 #define ICHIP_HAMR_BYTE_SWAP_ADDR_TR 0x08 40 #define ICHIP_HAMR_BYTE_SWAP_NO_ADDR_TR 0x04 41 42 /* NOVRAM defines */ 43 #define IPH5526_NOVRAM_SIZE 64 44 45 46 /* Offsets for the registers that correspond to the 47 * Qs on the Tachyon (As defined in the Tachyon Manual). 48 */ 49 50 /* Outbound Command Queue (OCQ). 51 */ 52 #define OCQ_BASE_REGISTER_OFFSET 0x000 53 #define OCQ_LENGTH_REGISTER_OFFSET 0x004 54 #define OCQ_PRODUCER_REGISTER_OFFSET 0x008 55 #define OCQ_CONSUMER_REGISTER_OFFSET 0x00C 56 57 /* Inbound Message Queue (IMQ). 58 */ 59 #define IMQ_BASE_REGISTER_OFFSET 0x080 60 #define IMQ_LENGTH_REGISTER_OFFSET 0x084 61 #define IMQ_CONSUMER_REGISTER_OFFSET 0x088 62 #define IMQ_PRODUCER_REGISTER_OFFSET 0x08C 63 64 /* Multiframe Sequence Buffer Queue (MFSBQ) 65 */ 66 #define MFSBQ_BASE_REGISTER_OFFSET 0x0C0 67 #define MFSBQ_LENGTH_REGISTER_OFFSET 0x0C4 68 #define MFSBQ_PRODUCER_REGISTER_OFFSET 0x0C8 69 #define MFSBQ_CONSUMER_REGISTER_OFFSET 0x0CC 70 #define MFS_LENGTH_REGISTER_OFFSET 0x0D0 71 72 /* Single Frame Sequence Buffer Queue (SFSBQ) 73 */ 74 #define SFSBQ_BASE_REGISTER_OFFSET 0x100 75 #define SFSBQ_LENGTH_REGISTER_OFFSET 0x104 76 #define SFSBQ_PRODUCER_REGISTER_OFFSET 0x108 77 #define SFSBQ_CONSUMER_REGISTER_OFFSET 0x10C 78 #define SFS_LENGTH_REGISTER_OFFSET 0x110 79 80 /* SCSI Exchange State Table (SEST) 81 */ 82 #define SEST_BASE_REGISTER_OFFSET 0x140 83 #define SEST_LENGTH_REGISTER_OFFSET 0x144 84 #define SCSI_LENGTH_REGISTER_OFFSET 0x148 85 86 /* Length of the various Qs 87 */ 88 #define NO_OF_ENTRIES 8 89 #define OCQ_LENGTH (MY_PAGE_SIZE/32) 90 #define IMQ_LENGTH (MY_PAGE_SIZE/32) 91 #define MFSBQ_LENGTH 8 92 #define SFSBQ_LENGTH 8 93 #define SEST_LENGTH MY_PAGE_SIZE 94 95 /* Size of the various buffers. 96 */ 97 #define TACH_FRAME_SIZE 2048 98 #define MFS_BUFFER_SIZE TACH_FRAME_SIZE 99 #define SFS_BUFFER_SIZE (TACH_FRAME_SIZE + TACHYON_HEADER_LEN) 100 #define SEST_BUFFER_SIZE 512 101 #define TACH_HEADER_SIZE 64 102 #define NO_OF_TACH_HEADERS ((MY_PAGE_SIZE)/TACH_HEADER_SIZE) 103 104 #define NO_OF_FCP_CMNDS (MY_PAGE_SIZE/32) 105 #define SDB_SIZE 2048 106 #define NO_OF_SDB_ENTRIES ((32*MY_PAGE_SIZE)/SDB_SIZE) 107 108 109 /* Offsets to the other Tachyon registers. 110 * (As defined in the Tachyon manual) 111 */ 112 #define TACHYON_CONFIG_REGISTER_OFFSET 0x184 113 #define TACHYON_CONTROL_REGISTER_OFFSET 0x188 114 #define TACHYON_STATUS_REGISTER_OFFSET 0x18C 115 #define TACHYON_FLUSH_SEST_REGISTER_OFFSET 0x190 116 117 /* Defines for the Tachyon Configuration register. 118 */ 119 #define SCSI_ENABLE 0x40000000 120 #define WRITE_STREAM_SIZE 0x800 /* size = 16 */ 121 #define READ_STREAM_SIZE 0x300 /* size = 64 */ 122 #define PARITY_EVEN 0x2 123 #define OOO_REASSEMBLY_DISABLE 0x40 124 125 /* Defines for the Tachyon Control register. 126 */ 127 #define SOFTWARE_RESET 0x80000000 128 #define OCQ_RESET 0x4 129 #define ERROR_RELEASE 0x2 130 131 /* Defines for the Tachyon Status register. 132 */ 133 #define RECEIVE_FIFO_EMPTY 0x10 134 #define OSM_FROZEN 0x1 135 #define OCQ_RESET_STATUS 0x20 136 #define SCSI_FREEZE_STATUS 0x40 137 138 139 /* Offsets to the Frame Manager registers. 140 */ 141 #define FMGR_CONFIG_REGISTER_OFFSET 0x1C0 142 #define FMGR_CONTROL_REGISTER_OFFSET 0x1C4 143 #define FMGR_STATUS_REGISTER_OFFSET 0x1C8 144 #define FMGR_TIMER_REGISTER_OFFSET 0x1CC 145 #define FMGR_WWN_HI_REGISTER_OFFSET 0x1E0 146 #define FMGR_WWN_LO_REGISTER_OFFSET 0x1E4 147 #define FMGR_RCVD_ALPA_REGISTER_OFFSET 0x1E8 148 149 /* Defines for the Frame Manager Configuration register. 150 */ 151 #define BB_CREDIT 0x10000 152 #define NPORT 0x8000 153 #define LOOP_INIT_FABRIC_ADDRESS 0x400 154 #define LOOP_INIT_PREVIOUS_ADDRESS 0x200 155 #define LOOP_INIT_SOFT_ADDRESS 0x80 156 157 /* Defines for the Frame Manager Control register. 158 */ 159 #define HOST_CONTROL 0x02 160 #define EXIT_HOST_CONTROL 0x03 161 #define OFFLINE 0x05 162 #define INITIALIZE 0x06 163 #define CLEAR_LF 0x07 164 165 /* Defines for the Frame Manager Status register. 166 */ 167 #define LOOP_UP 0x80000000 168 #define TRANSMIT_PARITY_ERROR 0x40000000 169 #define NON_PARTICIPATING 0x20000000 170 #define OUT_OF_SYNC 0x02000000 171 #define LOSS_OF_SIGNAL 0x01000000 172 #define NOS_OLS_RECEIVED 0x00080000 173 #define LOOP_STATE_TIMEOUT 0x00040000 174 #define LIPF_RECEIVED 0x00020000 175 #define BAD_ALPA 0x00010000 176 #define LINK_FAILURE 0x00001000 177 #define ELASTIC_STORE_ERROR 0x00000400 178 #define LINK_UP 0x00000200 179 #define LINK_DOWN 0x00000100 180 #define ARBITRATING 0x00000010 181 #define ARB_WON 0x00000020 182 #define OPEN 0x00000030 183 #define OPENED 0x00000040 184 #define TX_CLS 0x00000050 185 #define RX_CLS 0x00000060 186 #define TRANSFER 0x00000070 187 #define INITIALIZING 0x00000080 188 #define LOOP_FAIL 0x000000D0 189 #define OLD_PORT 0x000000F0 190 #define PORT_STATE_ACTIVE 0x0000000F 191 #define PORT_STATE_OFFLINE 0x00000000 192 #define PORT_STATE_LF1 0x00000009 193 #define PORT_STATE_LF2 0x0000000A 194 195 /* Completion Message Types 196 * (defined in P.177 of the Tachyon manual) 197 */ 198 #define OUTBOUND_COMPLETION 0x000 199 #define OUTBOUND_COMPLETION_I 0x100 200 #define OUT_HI_PRI_COMPLETION 0x001 201 #define OUT_HI_PRI_COMPLETION_I 0x101 202 #define INBOUND_MFS_COMPLETION 0x102 203 #define INBOUND_OOO_COMPLETION 0x003 204 #define INBOUND_SFS_COMPLETION 0x104 205 #define INBOUND_C1_TIMEOUT 0x105 206 #define INBOUND_UNKNOWN_FRAME_I 0x106 207 #define INBOUND_BUSIED_FRAME 0x006 208 #define SFS_BUF_WARN 0x107 209 #define MFS_BUF_WARN 0x108 210 #define IMQ_BUF_WARN 0x109 211 #define FRAME_MGR_INTERRUPT 0x10A 212 #define READ_STATUS 0x10B 213 #define INBOUND_SCSI_DATA_COMPLETION 0x10C 214 #define INBOUND_SCSI_COMMAND 0x10D 215 #define BAD_SCSI_FRAME 0x10E 216 #define INB_SCSI_STATUS_COMPLETION 0x10F 217 218 /* One of the things that we care about when we receive an 219 * Outbound Completion Message (OCM). 220 */ 221 #define OCM_TIMEOUT_OR_BAD_ALPA 0x0800 222 223 /* Defines for the Tachyon Header structure. 224 */ 225 #define SOFI3 0x70 226 #define SOFN3 0xB0 227 #define EOFN 0x5 228 229 /* R_CTL */ 230 #define FC4_DEVICE_DATA 0 231 #define EXTENDED_LINK_DATA 0x20000000 232 #define FC4_LINK_DATA 0x30000000 233 #define BASIC_LINK_DATA 0x80000000 234 #define LINK_CONTROL 0xC0000000 235 #define SOLICITED_DATA 0x1000000 236 #define UNSOLICITED_CONTROL 0x2000000 237 #define SOLICITED_CONTROL 0x3000000 238 #define UNSOLICITED_DATA 0x4000000 239 #define DATA_DESCRIPTOR 0x5000000 240 #define UNSOLICITED_COMMAND 0x6000000 241 242 #define RCTL_ELS_UCTL 0x22000000 243 #define RCTL_ELS_SCTL 0x23000000 244 #define RCTL_BASIC_ABTS 0x81000000 245 #define RCTL_BASIC_ACC 0x84000000 246 #define RCTL_BASIC_RJT 0x85000000 247 248 /* TYPE */ 249 #define TYPE_BLS 0x00000000 250 #define TYPE_ELS 0x01000000 251 #define TYPE_FC_SERVICES 0x20000000 252 #define TYPE_LLC_SNAP 0x05000000 253 #define TYPE_FCP 0x08000000 254 255 /* F_CTL */ 256 #define EXCHANGE_RESPONDER 0x800000 257 #define SEQUENCE_RESPONDER 0x400000 258 #define FIRST_SEQUENCE 0x200000 259 #define LAST_SEQUENCE 0x100000 260 #define SEQUENCE_INITIATIVE 0x10000 261 #define RELATIVE_OFF_PRESENT 0x8 262 #define END_SEQUENCE 0x80000 263 264 #define TACHYON_HEADER_LEN 32 265 #define NW_HEADER_LEN 16 266 /* Defines for the Outbound Descriptor Block (ODB). 267 */ 268 #define ODB_CLASS_3 0xC000 269 #define ODB_NO_COMP 0x400 270 #define ODB_NO_INT 0x200 271 #define ODB_EE_CREDIT 0xF 272 273 /* Defines for the Extended Descriptor Block (EDB). 274 */ 275 #define EDB_LEN ((32*MY_PAGE_SIZE)/8) 276 #define EDB_END 0x8000 277 #define EDB_FREE 0 278 #define EDB_BUSY 1 279 280 /* Command Codes */ 281 #define ELS_LS_RJT 0x01000000 282 #define ELS_ACC 0x02000000 283 #define ELS_PLOGI 0x03000000 284 #define ELS_FLOGI 0x04000000 285 #define ELS_LOGO 0x05000000 286 #define ELS_TPRLO 0x24000000 287 #define ELS_ADISC 0x52000000 288 #define ELS_PDISC 0x50000000 289 #define ELS_PRLI 0x20000000 290 #define ELS_PRLO 0x21000000 291 #define ELS_SCR 0x62000000 292 #define ELS_RSCN 0x61000000 293 #define ELS_FARP_REQ 0x54000000 294 #define ELS_ABTX 0x06000000 295 #define ELS_ADVC 0x0D000000 296 #define ELS_ECHO 0x10000000 297 #define ELS_ESTC 0x0C000000 298 #define ELS_ESTS 0x0B000000 299 #define ELS_RCS 0x07000000 300 #define ELS_RES 0x08000000 301 #define ELS_RLS 0x0F000000 302 #define ELS_RRQ 0x12000000 303 #define ELS_RSS 0x09000000 304 #define ELS_RTV 0x0E000000 305 #define ELS_RSI 0x0A000000 306 #define ELS_TEST 0x11000000 307 #define ELS_RNC 0x53000000 308 #define ELS_RVCS 0x41000000 309 #define ELS_TPLS 0x23000000 310 #define ELS_GAID 0x30000000 311 #define ELS_FACT 0x31000000 312 #define ELS_FAN 0x60000000 313 #define ELS_FDACT 0x32000000 314 #define ELS_NACT 0x33000000 315 #define ELS_NDACT 0x34000000 316 #define ELS_QoSR 0x40000000 317 #define ELS_FDISC 0x51000000 318 319 #define ELS_NS_PLOGI 0x03FFFFFC 320 321 /* LS_RJT reason codes. 322 */ 323 #define INV_LS_CMND_CODE 0x0001 324 #define LOGICAL_ERR 0x0003 325 #define LOGICAL_BUSY 0x0005 326 #define PROTOCOL_ERR 0x0007 327 #define UNABLE_TO_PERFORM 0x0009 328 #define CMND_NOT_SUPP 0x000B 329 330 /* LS_RJT explanation codes. 331 */ 332 #define NO_EXPLN 0x0000 333 #define RECV_FIELD_SIZE 0x0700 334 #define CONC_SEQ 0x0900 335 #define REQ_NOT_SUPPORTED 0x2C00 336 #define INV_PAYLOAD_LEN 0x2D00 337 338 /* Payload Length defines. 339 */ 340 #define PLOGI_LEN 116 341 342 #define CONCURRENT_SEQUENCES 0x01 343 #define RO_INFO_CATEGORY 0xFE 344 #define E_D_TOV 0x07D0 /* 2 Secs */ 345 #define AL_TIME 0x0010 /* ~15 msec */ 346 #define TOV_VALUES (AL_TIME << 16) | E_D_TOV 347 #define RT_TOV 0x64 /* 100 msec */ 348 #define PTP_TOV_VALUES (RT_TOV << 16) | E_D_TOV 349 #define SERVICE_VALID 0x8000 350 #define SEQUENCE_DELIVERY 0x0800 351 #define CLASS3_CONCURRENT_SEQUENCE 0x01 352 #define CLASS3_OPEN_SEQUENCE 0x01 353 354 /* These are retrieved from the NOVRAM. 355 */ 356 #define WORLD_WIDE_NAME_LOW fi->g.my_port_name_low 357 #define WORLD_WIDE_NAME_HIGH fi->g.my_port_name_high 358 #define N_PORT_NAME_HIGH fi->g.my_port_name_high 359 #define N_PORT_NAME_LOW fi->g.my_port_name_low 360 #define NODE_NAME_HIGH fi->g.my_node_name_high 361 #define NODE_NAME_LOW fi->g.my_node_name_low 362 363 #define PORT_NAME_LEN 8 364 #define NODE_NAME_LEN 8 365 366 367 #define PH_VERSION 0x0909 368 369 #define LOOP_BB_CREDIT 0x00 370 #define PT2PT_BB_CREDIT 0x01 371 #define FLOGI_C_F 0x0800 /* Alternate BB_Credit Mgmnt */ 372 #define PLOGI_C_F 0x8800 /* Continuously Increasing + Alternate BB_Credit Management */ 373 374 /* Fabric defines */ 375 #define DIRECTORY_SERVER 0xFFFFFC 376 #define FABRIC_CONTROLLER 0xFFFFFD 377 #define F_PORT 0xFFFFFE 378 379 #define FLOGI_DID 0xFFFE 380 #define NS_PLOGI_DID 0xFFFC 381 382 /* Fibre Channel Services defines */ 383 #define FCS_RFC_4 0x02170000 384 #define FCS_GP_ID4 0x01A10000 385 #define FCS_ACC 0x8002 386 #define FCS_REJECT 0x8001 387 388 /* CT Header defines */ 389 #define FC_CT_REV 0x01000000 390 #define DIRECTORY_SERVER_APP 0xFC 391 #define NAME_SERVICE 0x02 392 393 /* Port Type defines */ 394 #define PORT_TYPE_IP 0x05000000 395 #define PORT_TYPE_NX_PORTS 0x7F000000 396 397 /* SCR defines */ 398 #define FABRIC_DETECTED_REG 0x00000001 399 #define N_PORT_DETECTED_REG 0x00000002 400 #define FULL_REGISTRATION 0x00000003 401 #define CLEAR_REGISTRATION 0x000000FF 402 403 /* Command structure has only one byte to address targets 404 */ 405 #define MAX_SCSI_TARGETS 0xFF 406 407 #define FC_SCSI_READ 0x80 408 #define FC_SCSI_WRITE 0x81 409 #define FC_ELS 0x01 410 #define FC_BLS 0x00 411 #define FC_IP 0x05 412 #define FC_BROADCAST 0xFF 413 414 /* SEST defines. 415 */ 416 #define SEST_V 0x80000000 /* V = 1 */ 417 #define INB_SEST_VED 0xA0000000 /* V = 1, D = 1 */ 418 #define SEST_INV 0x7FFFFFFF 419 #define OUTB_SEST_VED 0x80000000 /* V = 1 */ 420 #define INV_SEQ_LEN 0xFFFFFFFF 421 #define OUTB_SEST_LINK 0xFFFF 422 423 /* PRLI defines. 424 */ 425 #define PAGE_LEN 0x100000 /* 3rd byte - 0x10 */ 426 #define PRLI_LEN 0x0014 /* 20 bytes */ 427 #define FCP_TYPE_CODE 0x0800 /* FCP-SCSI */ 428 #define IMAGE_PAIR 0x2000 /* establish image pair */ 429 #define INITIATOR_FUNC 0x00000020 430 #define TARGET_FUNC 0x00000010 431 #define READ_XFER_RDY_DISABLED 0x00000002 432 433 #define NODE_PROCESS_LOGGED_IN 0x3 434 #define NODE_NOT_PRESENT 0x2 435 #define NODE_LOGGED_IN 0x1 436 #define NODE_LOGGED_OUT 0x0 437 438 /* Defines to determine what should be returned when a SCSI frame 439 * times out. 440 */ 441 #define FC_SCSI_BAD_TARGET 0xFFFE0000 442 443 /* RSCN Address formats */ 444 #define PORT_ADDRESS_FORMAT 0x00 445 #define AREA_ADDRESS_FORMAT 0x01 446 #define DOMAIN_ADDRESS_FORMAT 0x02 447 448 /* Defines used to determine whether a frame transmission should 449 * be indicated by an interrupt or not. 450 */ 451 #define NO_COMP_AND_INT 0 452 #define INT_AND_COMP_REQ 1 453 #define NO_INT_COMP_REQ 2 454 455 /* Other junk... 456 */ 457 #define SDB_FREE 0 458 #define SDB_BUSY 1 459 #define MAX_PENDING_FRAMES 15 460 #define RX_ID_FIRST_SEQUENCE 0xFFFF 461 #define OX_ID_FIRST_SEQUENCE 0xFFFF 462 #define NOT_SCSI_XID 0x8000 463 #define MAX_SCSI_XID 0x0FFF /* X_IDs are from 0-4095 */ 464 #define SCSI_READ_BIT 0x4000 465 #define MAX_SCSI_OXID 0x4FFF 466 #define OXID_AVAILABLE 0 467 #define OXID_INUSE 1 468 #define MAX_SEQ_ID 0xFF 469 470 #define INITIATOR 2 471 #define TARGET 1 472 #define DELETE_ENTRY 1 473 #define ADD_ENTRY 2 474 475 #endif /* _TACH_H */ 476