1 /* 2 * MMUAccInt.h 3 * 4 * DSP-BIOS Bridge driver support functions for TI OMAP processors. 5 * 6 * Copyright (C) 2007 Texas Instruments, Inc. 7 * 8 * This package is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 13 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 14 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 15 */ 16 17 #ifndef _MMU_ACC_INT_H 18 #define _MMU_ACC_INT_H 19 20 /* Mappings of level 1 EASI function numbers to function names */ 21 22 #define EASIL1_MMUMMU_SYSCONFIG_READ_REGISTER32 (MMU_BASE_EASIL1 + 3) 23 #define EASIL1_MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32 (MMU_BASE_EASIL1 + 17) 24 #define EASIL1_MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32 (MMU_BASE_EASIL1 + 39) 25 #define EASIL1_MMUMMU_IRQSTATUS_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 51) 26 #define EASIL1_MMUMMU_IRQENABLE_READ_REGISTER32 (MMU_BASE_EASIL1 + 102) 27 #define EASIL1_MMUMMU_IRQENABLE_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 103) 28 #define EASIL1_MMUMMU_WALKING_STTWL_RUNNING_READ32 (MMU_BASE_EASIL1 + 156) 29 #define EASIL1_MMUMMU_CNTLTWL_ENABLE_READ32 (MMU_BASE_EASIL1 + 174) 30 #define EASIL1_MMUMMU_CNTLTWL_ENABLE_WRITE32 (MMU_BASE_EASIL1 + 180) 31 #define EASIL1_MMUMMU_CNTLMMU_ENABLE_WRITE32 (MMU_BASE_EASIL1 + 190) 32 #define EASIL1_MMUMMU_FAULT_AD_READ_REGISTER32 (MMU_BASE_EASIL1 + 194) 33 #define EASIL1_MMUMMU_TTB_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 198) 34 #define EASIL1_MMUMMU_LOCK_READ_REGISTER32 (MMU_BASE_EASIL1 + 203) 35 #define EASIL1_MMUMMU_LOCK_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 204) 36 #define EASIL1_MMUMMU_LOCK_BASE_VALUE_READ32 (MMU_BASE_EASIL1 + 205) 37 #define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_READ32 (MMU_BASE_EASIL1 + 209) 38 #define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_WRITE32 (MMU_BASE_EASIL1 + 211) 39 #define EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_SET32 (MMU_BASE_EASIL1 + 212) 40 #define EASIL1_MMUMMU_LD_TLB_READ_REGISTER32 (MMU_BASE_EASIL1 + 213) 41 #define EASIL1_MMUMMU_LD_TLB_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 214) 42 #define EASIL1_MMUMMU_CAM_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 226) 43 #define EASIL1_MMUMMU_RAM_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 268) 44 #define EASIL1_MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32 (MMU_BASE_EASIL1 + 322) 45 46 /* Register offset address definitions */ 47 #define MMU_MMU_SYSCONFIG_OFFSET 0x10 48 #define MMU_MMU_IRQSTATUS_OFFSET 0x18 49 #define MMU_MMU_IRQENABLE_OFFSET 0x1c 50 #define MMU_MMU_WALKING_ST_OFFSET 0x40 51 #define MMU_MMU_CNTL_OFFSET 0x44 52 #define MMU_MMU_FAULT_AD_OFFSET 0x48 53 #define MMU_MMU_TTB_OFFSET 0x4c 54 #define MMU_MMU_LOCK_OFFSET 0x50 55 #define MMU_MMU_LD_TLB_OFFSET 0x54 56 #define MMU_MMU_CAM_OFFSET 0x58 57 #define MMU_MMU_RAM_OFFSET 0x5c 58 #define MMU_MMU_GFLUSH_OFFSET 0x60 59 #define MMU_MMU_FLUSH_ENTRY_OFFSET 0x64 60 /* Bitfield mask and offset declarations */ 61 #define MMU_MMU_SYSCONFIG_IDLE_MODE_MASK 0x18 62 #define MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET 3 63 #define MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK 0x1 64 #define MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET 0 65 #define MMU_MMU_WALKING_ST_TWL_RUNNING_MASK 0x1 66 #define MMU_MMU_WALKING_ST_TWL_RUNNING_OFFSET 0 67 #define MMU_MMU_CNTL_TWL_ENABLE_MASK 0x4 68 #define MMU_MMU_CNTL_TWL_ENABLE_OFFSET 2 69 #define MMU_MMU_CNTL_MMU_ENABLE_MASK 0x2 70 #define MMU_MMU_CNTL_MMU_ENABLE_OFFSET 1 71 #define MMU_MMU_LOCK_BASE_VALUE_MASK 0xfc00 72 #define MMU_MMU_LOCK_BASE_VALUE_OFFSET 10 73 #define MMU_MMU_LOCK_CURRENT_VICTIM_MASK 0x3f0 74 #define MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET 4 75 76 #endif /* _MMU_ACC_INT_H */ 77