1 /** 2 * core.h - DesignWare USB3 DRD Core Header 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef __DRIVERS_USB_DWC3_CORE_H 40 #define __DRIVERS_USB_DWC3_CORE_H 41 42 #include <linux/device.h> 43 #include <linux/spinlock.h> 44 #include <linux/ioport.h> 45 #include <linux/list.h> 46 #include <linux/dma-mapping.h> 47 #include <linux/mm.h> 48 #include <linux/debugfs.h> 49 50 #include <linux/usb/ch9.h> 51 #include <linux/usb/gadget.h> 52 53 /* Global constants */ 54 #define DWC3_ENDPOINTS_NUM 32 55 56 #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE 57 #define DWC3_EVENT_TYPE_MASK 0xfe 58 59 #define DWC3_EVENT_TYPE_DEV 0 60 #define DWC3_EVENT_TYPE_CARKIT 3 61 #define DWC3_EVENT_TYPE_I2C 4 62 63 #define DWC3_DEVICE_EVENT_DISCONNECT 0 64 #define DWC3_DEVICE_EVENT_RESET 1 65 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 66 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 67 #define DWC3_DEVICE_EVENT_WAKEUP 4 68 #define DWC3_DEVICE_EVENT_EOPF 6 69 #define DWC3_DEVICE_EVENT_SOF 7 70 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 71 #define DWC3_DEVICE_EVENT_CMD_CMPL 10 72 #define DWC3_DEVICE_EVENT_OVERFLOW 11 73 74 #define DWC3_GEVNTCOUNT_MASK 0xfffc 75 #define DWC3_GSNPSID_MASK 0xffff0000 76 #define DWC3_GSNPSREV_MASK 0xffff 77 78 /* Global Registers */ 79 #define DWC3_GSBUSCFG0 0xc100 80 #define DWC3_GSBUSCFG1 0xc104 81 #define DWC3_GTXTHRCFG 0xc108 82 #define DWC3_GRXTHRCFG 0xc10c 83 #define DWC3_GCTL 0xc110 84 #define DWC3_GEVTEN 0xc114 85 #define DWC3_GSTS 0xc118 86 #define DWC3_GSNPSID 0xc120 87 #define DWC3_GGPIO 0xc124 88 #define DWC3_GUID 0xc128 89 #define DWC3_GUCTL 0xc12c 90 #define DWC3_GBUSERRADDR0 0xc130 91 #define DWC3_GBUSERRADDR1 0xc134 92 #define DWC3_GPRTBIMAP0 0xc138 93 #define DWC3_GPRTBIMAP1 0xc13c 94 #define DWC3_GHWPARAMS0 0xc140 95 #define DWC3_GHWPARAMS1 0xc144 96 #define DWC3_GHWPARAMS2 0xc148 97 #define DWC3_GHWPARAMS3 0xc14c 98 #define DWC3_GHWPARAMS4 0xc150 99 #define DWC3_GHWPARAMS5 0xc154 100 #define DWC3_GHWPARAMS6 0xc158 101 #define DWC3_GHWPARAMS7 0xc15c 102 #define DWC3_GDBGFIFOSPACE 0xc160 103 #define DWC3_GDBGLTSSM 0xc164 104 #define DWC3_GPRTBIMAP_HS0 0xc180 105 #define DWC3_GPRTBIMAP_HS1 0xc184 106 #define DWC3_GPRTBIMAP_FS0 0xc188 107 #define DWC3_GPRTBIMAP_FS1 0xc18c 108 109 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) 110 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) 111 112 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) 113 114 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) 115 116 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) 117 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) 118 119 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) 120 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) 121 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) 122 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) 123 124 #define DWC3_GHWPARAMS8 0xc600 125 126 /* Device Registers */ 127 #define DWC3_DCFG 0xc700 128 #define DWC3_DCTL 0xc704 129 #define DWC3_DEVTEN 0xc708 130 #define DWC3_DSTS 0xc70c 131 #define DWC3_DGCMDPAR 0xc710 132 #define DWC3_DGCMD 0xc714 133 #define DWC3_DALEPENA 0xc720 134 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10)) 135 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10)) 136 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10)) 137 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) 138 139 /* OTG Registers */ 140 #define DWC3_OCFG 0xcc00 141 #define DWC3_OCTL 0xcc04 142 #define DWC3_OEVTEN 0xcc08 143 #define DWC3_OSTS 0xcc0C 144 145 /* Bit fields */ 146 147 /* Global Configuration Register */ 148 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) 149 #define DWC3_GCTL_U2RSTECN (1 << 16) 150 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) 151 #define DWC3_GCTL_CLK_BUS (0) 152 #define DWC3_GCTL_CLK_PIPE (1) 153 #define DWC3_GCTL_CLK_PIPEHALF (2) 154 #define DWC3_GCTL_CLK_MASK (3) 155 156 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) 157 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) 158 #define DWC3_GCTL_PRTCAP_HOST 1 159 #define DWC3_GCTL_PRTCAP_DEVICE 2 160 #define DWC3_GCTL_PRTCAP_OTG 3 161 162 #define DWC3_GCTL_CORESOFTRESET (1 << 11) 163 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) 164 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) 165 #define DWC3_GCTL_DISSCRAMBLE (1 << 3) 166 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) 167 168 /* Global USB2 PHY Configuration Register */ 169 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) 170 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) 171 172 /* Global USB3 PIPE Control Register */ 173 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) 174 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) 175 176 /* Global TX Fifo Size Register */ 177 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) 178 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) 179 180 /* Global HWPARAMS1 Register */ 181 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) 182 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 183 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 184 185 /* Device Configuration Register */ 186 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) 187 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) 188 189 #define DWC3_DCFG_SPEED_MASK (7 << 0) 190 #define DWC3_DCFG_SUPERSPEED (4 << 0) 191 #define DWC3_DCFG_HIGHSPEED (0 << 0) 192 #define DWC3_DCFG_FULLSPEED2 (1 << 0) 193 #define DWC3_DCFG_LOWSPEED (2 << 0) 194 #define DWC3_DCFG_FULLSPEED1 (3 << 0) 195 196 /* Device Control Register */ 197 #define DWC3_DCTL_RUN_STOP (1 << 31) 198 #define DWC3_DCTL_CSFTRST (1 << 30) 199 #define DWC3_DCTL_LSFTRST (1 << 29) 200 201 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) 202 #define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24) 203 204 #define DWC3_DCTL_APPL1RES (1 << 23) 205 206 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) 207 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) 208 209 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) 210 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) 211 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) 212 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) 213 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) 214 215 #define DWC3_DCTL_INITU2ENA (1 << 12) 216 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) 217 #define DWC3_DCTL_INITU1ENA (1 << 10) 218 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) 219 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) 220 221 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) 222 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) 223 224 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) 225 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) 226 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) 227 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) 228 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) 229 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) 230 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) 231 232 /* Device Event Enable Register */ 233 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) 234 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) 235 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) 236 #define DWC3_DEVTEN_ERRTICERREN (1 << 9) 237 #define DWC3_DEVTEN_SOFEN (1 << 7) 238 #define DWC3_DEVTEN_EOPFEN (1 << 6) 239 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) 240 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) 241 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) 242 #define DWC3_DEVTEN_USBRSTEN (1 << 1) 243 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) 244 245 /* Device Status Register */ 246 #define DWC3_DSTS_PWRUPREQ (1 << 24) 247 #define DWC3_DSTS_COREIDLE (1 << 23) 248 #define DWC3_DSTS_DEVCTRLHLT (1 << 22) 249 250 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) 251 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) 252 253 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) 254 255 #define DWC3_DSTS_SOFFN_MASK (0x3ff << 3) 256 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) 257 258 #define DWC3_DSTS_CONNECTSPD (7 << 0) 259 260 #define DWC3_DSTS_SUPERSPEED (4 << 0) 261 #define DWC3_DSTS_HIGHSPEED (0 << 0) 262 #define DWC3_DSTS_FULLSPEED2 (1 << 0) 263 #define DWC3_DSTS_LOWSPEED (2 << 0) 264 #define DWC3_DSTS_FULLSPEED1 (3 << 0) 265 266 /* Device Generic Command Register */ 267 #define DWC3_DGCMD_SET_LMP 0x01 268 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 269 #define DWC3_DGCMD_XMIT_FUNCTION 0x03 270 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 271 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a 272 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c 273 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 274 275 /* Device Endpoint Command Register */ 276 #define DWC3_DEPCMD_PARAM_SHIFT 16 277 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) 278 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) 279 #define DWC3_DEPCMD_STATUS_MASK (0x0f << 12) 280 #define DWC3_DEPCMD_STATUS(x) (((x) & DWC3_DEPCMD_STATUS_MASK) >> 12) 281 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) 282 #define DWC3_DEPCMD_CMDACT (1 << 10) 283 #define DWC3_DEPCMD_CMDIOC (1 << 8) 284 285 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) 286 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) 287 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) 288 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) 289 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) 290 #define DWC3_DEPCMD_SETSTALL (0x04 << 0) 291 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) 292 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) 293 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) 294 295 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ 296 #define DWC3_DALEPENA_EP(n) (1 << n) 297 298 #define DWC3_DEPCMD_TYPE_CONTROL 0 299 #define DWC3_DEPCMD_TYPE_ISOC 1 300 #define DWC3_DEPCMD_TYPE_BULK 2 301 #define DWC3_DEPCMD_TYPE_INTR 3 302 303 /* Structures */ 304 305 struct dwc3_trb; 306 307 /** 308 * struct dwc3_event_buffer - Software event buffer representation 309 * @list: a list of event buffers 310 * @buf: _THE_ buffer 311 * @length: size of this buffer 312 * @dma: dma_addr_t 313 * @dwc: pointer to DWC controller 314 */ 315 struct dwc3_event_buffer { 316 void *buf; 317 unsigned length; 318 unsigned int lpos; 319 320 dma_addr_t dma; 321 322 struct dwc3 *dwc; 323 }; 324 325 #define DWC3_EP_FLAG_STALLED (1 << 0) 326 #define DWC3_EP_FLAG_WEDGED (1 << 1) 327 328 #define DWC3_EP_DIRECTION_TX true 329 #define DWC3_EP_DIRECTION_RX false 330 331 #define DWC3_TRB_NUM 32 332 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) 333 334 /** 335 * struct dwc3_ep - device side endpoint representation 336 * @endpoint: usb endpoint 337 * @request_list: list of requests for this endpoint 338 * @req_queued: list of requests on this ep which have TRBs setup 339 * @trb_pool: array of transaction buffers 340 * @trb_pool_dma: dma address of @trb_pool 341 * @free_slot: next slot which is going to be used 342 * @busy_slot: first slot which is owned by HW 343 * @desc: usb_endpoint_descriptor pointer 344 * @dwc: pointer to DWC controller 345 * @flags: endpoint flags (wedged, stalled, ...) 346 * @current_trb: index of current used trb 347 * @number: endpoint number (1 - 15) 348 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK 349 * @res_trans_idx: Resource transfer index 350 * @interval: the intervall on which the ISOC transfer is started 351 * @name: a human readable name e.g. ep1out-bulk 352 * @direction: true for TX, false for RX 353 * @stream_capable: true when streams are enabled 354 */ 355 struct dwc3_ep { 356 struct usb_ep endpoint; 357 struct list_head request_list; 358 struct list_head req_queued; 359 360 struct dwc3_trb *trb_pool; 361 dma_addr_t trb_pool_dma; 362 u32 free_slot; 363 u32 busy_slot; 364 const struct usb_endpoint_descriptor *desc; 365 const struct usb_ss_ep_comp_descriptor *comp_desc; 366 struct dwc3 *dwc; 367 368 unsigned flags; 369 #define DWC3_EP_ENABLED (1 << 0) 370 #define DWC3_EP_STALL (1 << 1) 371 #define DWC3_EP_WEDGE (1 << 2) 372 #define DWC3_EP_BUSY (1 << 4) 373 #define DWC3_EP_PENDING_REQUEST (1 << 5) 374 375 /* This last one is specific to EP0 */ 376 #define DWC3_EP0_DIR_IN (1 << 31) 377 378 unsigned current_trb; 379 380 u8 number; 381 u8 type; 382 u8 res_trans_idx; 383 u32 interval; 384 385 char name[20]; 386 387 unsigned direction:1; 388 unsigned stream_capable:1; 389 }; 390 391 enum dwc3_phy { 392 DWC3_PHY_UNKNOWN = 0, 393 DWC3_PHY_USB3, 394 DWC3_PHY_USB2, 395 }; 396 397 enum dwc3_ep0_next { 398 DWC3_EP0_UNKNOWN = 0, 399 DWC3_EP0_COMPLETE, 400 DWC3_EP0_NRDY_SETUP, 401 DWC3_EP0_NRDY_DATA, 402 DWC3_EP0_NRDY_STATUS, 403 }; 404 405 enum dwc3_ep0_state { 406 EP0_UNCONNECTED = 0, 407 EP0_SETUP_PHASE, 408 EP0_DATA_PHASE, 409 EP0_STATUS_PHASE, 410 }; 411 412 enum dwc3_link_state { 413 /* In SuperSpeed */ 414 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ 415 DWC3_LINK_STATE_U1 = 0x01, 416 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ 417 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ 418 DWC3_LINK_STATE_SS_DIS = 0x04, 419 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ 420 DWC3_LINK_STATE_SS_INACT = 0x06, 421 DWC3_LINK_STATE_POLL = 0x07, 422 DWC3_LINK_STATE_RECOV = 0x08, 423 DWC3_LINK_STATE_HRESET = 0x09, 424 DWC3_LINK_STATE_CMPLY = 0x0a, 425 DWC3_LINK_STATE_LPBK = 0x0b, 426 DWC3_LINK_STATE_MASK = 0x0f, 427 }; 428 429 enum dwc3_device_state { 430 DWC3_DEFAULT_STATE, 431 DWC3_ADDRESS_STATE, 432 DWC3_CONFIGURED_STATE, 433 }; 434 435 /* TRB Length, PCM and Status */ 436 #define DWC3_TRB_SIZE_MASK (0x00ffffff) 437 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) 438 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) 439 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28) >> 28)) 440 441 #define DWC3_TRBSTS_OK 0 442 #define DWC3_TRBSTS_MISSED_ISOC 1 443 #define DWC3_TRBSTS_SETUP_PENDING 2 444 445 /* TRB Control */ 446 #define DWC3_TRB_CTRL_HWO (1 << 0) 447 #define DWC3_TRB_CTRL_LST (1 << 1) 448 #define DWC3_TRB_CTRL_CHN (1 << 2) 449 #define DWC3_TRB_CTRL_CSP (1 << 3) 450 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) 451 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) 452 #define DWC3_TRB_CTRL_IOC (1 << 11) 453 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) 454 455 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) 456 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) 457 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) 458 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) 459 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) 460 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) 461 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) 462 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) 463 464 /** 465 * struct dwc3_trb - transfer request block (hw format) 466 * @bpl: DW0-3 467 * @bph: DW4-7 468 * @size: DW8-B 469 * @trl: DWC-F 470 */ 471 struct dwc3_trb { 472 u32 bpl; 473 u32 bph; 474 u32 size; 475 u32 ctrl; 476 } __packed; 477 478 /** 479 * dwc3_hwparams - copy of HWPARAMS registers 480 * @hwparams0 - GHWPARAMS0 481 * @hwparams1 - GHWPARAMS1 482 * @hwparams2 - GHWPARAMS2 483 * @hwparams3 - GHWPARAMS3 484 * @hwparams4 - GHWPARAMS4 485 * @hwparams5 - GHWPARAMS5 486 * @hwparams6 - GHWPARAMS6 487 * @hwparams7 - GHWPARAMS7 488 * @hwparams8 - GHWPARAMS8 489 */ 490 struct dwc3_hwparams { 491 u32 hwparams0; 492 u32 hwparams1; 493 u32 hwparams2; 494 u32 hwparams3; 495 u32 hwparams4; 496 u32 hwparams5; 497 u32 hwparams6; 498 u32 hwparams7; 499 u32 hwparams8; 500 }; 501 502 /* HWPARAMS0 */ 503 #define DWC3_MODE(n) ((n) & 0x7) 504 505 #define DWC3_MODE_DEVICE 0 506 #define DWC3_MODE_HOST 1 507 #define DWC3_MODE_DRD 2 508 #define DWC3_MODE_HUB 3 509 510 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) 511 512 /* HWPARAMS1 */ 513 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) 514 515 /* HWPARAMS7 */ 516 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) 517 518 struct dwc3_request { 519 struct usb_request request; 520 struct list_head list; 521 struct dwc3_ep *dep; 522 523 u8 epnum; 524 struct dwc3_trb *trb; 525 dma_addr_t trb_dma; 526 527 unsigned direction:1; 528 unsigned mapped:1; 529 unsigned queued:1; 530 }; 531 532 /** 533 * struct dwc3 - representation of our controller 534 * @ctrl_req: usb control request which is used for ep0 535 * @ep0_trb: trb which is used for the ctrl_req 536 * @ep0_bounce: bounce buffer for ep0 537 * @setup_buf: used while precessing STD USB requests 538 * @ctrl_req_addr: dma address of ctrl_req 539 * @ep0_trb: dma address of ep0_trb 540 * @ep0_usb_req: dummy req used while handling STD USB requests 541 * @ep0_bounce_addr: dma address of ep0_bounce 542 * @lock: for synchronizing 543 * @dev: pointer to our struct device 544 * @xhci: pointer to our xHCI child 545 * @event_buffer_list: a list of event buffers 546 * @gadget: device side representation of the peripheral controller 547 * @gadget_driver: pointer to the gadget driver 548 * @regs: base address for our registers 549 * @regs_size: address space size 550 * @irq: IRQ number 551 * @num_event_buffers: calculated number of event buffers 552 * @u1u2: only used on revisions <1.83a for workaround 553 * @maximum_speed: maximum speed requested (mainly for testing purposes) 554 * @revision: revision register contents 555 * @mode: mode of operation 556 * @is_selfpowered: true when we are selfpowered 557 * @three_stage_setup: set if we perform a three phase setup 558 * @ep0_bounced: true when we used bounce buffer 559 * @ep0_expect_in: true when we expect a DATA IN transfer 560 * @start_config_issued: true when StartConfig command has been issued 561 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround 562 * @needs_fifo_resize: not all users might want fifo resizing, flag it 563 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes. 564 * @ep0_next_event: hold the next expected event 565 * @ep0state: state of endpoint zero 566 * @link_state: link state 567 * @speed: device speed (super, high, full, low) 568 * @mem: points to start of memory which is used for this struct. 569 * @hwparams: copy of hwparams registers 570 * @root: debugfs root folder pointer 571 */ 572 struct dwc3 { 573 struct usb_ctrlrequest *ctrl_req; 574 struct dwc3_trb *ep0_trb; 575 void *ep0_bounce; 576 u8 *setup_buf; 577 dma_addr_t ctrl_req_addr; 578 dma_addr_t ep0_trb_addr; 579 dma_addr_t ep0_bounce_addr; 580 struct dwc3_request ep0_usb_req; 581 /* device lock */ 582 spinlock_t lock; 583 struct device *dev; 584 585 struct platform_device *xhci; 586 struct resource *res; 587 588 struct dwc3_event_buffer **ev_buffs; 589 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; 590 591 struct usb_gadget gadget; 592 struct usb_gadget_driver *gadget_driver; 593 594 void __iomem *regs; 595 size_t regs_size; 596 597 int irq; 598 599 u32 num_event_buffers; 600 u32 u1u2; 601 u32 maximum_speed; 602 u32 revision; 603 u32 mode; 604 605 #define DWC3_REVISION_173A 0x5533173a 606 #define DWC3_REVISION_175A 0x5533175a 607 #define DWC3_REVISION_180A 0x5533180a 608 #define DWC3_REVISION_183A 0x5533183a 609 #define DWC3_REVISION_185A 0x5533185a 610 #define DWC3_REVISION_188A 0x5533188a 611 #define DWC3_REVISION_190A 0x5533190a 612 613 unsigned is_selfpowered:1; 614 unsigned three_stage_setup:1; 615 unsigned ep0_bounced:1; 616 unsigned ep0_expect_in:1; 617 unsigned start_config_issued:1; 618 unsigned setup_packet_pending:1; 619 unsigned delayed_status:1; 620 unsigned needs_fifo_resize:1; 621 unsigned resize_fifos:1; 622 623 enum dwc3_ep0_next ep0_next_event; 624 enum dwc3_ep0_state ep0state; 625 enum dwc3_link_state link_state; 626 enum dwc3_device_state dev_state; 627 628 u8 speed; 629 void *mem; 630 631 struct dwc3_hwparams hwparams; 632 struct dentry *root; 633 634 u8 test_mode; 635 u8 test_mode_nr; 636 }; 637 638 /* -------------------------------------------------------------------------- */ 639 640 /* -------------------------------------------------------------------------- */ 641 642 struct dwc3_event_type { 643 u32 is_devspec:1; 644 u32 type:7; 645 u32 reserved8_31:24; 646 } __packed; 647 648 #define DWC3_DEPEVT_XFERCOMPLETE 0x01 649 #define DWC3_DEPEVT_XFERINPROGRESS 0x02 650 #define DWC3_DEPEVT_XFERNOTREADY 0x03 651 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 652 #define DWC3_DEPEVT_STREAMEVT 0x06 653 #define DWC3_DEPEVT_EPCMDCMPLT 0x07 654 655 /** 656 * struct dwc3_event_depvt - Device Endpoint Events 657 * @one_bit: indicates this is an endpoint event (not used) 658 * @endpoint_number: number of the endpoint 659 * @endpoint_event: The event we have: 660 * 0x00 - Reserved 661 * 0x01 - XferComplete 662 * 0x02 - XferInProgress 663 * 0x03 - XferNotReady 664 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) 665 * 0x05 - Reserved 666 * 0x06 - StreamEvt 667 * 0x07 - EPCmdCmplt 668 * @reserved11_10: Reserved, don't use. 669 * @status: Indicates the status of the event. Refer to databook for 670 * more information. 671 * @parameters: Parameters of the current event. Refer to databook for 672 * more information. 673 */ 674 struct dwc3_event_depevt { 675 u32 one_bit:1; 676 u32 endpoint_number:5; 677 u32 endpoint_event:4; 678 u32 reserved11_10:2; 679 u32 status:4; 680 681 /* Within XferNotReady */ 682 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) 683 684 /* Within XferComplete */ 685 #define DEPEVT_STATUS_BUSERR (1 << 0) 686 #define DEPEVT_STATUS_SHORT (1 << 1) 687 #define DEPEVT_STATUS_IOC (1 << 2) 688 #define DEPEVT_STATUS_LST (1 << 3) 689 690 /* Stream event only */ 691 #define DEPEVT_STREAMEVT_FOUND 1 692 #define DEPEVT_STREAMEVT_NOTFOUND 2 693 694 /* Control-only Status */ 695 #define DEPEVT_STATUS_CONTROL_SETUP 0 696 #define DEPEVT_STATUS_CONTROL_DATA 1 697 #define DEPEVT_STATUS_CONTROL_STATUS 2 698 699 u32 parameters:16; 700 } __packed; 701 702 /** 703 * struct dwc3_event_devt - Device Events 704 * @one_bit: indicates this is a non-endpoint event (not used) 705 * @device_event: indicates it's a device event. Should read as 0x00 706 * @type: indicates the type of device event. 707 * 0 - DisconnEvt 708 * 1 - USBRst 709 * 2 - ConnectDone 710 * 3 - ULStChng 711 * 4 - WkUpEvt 712 * 5 - Reserved 713 * 6 - EOPF 714 * 7 - SOF 715 * 8 - Reserved 716 * 9 - ErrticErr 717 * 10 - CmdCmplt 718 * 11 - EvntOverflow 719 * 12 - VndrDevTstRcved 720 * @reserved15_12: Reserved, not used 721 * @event_info: Information about this event 722 * @reserved31_25: Reserved, not used 723 */ 724 struct dwc3_event_devt { 725 u32 one_bit:1; 726 u32 device_event:7; 727 u32 type:4; 728 u32 reserved15_12:4; 729 u32 event_info:9; 730 u32 reserved31_25:7; 731 } __packed; 732 733 /** 734 * struct dwc3_event_gevt - Other Core Events 735 * @one_bit: indicates this is a non-endpoint event (not used) 736 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. 737 * @phy_port_number: self-explanatory 738 * @reserved31_12: Reserved, not used. 739 */ 740 struct dwc3_event_gevt { 741 u32 one_bit:1; 742 u32 device_event:7; 743 u32 phy_port_number:4; 744 u32 reserved31_12:20; 745 } __packed; 746 747 /** 748 * union dwc3_event - representation of Event Buffer contents 749 * @raw: raw 32-bit event 750 * @type: the type of the event 751 * @depevt: Device Endpoint Event 752 * @devt: Device Event 753 * @gevt: Global Event 754 */ 755 union dwc3_event { 756 u32 raw; 757 struct dwc3_event_type type; 758 struct dwc3_event_depevt depevt; 759 struct dwc3_event_devt devt; 760 struct dwc3_event_gevt gevt; 761 }; 762 763 /* 764 * DWC3 Features to be used as Driver Data 765 */ 766 767 #define DWC3_HAS_PERIPHERAL BIT(0) 768 #define DWC3_HAS_XHCI BIT(1) 769 #define DWC3_HAS_OTG BIT(3) 770 771 /* prototypes */ 772 void dwc3_set_mode(struct dwc3 *dwc, u32 mode); 773 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc); 774 775 int dwc3_host_init(struct dwc3 *dwc); 776 void dwc3_host_exit(struct dwc3 *dwc); 777 778 int dwc3_gadget_init(struct dwc3 *dwc); 779 void dwc3_gadget_exit(struct dwc3 *dwc); 780 781 extern int dwc3_get_device_id(void); 782 extern void dwc3_put_device_id(int id); 783 784 #endif /* __DRIVERS_USB_DWC3_CORE_H */ 785