1 /*
2 * linux/drivers/video/omap2/dss/dss.h
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #ifndef __OMAP2_DSS_H
24 #define __OMAP2_DSS_H
25
26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
27 #define DEBUG
28 #endif
29
30 #ifdef DEBUG
31 extern bool dss_debug;
32 #ifdef DSS_SUBSYS_NAME
33 #define DSSDBG(format, ...) \
34 if (dss_debug) \
35 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
36 ## __VA_ARGS__)
37 #else
38 #define DSSDBG(format, ...) \
39 if (dss_debug) \
40 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
41 #endif
42
43 #ifdef DSS_SUBSYS_NAME
44 #define DSSDBGF(format, ...) \
45 if (dss_debug) \
46 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
47 ": %s(" format ")\n", \
48 __func__, \
49 ## __VA_ARGS__)
50 #else
51 #define DSSDBGF(format, ...) \
52 if (dss_debug) \
53 printk(KERN_DEBUG "omapdss: " \
54 ": %s(" format ")\n", \
55 __func__, \
56 ## __VA_ARGS__)
57 #endif
58
59 #else /* DEBUG */
60 #define DSSDBG(format, ...)
61 #define DSSDBGF(format, ...)
62 #endif
63
64
65 #ifdef DSS_SUBSYS_NAME
66 #define DSSERR(format, ...) \
67 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
68 ## __VA_ARGS__)
69 #else
70 #define DSSERR(format, ...) \
71 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
72 #endif
73
74 #ifdef DSS_SUBSYS_NAME
75 #define DSSINFO(format, ...) \
76 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
77 ## __VA_ARGS__)
78 #else
79 #define DSSINFO(format, ...) \
80 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
81 #endif
82
83 #ifdef DSS_SUBSYS_NAME
84 #define DSSWARN(format, ...) \
85 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
86 ## __VA_ARGS__)
87 #else
88 #define DSSWARN(format, ...) \
89 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
90 #endif
91
92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
93 number. For example 7:0 */
94 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
97 #define FLD_MOD(orig, val, start, end) \
98 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
99
100 enum dss_io_pad_mode {
101 DSS_IO_PAD_MODE_RESET,
102 DSS_IO_PAD_MODE_RFBI,
103 DSS_IO_PAD_MODE_BYPASS,
104 };
105
106 enum dss_hdmi_venc_clk_source_select {
107 DSS_VENC_TV_CLK = 0,
108 DSS_HDMI_M_PCLK = 1,
109 };
110
111 enum dss_dsi_content_type {
112 DSS_DSI_CONTENT_DCS,
113 DSS_DSI_CONTENT_GENERIC,
114 };
115
116 struct dss_clock_info {
117 /* rates that we get with dividers below */
118 unsigned long fck;
119
120 /* dividers */
121 u16 fck_div;
122 };
123
124 struct dispc_clock_info {
125 /* rates that we get with dividers below */
126 unsigned long lck;
127 unsigned long pck;
128
129 /* dividers */
130 u16 lck_div;
131 u16 pck_div;
132 };
133
134 struct dsi_clock_info {
135 /* rates that we get with dividers below */
136 unsigned long fint;
137 unsigned long clkin4ddr;
138 unsigned long clkin;
139 unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK
140 * OMAP4: PLLx_CLK1 */
141 unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK
142 * OMAP4: PLLx_CLK2 */
143 unsigned long lp_clk;
144
145 /* dividers */
146 u16 regn;
147 u16 regm;
148 u16 regm_dispc; /* OMAP3: REGM3
149 * OMAP4: REGM4 */
150 u16 regm_dsi; /* OMAP3: REGM4
151 * OMAP4: REGM5 */
152 u16 lp_clk_div;
153
154 u8 highfreq;
155 bool use_sys_clk;
156 };
157
158 struct seq_file;
159 struct platform_device;
160
161 /* core */
162 struct bus_type *dss_get_bus(void);
163 struct regulator *dss_get_vdds_dsi(void);
164 struct regulator *dss_get_vdds_sdi(void);
165
166 /* apply */
167 void dss_apply_init(void);
168 int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr);
169 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
170 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
171 int omap_dss_mgr_apply(struct omap_overlay_manager *mgr);
172
173 int dss_mgr_enable(struct omap_overlay_manager *mgr);
174 void dss_mgr_disable(struct omap_overlay_manager *mgr);
175 int dss_mgr_set_info(struct omap_overlay_manager *mgr,
176 struct omap_overlay_manager_info *info);
177 void dss_mgr_get_info(struct omap_overlay_manager *mgr,
178 struct omap_overlay_manager_info *info);
179 int dss_mgr_set_device(struct omap_overlay_manager *mgr,
180 struct omap_dss_device *dssdev);
181 int dss_mgr_unset_device(struct omap_overlay_manager *mgr);
182
183 bool dss_ovl_is_enabled(struct omap_overlay *ovl);
184 int dss_ovl_enable(struct omap_overlay *ovl);
185 int dss_ovl_disable(struct omap_overlay *ovl);
186 int dss_ovl_set_info(struct omap_overlay *ovl,
187 struct omap_overlay_info *info);
188 void dss_ovl_get_info(struct omap_overlay *ovl,
189 struct omap_overlay_info *info);
190 int dss_ovl_set_manager(struct omap_overlay *ovl,
191 struct omap_overlay_manager *mgr);
192 int dss_ovl_unset_manager(struct omap_overlay *ovl);
193
194 /* display */
195 int dss_suspend_all_devices(void);
196 int dss_resume_all_devices(void);
197 void dss_disable_all_devices(void);
198
199 void dss_init_device(struct platform_device *pdev,
200 struct omap_dss_device *dssdev);
201 void dss_uninit_device(struct platform_device *pdev,
202 struct omap_dss_device *dssdev);
203 bool dss_use_replication(struct omap_dss_device *dssdev,
204 enum omap_color_mode mode);
205
206 /* manager */
207 int dss_init_overlay_managers(struct platform_device *pdev);
208 void dss_uninit_overlay_managers(struct platform_device *pdev);
209 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
210 const struct omap_overlay_manager_info *info);
211 int dss_mgr_check(struct omap_overlay_manager *mgr,
212 struct omap_dss_device *dssdev,
213 struct omap_overlay_manager_info *info,
214 struct omap_overlay_info **overlay_infos);
215
216 /* overlay */
217 void dss_init_overlays(struct platform_device *pdev);
218 void dss_uninit_overlays(struct platform_device *pdev);
219 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
220 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
221 int dss_ovl_simple_check(struct omap_overlay *ovl,
222 const struct omap_overlay_info *info);
223 int dss_ovl_check(struct omap_overlay *ovl,
224 struct omap_overlay_info *info, struct omap_dss_device *dssdev);
225
226 /* DSS */
227 int dss_init_platform_driver(void);
228 void dss_uninit_platform_driver(void);
229
230 int dss_runtime_get(void);
231 void dss_runtime_put(void);
232
233 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
234 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
235 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
236 void dss_dump_clocks(struct seq_file *s);
237
238 void dss_dump_regs(struct seq_file *s);
239 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
240 void dss_debug_dump_clocks(struct seq_file *s);
241 #endif
242
243 void dss_sdi_init(u8 datapairs);
244 int dss_sdi_enable(void);
245 void dss_sdi_disable(void);
246
247 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
248 void dss_select_dsi_clk_source(int dsi_module,
249 enum omap_dss_clk_source clk_src);
250 void dss_select_lcd_clk_source(enum omap_channel channel,
251 enum omap_dss_clk_source clk_src);
252 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
253 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
254 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
255
256 void dss_set_venc_output(enum omap_dss_venc_type type);
257 void dss_set_dac_pwrdn_bgz(bool enable);
258
259 unsigned long dss_get_dpll4_rate(void);
260 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
261 int dss_set_clock_div(struct dss_clock_info *cinfo);
262 int dss_get_clock_div(struct dss_clock_info *cinfo);
263 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
264 struct dss_clock_info *dss_cinfo,
265 struct dispc_clock_info *dispc_cinfo);
266
267 /* SDI */
268 #ifdef CONFIG_OMAP2_DSS_SDI
269 int sdi_init(void);
270 void sdi_exit(void);
271 int sdi_init_display(struct omap_dss_device *display);
272 #else
sdi_init(void)273 static inline int sdi_init(void)
274 {
275 return 0;
276 }
sdi_exit(void)277 static inline void sdi_exit(void)
278 {
279 }
280 #endif
281
282 /* DSI */
283 #ifdef CONFIG_OMAP2_DSS_DSI
284
285 struct dentry;
286 struct file_operations;
287
288 int dsi_init_platform_driver(void);
289 void dsi_uninit_platform_driver(void);
290
291 int dsi_runtime_get(struct platform_device *dsidev);
292 void dsi_runtime_put(struct platform_device *dsidev);
293
294 void dsi_dump_clocks(struct seq_file *s);
295 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
296 const struct file_operations *debug_fops);
297 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
298 const struct file_operations *debug_fops);
299
300 int dsi_init_display(struct omap_dss_device *display);
301 void dsi_irq_handler(void);
302 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
303
304 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
305 int dsi_pll_set_clock_div(struct platform_device *dsidev,
306 struct dsi_clock_info *cinfo);
307 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
308 unsigned long req_pck, struct dsi_clock_info *cinfo,
309 struct dispc_clock_info *dispc_cinfo);
310 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
311 bool enable_hsdiv);
312 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
313 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
314 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
315 struct platform_device *dsi_get_dsidev_from_id(int module);
316 #else
dsi_init_platform_driver(void)317 static inline int dsi_init_platform_driver(void)
318 {
319 return 0;
320 }
dsi_uninit_platform_driver(void)321 static inline void dsi_uninit_platform_driver(void)
322 {
323 }
dsi_runtime_get(struct platform_device * dsidev)324 static inline int dsi_runtime_get(struct platform_device *dsidev)
325 {
326 return 0;
327 }
dsi_runtime_put(struct platform_device * dsidev)328 static inline void dsi_runtime_put(struct platform_device *dsidev)
329 {
330 }
dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)331 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
332 {
333 WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
334 return 0;
335 }
dsi_get_pll_hsdiv_dispc_rate(struct platform_device * dsidev)336 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
337 {
338 WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
339 return 0;
340 }
dsi_pll_set_clock_div(struct platform_device * dsidev,struct dsi_clock_info * cinfo)341 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
342 struct dsi_clock_info *cinfo)
343 {
344 WARN("%s: DSI not compiled in\n", __func__);
345 return -ENODEV;
346 }
dsi_pll_calc_clock_div_pck(struct platform_device * dsidev,bool is_tft,unsigned long req_pck,struct dsi_clock_info * dsi_cinfo,struct dispc_clock_info * dispc_cinfo)347 static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
348 bool is_tft, unsigned long req_pck,
349 struct dsi_clock_info *dsi_cinfo,
350 struct dispc_clock_info *dispc_cinfo)
351 {
352 WARN("%s: DSI not compiled in\n", __func__);
353 return -ENODEV;
354 }
dsi_pll_init(struct platform_device * dsidev,bool enable_hsclk,bool enable_hsdiv)355 static inline int dsi_pll_init(struct platform_device *dsidev,
356 bool enable_hsclk, bool enable_hsdiv)
357 {
358 WARN("%s: DSI not compiled in\n", __func__);
359 return -ENODEV;
360 }
dsi_pll_uninit(struct platform_device * dsidev,bool disconnect_lanes)361 static inline void dsi_pll_uninit(struct platform_device *dsidev,
362 bool disconnect_lanes)
363 {
364 }
dsi_wait_pll_hsdiv_dispc_active(struct platform_device * dsidev)365 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
366 {
367 }
dsi_wait_pll_hsdiv_dsi_active(struct platform_device * dsidev)368 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
369 {
370 }
dsi_get_dsidev_from_id(int module)371 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
372 {
373 WARN("%s: DSI not compiled in, returning platform device as NULL\n",
374 __func__);
375 return NULL;
376 }
377 #endif
378
379 /* DPI */
380 #ifdef CONFIG_OMAP2_DSS_DPI
381 int dpi_init(void);
382 void dpi_exit(void);
383 int dpi_init_display(struct omap_dss_device *dssdev);
384 #else
dpi_init(void)385 static inline int dpi_init(void)
386 {
387 return 0;
388 }
dpi_exit(void)389 static inline void dpi_exit(void)
390 {
391 }
392 #endif
393
394 /* DISPC */
395 int dispc_init_platform_driver(void);
396 void dispc_uninit_platform_driver(void);
397 void dispc_dump_clocks(struct seq_file *s);
398 void dispc_dump_irqs(struct seq_file *s);
399 void dispc_dump_regs(struct seq_file *s);
400 void dispc_irq_handler(void);
401 void dispc_fake_vsync_irq(void);
402
403 int dispc_runtime_get(void);
404 void dispc_runtime_put(void);
405
406 void dispc_enable_sidle(void);
407 void dispc_disable_sidle(void);
408
409 void dispc_lcd_enable_signal_polarity(bool act_high);
410 void dispc_lcd_enable_signal(bool enable);
411 void dispc_pck_free_enable(bool enable);
412 void dispc_set_digit_size(u16 width, u16 height);
413 void dispc_enable_fifomerge(bool enable);
414 void dispc_enable_gamma_table(bool enable);
415 void dispc_set_loadmode(enum omap_dss_load_mode mode);
416
417 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
418 unsigned long dispc_fclk_rate(void);
419 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
420 struct dispc_clock_info *cinfo);
421 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
422 struct dispc_clock_info *cinfo);
423
424
425 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
426 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
427 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
428 bool manual_update);
429 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
430 bool ilace, bool replication);
431 int dispc_ovl_enable(enum omap_plane plane, bool enable);
432 void dispc_ovl_set_channel_out(enum omap_plane plane,
433 enum omap_channel channel);
434
435 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable);
436 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
437 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
438 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
439 bool dispc_mgr_go_busy(enum omap_channel channel);
440 void dispc_mgr_go(enum omap_channel channel);
441 bool dispc_mgr_is_enabled(enum omap_channel channel);
442 void dispc_mgr_enable(enum omap_channel channel, bool enable);
443 bool dispc_mgr_is_channel_enabled(enum omap_channel channel);
444 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode);
445 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable);
446 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
447 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
448 enum omap_lcd_display_type type);
449 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
450 struct omap_video_timings *timings);
451 void dispc_mgr_set_pol_freq(enum omap_channel channel,
452 enum omap_panel_config config, u8 acbi, u8 acb);
453 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
454 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
455 int dispc_mgr_set_clock_div(enum omap_channel channel,
456 struct dispc_clock_info *cinfo);
457 int dispc_mgr_get_clock_div(enum omap_channel channel,
458 struct dispc_clock_info *cinfo);
459 void dispc_mgr_setup(enum omap_channel channel,
460 struct omap_overlay_manager_info *info);
461
462 /* VENC */
463 #ifdef CONFIG_OMAP2_DSS_VENC
464 int venc_init_platform_driver(void);
465 void venc_uninit_platform_driver(void);
466 void venc_dump_regs(struct seq_file *s);
467 int venc_init_display(struct omap_dss_device *display);
468 unsigned long venc_get_pixel_clock(void);
469 #else
venc_init_platform_driver(void)470 static inline int venc_init_platform_driver(void)
471 {
472 return 0;
473 }
venc_uninit_platform_driver(void)474 static inline void venc_uninit_platform_driver(void)
475 {
476 }
venc_get_pixel_clock(void)477 static inline unsigned long venc_get_pixel_clock(void)
478 {
479 WARN("%s: VENC not compiled in, returning pclk as 0\n", __func__);
480 return 0;
481 }
482 #endif
483
484 /* HDMI */
485 #ifdef CONFIG_OMAP4_DSS_HDMI
486 int hdmi_init_platform_driver(void);
487 void hdmi_uninit_platform_driver(void);
488 int hdmi_init_display(struct omap_dss_device *dssdev);
489 unsigned long hdmi_get_pixel_clock(void);
490 void hdmi_dump_regs(struct seq_file *s);
491 #else
hdmi_init_display(struct omap_dss_device * dssdev)492 static inline int hdmi_init_display(struct omap_dss_device *dssdev)
493 {
494 return 0;
495 }
hdmi_init_platform_driver(void)496 static inline int hdmi_init_platform_driver(void)
497 {
498 return 0;
499 }
hdmi_uninit_platform_driver(void)500 static inline void hdmi_uninit_platform_driver(void)
501 {
502 }
hdmi_get_pixel_clock(void)503 static inline unsigned long hdmi_get_pixel_clock(void)
504 {
505 WARN("%s: HDMI not compiled in, returning pclk as 0\n", __func__);
506 return 0;
507 }
508 #endif
509 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
510 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
511 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev);
512 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
513 struct omap_video_timings *timings);
514 int omapdss_hdmi_read_edid(u8 *buf, int len);
515 bool omapdss_hdmi_detect(void);
516 int hdmi_panel_init(void);
517 void hdmi_panel_exit(void);
518
519 /* RFBI */
520 #ifdef CONFIG_OMAP2_DSS_RFBI
521 int rfbi_init_platform_driver(void);
522 void rfbi_uninit_platform_driver(void);
523 void rfbi_dump_regs(struct seq_file *s);
524 int rfbi_init_display(struct omap_dss_device *display);
525 #else
rfbi_init_platform_driver(void)526 static inline int rfbi_init_platform_driver(void)
527 {
528 return 0;
529 }
rfbi_uninit_platform_driver(void)530 static inline void rfbi_uninit_platform_driver(void)
531 {
532 }
533 #endif
534
535
536 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
dss_collect_irq_stats(u32 irqstatus,unsigned * irq_arr)537 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
538 {
539 int b;
540 for (b = 0; b < 32; ++b) {
541 if (irqstatus & (1 << b))
542 irq_arr[b]++;
543 }
544 }
545 #endif
546
547 #endif
548