1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2009 Nokia Corporation
4  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5  *
6  * Some code and ideas taken from drivers/video/omap/ driver
7  * by Imre Deak.
8  */
9 
10 #ifndef __OMAP2_DSS_H
11 #define __OMAP2_DSS_H
12 
13 #include <linux/interrupt.h>
14 
15 #include "omapdss.h"
16 
17 struct dispc_device;
18 struct dss_debugfs_entry;
19 struct platform_device;
20 struct seq_file;
21 
22 #define MAX_DSS_LCD_MANAGERS	3
23 #define MAX_NUM_DSI		2
24 
25 #ifdef pr_fmt
26 #undef pr_fmt
27 #endif
28 
29 #ifdef DSS_SUBSYS_NAME
30 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
31 #else
32 #define pr_fmt(fmt) fmt
33 #endif
34 
35 #define DSSDBG(format, ...) \
36 	pr_debug(format, ## __VA_ARGS__)
37 
38 #ifdef DSS_SUBSYS_NAME
39 #define DSSERR(format, ...) \
40 	pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__)
41 #else
42 #define DSSERR(format, ...) \
43 	pr_err("omapdss error: " format, ##__VA_ARGS__)
44 #endif
45 
46 #ifdef DSS_SUBSYS_NAME
47 #define DSSINFO(format, ...) \
48 	pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
49 #else
50 #define DSSINFO(format, ...) \
51 	pr_info("omapdss: " format, ## __VA_ARGS__)
52 #endif
53 
54 #ifdef DSS_SUBSYS_NAME
55 #define DSSWARN(format, ...) \
56 	pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
57 #else
58 #define DSSWARN(format, ...) \
59 	pr_warn("omapdss: " format, ##__VA_ARGS__)
60 #endif
61 
62 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
63    number. For example 7:0 */
64 #define FLD_MASK(start, end)	(((1 << ((start) - (end) + 1)) - 1) << (end))
65 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
66 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
67 #define FLD_MOD(orig, val, start, end) \
68 	(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
69 
70 enum dss_model {
71 	DSS_MODEL_OMAP2,
72 	DSS_MODEL_OMAP3,
73 	DSS_MODEL_OMAP4,
74 	DSS_MODEL_OMAP5,
75 	DSS_MODEL_DRA7,
76 };
77 
78 enum dss_io_pad_mode {
79 	DSS_IO_PAD_MODE_RESET,
80 	DSS_IO_PAD_MODE_RFBI,
81 	DSS_IO_PAD_MODE_BYPASS,
82 };
83 
84 enum dss_hdmi_venc_clk_source_select {
85 	DSS_VENC_TV_CLK = 0,
86 	DSS_HDMI_M_PCLK = 1,
87 };
88 
89 enum dss_dsi_content_type {
90 	DSS_DSI_CONTENT_DCS,
91 	DSS_DSI_CONTENT_GENERIC,
92 };
93 
94 enum dss_clk_source {
95 	DSS_CLK_SRC_FCK = 0,
96 
97 	DSS_CLK_SRC_PLL1_1,
98 	DSS_CLK_SRC_PLL1_2,
99 	DSS_CLK_SRC_PLL1_3,
100 
101 	DSS_CLK_SRC_PLL2_1,
102 	DSS_CLK_SRC_PLL2_2,
103 	DSS_CLK_SRC_PLL2_3,
104 
105 	DSS_CLK_SRC_HDMI_PLL,
106 };
107 
108 enum dss_pll_id {
109 	DSS_PLL_DSI1,
110 	DSS_PLL_DSI2,
111 	DSS_PLL_HDMI,
112 	DSS_PLL_VIDEO1,
113 	DSS_PLL_VIDEO2,
114 };
115 
116 struct dss_pll;
117 
118 #define DSS_PLL_MAX_HSDIVS 4
119 
120 enum dss_pll_type {
121 	DSS_PLL_TYPE_A,
122 	DSS_PLL_TYPE_B,
123 };
124 
125 /*
126  * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
127  * Type-B PLLs: clkout[0] refers to m2.
128  */
129 struct dss_pll_clock_info {
130 	/* rates that we get with dividers below */
131 	unsigned long fint;
132 	unsigned long clkdco;
133 	unsigned long clkout[DSS_PLL_MAX_HSDIVS];
134 
135 	/* dividers */
136 	u16 n;
137 	u16 m;
138 	u32 mf;
139 	u16 mX[DSS_PLL_MAX_HSDIVS];
140 	u16 sd;
141 };
142 
143 struct dss_pll_ops {
144 	int (*enable)(struct dss_pll *pll);
145 	void (*disable)(struct dss_pll *pll);
146 	int (*set_config)(struct dss_pll *pll,
147 		const struct dss_pll_clock_info *cinfo);
148 };
149 
150 struct dss_pll_hw {
151 	enum dss_pll_type type;
152 
153 	unsigned int n_max;
154 	unsigned int m_min;
155 	unsigned int m_max;
156 	unsigned int mX_max;
157 
158 	unsigned long fint_min, fint_max;
159 	unsigned long clkdco_min, clkdco_low, clkdco_max;
160 
161 	u8 n_msb, n_lsb;
162 	u8 m_msb, m_lsb;
163 	u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
164 
165 	bool has_stopmode;
166 	bool has_freqsel;
167 	bool has_selfreqdco;
168 	bool has_refsel;
169 
170 	/* DRA7 errata i886: use high N & M to avoid jitter */
171 	bool errata_i886;
172 
173 	/* DRA7 errata i932: retry pll lock on failure */
174 	bool errata_i932;
175 };
176 
177 struct dss_pll {
178 	const char *name;
179 	enum dss_pll_id id;
180 	struct dss_device *dss;
181 
182 	struct clk *clkin;
183 	struct regulator *regulator;
184 
185 	void __iomem *base;
186 
187 	const struct dss_pll_hw *hw;
188 
189 	const struct dss_pll_ops *ops;
190 
191 	struct dss_pll_clock_info cinfo;
192 };
193 
194 /* Defines a generic omap register field */
195 struct dss_reg_field {
196 	u8 start, end;
197 };
198 
199 struct dispc_clock_info {
200 	/* rates that we get with dividers below */
201 	unsigned long lck;
202 	unsigned long pck;
203 
204 	/* dividers */
205 	u16 lck_div;
206 	u16 pck_div;
207 };
208 
209 struct dss_lcd_mgr_config {
210 	enum dss_io_pad_mode io_pad_mode;
211 
212 	bool stallmode;
213 	bool fifohandcheck;
214 
215 	struct dispc_clock_info clock_info;
216 
217 	int video_port_width;
218 
219 	int lcden_sig_polarity;
220 };
221 
222 #define DSS_SZ_REGS			SZ_512
223 
224 struct dss_device {
225 	struct platform_device *pdev;
226 	void __iomem    *base;
227 	struct regmap	*syscon_pll_ctrl;
228 	u32		syscon_pll_ctrl_offset;
229 
230 	struct platform_device *drm_pdev;
231 
232 	struct clk	*parent_clk;
233 	struct clk	*dss_clk;
234 	unsigned long	dss_clk_rate;
235 
236 	unsigned long	cache_req_pck;
237 	unsigned long	cache_prate;
238 	struct dispc_clock_info cache_dispc_cinfo;
239 
240 	enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
241 	enum dss_clk_source dispc_clk_source;
242 	enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
243 
244 	bool		ctx_valid;
245 	u32		ctx[DSS_SZ_REGS / sizeof(u32)];
246 
247 	const struct dss_features *feat;
248 
249 	struct {
250 		struct dentry *root;
251 		struct dss_debugfs_entry *clk;
252 		struct dss_debugfs_entry *dss;
253 	} debugfs;
254 
255 	struct dss_pll *plls[4];
256 	struct dss_pll	*video1_pll;
257 	struct dss_pll	*video2_pll;
258 
259 	struct dispc_device *dispc;
260 	struct omap_drm_private *mgr_ops_priv;
261 };
262 
263 /* core */
dss_set_min_bus_tput(struct device * dev,unsigned long tput)264 static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput)
265 {
266 	/* To be implemented when the OMAP platform will provide this feature */
267 	return 0;
268 }
269 
dss_mgr_is_lcd(enum omap_channel id)270 static inline bool dss_mgr_is_lcd(enum omap_channel id)
271 {
272 	if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
273 			id == OMAP_DSS_CHANNEL_LCD3)
274 		return true;
275 	else
276 		return false;
277 }
278 
279 /* DSS */
280 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
281 struct dss_debugfs_entry *
282 dss_debugfs_create_file(struct dss_device *dss, const char *name,
283 			int (*show_fn)(struct seq_file *s, void *data),
284 			void *data);
285 void dss_debugfs_remove_file(struct dss_debugfs_entry *entry);
286 #else
287 static inline struct dss_debugfs_entry *
dss_debugfs_create_file(struct dss_device * dss,const char * name,int (* show_fn)(struct seq_file * s,void * data),void * data)288 dss_debugfs_create_file(struct dss_device *dss, const char *name,
289 			int (*show_fn)(struct seq_file *s, void *data),
290 			void *data)
291 {
292 	return NULL;
293 }
294 
dss_debugfs_remove_file(struct dss_debugfs_entry * entry)295 static inline void dss_debugfs_remove_file(struct dss_debugfs_entry *entry)
296 {
297 }
298 #endif /* CONFIG_OMAP2_DSS_DEBUGFS */
299 
300 struct dss_device *dss_get_device(struct device *dev);
301 
302 int dss_runtime_get(struct dss_device *dss);
303 void dss_runtime_put(struct dss_device *dss);
304 
305 unsigned long dss_get_dispc_clk_rate(struct dss_device *dss);
306 unsigned long dss_get_max_fck_rate(struct dss_device *dss);
307 int dss_dpi_select_source(struct dss_device *dss, int port,
308 			  enum omap_channel channel);
309 void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
310 				     enum dss_hdmi_venc_clk_source_select src);
311 const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
312 
313 /* DSS VIDEO PLL */
314 struct dss_pll *dss_video_pll_init(struct dss_device *dss,
315 				   struct platform_device *pdev, int id,
316 				   struct regulator *regulator);
317 void dss_video_pll_uninit(struct dss_pll *pll);
318 
319 void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable);
320 
321 void dss_sdi_init(struct dss_device *dss, int datapairs);
322 int dss_sdi_enable(struct dss_device *dss);
323 void dss_sdi_disable(struct dss_device *dss);
324 
325 void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
326 			       enum dss_clk_source clk_src);
327 void dss_select_lcd_clk_source(struct dss_device *dss,
328 			       enum omap_channel channel,
329 			       enum dss_clk_source clk_src);
330 enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss);
331 enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss,
332 					   int dsi_module);
333 enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss,
334 					   enum omap_channel channel);
335 
336 void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type);
337 void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable);
338 
339 int dss_set_fck_rate(struct dss_device *dss, unsigned long rate);
340 
341 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
342 bool dss_div_calc(struct dss_device *dss, unsigned long pck,
343 		  unsigned long fck_min, dss_div_calc_func func, void *data);
344 
345 /* SDI */
346 #ifdef CONFIG_OMAP2_DSS_SDI
347 int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
348 		  struct device_node *port);
349 void sdi_uninit_port(struct device_node *port);
350 #else
sdi_init_port(struct dss_device * dss,struct platform_device * pdev,struct device_node * port)351 static inline int sdi_init_port(struct dss_device *dss,
352 				struct platform_device *pdev,
353 				struct device_node *port)
354 {
355 	return 0;
356 }
sdi_uninit_port(struct device_node * port)357 static inline void sdi_uninit_port(struct device_node *port)
358 {
359 }
360 #endif
361 
362 /* DSI */
363 
364 #ifdef CONFIG_OMAP2_DSS_DSI
365 
366 void dsi_irq_handler(void);
367 
368 #endif
369 
370 /* DPI */
371 #ifdef CONFIG_OMAP2_DSS_DPI
372 int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
373 		  struct device_node *port, enum dss_model dss_model);
374 void dpi_uninit_port(struct device_node *port);
375 #else
dpi_init_port(struct dss_device * dss,struct platform_device * pdev,struct device_node * port,enum dss_model dss_model)376 static inline int dpi_init_port(struct dss_device *dss,
377 				struct platform_device *pdev,
378 				struct device_node *port,
379 				enum dss_model dss_model)
380 {
381 	return 0;
382 }
dpi_uninit_port(struct device_node * port)383 static inline void dpi_uninit_port(struct device_node *port)
384 {
385 }
386 #endif
387 
388 /* DISPC */
389 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s);
390 
391 int dispc_runtime_get(struct dispc_device *dispc);
392 void dispc_runtime_put(struct dispc_device *dispc);
393 
394 int dispc_get_num_ovls(struct dispc_device *dispc);
395 int dispc_get_num_mgrs(struct dispc_device *dispc);
396 
397 const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc,
398 					    enum omap_plane_id plane);
399 
400 void dispc_ovl_get_max_size(struct dispc_device *dispc, u16 *width, u16 *height);
401 bool dispc_ovl_color_mode_supported(struct dispc_device *dispc,
402 				    enum omap_plane_id plane, u32 fourcc);
403 enum omap_overlay_caps dispc_ovl_get_caps(struct dispc_device *dispc, enum omap_plane_id plane);
404 
405 u32 dispc_read_irqstatus(struct dispc_device *dispc);
406 void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask);
407 void dispc_write_irqenable(struct dispc_device *dispc, u32 mask);
408 
409 int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler,
410 			     void *dev_id);
411 void dispc_free_irq(struct dispc_device *dispc, void *dev_id);
412 
413 u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc,
414 				   enum omap_channel channel);
415 u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc,
416 				       enum omap_channel channel);
417 u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc,
418 				       enum omap_channel channel);
419 u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc);
420 
421 u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc);
422 
423 void dispc_mgr_enable(struct dispc_device *dispc,
424 			     enum omap_channel channel, bool enable);
425 
426 bool dispc_mgr_go_busy(struct dispc_device *dispc,
427 			      enum omap_channel channel);
428 
429 void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel);
430 
431 void dispc_mgr_set_lcd_config(struct dispc_device *dispc,
432 				     enum omap_channel channel,
433 				     const struct dss_lcd_mgr_config *config);
434 void dispc_mgr_set_timings(struct dispc_device *dispc,
435 				  enum omap_channel channel,
436 				  const struct videomode *vm);
437 void dispc_mgr_setup(struct dispc_device *dispc,
438 			    enum omap_channel channel,
439 			    const struct omap_overlay_manager_info *info);
440 
441 int dispc_mgr_check_timings(struct dispc_device *dispc,
442 				   enum omap_channel channel,
443 				   const struct videomode *vm);
444 
445 u32 dispc_mgr_gamma_size(struct dispc_device *dispc,
446 				enum omap_channel channel);
447 void dispc_mgr_set_gamma(struct dispc_device *dispc,
448 				enum omap_channel channel,
449 				const struct drm_color_lut *lut,
450 				unsigned int length);
451 
452 int dispc_ovl_setup(struct dispc_device *dispc,
453 			   enum omap_plane_id plane,
454 			   const struct omap_overlay_info *oi,
455 			   const struct videomode *vm, bool mem_to_mem,
456 			   enum omap_channel channel);
457 
458 int dispc_ovl_enable(struct dispc_device *dispc,
459 			    enum omap_plane_id plane, bool enable);
460 
461 bool dispc_has_writeback(struct dispc_device *dispc);
462 int dispc_wb_setup(struct dispc_device *dispc,
463 		   const struct omap_dss_writeback_info *wi,
464 		   bool mem_to_mem, const struct videomode *vm,
465 		   enum dss_writeback_channel channel_in);
466 bool dispc_wb_go_busy(struct dispc_device *dispc);
467 void dispc_wb_go(struct dispc_device *dispc);
468 
469 void dispc_enable_sidle(struct dispc_device *dispc);
470 void dispc_disable_sidle(struct dispc_device *dispc);
471 
472 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable);
473 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable);
474 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable);
475 
476 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
477 		unsigned long pck, void *data);
478 bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq,
479 		    unsigned long pck_min, unsigned long pck_max,
480 		    dispc_div_calc_func func, void *data);
481 
482 int dispc_calc_clock_rates(struct dispc_device *dispc,
483 			   unsigned long dispc_fclk_rate,
484 			   struct dispc_clock_info *cinfo);
485 
486 
487 void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc,
488 				  enum omap_plane_id plane, u32 low, u32 high);
489 void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc,
490 				       enum omap_plane_id plane,
491 				       u32 *fifo_low, u32 *fifo_high,
492 				       bool use_fifomerge, bool manual_update);
493 
494 void dispc_mgr_set_clock_div(struct dispc_device *dispc,
495 			     enum omap_channel channel,
496 			     const struct dispc_clock_info *cinfo);
497 int dispc_mgr_get_clock_div(struct dispc_device *dispc,
498 			    enum omap_channel channel,
499 			    struct dispc_clock_info *cinfo);
500 void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk);
501 
502 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
dss_collect_irq_stats(u32 irqstatus,unsigned int * irq_arr)503 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned int *irq_arr)
504 {
505 	int b;
506 	for (b = 0; b < 32; ++b) {
507 		if (irqstatus & (1 << b))
508 			irq_arr[b]++;
509 	}
510 }
511 #endif
512 
513 /* PLL */
514 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
515 		unsigned long clkdco, void *data);
516 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
517 		void *data);
518 
519 int dss_pll_register(struct dss_device *dss, struct dss_pll *pll);
520 void dss_pll_unregister(struct dss_pll *pll);
521 struct dss_pll *dss_pll_find(struct dss_device *dss, const char *name);
522 struct dss_pll *dss_pll_find_by_src(struct dss_device *dss,
523 				    enum dss_clk_source src);
524 unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
525 int dss_pll_enable(struct dss_pll *pll);
526 void dss_pll_disable(struct dss_pll *pll);
527 int dss_pll_set_config(struct dss_pll *pll,
528 		const struct dss_pll_clock_info *cinfo);
529 
530 bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
531 		unsigned long out_min, unsigned long out_max,
532 		dss_hsdiv_calc_func func, void *data);
533 bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
534 		unsigned long pll_min, unsigned long pll_max,
535 		dss_pll_calc_func func, void *data);
536 
537 bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
538 	unsigned long target_clkout, struct dss_pll_clock_info *cinfo);
539 
540 int dss_pll_write_config_type_a(struct dss_pll *pll,
541 		const struct dss_pll_clock_info *cinfo);
542 int dss_pll_write_config_type_b(struct dss_pll *pll,
543 		const struct dss_pll_clock_info *cinfo);
544 int dss_pll_wait_reset_done(struct dss_pll *pll);
545 
546 extern struct platform_driver omap_dsshw_driver;
547 extern struct platform_driver omap_dispchw_driver;
548 #ifdef CONFIG_OMAP2_DSS_DSI
549 extern struct platform_driver omap_dsihw_driver;
550 #endif
551 #ifdef CONFIG_OMAP2_DSS_VENC
552 extern struct platform_driver omap_venchw_driver;
553 #endif
554 #ifdef CONFIG_OMAP4_DSS_HDMI
555 extern struct platform_driver omapdss_hdmi4hw_driver;
556 #endif
557 #ifdef CONFIG_OMAP5_DSS_HDMI
558 extern struct platform_driver omapdss_hdmi5hw_driver;
559 #endif
560 
561 #endif
562