1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /*
3  * Copyright 2013-2016 Freescale Semiconductor Inc.
4  * Copyright 2017-2018 NXP
5  */
6 
7 #ifndef _DPSECI_CMD_H_
8 #define _DPSECI_CMD_H_
9 
10 /* DPSECI Version */
11 #define DPSECI_VER_MAJOR				5
12 #define DPSECI_VER_MINOR				3
13 
14 #define DPSECI_VER(maj, min)	(((maj) << 16) | (min))
15 #define DPSECI_VERSION		DPSECI_VER(DPSECI_VER_MAJOR, DPSECI_VER_MINOR)
16 
17 /* Command versioning */
18 #define DPSECI_CMD_BASE_VERSION		1
19 #define DPSECI_CMD_BASE_VERSION_V2	2
20 #define DPSECI_CMD_ID_OFFSET		4
21 
22 #define DPSECI_CMD_V1(id)	(((id) << DPSECI_CMD_ID_OFFSET) | \
23 				 DPSECI_CMD_BASE_VERSION)
24 
25 #define DPSECI_CMD_V2(id)	(((id) << DPSECI_CMD_ID_OFFSET) | \
26 				 DPSECI_CMD_BASE_VERSION_V2)
27 
28 /* Command IDs */
29 #define DPSECI_CMDID_CLOSE				DPSECI_CMD_V1(0x800)
30 #define DPSECI_CMDID_OPEN				DPSECI_CMD_V1(0x809)
31 #define DPSECI_CMDID_GET_API_VERSION			DPSECI_CMD_V1(0xa09)
32 
33 #define DPSECI_CMDID_ENABLE				DPSECI_CMD_V1(0x002)
34 #define DPSECI_CMDID_DISABLE				DPSECI_CMD_V1(0x003)
35 #define DPSECI_CMDID_GET_ATTR				DPSECI_CMD_V1(0x004)
36 #define DPSECI_CMDID_RESET				DPSECI_CMD_V1(0x005)
37 #define DPSECI_CMDID_IS_ENABLED				DPSECI_CMD_V1(0x006)
38 
39 #define DPSECI_CMDID_SET_RX_QUEUE			DPSECI_CMD_V1(0x194)
40 #define DPSECI_CMDID_GET_RX_QUEUE			DPSECI_CMD_V1(0x196)
41 #define DPSECI_CMDID_GET_TX_QUEUE			DPSECI_CMD_V1(0x197)
42 #define DPSECI_CMDID_GET_SEC_ATTR			DPSECI_CMD_V2(0x198)
43 #define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION	DPSECI_CMD_V1(0x170)
44 #define DPSECI_CMDID_GET_CONGESTION_NOTIFICATION	DPSECI_CMD_V1(0x171)
45 
46 /* Macros for accessing command fields smaller than 1 byte */
47 #define DPSECI_MASK(field)	\
48 	GENMASK(DPSECI_##field##_SHIFT + DPSECI_##field##_SIZE - 1,	\
49 		DPSECI_##field##_SHIFT)
50 
51 #define dpseci_set_field(var, field, val)	\
52 	((var) |= (((val) << DPSECI_##field##_SHIFT) & DPSECI_MASK(field)))
53 
54 #define dpseci_get_field(var, field)	\
55 	(((var) & DPSECI_MASK(field)) >> DPSECI_##field##_SHIFT)
56 
57 struct dpseci_cmd_open {
58 	__le32 dpseci_id;
59 };
60 
61 #define DPSECI_ENABLE_SHIFT	0
62 #define DPSECI_ENABLE_SIZE	1
63 
64 struct dpseci_rsp_is_enabled {
65 	u8 is_enabled;
66 };
67 
68 struct dpseci_rsp_get_attributes {
69 	__le32 id;
70 	__le32 pad0;
71 	u8 num_tx_queues;
72 	u8 num_rx_queues;
73 	u8 pad1[6];
74 	__le32 options;
75 };
76 
77 #define DPSECI_DEST_TYPE_SHIFT	0
78 #define DPSECI_DEST_TYPE_SIZE	4
79 
80 #define DPSECI_ORDER_PRESERVATION_SHIFT	0
81 #define DPSECI_ORDER_PRESERVATION_SIZE	1
82 
83 struct dpseci_cmd_queue {
84 	__le32 dest_id;
85 	u8 priority;
86 	u8 queue;
87 	u8 dest_type;
88 	u8 pad;
89 	__le64 user_ctx;
90 	union {
91 		__le32 options;
92 		__le32 fqid;
93 	};
94 	u8 order_preservation_en;
95 };
96 
97 struct dpseci_rsp_get_tx_queue {
98 	__le32 pad;
99 	__le32 fqid;
100 	u8 priority;
101 };
102 
103 struct dpseci_rsp_get_sec_attr {
104 	__le16 ip_id;
105 	u8 major_rev;
106 	u8 minor_rev;
107 	u8 era;
108 	u8 pad0[3];
109 	u8 deco_num;
110 	u8 zuc_auth_acc_num;
111 	u8 zuc_enc_acc_num;
112 	u8 pad1;
113 	u8 snow_f8_acc_num;
114 	u8 snow_f9_acc_num;
115 	u8 crc_acc_num;
116 	u8 pad2;
117 	u8 pk_acc_num;
118 	u8 kasumi_acc_num;
119 	u8 rng_acc_num;
120 	u8 pad3;
121 	u8 md_acc_num;
122 	u8 arc4_acc_num;
123 	u8 des_acc_num;
124 	u8 aes_acc_num;
125 	u8 ccha_acc_num;
126 	u8 ptha_acc_num;
127 };
128 
129 struct dpseci_rsp_get_api_version {
130 	__le16 major;
131 	__le16 minor;
132 };
133 
134 #define DPSECI_CGN_DEST_TYPE_SHIFT	0
135 #define DPSECI_CGN_DEST_TYPE_SIZE	4
136 #define DPSECI_CGN_UNITS_SHIFT		4
137 #define DPSECI_CGN_UNITS_SIZE		2
138 
139 struct dpseci_cmd_congestion_notification {
140 	__le32 dest_id;
141 	__le16 notification_mode;
142 	u8 priority;
143 	u8 options;
144 	__le64 message_iova;
145 	__le64 message_ctx;
146 	__le32 threshold_entry;
147 	__le32 threshold_exit;
148 };
149 
150 #endif /* _DPSECI_CMD_H_ */
151