1 /* SPDX-License-Identifier: MIT */ 2 #ifndef __NVKM_DISP_DP_H__ 3 #define __NVKM_DISP_DP_H__ 4 #include "outp.h" 5 6 int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *, 7 struct nvkm_outp **); 8 void nvkm_dp_disable(struct nvkm_outp *, struct nvkm_ior *); 9 10 /* DPCD Receiver Capabilities */ 11 #define DPCD_RC00_DPCD_REV 0x00000 12 #define DPCD_RC01_MAX_LINK_RATE 0x00001 13 #define DPCD_RC02 0x00002 14 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x80 15 #define DPCD_RC02_TPS3_SUPPORTED 0x40 16 #define DPCD_RC02_MAX_LANE_COUNT 0x1f 17 #define DPCD_RC03 0x00003 18 #define DPCD_RC03_TPS4_SUPPORTED 0x80 19 #define DPCD_RC03_MAX_DOWNSPREAD 0x01 20 #define DPCD_RC0E 0x0000e 21 #define DPCD_RC0E_AUX_RD_INTERVAL 0x7f 22 #define DPCD_RC10_SUPPORTED_LINK_RATES(i) 0x00010 23 #define DPCD_RC10_SUPPORTED_LINK_RATES__SIZE 16 24 25 /* DPCD Link Configuration */ 26 #define DPCD_LC00_LINK_BW_SET 0x00100 27 #define DPCD_LC01 0x00101 28 #define DPCD_LC01_ENHANCED_FRAME_EN 0x80 29 #define DPCD_LC01_LANE_COUNT_SET 0x1f 30 #define DPCD_LC02 0x00102 31 #define DPCD_LC02_TRAINING_PATTERN_SET 0x0f 32 #define DPCD_LC02_SCRAMBLING_DISABLE 0x20 33 #define DPCD_LC03(l) ((l) + 0x00103) 34 #define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED 0x20 35 #define DPCD_LC03_PRE_EMPHASIS_SET 0x18 36 #define DPCD_LC03_MAX_SWING_REACHED 0x04 37 #define DPCD_LC03_VOLTAGE_SWING_SET 0x03 38 #define DPCD_LC0F 0x0010f 39 #define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED 0x40 40 #define DPCD_LC0F_LANE1_POST_CURSOR2_SET 0x30 41 #define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED 0x04 42 #define DPCD_LC0F_LANE0_POST_CURSOR2_SET 0x03 43 #define DPCD_LC10 0x00110 44 #define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED 0x40 45 #define DPCD_LC10_LANE3_POST_CURSOR2_SET 0x30 46 #define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED 0x04 47 #define DPCD_LC10_LANE2_POST_CURSOR2_SET 0x03 48 #define DPCD_LC15_LINK_RATE_SET 0x00115 49 #define DPCD_LC15_LINK_RATE_SET_MASK 0x07 50 51 /* DPCD Link/Sink Status */ 52 #define DPCD_LS02 0x00202 53 #define DPCD_LS02_LANE1_SYMBOL_LOCKED 0x40 54 #define DPCD_LS02_LANE1_CHANNEL_EQ_DONE 0x20 55 #define DPCD_LS02_LANE1_CR_DONE 0x10 56 #define DPCD_LS02_LANE0_SYMBOL_LOCKED 0x04 57 #define DPCD_LS02_LANE0_CHANNEL_EQ_DONE 0x02 58 #define DPCD_LS02_LANE0_CR_DONE 0x01 59 #define DPCD_LS03 0x00203 60 #define DPCD_LS03_LANE3_SYMBOL_LOCKED 0x40 61 #define DPCD_LS03_LANE3_CHANNEL_EQ_DONE 0x20 62 #define DPCD_LS03_LANE3_CR_DONE 0x10 63 #define DPCD_LS03_LANE2_SYMBOL_LOCKED 0x04 64 #define DPCD_LS03_LANE2_CHANNEL_EQ_DONE 0x02 65 #define DPCD_LS03_LANE2_CR_DONE 0x01 66 #define DPCD_LS04 0x00204 67 #define DPCD_LS04_LINK_STATUS_UPDATED 0x80 68 #define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED 0x40 69 #define DPCD_LS04_INTERLANE_ALIGN_DONE 0x01 70 #define DPCD_LS06 0x00206 71 #define DPCD_LS06_LANE1_PRE_EMPHASIS 0xc0 72 #define DPCD_LS06_LANE1_VOLTAGE_SWING 0x30 73 #define DPCD_LS06_LANE0_PRE_EMPHASIS 0x0c 74 #define DPCD_LS06_LANE0_VOLTAGE_SWING 0x03 75 #define DPCD_LS07 0x00207 76 #define DPCD_LS07_LANE3_PRE_EMPHASIS 0xc0 77 #define DPCD_LS07_LANE3_VOLTAGE_SWING 0x30 78 #define DPCD_LS07_LANE2_PRE_EMPHASIS 0x0c 79 #define DPCD_LS07_LANE2_VOLTAGE_SWING 0x03 80 #define DPCD_LS0C 0x0020c 81 #define DPCD_LS0C_LANE3_POST_CURSOR2 0xc0 82 #define DPCD_LS0C_LANE2_POST_CURSOR2 0x30 83 #define DPCD_LS0C_LANE1_POST_CURSOR2 0x0c 84 #define DPCD_LS0C_LANE0_POST_CURSOR2 0x03 85 86 /* DPCD Sink Control */ 87 #define DPCD_SC00 0x00600 88 #define DPCD_SC00_SET_POWER 0x03 89 #define DPCD_SC00_SET_POWER_D0 0x01 90 #define DPCD_SC00_SET_POWER_D3 0x03 91 92 #define DPCD_LTTPR_REV 0xf0000 93 #define DPCD_LTTPR_MODE 0xf0003 94 #define DPCD_LTTPR_MODE_TRANSPARENT 0x55 95 #define DPCD_LTTPR_MODE_NON_TRANSPARENT 0xaa 96 #define DPCD_LTTPR_PATTERN_SET(i) ((i - 1) * 0x50 + 0xf0010) 97 #define DPCD_LTTPR_LANE0_SET(i) ((i - 1) * 0x50 + 0xf0011) 98 #define DPCD_LTTPR_AUX_RD_INTERVAL(i) ((i - 1) * 0x50 + 0xf0020) 99 #define DPCD_LTTPR_LANE0_1_STATUS(i) ((i - 1) * 0x50 + 0xf0030) 100 #define DPCD_LTTPR_LANE0_1_ADJUST(i) ((i - 1) * 0x50 + 0xf0033) 101 #endif 102