1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2014-2016 Freescale Semiconductor Inc.
3 * Copyright 2016-2020 NXP
4 */
5
6 #ifndef __DPAA2_ETH_H
7 #define __DPAA2_ETH_H
8
9 #include <linux/dcbnl.h>
10 #include <linux/netdevice.h>
11 #include <linux/if_vlan.h>
12 #include <linux/fsl/mc.h>
13 #include <linux/net_tstamp.h>
14 #include <net/devlink.h>
15
16 #include <soc/fsl/dpaa2-io.h>
17 #include <soc/fsl/dpaa2-fd.h>
18 #include "dpni.h"
19 #include "dpni-cmd.h"
20
21 #include "dpaa2-eth-trace.h"
22 #include "dpaa2-eth-debugfs.h"
23 #include "dpaa2-mac.h"
24
25 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0)
26
27 #define DPAA2_ETH_STORE_SIZE 16
28
29 /* Maximum number of scatter-gather entries in an ingress frame,
30 * considering the maximum receive frame size is 64K
31 */
32 #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)
33
34 /* Maximum acceptable MTU value. It is in direct relation with the hardware
35 * enforced Max Frame Length (currently 10k).
36 */
37 #define DPAA2_ETH_MFL (10 * 1024)
38 #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN)
39 /* Convert L3 MTU to L2 MFL */
40 #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN)
41
42 /* Set the taildrop threshold (in bytes) to allow the enqueue of a large
43 * enough number of jumbo frames in the Rx queues (length of the current
44 * frame is not taken into account when making the taildrop decision)
45 */
46 #define DPAA2_ETH_FQ_TAILDROP_THRESH (1024 * 1024)
47
48 /* Maximum burst size value for Tx shaping */
49 #define DPAA2_ETH_MAX_BURST_SIZE 0xF7FF
50
51 /* Maximum number of Tx confirmation frames to be processed
52 * in a single NAPI call
53 */
54 #define DPAA2_ETH_TXCONF_PER_NAPI 256
55
56 /* Buffer qouta per channel. We want to keep in check number of ingress frames
57 * in flight: for small sized frames, congestion group taildrop may kick in
58 * first; for large sizes, Rx FQ taildrop threshold will ensure only a
59 * reasonable number of frames will be pending at any given time.
60 * Ingress frame drop due to buffer pool depletion should be a corner case only
61 */
62 #define DPAA2_ETH_NUM_BUFS 1280
63 #define DPAA2_ETH_REFILL_THRESH \
64 (DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD)
65
66 /* Congestion group taildrop threshold: number of frames allowed to accumulate
67 * at any moment in a group of Rx queues belonging to the same traffic class.
68 * Choose value such that we don't risk depleting the buffer pool before the
69 * taildrop kicks in
70 */
71 #define DPAA2_ETH_CG_TAILDROP_THRESH(priv) \
72 (1024 * dpaa2_eth_queue_count(priv) / dpaa2_eth_tc_count(priv))
73
74 /* Congestion group notification threshold: when this many frames accumulate
75 * on the Rx queues belonging to the same TC, the MAC is instructed to send
76 * PFC frames for that TC.
77 * When number of pending frames drops below exit threshold transmission of
78 * PFC frames is stopped.
79 */
80 #define DPAA2_ETH_CN_THRESH_ENTRY(priv) \
81 (DPAA2_ETH_CG_TAILDROP_THRESH(priv) / 2)
82 #define DPAA2_ETH_CN_THRESH_EXIT(priv) \
83 (DPAA2_ETH_CN_THRESH_ENTRY(priv) * 3 / 4)
84
85 /* Maximum number of buffers that can be acquired/released through a single
86 * QBMan command
87 */
88 #define DPAA2_ETH_BUFS_PER_CMD 7
89
90 /* Hardware requires alignment for ingress/egress buffer addresses */
91 #define DPAA2_ETH_TX_BUF_ALIGN 64
92
93 #define DPAA2_ETH_RX_BUF_RAW_SIZE PAGE_SIZE
94 #define DPAA2_ETH_RX_BUF_TAILROOM \
95 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
96 #define DPAA2_ETH_RX_BUF_SIZE \
97 (DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM)
98
99 /* Hardware annotation area in RX/TX buffers */
100 #define DPAA2_ETH_RX_HWA_SIZE 64
101 #define DPAA2_ETH_TX_HWA_SIZE 128
102
103 /* PTP nominal frequency 1GHz */
104 #define DPAA2_PTP_CLK_PERIOD_NS 1
105
106 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned
107 * to 256B. For newer revisions, the requirement is only for 64B alignment
108 */
109 #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256
110 #define DPAA2_ETH_RX_BUF_ALIGN 64
111
112 /* We are accommodating a skb backpointer and some S/G info
113 * in the frame's software annotation. The hardware
114 * options are either 0 or 64, so we choose the latter.
115 */
116 #define DPAA2_ETH_SWA_SIZE 64
117
118 /* We store different information in the software annotation area of a Tx frame
119 * based on what type of frame it is
120 */
121 enum dpaa2_eth_swa_type {
122 DPAA2_ETH_SWA_SINGLE,
123 DPAA2_ETH_SWA_SG,
124 DPAA2_ETH_SWA_XDP,
125 DPAA2_ETH_SWA_SW_TSO,
126 };
127
128 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
129 struct dpaa2_eth_swa {
130 enum dpaa2_eth_swa_type type;
131 union {
132 struct {
133 struct sk_buff *skb;
134 int sgt_size;
135 } single;
136 struct {
137 struct sk_buff *skb;
138 struct scatterlist *scl;
139 int num_sg;
140 int sgt_size;
141 } sg;
142 struct {
143 int dma_size;
144 struct xdp_frame *xdpf;
145 } xdp;
146 struct {
147 struct sk_buff *skb;
148 int num_sg;
149 int sgt_size;
150 int is_last_fd;
151 } tso;
152 };
153 };
154
155 /* Annotation valid bits in FD FRC */
156 #define DPAA2_FD_FRC_FASV 0x8000
157 #define DPAA2_FD_FRC_FAEADV 0x4000
158 #define DPAA2_FD_FRC_FAPRV 0x2000
159 #define DPAA2_FD_FRC_FAIADV 0x1000
160 #define DPAA2_FD_FRC_FASWOV 0x0800
161 #define DPAA2_FD_FRC_FAICFDV 0x0400
162
163 /* Error bits in FD CTRL */
164 #define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR)
165 #define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \
166 FD_CTRL_SBE | \
167 FD_CTRL_FSE | \
168 FD_CTRL_FAERR)
169
170 /* Annotation bits in FD CTRL */
171 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */
172
173 /* Frame annotation status */
174 struct dpaa2_fas {
175 u8 reserved;
176 u8 ppid;
177 __le16 ifpid;
178 __le32 status;
179 };
180
181 /* Frame annotation status word is located in the first 8 bytes
182 * of the buffer's hardware annoatation area
183 */
184 #define DPAA2_FAS_OFFSET 0
185 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas))
186
187 /* Timestamp is located in the next 8 bytes of the buffer's
188 * hardware annotation area
189 */
190 #define DPAA2_TS_OFFSET 0x8
191
192 /* Frame annotation parse results */
193 struct dpaa2_fapr {
194 /* 64-bit word 1 */
195 __le32 faf_lo;
196 __le16 faf_ext;
197 __le16 nxt_hdr;
198 /* 64-bit word 2 */
199 __le64 faf_hi;
200 /* 64-bit word 3 */
201 u8 last_ethertype_offset;
202 u8 vlan_tci_offset_n;
203 u8 vlan_tci_offset_1;
204 u8 llc_snap_offset;
205 u8 eth_offset;
206 u8 ip1_pid_offset;
207 u8 shim_offset_2;
208 u8 shim_offset_1;
209 /* 64-bit word 4 */
210 u8 l5_offset;
211 u8 l4_offset;
212 u8 gre_offset;
213 u8 l3_offset_n;
214 u8 l3_offset_1;
215 u8 mpls_offset_n;
216 u8 mpls_offset_1;
217 u8 pppoe_offset;
218 /* 64-bit word 5 */
219 __le16 running_sum;
220 __le16 gross_running_sum;
221 u8 ipv6_frag_offset;
222 u8 nxt_hdr_offset;
223 u8 routing_hdr_offset_2;
224 u8 routing_hdr_offset_1;
225 /* 64-bit word 6 */
226 u8 reserved[5]; /* Soft-parsing context */
227 u8 ip_proto_offset_n;
228 u8 nxt_hdr_frag_offset;
229 u8 parse_error_code;
230 };
231
232 #define DPAA2_FAPR_OFFSET 0x10
233 #define DPAA2_FAPR_SIZE sizeof((struct dpaa2_fapr))
234
235 /* Frame annotation egress action descriptor */
236 #define DPAA2_FAEAD_OFFSET 0x58
237
238 struct dpaa2_faead {
239 __le32 conf_fqid;
240 __le32 ctrl;
241 };
242
243 #define DPAA2_FAEAD_A2V 0x20000000
244 #define DPAA2_FAEAD_A4V 0x08000000
245 #define DPAA2_FAEAD_UPDV 0x00001000
246 #define DPAA2_FAEAD_EBDDV 0x00002000
247 #define DPAA2_FAEAD_UPD 0x00000010
248
249 struct ptp_tstamp {
250 u16 sec_msb;
251 u32 sec_lsb;
252 u32 nsec;
253 };
254
ns_to_ptp_tstamp(struct ptp_tstamp * tstamp,u64 ns)255 static inline void ns_to_ptp_tstamp(struct ptp_tstamp *tstamp, u64 ns)
256 {
257 u64 sec, nsec;
258
259 sec = ns;
260 nsec = do_div(sec, 1000000000);
261
262 tstamp->sec_lsb = sec & 0xFFFFFFFF;
263 tstamp->sec_msb = (sec >> 32) & 0xFFFF;
264 tstamp->nsec = nsec;
265 }
266
267 /* Accessors for the hardware annotation fields that we use */
dpaa2_get_hwa(void * buf_addr,bool swa)268 static inline void *dpaa2_get_hwa(void *buf_addr, bool swa)
269 {
270 return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0);
271 }
272
dpaa2_get_fas(void * buf_addr,bool swa)273 static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa)
274 {
275 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET;
276 }
277
dpaa2_get_ts(void * buf_addr,bool swa)278 static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa)
279 {
280 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET;
281 }
282
dpaa2_get_fapr(void * buf_addr,bool swa)283 static inline struct dpaa2_fapr *dpaa2_get_fapr(void *buf_addr, bool swa)
284 {
285 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAPR_OFFSET;
286 }
287
dpaa2_get_faead(void * buf_addr,bool swa)288 static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa)
289 {
290 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET;
291 }
292
293 /* Error and status bits in the frame annotation status word */
294 /* Debug frame, otherwise supposed to be discarded */
295 #define DPAA2_FAS_DISC 0x80000000
296 /* MACSEC frame */
297 #define DPAA2_FAS_MS 0x40000000
298 #define DPAA2_FAS_PTP 0x08000000
299 /* Ethernet multicast frame */
300 #define DPAA2_FAS_MC 0x04000000
301 /* Ethernet broadcast frame */
302 #define DPAA2_FAS_BC 0x02000000
303 #define DPAA2_FAS_KSE 0x00040000
304 #define DPAA2_FAS_EOFHE 0x00020000
305 #define DPAA2_FAS_MNLE 0x00010000
306 #define DPAA2_FAS_TIDE 0x00008000
307 #define DPAA2_FAS_PIEE 0x00004000
308 /* Frame length error */
309 #define DPAA2_FAS_FLE 0x00002000
310 /* Frame physical error */
311 #define DPAA2_FAS_FPE 0x00001000
312 #define DPAA2_FAS_PTE 0x00000080
313 #define DPAA2_FAS_ISP 0x00000040
314 #define DPAA2_FAS_PHE 0x00000020
315 #define DPAA2_FAS_BLE 0x00000010
316 /* L3 csum validation performed */
317 #define DPAA2_FAS_L3CV 0x00000008
318 /* L3 csum error */
319 #define DPAA2_FAS_L3CE 0x00000004
320 /* L4 csum validation performed */
321 #define DPAA2_FAS_L4CV 0x00000002
322 /* L4 csum error */
323 #define DPAA2_FAS_L4CE 0x00000001
324 /* Possible errors on the ingress path */
325 #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \
326 DPAA2_FAS_EOFHE | \
327 DPAA2_FAS_MNLE | \
328 DPAA2_FAS_TIDE | \
329 DPAA2_FAS_PIEE | \
330 DPAA2_FAS_FLE | \
331 DPAA2_FAS_FPE | \
332 DPAA2_FAS_PTE | \
333 DPAA2_FAS_ISP | \
334 DPAA2_FAS_PHE | \
335 DPAA2_FAS_BLE | \
336 DPAA2_FAS_L3CE | \
337 DPAA2_FAS_L4CE)
338
339 /* Time in milliseconds between link state updates */
340 #define DPAA2_ETH_LINK_STATE_REFRESH 1000
341
342 /* Number of times to retry a frame enqueue before giving up.
343 * Value determined empirically, in order to minimize the number
344 * of frames dropped on Tx
345 */
346 #define DPAA2_ETH_ENQUEUE_RETRIES 10
347
348 /* Number of times to retry DPIO portal operations while waiting
349 * for portal to finish executing current command and become
350 * available. We want to avoid being stuck in a while loop in case
351 * hardware becomes unresponsive, but not give up too easily if
352 * the portal really is busy for valid reasons
353 */
354 #define DPAA2_ETH_SWP_BUSY_RETRIES 1000
355
356 /* Driver statistics, other than those in struct rtnl_link_stats64.
357 * These are usually collected per-CPU and aggregated by ethtool.
358 */
359 struct dpaa2_eth_drv_stats {
360 __u64 tx_conf_frames;
361 __u64 tx_conf_bytes;
362 __u64 tx_sg_frames;
363 __u64 tx_sg_bytes;
364 __u64 tx_tso_frames;
365 __u64 tx_tso_bytes;
366 __u64 rx_sg_frames;
367 __u64 rx_sg_bytes;
368 /* Linear skbs sent as a S/G FD due to insufficient headroom */
369 __u64 tx_converted_sg_frames;
370 __u64 tx_converted_sg_bytes;
371 /* Enqueues retried due to portal busy */
372 __u64 tx_portal_busy;
373 };
374
375 /* Per-FQ statistics */
376 struct dpaa2_eth_fq_stats {
377 /* Number of frames received on this queue */
378 __u64 frames;
379 };
380
381 /* Per-channel statistics */
382 struct dpaa2_eth_ch_stats {
383 /* Volatile dequeues retried due to portal busy */
384 __u64 dequeue_portal_busy;
385 /* Pull errors */
386 __u64 pull_err;
387 /* Number of CDANs; useful to estimate avg NAPI len */
388 __u64 cdan;
389 /* XDP counters */
390 __u64 xdp_drop;
391 __u64 xdp_tx;
392 __u64 xdp_tx_err;
393 __u64 xdp_redirect;
394 /* Must be last, does not show up in ethtool stats */
395 __u64 frames;
396 __u64 frames_per_cdan;
397 __u64 bytes_per_cdan;
398 };
399
400 #define DPAA2_ETH_CH_STATS 7
401
402 /* Maximum number of queues associated with a DPNI */
403 #define DPAA2_ETH_MAX_TCS 8
404 #define DPAA2_ETH_MAX_RX_QUEUES_PER_TC 16
405 #define DPAA2_ETH_MAX_RX_QUEUES \
406 (DPAA2_ETH_MAX_RX_QUEUES_PER_TC * DPAA2_ETH_MAX_TCS)
407 #define DPAA2_ETH_MAX_TX_QUEUES 16
408 #define DPAA2_ETH_MAX_RX_ERR_QUEUES 1
409 #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \
410 DPAA2_ETH_MAX_TX_QUEUES + \
411 DPAA2_ETH_MAX_RX_ERR_QUEUES)
412 #define DPAA2_ETH_MAX_NETDEV_QUEUES \
413 (DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS)
414
415 #define DPAA2_ETH_MAX_DPCONS 16
416
417 enum dpaa2_eth_fq_type {
418 DPAA2_RX_FQ = 0,
419 DPAA2_TX_CONF_FQ,
420 DPAA2_RX_ERR_FQ
421 };
422
423 struct dpaa2_eth_priv;
424
425 struct dpaa2_eth_xdp_fds {
426 struct dpaa2_fd fds[DEV_MAP_BULK_SIZE];
427 ssize_t num;
428 };
429
430 struct dpaa2_eth_fq {
431 u32 fqid;
432 u32 tx_qdbin;
433 u32 tx_fqid[DPAA2_ETH_MAX_TCS];
434 u16 flowid;
435 u8 tc;
436 int target_cpu;
437 u32 dq_frames;
438 u32 dq_bytes;
439 struct dpaa2_eth_channel *channel;
440 enum dpaa2_eth_fq_type type;
441
442 void (*consume)(struct dpaa2_eth_priv *priv,
443 struct dpaa2_eth_channel *ch,
444 const struct dpaa2_fd *fd,
445 struct dpaa2_eth_fq *fq);
446 struct dpaa2_eth_fq_stats stats;
447
448 struct dpaa2_eth_xdp_fds xdp_redirect_fds;
449 struct dpaa2_eth_xdp_fds xdp_tx_fds;
450 };
451
452 struct dpaa2_eth_ch_xdp {
453 struct bpf_prog *prog;
454 unsigned int res;
455 };
456
457 struct dpaa2_eth_channel {
458 struct dpaa2_io_notification_ctx nctx;
459 struct fsl_mc_device *dpcon;
460 int dpcon_id;
461 int ch_id;
462 struct napi_struct napi;
463 struct dpaa2_io *dpio;
464 struct dpaa2_io_store *store;
465 struct dpaa2_eth_priv *priv;
466 int buf_count;
467 struct dpaa2_eth_ch_stats stats;
468 struct dpaa2_eth_ch_xdp xdp;
469 struct xdp_rxq_info xdp_rxq;
470 struct list_head *rx_list;
471
472 /* Buffers to be recycled back in the buffer pool */
473 u64 recycled_bufs[DPAA2_ETH_BUFS_PER_CMD];
474 int recycled_bufs_cnt;
475 };
476
477 struct dpaa2_eth_dist_fields {
478 u64 rxnfc_field;
479 enum net_prot cls_prot;
480 int cls_field;
481 int size;
482 u64 id;
483 };
484
485 struct dpaa2_eth_cls_rule {
486 struct ethtool_rx_flow_spec fs;
487 u8 in_use;
488 };
489
490 #define DPAA2_ETH_SGT_CACHE_SIZE 256
491 struct dpaa2_eth_sgt_cache {
492 void *buf[DPAA2_ETH_SGT_CACHE_SIZE];
493 u16 count;
494 };
495
496 struct dpaa2_eth_trap_item {
497 void *trap_ctx;
498 };
499
500 struct dpaa2_eth_trap_data {
501 struct dpaa2_eth_trap_item *trap_items_arr;
502 struct dpaa2_eth_priv *priv;
503 };
504
505 #define DPAA2_ETH_SG_ENTRIES_MAX (PAGE_SIZE / sizeof(struct scatterlist))
506
507 #define DPAA2_ETH_DEFAULT_COPYBREAK 512
508
509 #define DPAA2_ETH_ENQUEUE_MAX_FDS 200
510 struct dpaa2_eth_fds {
511 struct dpaa2_fd array[DPAA2_ETH_ENQUEUE_MAX_FDS];
512 };
513
514 /* Driver private data */
515 struct dpaa2_eth_priv {
516 struct net_device *net_dev;
517
518 u8 num_fqs;
519 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
520 int (*enqueue)(struct dpaa2_eth_priv *priv,
521 struct dpaa2_eth_fq *fq,
522 struct dpaa2_fd *fd, u8 prio,
523 u32 num_frames,
524 int *frames_enqueued);
525
526 u8 num_channels;
527 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
528 struct dpaa2_eth_sgt_cache __percpu *sgt_cache;
529 unsigned long features;
530 struct dpni_attr dpni_attrs;
531 u16 dpni_ver_major;
532 u16 dpni_ver_minor;
533 u16 tx_data_offset;
534 void __iomem *onestep_reg_base;
535 u8 ptp_correction_off;
536 void (*dpaa2_set_onestep_params_cb)(struct dpaa2_eth_priv *priv,
537 u32 offset, u8 udp);
538 struct fsl_mc_device *dpbp_dev;
539 u16 rx_buf_size;
540 u16 bpid;
541 struct iommu_domain *iommu_domain;
542
543 enum hwtstamp_tx_types tx_tstamp_type; /* Tx timestamping type */
544 bool rx_tstamp; /* Rx timestamping enabled */
545
546 u16 tx_qdid;
547 struct fsl_mc_io *mc_io;
548 /* Cores which have an affine DPIO/DPCON.
549 * This is the cpu set on which Rx and Tx conf frames are processed
550 */
551 struct cpumask dpio_cpumask;
552
553 /* Standard statistics */
554 struct rtnl_link_stats64 __percpu *percpu_stats;
555 /* Extra stats, in addition to the ones known by the kernel */
556 struct dpaa2_eth_drv_stats __percpu *percpu_extras;
557
558 u16 mc_token;
559 u8 rx_fqtd_enabled;
560 u8 rx_cgtd_enabled;
561
562 struct dpni_link_state link_state;
563 bool do_link_poll;
564 struct task_struct *poll_thread;
565
566 /* enabled ethtool hashing bits */
567 u64 rx_hash_fields;
568 u64 rx_cls_fields;
569 struct dpaa2_eth_cls_rule *cls_rules;
570 u8 rx_cls_enabled;
571 u8 vlan_cls_enabled;
572 u8 pfc_enabled;
573 #ifdef CONFIG_FSL_DPAA2_ETH_DCB
574 u8 dcbx_mode;
575 struct ieee_pfc pfc;
576 #endif
577 struct bpf_prog *xdp_prog;
578 #ifdef CONFIG_DEBUG_FS
579 struct dpaa2_debugfs dbg;
580 #endif
581
582 struct dpaa2_mac *mac;
583 struct workqueue_struct *dpaa2_ptp_wq;
584 struct work_struct tx_onestep_tstamp;
585 struct sk_buff_head tx_skbs;
586 /* The one-step timestamping configuration on hardware
587 * registers could only be done when no one-step
588 * timestamping frames are in flight. So we use a mutex
589 * lock here to make sure the lock is released by last
590 * one-step timestamping packet through TX confirmation
591 * queue before transmit current packet.
592 */
593 struct mutex onestep_tstamp_lock;
594 struct devlink *devlink;
595 struct dpaa2_eth_trap_data *trap_data;
596 struct devlink_port devlink_port;
597
598 u32 rx_copybreak;
599
600 struct dpaa2_eth_fds __percpu *fd;
601 };
602
603 struct dpaa2_eth_devlink_priv {
604 struct dpaa2_eth_priv *dpaa2_priv;
605 };
606
607 #define TX_TSTAMP 0x1
608 #define TX_TSTAMP_ONESTEP_SYNC 0x2
609
610 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \
611 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \
612 | RXH_L4_B_2_3)
613
614 /* default Rx hash options, set during probing */
615 #define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \
616 RXH_L4_B_0_1 | RXH_L4_B_2_3)
617
618 #define dpaa2_eth_hash_enabled(priv) \
619 ((priv)->dpni_attrs.num_queues > 1)
620
621 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
622 #define DPAA2_CLASSIFIER_DMA_SIZE 256
623
624 extern const struct ethtool_ops dpaa2_ethtool_ops;
625 extern int dpaa2_phc_index;
626 extern struct ptp_qoriq *dpaa2_ptp;
627
dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv * priv,u16 ver_major,u16 ver_minor)628 static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv,
629 u16 ver_major, u16 ver_minor)
630 {
631 if (priv->dpni_ver_major == ver_major)
632 return priv->dpni_ver_minor - ver_minor;
633 return priv->dpni_ver_major - ver_major;
634 }
635
636 /* Minimum firmware version that supports a more flexible API
637 * for configuring the Rx flow hash key
638 */
639 #define DPNI_RX_DIST_KEY_VER_MAJOR 7
640 #define DPNI_RX_DIST_KEY_VER_MINOR 5
641
642 #define dpaa2_eth_has_legacy_dist(priv) \
643 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \
644 DPNI_RX_DIST_KEY_VER_MINOR) < 0)
645
646 #define dpaa2_eth_fs_enabled(priv) \
647 (!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS))
648
649 #define dpaa2_eth_fs_mask_enabled(priv) \
650 ((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING)
651
652 #define dpaa2_eth_fs_count(priv) \
653 ((priv)->dpni_attrs.fs_entries)
654
655 #define dpaa2_eth_tc_count(priv) \
656 ((priv)->dpni_attrs.num_tcs)
657
658 /* We have exactly one {Rx, Tx conf} queue per channel */
659 #define dpaa2_eth_queue_count(priv) \
660 ((priv)->num_channels)
661
662 enum dpaa2_eth_rx_dist {
663 DPAA2_ETH_RX_DIST_HASH,
664 DPAA2_ETH_RX_DIST_CLS
665 };
666
667 /* Unique IDs for the supported Rx classification header fields */
668 #define DPAA2_ETH_DIST_ETHDST BIT(0)
669 #define DPAA2_ETH_DIST_ETHSRC BIT(1)
670 #define DPAA2_ETH_DIST_ETHTYPE BIT(2)
671 #define DPAA2_ETH_DIST_VLAN BIT(3)
672 #define DPAA2_ETH_DIST_IPSRC BIT(4)
673 #define DPAA2_ETH_DIST_IPDST BIT(5)
674 #define DPAA2_ETH_DIST_IPPROTO BIT(6)
675 #define DPAA2_ETH_DIST_L4SRC BIT(7)
676 #define DPAA2_ETH_DIST_L4DST BIT(8)
677 #define DPAA2_ETH_DIST_ALL (~0ULL)
678
679 #define DPNI_PTP_ONESTEP_VER_MAJOR 8
680 #define DPNI_PTP_ONESTEP_VER_MINOR 2
681 #define DPAA2_ETH_FEATURE_ONESTEP_CFG_DIRECT BIT(0)
682 #define DPAA2_PTP_SINGLE_STEP_ENABLE BIT(31)
683 #define DPAA2_PTP_SINGLE_STEP_CH BIT(7)
684 #define DPAA2_PTP_SINGLE_CORRECTION_OFF(v) ((v) << 8)
685
686 #define DPNI_PAUSE_VER_MAJOR 7
687 #define DPNI_PAUSE_VER_MINOR 13
688 #define dpaa2_eth_has_pause_support(priv) \
689 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_PAUSE_VER_MAJOR, \
690 DPNI_PAUSE_VER_MINOR) >= 0)
691
dpaa2_eth_tx_pause_enabled(u64 link_options)692 static inline bool dpaa2_eth_tx_pause_enabled(u64 link_options)
693 {
694 return !!(link_options & DPNI_LINK_OPT_PAUSE) ^
695 !!(link_options & DPNI_LINK_OPT_ASYM_PAUSE);
696 }
697
dpaa2_eth_rx_pause_enabled(u64 link_options)698 static inline bool dpaa2_eth_rx_pause_enabled(u64 link_options)
699 {
700 return !!(link_options & DPNI_LINK_OPT_PAUSE);
701 }
702
dpaa2_eth_needed_headroom(struct sk_buff * skb)703 static inline unsigned int dpaa2_eth_needed_headroom(struct sk_buff *skb)
704 {
705 unsigned int headroom = DPAA2_ETH_SWA_SIZE;
706
707 /* If we don't have an skb (e.g. XDP buffer), we only need space for
708 * the software annotation area
709 */
710 if (!skb)
711 return headroom;
712
713 /* For non-linear skbs we have no headroom requirement, as we build a
714 * SG frame with a newly allocated SGT buffer
715 */
716 if (skb_is_nonlinear(skb))
717 return 0;
718
719 /* If we have Tx timestamping, need 128B hardware annotation */
720 if (skb->cb[0])
721 headroom += DPAA2_ETH_TX_HWA_SIZE;
722
723 return headroom;
724 }
725
726 /* Extra headroom space requested to hardware, in order to make sure there's
727 * no realloc'ing in forwarding scenarios
728 */
dpaa2_eth_rx_head_room(struct dpaa2_eth_priv * priv)729 static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv)
730 {
731 return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE;
732 }
733
dpaa2_eth_is_type_phy(struct dpaa2_eth_priv * priv)734 static inline bool dpaa2_eth_is_type_phy(struct dpaa2_eth_priv *priv)
735 {
736 if (priv->mac &&
737 (priv->mac->attr.link_type == DPMAC_LINK_TYPE_PHY ||
738 priv->mac->attr.link_type == DPMAC_LINK_TYPE_BACKPLANE))
739 return true;
740
741 return false;
742 }
743
dpaa2_eth_has_mac(struct dpaa2_eth_priv * priv)744 static inline bool dpaa2_eth_has_mac(struct dpaa2_eth_priv *priv)
745 {
746 return priv->mac ? true : false;
747 }
748
749 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags);
750 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 key);
751 int dpaa2_eth_cls_key_size(u64 key);
752 int dpaa2_eth_cls_fld_off(int prot, int field);
753 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields);
754
755 void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv,
756 bool tx_pause, bool pfc);
757
758 extern const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops;
759
760 int dpaa2_eth_dl_alloc(struct dpaa2_eth_priv *priv);
761 void dpaa2_eth_dl_free(struct dpaa2_eth_priv *priv);
762
763 void dpaa2_eth_dl_register(struct dpaa2_eth_priv *priv);
764 void dpaa2_eth_dl_unregister(struct dpaa2_eth_priv *priv);
765
766 int dpaa2_eth_dl_port_add(struct dpaa2_eth_priv *priv);
767 void dpaa2_eth_dl_port_del(struct dpaa2_eth_priv *priv);
768
769 int dpaa2_eth_dl_traps_register(struct dpaa2_eth_priv *priv);
770 void dpaa2_eth_dl_traps_unregister(struct dpaa2_eth_priv *priv);
771
772 struct dpaa2_eth_trap_item *dpaa2_eth_dl_get_trap(struct dpaa2_eth_priv *priv,
773 struct dpaa2_fapr *fapr);
774 #endif /* __DPAA2_H */
775