1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
22 */
23 #ifndef LINUX_PCI_H
24 #define LINUX_PCI_H
25
26
27 #include <linux/mod_devicetable.h>
28
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
42
43 #include <linux/pci_ids.h>
44
45 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
50 PCI_STATUS_PARITY)
51
52 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
53 #define PCI_NUM_RESET_METHODS 7
54
55 #define PCI_RESET_PROBE true
56 #define PCI_RESET_DO_RESET false
57
58 /*
59 * The PCI interface treats multi-function devices as independent
60 * devices. The slot/function address of each device is encoded
61 * in a single byte as follows:
62 *
63 * 7:3 = slot
64 * 2:0 = function
65 *
66 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
67 * In the interest of not exposing interfaces to user-space unnecessarily,
68 * the following kernel-only defines are being added here.
69 */
70 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
71 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
72 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
73
74 /* pci_slot represents a physical slot */
75 struct pci_slot {
76 struct pci_bus *bus; /* Bus this slot is on */
77 struct list_head list; /* Node in list of slots */
78 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
79 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
80 struct kobject kobj;
81 };
82
pci_slot_name(const struct pci_slot * slot)83 static inline const char *pci_slot_name(const struct pci_slot *slot)
84 {
85 return kobject_name(&slot->kobj);
86 }
87
88 /* File state for mmap()s on /proc/bus/pci/X/Y */
89 enum pci_mmap_state {
90 pci_mmap_io,
91 pci_mmap_mem
92 };
93
94 /* For PCI devices, the region numbers are assigned this way: */
95 enum {
96 /* #0-5: standard PCI resources */
97 PCI_STD_RESOURCES,
98 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
99
100 /* #6: expansion ROM resource */
101 PCI_ROM_RESOURCE,
102
103 /* Device-specific resources */
104 #ifdef CONFIG_PCI_IOV
105 PCI_IOV_RESOURCES,
106 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
107 #endif
108
109 /* PCI-to-PCI (P2P) bridge windows */
110 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
111 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
112 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
113
114 /* CardBus bridge windows */
115 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
116 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
117 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
118 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
119
120 /* Total number of bridge resources for P2P and CardBus */
121 #define PCI_BRIDGE_RESOURCE_NUM 4
122
123 /* Resources assigned to buses behind the bridge */
124 PCI_BRIDGE_RESOURCES,
125 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
126 PCI_BRIDGE_RESOURCE_NUM - 1,
127
128 /* Total resources associated with a PCI device */
129 PCI_NUM_RESOURCES,
130
131 /* Preserve this for compatibility */
132 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
133 };
134
135 /**
136 * enum pci_interrupt_pin - PCI INTx interrupt values
137 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
138 * @PCI_INTERRUPT_INTA: PCI INTA pin
139 * @PCI_INTERRUPT_INTB: PCI INTB pin
140 * @PCI_INTERRUPT_INTC: PCI INTC pin
141 * @PCI_INTERRUPT_INTD: PCI INTD pin
142 *
143 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
144 * PCI_INTERRUPT_PIN register.
145 */
146 enum pci_interrupt_pin {
147 PCI_INTERRUPT_UNKNOWN,
148 PCI_INTERRUPT_INTA,
149 PCI_INTERRUPT_INTB,
150 PCI_INTERRUPT_INTC,
151 PCI_INTERRUPT_INTD,
152 };
153
154 /* The number of legacy PCI INTx interrupts */
155 #define PCI_NUM_INTX 4
156
157 /*
158 * Reading from a device that doesn't respond typically returns ~0. A
159 * successful read from a device may also return ~0, so you need additional
160 * information to reliably identify errors.
161 */
162 #define PCI_ERROR_RESPONSE (~0ULL)
163 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
164 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
165
166 /*
167 * pci_power_t values must match the bits in the Capabilities PME_Support
168 * and Control/Status PowerState fields in the Power Management capability.
169 */
170 typedef int __bitwise pci_power_t;
171
172 #define PCI_D0 ((pci_power_t __force) 0)
173 #define PCI_D1 ((pci_power_t __force) 1)
174 #define PCI_D2 ((pci_power_t __force) 2)
175 #define PCI_D3hot ((pci_power_t __force) 3)
176 #define PCI_D3cold ((pci_power_t __force) 4)
177 #define PCI_UNKNOWN ((pci_power_t __force) 5)
178 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
179
180 /* Remember to update this when the list above changes! */
181 extern const char *pci_power_names[];
182
pci_power_name(pci_power_t state)183 static inline const char *pci_power_name(pci_power_t state)
184 {
185 return pci_power_names[1 + (__force int) state];
186 }
187
188 /**
189 * typedef pci_channel_state_t
190 *
191 * The pci_channel state describes connectivity between the CPU and
192 * the PCI device. If some PCI bus between here and the PCI device
193 * has crashed or locked up, this info is reflected here.
194 */
195 typedef unsigned int __bitwise pci_channel_state_t;
196
197 enum {
198 /* I/O channel is in normal state */
199 pci_channel_io_normal = (__force pci_channel_state_t) 1,
200
201 /* I/O to channel is blocked */
202 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
203
204 /* PCI card is dead */
205 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
206 };
207
208 typedef unsigned int __bitwise pcie_reset_state_t;
209
210 enum pcie_reset_state {
211 /* Reset is NOT asserted (Use to deassert reset) */
212 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
213
214 /* Use #PERST to reset PCIe device */
215 pcie_warm_reset = (__force pcie_reset_state_t) 2,
216
217 /* Use PCIe Hot Reset to reset device */
218 pcie_hot_reset = (__force pcie_reset_state_t) 3
219 };
220
221 typedef unsigned short __bitwise pci_dev_flags_t;
222 enum pci_dev_flags {
223 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
224 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
225 /* Device configuration is irrevocably lost if disabled into D3 */
226 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
227 /* Provide indication device is assigned by a Virtual Machine Manager */
228 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
229 /* Flag for quirk use to store if quirk-specific ACS is enabled */
230 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
231 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
232 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
233 /* Do not use bus resets for device */
234 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
235 /* Do not use PM reset even if device advertises NoSoftRst- */
236 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
237 /* Get VPD from function 0 VPD */
238 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
239 /* A non-root bridge where translation occurs, stop alias search here */
240 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
241 /* Do not use FLR even if device advertises PCI_AF_CAP */
242 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
243 /* Don't use Relaxed Ordering for TLPs directed at this device */
244 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
245 /* Device does honor MSI masking despite saying otherwise */
246 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
247 };
248
249 enum pci_irq_reroute_variant {
250 INTEL_IRQ_REROUTE_VARIANT = 1,
251 MAX_IRQ_REROUTE_VARIANTS = 3
252 };
253
254 typedef unsigned short __bitwise pci_bus_flags_t;
255 enum pci_bus_flags {
256 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
257 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
258 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
259 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
260 };
261
262 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
263 enum pcie_link_width {
264 PCIE_LNK_WIDTH_RESRV = 0x00,
265 PCIE_LNK_X1 = 0x01,
266 PCIE_LNK_X2 = 0x02,
267 PCIE_LNK_X4 = 0x04,
268 PCIE_LNK_X8 = 0x08,
269 PCIE_LNK_X12 = 0x0c,
270 PCIE_LNK_X16 = 0x10,
271 PCIE_LNK_X32 = 0x20,
272 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
273 };
274
275 /* See matching string table in pci_speed_string() */
276 enum pci_bus_speed {
277 PCI_SPEED_33MHz = 0x00,
278 PCI_SPEED_66MHz = 0x01,
279 PCI_SPEED_66MHz_PCIX = 0x02,
280 PCI_SPEED_100MHz_PCIX = 0x03,
281 PCI_SPEED_133MHz_PCIX = 0x04,
282 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
283 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
284 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
285 PCI_SPEED_66MHz_PCIX_266 = 0x09,
286 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
287 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
288 AGP_UNKNOWN = 0x0c,
289 AGP_1X = 0x0d,
290 AGP_2X = 0x0e,
291 AGP_4X = 0x0f,
292 AGP_8X = 0x10,
293 PCI_SPEED_66MHz_PCIX_533 = 0x11,
294 PCI_SPEED_100MHz_PCIX_533 = 0x12,
295 PCI_SPEED_133MHz_PCIX_533 = 0x13,
296 PCIE_SPEED_2_5GT = 0x14,
297 PCIE_SPEED_5_0GT = 0x15,
298 PCIE_SPEED_8_0GT = 0x16,
299 PCIE_SPEED_16_0GT = 0x17,
300 PCIE_SPEED_32_0GT = 0x18,
301 PCIE_SPEED_64_0GT = 0x19,
302 PCI_SPEED_UNKNOWN = 0xff,
303 };
304
305 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
306 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
307
308 struct pci_vpd {
309 struct mutex lock;
310 unsigned int len;
311 u8 cap;
312 };
313
314 struct irq_affinity;
315 struct pcie_link_state;
316 struct pci_sriov;
317 struct pci_p2pdma;
318 struct rcec_ea;
319
320 /* The pci_dev structure describes PCI devices */
321 struct pci_dev {
322 struct list_head bus_list; /* Node in per-bus list */
323 struct pci_bus *bus; /* Bus this device is on */
324 struct pci_bus *subordinate; /* Bus this device bridges to */
325
326 void *sysdata; /* Hook for sys-specific extension */
327 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
328 struct pci_slot *slot; /* Physical slot this device is in */
329
330 unsigned int devfn; /* Encoded device & function index */
331 unsigned short vendor;
332 unsigned short device;
333 unsigned short subsystem_vendor;
334 unsigned short subsystem_device;
335 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
336 u8 revision; /* PCI revision, low byte of class word */
337 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
338 #ifdef CONFIG_PCIEAER
339 u16 aer_cap; /* AER capability offset */
340 struct aer_stats *aer_stats; /* AER stats for this device */
341 #endif
342 #ifdef CONFIG_PCIEPORTBUS
343 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
344 struct pci_dev *rcec; /* Associated RCEC device */
345 #endif
346 u32 devcap; /* PCIe Device Capabilities */
347 u8 pcie_cap; /* PCIe capability offset */
348 u8 msi_cap; /* MSI capability offset */
349 u8 msix_cap; /* MSI-X capability offset */
350 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
351 u8 rom_base_reg; /* Config register controlling ROM */
352 u8 pin; /* Interrupt pin this device uses */
353 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
354 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
355
356 struct pci_driver *driver; /* Driver bound to this device */
357 u64 dma_mask; /* Mask of the bits of bus address this
358 device implements. Normally this is
359 0xffffffff. You only need to change
360 this if your device has broken DMA
361 or supports 64-bit transfers. */
362
363 struct device_dma_parameters dma_parms;
364
365 pci_power_t current_state; /* Current operating state. In ACPI,
366 this is D0-D3, D0 being fully
367 functional, and D3 being off. */
368 unsigned int imm_ready:1; /* Supports Immediate Readiness */
369 u8 pm_cap; /* PM capability offset */
370 unsigned int pme_support:5; /* Bitmask of states from which PME#
371 can be generated */
372 unsigned int pme_poll:1; /* Poll device's PME status bit */
373 unsigned int d1_support:1; /* Low power state D1 is supported */
374 unsigned int d2_support:1; /* Low power state D2 is supported */
375 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
376 unsigned int no_d3cold:1; /* D3cold is forbidden */
377 unsigned int bridge_d3:1; /* Allow D3 for bridge */
378 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
379 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
380 decoding during BAR sizing */
381 unsigned int wakeup_prepared:1;
382 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
383 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
384 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
385 controlled exclusively by
386 user sysfs */
387 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
388 bit manually */
389 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
390 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
391
392 #ifdef CONFIG_PCIEASPM
393 struct pcie_link_state *link_state; /* ASPM link state */
394 unsigned int ltr_path:1; /* Latency Tolerance Reporting
395 supported from root to here */
396 u16 l1ss; /* L1SS Capability pointer */
397 #endif
398 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
399 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
400
401 pci_channel_state_t error_state; /* Current connectivity state */
402 struct device dev; /* Generic device interface */
403
404 int cfg_size; /* Size of config space */
405
406 /*
407 * Instead of touching interrupt line and base address registers
408 * directly, use the values stored here. They might be different!
409 */
410 unsigned int irq;
411 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
412
413 bool match_driver; /* Skip attaching driver */
414
415 unsigned int transparent:1; /* Subtractive decode bridge */
416 unsigned int io_window:1; /* Bridge has I/O window */
417 unsigned int pref_window:1; /* Bridge has pref mem window */
418 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
419 unsigned int multifunction:1; /* Multi-function device */
420
421 unsigned int is_busmaster:1; /* Is busmaster */
422 unsigned int no_msi:1; /* May not use MSI */
423 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
424 unsigned int block_cfg_access:1; /* Config space access blocked */
425 unsigned int broken_parity_status:1; /* Generates false positive parity */
426 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
427 unsigned int msi_enabled:1;
428 unsigned int msix_enabled:1;
429 unsigned int ari_enabled:1; /* ARI forwarding */
430 unsigned int ats_enabled:1; /* Address Translation Svc */
431 unsigned int pasid_enabled:1; /* Process Address Space ID */
432 unsigned int pri_enabled:1; /* Page Request Interface */
433 unsigned int is_managed:1; /* Managed via devres */
434 unsigned int is_msi_managed:1; /* MSI release via devres installed */
435 unsigned int needs_freset:1; /* Requires fundamental reset */
436 unsigned int state_saved:1;
437 unsigned int is_physfn:1;
438 unsigned int is_virtfn:1;
439 unsigned int is_hotplug_bridge:1;
440 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
441 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
442 /*
443 * Devices marked being untrusted are the ones that can potentially
444 * execute DMA attacks and similar. They are typically connected
445 * through external ports such as Thunderbolt but not limited to
446 * that. When an IOMMU is enabled they should be getting full
447 * mappings to make sure they cannot access arbitrary memory.
448 */
449 unsigned int untrusted:1;
450 /*
451 * Info from the platform, e.g., ACPI or device tree, may mark a
452 * device as "external-facing". An external-facing device is
453 * itself internal but devices downstream from it are external.
454 */
455 unsigned int external_facing:1;
456 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
457 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
458 unsigned int irq_managed:1;
459 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
460 unsigned int is_probed:1; /* Device probing in progress */
461 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
462 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
463 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
464 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
465 pci_dev_flags_t dev_flags;
466 atomic_t enable_cnt; /* pci_enable_device has been called */
467
468 u32 saved_config_space[16]; /* Config space saved at suspend time */
469 struct hlist_head saved_cap_space;
470 int rom_attr_enabled; /* Display of ROM attribute enabled? */
471 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
472 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
473
474 #ifdef CONFIG_HOTPLUG_PCI_PCIE
475 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
476 #endif
477 #ifdef CONFIG_PCIE_PTM
478 unsigned int ptm_root:1;
479 unsigned int ptm_enabled:1;
480 u8 ptm_granularity;
481 #endif
482 #ifdef CONFIG_PCI_MSI
483 void __iomem *msix_base;
484 raw_spinlock_t msi_lock;
485 #endif
486 struct pci_vpd vpd;
487 #ifdef CONFIG_PCIE_DPC
488 u16 dpc_cap;
489 unsigned int dpc_rp_extensions:1;
490 u8 dpc_rp_log_size;
491 #endif
492 #ifdef CONFIG_PCI_ATS
493 union {
494 struct pci_sriov *sriov; /* PF: SR-IOV info */
495 struct pci_dev *physfn; /* VF: related PF */
496 };
497 u16 ats_cap; /* ATS Capability offset */
498 u8 ats_stu; /* ATS Smallest Translation Unit */
499 #endif
500 #ifdef CONFIG_PCI_PRI
501 u16 pri_cap; /* PRI Capability offset */
502 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
503 unsigned int pasid_required:1; /* PRG Response PASID Required */
504 #endif
505 #ifdef CONFIG_PCI_PASID
506 u16 pasid_cap; /* PASID Capability offset */
507 u16 pasid_features;
508 #endif
509 #ifdef CONFIG_PCI_P2PDMA
510 struct pci_p2pdma __rcu *p2pdma;
511 #endif
512 u16 acs_cap; /* ACS Capability offset */
513 phys_addr_t rom; /* Physical address if not from BAR */
514 size_t romlen; /* Length if not from BAR */
515 /*
516 * Driver name to force a match. Do not set directly, because core
517 * frees it. Use driver_set_override() to set or clear it.
518 */
519 const char *driver_override;
520
521 unsigned long priv_flags; /* Private flags for the PCI driver */
522
523 /* These methods index pci_reset_fn_methods[] */
524 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
525 };
526
pci_physfn(struct pci_dev * dev)527 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
528 {
529 #ifdef CONFIG_PCI_IOV
530 if (dev->is_virtfn)
531 dev = dev->physfn;
532 #endif
533 return dev;
534 }
535
536 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
537
538 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
539 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
540
pci_channel_offline(struct pci_dev * pdev)541 static inline int pci_channel_offline(struct pci_dev *pdev)
542 {
543 return (pdev->error_state != pci_channel_io_normal);
544 }
545
546 /*
547 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
548 * Group number is limited to a 16-bit value, therefore (int)-1 is
549 * not a valid PCI domain number, and can be used as a sentinel
550 * value indicating ->domain_nr is not set by the driver (and
551 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
552 * pci_bus_find_domain_nr()).
553 */
554 #define PCI_DOMAIN_NR_NOT_SET (-1)
555
556 struct pci_host_bridge {
557 struct device dev;
558 struct pci_bus *bus; /* Root bus */
559 struct pci_ops *ops;
560 struct pci_ops *child_ops;
561 void *sysdata;
562 int busnr;
563 int domain_nr;
564 struct list_head windows; /* resource_entry */
565 struct list_head dma_ranges; /* dma ranges resource list */
566 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
567 int (*map_irq)(const struct pci_dev *, u8, u8);
568 void (*release_fn)(struct pci_host_bridge *);
569 void *release_data;
570 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
571 unsigned int no_ext_tags:1; /* No Extended Tags */
572 unsigned int native_aer:1; /* OS may use PCIe AER */
573 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
574 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
575 unsigned int native_pme:1; /* OS may use PCIe PME */
576 unsigned int native_ltr:1; /* OS may use PCIe LTR */
577 unsigned int native_dpc:1; /* OS may use PCIe DPC */
578 unsigned int preserve_config:1; /* Preserve FW resource setup */
579 unsigned int size_windows:1; /* Enable root bus sizing */
580 unsigned int msi_domain:1; /* Bridge wants MSI domain */
581
582 /* Resource alignment requirements */
583 resource_size_t (*align_resource)(struct pci_dev *dev,
584 const struct resource *res,
585 resource_size_t start,
586 resource_size_t size,
587 resource_size_t align);
588 unsigned long private[] ____cacheline_aligned;
589 };
590
591 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
592
pci_host_bridge_priv(struct pci_host_bridge * bridge)593 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
594 {
595 return (void *)bridge->private;
596 }
597
pci_host_bridge_from_priv(void * priv)598 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
599 {
600 return container_of(priv, struct pci_host_bridge, private);
601 }
602
603 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
604 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
605 size_t priv);
606 void pci_free_host_bridge(struct pci_host_bridge *bridge);
607 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
608
609 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
610 void (*release_fn)(struct pci_host_bridge *),
611 void *release_data);
612
613 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
614
615 /*
616 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
617 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
618 * buses below host bridges or subtractive decode bridges) go in the list.
619 * Use pci_bus_for_each_resource() to iterate through all the resources.
620 */
621
622 /*
623 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
624 * and there's no way to program the bridge with the details of the window.
625 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
626 * decode bit set, because they are explicit and can be programmed with _SRS.
627 */
628 #define PCI_SUBTRACTIVE_DECODE 0x1
629
630 struct pci_bus_resource {
631 struct list_head list;
632 struct resource *res;
633 unsigned int flags;
634 };
635
636 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
637
638 struct pci_bus {
639 struct list_head node; /* Node in list of buses */
640 struct pci_bus *parent; /* Parent bus this bridge is on */
641 struct list_head children; /* List of child buses */
642 struct list_head devices; /* List of devices on this bus */
643 struct pci_dev *self; /* Bridge device as seen by parent */
644 struct list_head slots; /* List of slots on this bus;
645 protected by pci_slot_mutex */
646 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
647 struct list_head resources; /* Address space routed to this bus */
648 struct resource busn_res; /* Bus numbers routed to this bus */
649
650 struct pci_ops *ops; /* Configuration access functions */
651 void *sysdata; /* Hook for sys-specific extension */
652 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
653
654 unsigned char number; /* Bus number */
655 unsigned char primary; /* Number of primary bridge */
656 unsigned char max_bus_speed; /* enum pci_bus_speed */
657 unsigned char cur_bus_speed; /* enum pci_bus_speed */
658 #ifdef CONFIG_PCI_DOMAINS_GENERIC
659 int domain_nr;
660 #endif
661
662 char name[48];
663
664 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
665 pci_bus_flags_t bus_flags; /* Inherited by child buses */
666 struct device *bridge;
667 struct device dev;
668 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
669 struct bin_attribute *legacy_mem; /* Legacy mem */
670 unsigned int is_added:1;
671 unsigned int unsafe_warn:1; /* warned about RW1C config write */
672 };
673
674 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
675
pci_dev_id(struct pci_dev * dev)676 static inline u16 pci_dev_id(struct pci_dev *dev)
677 {
678 return PCI_DEVID(dev->bus->number, dev->devfn);
679 }
680
681 /*
682 * Returns true if the PCI bus is root (behind host-PCI bridge),
683 * false otherwise
684 *
685 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
686 * This is incorrect because "virtual" buses added for SR-IOV (via
687 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
688 */
pci_is_root_bus(struct pci_bus * pbus)689 static inline bool pci_is_root_bus(struct pci_bus *pbus)
690 {
691 return !(pbus->parent);
692 }
693
694 /**
695 * pci_is_bridge - check if the PCI device is a bridge
696 * @dev: PCI device
697 *
698 * Return true if the PCI device is bridge whether it has subordinate
699 * or not.
700 */
pci_is_bridge(struct pci_dev * dev)701 static inline bool pci_is_bridge(struct pci_dev *dev)
702 {
703 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
704 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
705 }
706
707 #define for_each_pci_bridge(dev, bus) \
708 list_for_each_entry(dev, &bus->devices, bus_list) \
709 if (!pci_is_bridge(dev)) {} else
710
pci_upstream_bridge(struct pci_dev * dev)711 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
712 {
713 dev = pci_physfn(dev);
714 if (pci_is_root_bus(dev->bus))
715 return NULL;
716
717 return dev->bus->self;
718 }
719
720 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)721 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
722 {
723 return pci_dev->msi_enabled || pci_dev->msix_enabled;
724 }
725 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)726 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
727 #endif
728
729 /* Error values that may be returned by PCI functions */
730 #define PCIBIOS_SUCCESSFUL 0x00
731 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
732 #define PCIBIOS_BAD_VENDOR_ID 0x83
733 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
734 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
735 #define PCIBIOS_SET_FAILED 0x88
736 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
737
738 /* Translate above to generic errno for passing back through non-PCI code */
pcibios_err_to_errno(int err)739 static inline int pcibios_err_to_errno(int err)
740 {
741 if (err <= PCIBIOS_SUCCESSFUL)
742 return err; /* Assume already errno */
743
744 switch (err) {
745 case PCIBIOS_FUNC_NOT_SUPPORTED:
746 return -ENOENT;
747 case PCIBIOS_BAD_VENDOR_ID:
748 return -ENOTTY;
749 case PCIBIOS_DEVICE_NOT_FOUND:
750 return -ENODEV;
751 case PCIBIOS_BAD_REGISTER_NUMBER:
752 return -EFAULT;
753 case PCIBIOS_SET_FAILED:
754 return -EIO;
755 case PCIBIOS_BUFFER_TOO_SMALL:
756 return -ENOSPC;
757 }
758
759 return -ERANGE;
760 }
761
762 /* Low-level architecture-dependent routines */
763
764 struct pci_ops {
765 int (*add_bus)(struct pci_bus *bus);
766 void (*remove_bus)(struct pci_bus *bus);
767 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
768 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
769 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
770 };
771
772 /*
773 * ACPI needs to be able to access PCI config space before we've done a
774 * PCI bus scan and created pci_bus structures.
775 */
776 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
777 int reg, int len, u32 *val);
778 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
779 int reg, int len, u32 val);
780
781 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
782 typedef u64 pci_bus_addr_t;
783 #else
784 typedef u32 pci_bus_addr_t;
785 #endif
786
787 struct pci_bus_region {
788 pci_bus_addr_t start;
789 pci_bus_addr_t end;
790 };
791
792 struct pci_dynids {
793 spinlock_t lock; /* Protects list, index */
794 struct list_head list; /* For IDs added at runtime */
795 };
796
797
798 /*
799 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
800 * a set of callbacks in struct pci_error_handlers, that device driver
801 * will be notified of PCI bus errors, and will be driven to recovery
802 * when an error occurs.
803 */
804
805 typedef unsigned int __bitwise pci_ers_result_t;
806
807 enum pci_ers_result {
808 /* No result/none/not supported in device driver */
809 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
810
811 /* Device driver can recover without slot reset */
812 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
813
814 /* Device driver wants slot to be reset */
815 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
816
817 /* Device has completely failed, is unrecoverable */
818 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
819
820 /* Device driver is fully recovered and operational */
821 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
822
823 /* No AER capabilities registered for the driver */
824 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
825 };
826
827 /* PCI bus error event callbacks */
828 struct pci_error_handlers {
829 /* PCI bus error detected on this device */
830 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
831 pci_channel_state_t error);
832
833 /* MMIO has been re-enabled, but not DMA */
834 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
835
836 /* PCI slot has been reset */
837 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
838
839 /* PCI function reset prepare or completed */
840 void (*reset_prepare)(struct pci_dev *dev);
841 void (*reset_done)(struct pci_dev *dev);
842
843 /* Device driver may resume normal operations */
844 void (*resume)(struct pci_dev *dev);
845 };
846
847
848 struct module;
849
850 /**
851 * struct pci_driver - PCI driver structure
852 * @node: List of driver structures.
853 * @name: Driver name.
854 * @id_table: Pointer to table of device IDs the driver is
855 * interested in. Most drivers should export this
856 * table using MODULE_DEVICE_TABLE(pci,...).
857 * @probe: This probing function gets called (during execution
858 * of pci_register_driver() for already existing
859 * devices or later if a new device gets inserted) for
860 * all PCI devices which match the ID table and are not
861 * "owned" by the other drivers yet. This function gets
862 * passed a "struct pci_dev \*" for each device whose
863 * entry in the ID table matches the device. The probe
864 * function returns zero when the driver chooses to
865 * take "ownership" of the device or an error code
866 * (negative number) otherwise.
867 * The probe function always gets called from process
868 * context, so it can sleep.
869 * @remove: The remove() function gets called whenever a device
870 * being handled by this driver is removed (either during
871 * deregistration of the driver or when it's manually
872 * pulled out of a hot-pluggable slot).
873 * The remove function always gets called from process
874 * context, so it can sleep.
875 * @suspend: Put device into low power state.
876 * @resume: Wake device from low power state.
877 * (Please see Documentation/power/pci.rst for descriptions
878 * of PCI Power Management and the related functions.)
879 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
880 * Intended to stop any idling DMA operations.
881 * Useful for enabling wake-on-lan (NIC) or changing
882 * the power state of a device before reboot.
883 * e.g. drivers/net/e100.c.
884 * @sriov_configure: Optional driver callback to allow configuration of
885 * number of VFs to enable via sysfs "sriov_numvfs" file.
886 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
887 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
888 * This will change MSI-X Table Size in the VF Message Control
889 * registers.
890 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
891 * MSI-X vectors available for distribution to the VFs.
892 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
893 * @groups: Sysfs attribute groups.
894 * @dev_groups: Attributes attached to the device that will be
895 * created once it is bound to the driver.
896 * @driver: Driver model structure.
897 * @dynids: List of dynamically added device IDs.
898 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
899 * For most device drivers, no need to care about this flag
900 * as long as all DMAs are handled through the kernel DMA API.
901 * For some special ones, for example VFIO drivers, they know
902 * how to manage the DMA themselves and set this flag so that
903 * the IOMMU layer will allow them to setup and manage their
904 * own I/O address space.
905 */
906 struct pci_driver {
907 struct list_head node;
908 const char *name;
909 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
910 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
911 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
912 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
913 int (*resume)(struct pci_dev *dev); /* Device woken up */
914 void (*shutdown)(struct pci_dev *dev);
915 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
916 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
917 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
918 const struct pci_error_handlers *err_handler;
919 const struct attribute_group **groups;
920 const struct attribute_group **dev_groups;
921 struct device_driver driver;
922 struct pci_dynids dynids;
923 bool driver_managed_dma;
924 };
925
to_pci_driver(struct device_driver * drv)926 static inline struct pci_driver *to_pci_driver(struct device_driver *drv)
927 {
928 return drv ? container_of(drv, struct pci_driver, driver) : NULL;
929 }
930
931 /**
932 * PCI_DEVICE - macro used to describe a specific PCI device
933 * @vend: the 16 bit PCI Vendor ID
934 * @dev: the 16 bit PCI Device ID
935 *
936 * This macro is used to create a struct pci_device_id that matches a
937 * specific device. The subvendor and subdevice fields will be set to
938 * PCI_ANY_ID.
939 */
940 #define PCI_DEVICE(vend,dev) \
941 .vendor = (vend), .device = (dev), \
942 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
943
944 /**
945 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
946 * override_only flags.
947 * @vend: the 16 bit PCI Vendor ID
948 * @dev: the 16 bit PCI Device ID
949 * @driver_override: the 32 bit PCI Device override_only
950 *
951 * This macro is used to create a struct pci_device_id that matches only a
952 * driver_override device. The subvendor and subdevice fields will be set to
953 * PCI_ANY_ID.
954 */
955 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
956 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
957 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
958
959 /**
960 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
961 * "driver_override" PCI device.
962 * @vend: the 16 bit PCI Vendor ID
963 * @dev: the 16 bit PCI Device ID
964 *
965 * This macro is used to create a struct pci_device_id that matches a
966 * specific device. The subvendor and subdevice fields will be set to
967 * PCI_ANY_ID and the driver_override will be set to
968 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
969 */
970 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
971 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
972
973 /**
974 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
975 * @vend: the 16 bit PCI Vendor ID
976 * @dev: the 16 bit PCI Device ID
977 * @subvend: the 16 bit PCI Subvendor ID
978 * @subdev: the 16 bit PCI Subdevice ID
979 *
980 * This macro is used to create a struct pci_device_id that matches a
981 * specific device with subsystem information.
982 */
983 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
984 .vendor = (vend), .device = (dev), \
985 .subvendor = (subvend), .subdevice = (subdev)
986
987 /**
988 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
989 * @dev_class: the class, subclass, prog-if triple for this device
990 * @dev_class_mask: the class mask for this device
991 *
992 * This macro is used to create a struct pci_device_id that matches a
993 * specific PCI class. The vendor, device, subvendor, and subdevice
994 * fields will be set to PCI_ANY_ID.
995 */
996 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
997 .class = (dev_class), .class_mask = (dev_class_mask), \
998 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
999 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1000
1001 /**
1002 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
1003 * @vend: the vendor name
1004 * @dev: the 16 bit PCI Device ID
1005 *
1006 * This macro is used to create a struct pci_device_id that matches a
1007 * specific PCI device. The subvendor, and subdevice fields will be set
1008 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1009 * private data.
1010 */
1011 #define PCI_VDEVICE(vend, dev) \
1012 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1013 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1014
1015 /**
1016 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1017 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1018 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1019 * @data: the driver data to be filled
1020 *
1021 * This macro is used to create a struct pci_device_id that matches a
1022 * specific PCI device. The subvendor, and subdevice fields will be set
1023 * to PCI_ANY_ID.
1024 */
1025 #define PCI_DEVICE_DATA(vend, dev, data) \
1026 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1027 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1028 .driver_data = (kernel_ulong_t)(data)
1029
1030 enum {
1031 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1032 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1033 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1034 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1035 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1036 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1037 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1038 };
1039
1040 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1041 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1042 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1043 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1044
1045 /* These external functions are only available when PCI support is enabled */
1046 #ifdef CONFIG_PCI
1047
1048 extern unsigned int pci_flags;
1049
pci_set_flags(int flags)1050 static inline void pci_set_flags(int flags) { pci_flags = flags; }
pci_add_flags(int flags)1051 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
pci_clear_flags(int flags)1052 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
pci_has_flag(int flag)1053 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1054
1055 void pcie_bus_configure_settings(struct pci_bus *bus);
1056
1057 enum pcie_bus_config_types {
1058 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1059 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1060 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1061 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1062 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1063 };
1064
1065 extern enum pcie_bus_config_types pcie_bus_config;
1066
1067 extern struct bus_type pci_bus_type;
1068
1069 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1070 * code, or PCI core code. */
1071 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1072 /* Some device drivers need know if PCI is initiated */
1073 int no_pci_devices(void);
1074
1075 void pcibios_resource_survey_bus(struct pci_bus *bus);
1076 void pcibios_bus_add_device(struct pci_dev *pdev);
1077 void pcibios_add_bus(struct pci_bus *bus);
1078 void pcibios_remove_bus(struct pci_bus *bus);
1079 void pcibios_fixup_bus(struct pci_bus *);
1080 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1081 /* Architecture-specific versions may override this (weak) */
1082 char *pcibios_setup(char *str);
1083
1084 /* Used only when drivers/pci/setup.c is used */
1085 resource_size_t pcibios_align_resource(void *, const struct resource *,
1086 resource_size_t,
1087 resource_size_t);
1088
1089 /* Weak but can be overridden by arch */
1090 void pci_fixup_cardbus(struct pci_bus *);
1091
1092 /* Generic PCI functions used internally */
1093
1094 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1095 struct resource *res);
1096 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1097 struct pci_bus_region *region);
1098 void pcibios_scan_specific_bus(int busn);
1099 struct pci_bus *pci_find_bus(int domain, int busnr);
1100 void pci_bus_add_devices(const struct pci_bus *bus);
1101 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1102 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1103 struct pci_ops *ops, void *sysdata,
1104 struct list_head *resources);
1105 int pci_host_probe(struct pci_host_bridge *bridge);
1106 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1107 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1108 void pci_bus_release_busn_res(struct pci_bus *b);
1109 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1110 struct pci_ops *ops, void *sysdata,
1111 struct list_head *resources);
1112 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1113 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1114 int busnr);
1115 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1116 const char *name,
1117 struct hotplug_slot *hotplug);
1118 void pci_destroy_slot(struct pci_slot *slot);
1119 #ifdef CONFIG_SYSFS
1120 void pci_dev_assign_slot(struct pci_dev *dev);
1121 #else
pci_dev_assign_slot(struct pci_dev * dev)1122 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1123 #endif
1124 int pci_scan_slot(struct pci_bus *bus, int devfn);
1125 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1126 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1127 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1128 void pci_bus_add_device(struct pci_dev *dev);
1129 void pci_read_bridge_bases(struct pci_bus *child);
1130 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1131 struct resource *res);
1132 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1133 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1134 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1135 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1136 void pci_dev_put(struct pci_dev *dev);
1137 void pci_remove_bus(struct pci_bus *b);
1138 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1139 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1140 void pci_stop_root_bus(struct pci_bus *bus);
1141 void pci_remove_root_bus(struct pci_bus *bus);
1142 void pci_setup_cardbus(struct pci_bus *bus);
1143 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1144 void pci_sort_breadthfirst(void);
1145 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1146 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1147
1148 /* Generic PCI functions exported to card drivers */
1149
1150 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1151 u8 pci_find_capability(struct pci_dev *dev, int cap);
1152 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1153 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1154 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1155 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1156 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1157 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1158 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1159 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1160
1161 u64 pci_get_dsn(struct pci_dev *dev);
1162
1163 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1164 struct pci_dev *from);
1165 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1166 unsigned int ss_vendor, unsigned int ss_device,
1167 struct pci_dev *from);
1168 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1169 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1170 unsigned int devfn);
1171 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1172 int pci_dev_present(const struct pci_device_id *ids);
1173
1174 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1175 int where, u8 *val);
1176 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1177 int where, u16 *val);
1178 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1179 int where, u32 *val);
1180 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1181 int where, u8 val);
1182 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1183 int where, u16 val);
1184 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1185 int where, u32 val);
1186
1187 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1188 int where, int size, u32 *val);
1189 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1190 int where, int size, u32 val);
1191 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1192 int where, int size, u32 *val);
1193 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1194 int where, int size, u32 val);
1195
1196 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1197
1198 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1199 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1200 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1201 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1202 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1203 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1204
1205 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1206 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1207 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1208 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1209 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1210 u16 clear, u16 set);
1211 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1212 u32 clear, u32 set);
1213
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)1214 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1215 u16 set)
1216 {
1217 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1218 }
1219
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)1220 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1221 u32 set)
1222 {
1223 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1224 }
1225
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)1226 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1227 u16 clear)
1228 {
1229 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1230 }
1231
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)1232 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1233 u32 clear)
1234 {
1235 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1236 }
1237
1238 /* User-space driven config access */
1239 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1240 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1241 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1242 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1243 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1244 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1245
1246 int __must_check pci_enable_device(struct pci_dev *dev);
1247 int __must_check pci_enable_device_io(struct pci_dev *dev);
1248 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1249 int __must_check pci_reenable_device(struct pci_dev *);
1250 int __must_check pcim_enable_device(struct pci_dev *pdev);
1251 void pcim_pin_device(struct pci_dev *pdev);
1252
pci_intx_mask_supported(struct pci_dev * pdev)1253 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1254 {
1255 /*
1256 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1257 * writable and no quirk has marked the feature broken.
1258 */
1259 return !pdev->broken_intx_masking;
1260 }
1261
pci_is_enabled(struct pci_dev * pdev)1262 static inline int pci_is_enabled(struct pci_dev *pdev)
1263 {
1264 return (atomic_read(&pdev->enable_cnt) > 0);
1265 }
1266
pci_is_managed(struct pci_dev * pdev)1267 static inline int pci_is_managed(struct pci_dev *pdev)
1268 {
1269 return pdev->is_managed;
1270 }
1271
1272 void pci_disable_device(struct pci_dev *dev);
1273
1274 extern unsigned int pcibios_max_latency;
1275 void pci_set_master(struct pci_dev *dev);
1276 void pci_clear_master(struct pci_dev *dev);
1277
1278 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1279 int pci_set_cacheline_size(struct pci_dev *dev);
1280 int __must_check pci_set_mwi(struct pci_dev *dev);
1281 int __must_check pcim_set_mwi(struct pci_dev *dev);
1282 int pci_try_set_mwi(struct pci_dev *dev);
1283 void pci_clear_mwi(struct pci_dev *dev);
1284 void pci_disable_parity(struct pci_dev *dev);
1285 void pci_intx(struct pci_dev *dev, int enable);
1286 bool pci_check_and_mask_intx(struct pci_dev *dev);
1287 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1288 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1289 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1290 int pcix_get_max_mmrbc(struct pci_dev *dev);
1291 int pcix_get_mmrbc(struct pci_dev *dev);
1292 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1293 int pcie_get_readrq(struct pci_dev *dev);
1294 int pcie_set_readrq(struct pci_dev *dev, int rq);
1295 int pcie_get_mps(struct pci_dev *dev);
1296 int pcie_set_mps(struct pci_dev *dev, int mps);
1297 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1298 enum pci_bus_speed *speed,
1299 enum pcie_link_width *width);
1300 void pcie_print_link_status(struct pci_dev *dev);
1301 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1302 int pcie_flr(struct pci_dev *dev);
1303 int __pci_reset_function_locked(struct pci_dev *dev);
1304 int pci_reset_function(struct pci_dev *dev);
1305 int pci_reset_function_locked(struct pci_dev *dev);
1306 int pci_try_reset_function(struct pci_dev *dev);
1307 int pci_probe_reset_slot(struct pci_slot *slot);
1308 int pci_probe_reset_bus(struct pci_bus *bus);
1309 int pci_reset_bus(struct pci_dev *dev);
1310 void pci_reset_secondary_bus(struct pci_dev *dev);
1311 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1312 void pci_update_resource(struct pci_dev *dev, int resno);
1313 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1314 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1315 void pci_release_resource(struct pci_dev *dev, int resno);
pci_rebar_bytes_to_size(u64 bytes)1316 static inline int pci_rebar_bytes_to_size(u64 bytes)
1317 {
1318 bytes = roundup_pow_of_two(bytes);
1319
1320 /* Return BAR size as defined in the resizable BAR specification */
1321 return max(ilog2(bytes), 20) - 20;
1322 }
1323
1324 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1325 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1326 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1327 bool pci_device_is_present(struct pci_dev *pdev);
1328 void pci_ignore_hotplug(struct pci_dev *dev);
1329 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1330 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1331
1332 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1333 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1334 const char *fmt, ...);
1335 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1336
1337 /* ROM control related routines */
1338 int pci_enable_rom(struct pci_dev *pdev);
1339 void pci_disable_rom(struct pci_dev *pdev);
1340 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1341 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1342
1343 /* Power management related routines */
1344 int pci_save_state(struct pci_dev *dev);
1345 void pci_restore_state(struct pci_dev *dev);
1346 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1347 int pci_load_saved_state(struct pci_dev *dev,
1348 struct pci_saved_state *state);
1349 int pci_load_and_free_saved_state(struct pci_dev *dev,
1350 struct pci_saved_state **state);
1351 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1352 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1353 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1354 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1355 void pci_pme_active(struct pci_dev *dev, bool enable);
1356 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1357 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1358 int pci_prepare_to_sleep(struct pci_dev *dev);
1359 int pci_back_from_sleep(struct pci_dev *dev);
1360 bool pci_dev_run_wake(struct pci_dev *dev);
1361 void pci_d3cold_enable(struct pci_dev *dev);
1362 void pci_d3cold_disable(struct pci_dev *dev);
1363 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1364 void pci_resume_bus(struct pci_bus *bus);
1365 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1366
1367 /* For use by arch with custom probe code */
1368 void set_pcie_port_type(struct pci_dev *pdev);
1369 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1370
1371 /* Functions for PCI Hotplug drivers to use */
1372 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1373 unsigned int pci_rescan_bus(struct pci_bus *bus);
1374 void pci_lock_rescan_remove(void);
1375 void pci_unlock_rescan_remove(void);
1376
1377 /* Vital Product Data routines */
1378 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1379 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1380 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1381 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1382
1383 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1384 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1385 void pci_bus_assign_resources(const struct pci_bus *bus);
1386 void pci_bus_claim_resources(struct pci_bus *bus);
1387 void pci_bus_size_bridges(struct pci_bus *bus);
1388 int pci_claim_resource(struct pci_dev *, int);
1389 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1390 void pci_assign_unassigned_resources(void);
1391 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1392 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1393 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1394 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1395 void pdev_enable_device(struct pci_dev *);
1396 int pci_enable_resources(struct pci_dev *, int mask);
1397 void pci_assign_irq(struct pci_dev *dev);
1398 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1399 #define HAVE_PCI_REQ_REGIONS 2
1400 int __must_check pci_request_regions(struct pci_dev *, const char *);
1401 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1402 void pci_release_regions(struct pci_dev *);
1403 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1404 void pci_release_region(struct pci_dev *, int);
1405 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1406 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1407 void pci_release_selected_regions(struct pci_dev *, int);
1408
1409 /* drivers/pci/bus.c */
1410 void pci_add_resource(struct list_head *resources, struct resource *res);
1411 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1412 resource_size_t offset);
1413 void pci_free_resource_list(struct list_head *resources);
1414 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1415 unsigned int flags);
1416 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1417 void pci_bus_remove_resources(struct pci_bus *bus);
1418 int devm_request_pci_bus_resources(struct device *dev,
1419 struct list_head *resources);
1420
1421 /* Temporary until new and working PCI SBR API in place */
1422 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1423
1424 #define pci_bus_for_each_resource(bus, res, i) \
1425 for (i = 0; \
1426 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1427 i++)
1428
1429 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1430 struct resource *res, resource_size_t size,
1431 resource_size_t align, resource_size_t min,
1432 unsigned long type_mask,
1433 resource_size_t (*alignf)(void *,
1434 const struct resource *,
1435 resource_size_t,
1436 resource_size_t),
1437 void *alignf_data);
1438
1439
1440 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1441 resource_size_t size);
1442 unsigned long pci_address_to_pio(phys_addr_t addr);
1443 phys_addr_t pci_pio_to_address(unsigned long pio);
1444 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1445 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1446 phys_addr_t phys_addr);
1447 void pci_unmap_iospace(struct resource *res);
1448 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1449 resource_size_t offset,
1450 resource_size_t size);
1451 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1452 struct resource *res);
1453
pci_bus_address(struct pci_dev * pdev,int bar)1454 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1455 {
1456 struct pci_bus_region region;
1457
1458 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1459 return region.start;
1460 }
1461
1462 /* Proper probing supporting hot-pluggable devices */
1463 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1464 const char *mod_name);
1465
1466 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1467 #define pci_register_driver(driver) \
1468 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1469
1470 void pci_unregister_driver(struct pci_driver *dev);
1471
1472 /**
1473 * module_pci_driver() - Helper macro for registering a PCI driver
1474 * @__pci_driver: pci_driver struct
1475 *
1476 * Helper macro for PCI drivers which do not do anything special in module
1477 * init/exit. This eliminates a lot of boilerplate. Each module may only
1478 * use this macro once, and calling it replaces module_init() and module_exit()
1479 */
1480 #define module_pci_driver(__pci_driver) \
1481 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1482
1483 /**
1484 * builtin_pci_driver() - Helper macro for registering a PCI driver
1485 * @__pci_driver: pci_driver struct
1486 *
1487 * Helper macro for PCI drivers which do not do anything special in their
1488 * init code. This eliminates a lot of boilerplate. Each driver may only
1489 * use this macro once, and calling it replaces device_initcall(...)
1490 */
1491 #define builtin_pci_driver(__pci_driver) \
1492 builtin_driver(__pci_driver, pci_register_driver)
1493
1494 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1495 int pci_add_dynid(struct pci_driver *drv,
1496 unsigned int vendor, unsigned int device,
1497 unsigned int subvendor, unsigned int subdevice,
1498 unsigned int class, unsigned int class_mask,
1499 unsigned long driver_data);
1500 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1501 struct pci_dev *dev);
1502 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1503 int pass);
1504
1505 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1506 void *userdata);
1507 int pci_cfg_space_size(struct pci_dev *dev);
1508 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1509 void pci_setup_bridge(struct pci_bus *bus);
1510 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1511 unsigned long type);
1512
1513 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1514 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1515
1516 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1517 unsigned int command_bits, u32 flags);
1518
1519 /*
1520 * Virtual interrupts allow for more interrupts to be allocated
1521 * than the device has interrupts for. These are not programmed
1522 * into the device's MSI-X table and must be handled by some
1523 * other driver means.
1524 */
1525 #define PCI_IRQ_VIRTUAL (1 << 4)
1526
1527 #define PCI_IRQ_ALL_TYPES \
1528 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1529
1530 #include <linux/dmapool.h>
1531
1532 struct msix_entry {
1533 u32 vector; /* Kernel uses to write allocated vector */
1534 u16 entry; /* Driver uses to specify entry, OS writes */
1535 };
1536
1537 #ifdef CONFIG_PCI_MSI
1538 int pci_msi_vec_count(struct pci_dev *dev);
1539 void pci_disable_msi(struct pci_dev *dev);
1540 int pci_msix_vec_count(struct pci_dev *dev);
1541 void pci_disable_msix(struct pci_dev *dev);
1542 void pci_restore_msi_state(struct pci_dev *dev);
1543 int pci_msi_enabled(void);
1544 int pci_enable_msi(struct pci_dev *dev);
1545 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1546 int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1547 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1548 struct msix_entry *entries, int nvec)
1549 {
1550 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1551 if (rc < 0)
1552 return rc;
1553 return 0;
1554 }
1555 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1556 unsigned int max_vecs, unsigned int flags,
1557 struct irq_affinity *affd);
1558
1559 void pci_free_irq_vectors(struct pci_dev *dev);
1560 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1561 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1562
1563 #else
pci_msi_vec_count(struct pci_dev * dev)1564 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msi(struct pci_dev * dev)1565 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1566 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msix(struct pci_dev * dev)1567 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1568 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1569 static inline int pci_msi_enabled(void) { return 0; }
pci_enable_msi(struct pci_dev * dev)1570 static inline int pci_enable_msi(struct pci_dev *dev)
1571 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1572 static inline int pci_enable_msix_range(struct pci_dev *dev,
1573 struct msix_entry *entries, int minvec, int maxvec)
1574 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1575 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1576 struct msix_entry *entries, int nvec)
1577 { return -ENOSYS; }
1578
1579 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1580 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1581 unsigned int max_vecs, unsigned int flags,
1582 struct irq_affinity *aff_desc)
1583 {
1584 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1585 return 1;
1586 return -ENOSPC;
1587 }
1588
pci_free_irq_vectors(struct pci_dev * dev)1589 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1590 {
1591 }
1592
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1593 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1594 {
1595 if (WARN_ON_ONCE(nr > 0))
1596 return -EINVAL;
1597 return dev->irq;
1598 }
pci_irq_get_affinity(struct pci_dev * pdev,int vec)1599 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1600 int vec)
1601 {
1602 return cpu_possible_mask;
1603 }
1604 #endif
1605
1606 /**
1607 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1608 * @d: the INTx IRQ domain
1609 * @node: the DT node for the device whose interrupt we're translating
1610 * @intspec: the interrupt specifier data from the DT
1611 * @intsize: the number of entries in @intspec
1612 * @out_hwirq: pointer at which to write the hwirq number
1613 * @out_type: pointer at which to write the interrupt type
1614 *
1615 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1616 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1617 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1618 * INTx value to obtain the hwirq number.
1619 *
1620 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1621 */
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1622 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1623 struct device_node *node,
1624 const u32 *intspec,
1625 unsigned int intsize,
1626 unsigned long *out_hwirq,
1627 unsigned int *out_type)
1628 {
1629 const u32 intx = intspec[0];
1630
1631 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1632 return -EINVAL;
1633
1634 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1635 return 0;
1636 }
1637
1638 #ifdef CONFIG_PCIEPORTBUS
1639 extern bool pcie_ports_disabled;
1640 extern bool pcie_ports_native;
1641 #else
1642 #define pcie_ports_disabled true
1643 #define pcie_ports_native false
1644 #endif
1645
1646 #define PCIE_LINK_STATE_L0S BIT(0)
1647 #define PCIE_LINK_STATE_L1 BIT(1)
1648 #define PCIE_LINK_STATE_CLKPM BIT(2)
1649 #define PCIE_LINK_STATE_L1_1 BIT(3)
1650 #define PCIE_LINK_STATE_L1_2 BIT(4)
1651 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1652 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1653
1654 #ifdef CONFIG_PCIEASPM
1655 int pci_disable_link_state(struct pci_dev *pdev, int state);
1656 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1657 void pcie_no_aspm(void);
1658 bool pcie_aspm_support_enabled(void);
1659 bool pcie_aspm_enabled(struct pci_dev *pdev);
1660 #else
pci_disable_link_state(struct pci_dev * pdev,int state)1661 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1662 { return 0; }
pci_disable_link_state_locked(struct pci_dev * pdev,int state)1663 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1664 { return 0; }
pcie_no_aspm(void)1665 static inline void pcie_no_aspm(void) { }
pcie_aspm_support_enabled(void)1666 static inline bool pcie_aspm_support_enabled(void) { return false; }
pcie_aspm_enabled(struct pci_dev * pdev)1667 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1668 #endif
1669
1670 #ifdef CONFIG_PCIEAER
1671 bool pci_aer_available(void);
1672 #else
pci_aer_available(void)1673 static inline bool pci_aer_available(void) { return false; }
1674 #endif
1675
1676 bool pci_ats_disabled(void);
1677
1678 #ifdef CONFIG_PCIE_PTM
1679 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1680 bool pcie_ptm_enabled(struct pci_dev *dev);
1681 #else
pci_enable_ptm(struct pci_dev * dev,u8 * granularity)1682 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1683 { return -EINVAL; }
pcie_ptm_enabled(struct pci_dev * dev)1684 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1685 { return false; }
1686 #endif
1687
1688 void pci_cfg_access_lock(struct pci_dev *dev);
1689 bool pci_cfg_access_trylock(struct pci_dev *dev);
1690 void pci_cfg_access_unlock(struct pci_dev *dev);
1691
1692 void pci_dev_lock(struct pci_dev *dev);
1693 int pci_dev_trylock(struct pci_dev *dev);
1694 void pci_dev_unlock(struct pci_dev *dev);
1695
1696 /*
1697 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1698 * a PCI domain is defined to be a set of PCI buses which share
1699 * configuration space.
1700 */
1701 #ifdef CONFIG_PCI_DOMAINS
1702 extern int pci_domains_supported;
1703 #else
1704 enum { pci_domains_supported = 0 };
pci_domain_nr(struct pci_bus * bus)1705 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_proc_domain(struct pci_bus * bus)1706 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1707 #endif /* CONFIG_PCI_DOMAINS */
1708
1709 /*
1710 * Generic implementation for PCI domain support. If your
1711 * architecture does not need custom management of PCI
1712 * domains then this implementation will be used
1713 */
1714 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)1715 static inline int pci_domain_nr(struct pci_bus *bus)
1716 {
1717 return bus->domain_nr;
1718 }
1719 #ifdef CONFIG_ACPI
1720 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1721 #else
acpi_pci_bus_find_domain_nr(struct pci_bus * bus)1722 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1723 { return 0; }
1724 #endif
1725 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1726 #endif
1727
1728 /* Some architectures require additional setup to direct VGA traffic */
1729 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1730 unsigned int command_bits, u32 flags);
1731 void pci_register_set_vga_state(arch_set_vga_state_t func);
1732
1733 static inline int
pci_request_io_regions(struct pci_dev * pdev,const char * name)1734 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1735 {
1736 return pci_request_selected_regions(pdev,
1737 pci_select_bars(pdev, IORESOURCE_IO), name);
1738 }
1739
1740 static inline void
pci_release_io_regions(struct pci_dev * pdev)1741 pci_release_io_regions(struct pci_dev *pdev)
1742 {
1743 return pci_release_selected_regions(pdev,
1744 pci_select_bars(pdev, IORESOURCE_IO));
1745 }
1746
1747 static inline int
pci_request_mem_regions(struct pci_dev * pdev,const char * name)1748 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1749 {
1750 return pci_request_selected_regions(pdev,
1751 pci_select_bars(pdev, IORESOURCE_MEM), name);
1752 }
1753
1754 static inline void
pci_release_mem_regions(struct pci_dev * pdev)1755 pci_release_mem_regions(struct pci_dev *pdev)
1756 {
1757 return pci_release_selected_regions(pdev,
1758 pci_select_bars(pdev, IORESOURCE_MEM));
1759 }
1760
1761 #else /* CONFIG_PCI is not enabled */
1762
pci_set_flags(int flags)1763 static inline void pci_set_flags(int flags) { }
pci_add_flags(int flags)1764 static inline void pci_add_flags(int flags) { }
pci_clear_flags(int flags)1765 static inline void pci_clear_flags(int flags) { }
pci_has_flag(int flag)1766 static inline int pci_has_flag(int flag) { return 0; }
1767
1768 /*
1769 * If the system does not have PCI, clearly these return errors. Define
1770 * these as simple inline functions to avoid hair in drivers.
1771 */
1772 #define _PCI_NOP(o, s, t) \
1773 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1774 int where, t val) \
1775 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1776
1777 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1778 _PCI_NOP(o, word, u16 x) \
1779 _PCI_NOP(o, dword, u32 x)
1780 _PCI_NOP_ALL(read, *)
1781 _PCI_NOP_ALL(write,)
1782
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)1783 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1784 unsigned int device,
1785 struct pci_dev *from)
1786 { return NULL; }
1787
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)1788 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1789 unsigned int device,
1790 unsigned int ss_vendor,
1791 unsigned int ss_device,
1792 struct pci_dev *from)
1793 { return NULL; }
1794
pci_get_class(unsigned int class,struct pci_dev * from)1795 static inline struct pci_dev *pci_get_class(unsigned int class,
1796 struct pci_dev *from)
1797 { return NULL; }
1798
1799
pci_dev_present(const struct pci_device_id * ids)1800 static inline int pci_dev_present(const struct pci_device_id *ids)
1801 { return 0; }
1802
1803 #define no_pci_devices() (1)
1804 #define pci_dev_put(dev) do { } while (0)
1805
pci_set_master(struct pci_dev * dev)1806 static inline void pci_set_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)1807 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)1808 static inline void pci_disable_device(struct pci_dev *dev) { }
pcim_enable_device(struct pci_dev * pdev)1809 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)1810 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1811 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner,const char * mod_name)1812 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1813 struct module *owner,
1814 const char *mod_name)
1815 { return 0; }
pci_register_driver(struct pci_driver * drv)1816 static inline int pci_register_driver(struct pci_driver *drv)
1817 { return 0; }
pci_unregister_driver(struct pci_driver * drv)1818 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)1819 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1820 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)1821 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1822 int cap)
1823 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)1824 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1825 { return 0; }
1826
pci_get_dsn(struct pci_dev * dev)1827 static inline u64 pci_get_dsn(struct pci_dev *dev)
1828 { return 0; }
1829
1830 /* Power management related routines */
pci_save_state(struct pci_dev * dev)1831 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)1832 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1833 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1834 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)1835 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1836 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)1837 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1838 pm_message_t state)
1839 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)1840 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1841 int enable)
1842 { return 0; }
1843
pci_find_resource(struct pci_dev * dev,struct resource * res)1844 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1845 struct resource *res)
1846 { return NULL; }
pci_request_regions(struct pci_dev * dev,const char * res_name)1847 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1848 { return -EIO; }
pci_release_regions(struct pci_dev * dev)1849 static inline void pci_release_regions(struct pci_dev *dev) { }
1850
pci_register_io_range(struct fwnode_handle * fwnode,phys_addr_t addr,resource_size_t size)1851 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1852 phys_addr_t addr, resource_size_t size)
1853 { return -EINVAL; }
1854
pci_address_to_pio(phys_addr_t addr)1855 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1856
pci_find_next_bus(const struct pci_bus * from)1857 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1858 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)1859 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1860 unsigned int devfn)
1861 { return NULL; }
pci_get_domain_bus_and_slot(int domain,unsigned int bus,unsigned int devfn)1862 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1863 unsigned int bus, unsigned int devfn)
1864 { return NULL; }
1865
pci_domain_nr(struct pci_bus * bus)1866 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)1867 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1868
1869 #define dev_is_pci(d) (false)
1870 #define dev_is_pf(d) (false)
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)1871 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1872 { return false; }
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1873 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1874 struct device_node *node,
1875 const u32 *intspec,
1876 unsigned int intsize,
1877 unsigned long *out_hwirq,
1878 unsigned int *out_type)
1879 { return -EINVAL; }
1880
pci_match_id(const struct pci_device_id * ids,struct pci_dev * dev)1881 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1882 struct pci_dev *dev)
1883 { return NULL; }
pci_ats_disabled(void)1884 static inline bool pci_ats_disabled(void) { return true; }
1885
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1886 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1887 {
1888 return -EINVAL;
1889 }
1890
1891 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1892 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1893 unsigned int max_vecs, unsigned int flags,
1894 struct irq_affinity *aff_desc)
1895 {
1896 return -ENOSPC;
1897 }
1898 #endif /* CONFIG_PCI */
1899
1900 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1901 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1902 unsigned int max_vecs, unsigned int flags)
1903 {
1904 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1905 NULL);
1906 }
1907
1908 /* Include architecture-dependent settings and functions */
1909
1910 #include <asm/pci.h>
1911
1912 /* These two functions provide almost identical functionality. Depending
1913 * on the architecture, one will be implemented as a wrapper around the
1914 * other (in drivers/pci/mmap.c).
1915 *
1916 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1917 * is expected to be an offset within that region.
1918 *
1919 * pci_mmap_page_range() is the legacy architecture-specific interface,
1920 * which accepts a "user visible" resource address converted by
1921 * pci_resource_to_user(), as used in the legacy mmap() interface in
1922 * /proc/bus/pci/.
1923 */
1924 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1925 struct vm_area_struct *vma,
1926 enum pci_mmap_state mmap_state, int write_combine);
1927 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1928 struct vm_area_struct *vma,
1929 enum pci_mmap_state mmap_state, int write_combine);
1930
1931 #ifndef arch_can_pci_mmap_wc
1932 #define arch_can_pci_mmap_wc() 0
1933 #endif
1934
1935 #ifndef arch_can_pci_mmap_io
1936 #define arch_can_pci_mmap_io() 0
1937 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1938 #else
1939 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1940 #endif
1941
1942 #ifndef pci_root_bus_fwnode
1943 #define pci_root_bus_fwnode(bus) NULL
1944 #endif
1945
1946 /*
1947 * These helpers provide future and backwards compatibility
1948 * for accessing popular PCI BAR info
1949 */
1950 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1951 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1952 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1953 #define pci_resource_len(dev,bar) \
1954 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
1955 \
1956 (pci_resource_end((dev), (bar)) - \
1957 pci_resource_start((dev), (bar)) + 1))
1958
1959 /*
1960 * Similar to the helpers above, these manipulate per-pci_dev
1961 * driver-specific data. They are really just a wrapper around
1962 * the generic device structure functions of these calls.
1963 */
pci_get_drvdata(struct pci_dev * pdev)1964 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1965 {
1966 return dev_get_drvdata(&pdev->dev);
1967 }
1968
pci_set_drvdata(struct pci_dev * pdev,void * data)1969 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1970 {
1971 dev_set_drvdata(&pdev->dev, data);
1972 }
1973
pci_name(const struct pci_dev * pdev)1974 static inline const char *pci_name(const struct pci_dev *pdev)
1975 {
1976 return dev_name(&pdev->dev);
1977 }
1978
1979 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1980 const struct resource *rsrc,
1981 resource_size_t *start, resource_size_t *end);
1982
1983 /*
1984 * The world is not perfect and supplies us with broken PCI devices.
1985 * For at least a part of these bugs we need a work-around, so both
1986 * generic (drivers/pci/quirks.c) and per-architecture code can define
1987 * fixup hooks to be called for particular buggy devices.
1988 */
1989
1990 struct pci_fixup {
1991 u16 vendor; /* Or PCI_ANY_ID */
1992 u16 device; /* Or PCI_ANY_ID */
1993 u32 class; /* Or PCI_ANY_ID */
1994 unsigned int class_shift; /* should be 0, 8, 16 */
1995 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1996 int hook_offset;
1997 #else
1998 void (*hook)(struct pci_dev *dev);
1999 #endif
2000 };
2001
2002 enum pci_fixup_pass {
2003 pci_fixup_early, /* Before probing BARs */
2004 pci_fixup_header, /* After reading configuration header */
2005 pci_fixup_final, /* Final phase of device fixups */
2006 pci_fixup_enable, /* pci_enable_device() time */
2007 pci_fixup_resume, /* pci_device_resume() */
2008 pci_fixup_suspend, /* pci_device_suspend() */
2009 pci_fixup_resume_early, /* pci_device_resume_early() */
2010 pci_fixup_suspend_late, /* pci_device_suspend_late() */
2011 };
2012
2013 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2014 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2015 class_shift, hook) \
2016 __ADDRESSABLE(hook) \
2017 asm(".section " #sec ", \"a\" \n" \
2018 ".balign 16 \n" \
2019 ".short " #vendor ", " #device " \n" \
2020 ".long " #class ", " #class_shift " \n" \
2021 ".long " #hook " - . \n" \
2022 ".previous \n");
2023
2024 /*
2025 * Clang's LTO may rename static functions in C, but has no way to
2026 * handle such renamings when referenced from inline asm. To work
2027 * around this, create global C stubs for these cases.
2028 */
2029 #ifdef CONFIG_LTO_CLANG
2030 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2031 class_shift, hook, stub) \
2032 void __cficanonical stub(struct pci_dev *dev); \
2033 void __cficanonical stub(struct pci_dev *dev) \
2034 { \
2035 hook(dev); \
2036 } \
2037 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2038 class_shift, stub)
2039 #else
2040 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2041 class_shift, hook, stub) \
2042 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2043 class_shift, hook)
2044 #endif
2045
2046 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2047 class_shift, hook) \
2048 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2049 class_shift, hook, __UNIQUE_ID(hook))
2050 #else
2051 /* Anonymous variables would be nice... */
2052 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2053 class_shift, hook) \
2054 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2055 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2056 = { vendor, device, class, class_shift, hook };
2057 #endif
2058
2059 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2060 class_shift, hook) \
2061 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2062 hook, vendor, device, class, class_shift, hook)
2063 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2064 class_shift, hook) \
2065 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2066 hook, vendor, device, class, class_shift, hook)
2067 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2068 class_shift, hook) \
2069 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2070 hook, vendor, device, class, class_shift, hook)
2071 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2072 class_shift, hook) \
2073 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2074 hook, vendor, device, class, class_shift, hook)
2075 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2076 class_shift, hook) \
2077 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2078 resume##hook, vendor, device, class, class_shift, hook)
2079 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2080 class_shift, hook) \
2081 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2082 resume_early##hook, vendor, device, class, class_shift, hook)
2083 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2084 class_shift, hook) \
2085 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2086 suspend##hook, vendor, device, class, class_shift, hook)
2087 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2088 class_shift, hook) \
2089 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2090 suspend_late##hook, vendor, device, class, class_shift, hook)
2091
2092 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2093 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2094 hook, vendor, device, PCI_ANY_ID, 0, hook)
2095 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2096 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2097 hook, vendor, device, PCI_ANY_ID, 0, hook)
2098 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2099 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2100 hook, vendor, device, PCI_ANY_ID, 0, hook)
2101 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2102 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2103 hook, vendor, device, PCI_ANY_ID, 0, hook)
2104 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2105 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2106 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2107 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2108 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2109 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2110 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2111 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2112 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2113 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2114 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2115 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2116
2117 #ifdef CONFIG_PCI_QUIRKS
2118 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2119 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)2120 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2121 struct pci_dev *dev) { }
2122 #endif
2123
2124 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2125 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2126 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2127 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2128 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2129 const char *name);
2130 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2131
2132 extern int pci_pci_problems;
2133 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2134 #define PCIPCI_TRITON 2
2135 #define PCIPCI_NATOMA 4
2136 #define PCIPCI_VIAETBF 8
2137 #define PCIPCI_VSFX 16
2138 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2139 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2140
2141 extern unsigned long pci_cardbus_io_size;
2142 extern unsigned long pci_cardbus_mem_size;
2143 extern u8 pci_dfl_cache_line_size;
2144 extern u8 pci_cache_line_size;
2145
2146 /* Architecture-specific versions may override these (weak) */
2147 void pcibios_disable_device(struct pci_dev *dev);
2148 void pcibios_set_master(struct pci_dev *dev);
2149 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2150 enum pcie_reset_state state);
2151 int pcibios_device_add(struct pci_dev *dev);
2152 void pcibios_release_device(struct pci_dev *dev);
2153 #ifdef CONFIG_PCI
2154 void pcibios_penalize_isa_irq(int irq, int active);
2155 #else
pcibios_penalize_isa_irq(int irq,int active)2156 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2157 #endif
2158 int pcibios_alloc_irq(struct pci_dev *dev);
2159 void pcibios_free_irq(struct pci_dev *dev);
2160 resource_size_t pcibios_default_alignment(void);
2161
2162 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2163 void __init pci_mmcfg_early_init(void);
2164 void __init pci_mmcfg_late_init(void);
2165 #else
pci_mmcfg_early_init(void)2166 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)2167 static inline void pci_mmcfg_late_init(void) { }
2168 #endif
2169
2170 int pci_ext_cfg_avail(void);
2171
2172 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2173 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2174
2175 #ifdef CONFIG_PCI_IOV
2176 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2177 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2178 int pci_iov_vf_id(struct pci_dev *dev);
2179 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
2180 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2181 void pci_disable_sriov(struct pci_dev *dev);
2182
2183 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2184 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2185 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2186 int pci_num_vf(struct pci_dev *dev);
2187 int pci_vfs_assigned(struct pci_dev *dev);
2188 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2189 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2190 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2191 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2192 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2193
2194 /* Arch may override these (weak) */
2195 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2196 int pcibios_sriov_disable(struct pci_dev *pdev);
2197 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2198 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)2199 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2200 {
2201 return -ENOSYS;
2202 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)2203 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2204 {
2205 return -ENOSYS;
2206 }
2207
pci_iov_vf_id(struct pci_dev * dev)2208 static inline int pci_iov_vf_id(struct pci_dev *dev)
2209 {
2210 return -ENOSYS;
2211 }
2212
pci_iov_get_pf_drvdata(struct pci_dev * dev,struct pci_driver * pf_driver)2213 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2214 struct pci_driver *pf_driver)
2215 {
2216 return ERR_PTR(-EINVAL);
2217 }
2218
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)2219 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2220 { return -ENODEV; }
2221
pci_iov_sysfs_link(struct pci_dev * dev,struct pci_dev * virtfn,int id)2222 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2223 struct pci_dev *virtfn, int id)
2224 {
2225 return -ENODEV;
2226 }
pci_iov_add_virtfn(struct pci_dev * dev,int id)2227 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2228 {
2229 return -ENOSYS;
2230 }
pci_iov_remove_virtfn(struct pci_dev * dev,int id)2231 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2232 int id) { }
pci_disable_sriov(struct pci_dev * dev)2233 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)2234 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)2235 static inline int pci_vfs_assigned(struct pci_dev *dev)
2236 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)2237 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2238 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)2239 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2240 { return 0; }
2241 #define pci_sriov_configure_simple NULL
pci_iov_resource_size(struct pci_dev * dev,int resno)2242 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2243 { return 0; }
pci_vf_drivers_autoprobe(struct pci_dev * dev,bool probe)2244 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2245 #endif
2246
2247 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2248 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2249 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2250 #endif
2251
2252 /**
2253 * pci_pcie_cap - get the saved PCIe capability offset
2254 * @dev: PCI device
2255 *
2256 * PCIe capability offset is calculated at PCI device initialization
2257 * time and saved in the data structure. This function returns saved
2258 * PCIe capability offset. Using this instead of pci_find_capability()
2259 * reduces unnecessary search in the PCI configuration space. If you
2260 * need to calculate PCIe capability offset from raw device for some
2261 * reasons, please use pci_find_capability() instead.
2262 */
pci_pcie_cap(struct pci_dev * dev)2263 static inline int pci_pcie_cap(struct pci_dev *dev)
2264 {
2265 return dev->pcie_cap;
2266 }
2267
2268 /**
2269 * pci_is_pcie - check if the PCI device is PCI Express capable
2270 * @dev: PCI device
2271 *
2272 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2273 */
pci_is_pcie(struct pci_dev * dev)2274 static inline bool pci_is_pcie(struct pci_dev *dev)
2275 {
2276 return pci_pcie_cap(dev);
2277 }
2278
2279 /**
2280 * pcie_caps_reg - get the PCIe Capabilities Register
2281 * @dev: PCI device
2282 */
pcie_caps_reg(const struct pci_dev * dev)2283 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2284 {
2285 return dev->pcie_flags_reg;
2286 }
2287
2288 /**
2289 * pci_pcie_type - get the PCIe device/port type
2290 * @dev: PCI device
2291 */
pci_pcie_type(const struct pci_dev * dev)2292 static inline int pci_pcie_type(const struct pci_dev *dev)
2293 {
2294 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2295 }
2296
2297 /**
2298 * pcie_find_root_port - Get the PCIe root port device
2299 * @dev: PCI device
2300 *
2301 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2302 * for a given PCI/PCIe Device.
2303 */
pcie_find_root_port(struct pci_dev * dev)2304 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2305 {
2306 while (dev) {
2307 if (pci_is_pcie(dev) &&
2308 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2309 return dev;
2310 dev = pci_upstream_bridge(dev);
2311 }
2312
2313 return NULL;
2314 }
2315
2316 void pci_request_acs(void);
2317 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2318 bool pci_acs_path_enabled(struct pci_dev *start,
2319 struct pci_dev *end, u16 acs_flags);
2320 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2321
2322 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2323 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2324
2325 /* Large Resource Data Type Tag Item Names */
2326 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2327 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2328 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2329
2330 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2331 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2332 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2333
2334 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2335 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2336 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2337 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2338 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2339
2340 /**
2341 * pci_vpd_alloc - Allocate buffer and read VPD into it
2342 * @dev: PCI device
2343 * @size: pointer to field where VPD length is returned
2344 *
2345 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2346 */
2347 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2348
2349 /**
2350 * pci_vpd_find_id_string - Locate id string in VPD
2351 * @buf: Pointer to buffered VPD data
2352 * @len: The length of the buffer area in which to search
2353 * @size: Pointer to field where length of id string is returned
2354 *
2355 * Returns the index of the id string or -ENOENT if not found.
2356 */
2357 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2358
2359 /**
2360 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2361 * @buf: Pointer to buffered VPD data
2362 * @len: The length of the buffer area in which to search
2363 * @kw: The keyword to search for
2364 * @size: Pointer to field where length of found keyword data is returned
2365 *
2366 * Returns the index of the information field keyword data or -ENOENT if
2367 * not found.
2368 */
2369 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2370 const char *kw, unsigned int *size);
2371
2372 /**
2373 * pci_vpd_check_csum - Check VPD checksum
2374 * @buf: Pointer to buffered VPD data
2375 * @len: VPD size
2376 *
2377 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2378 */
2379 int pci_vpd_check_csum(const void *buf, unsigned int len);
2380
2381 /* PCI <-> OF binding helpers */
2382 #ifdef CONFIG_OF
2383 struct device_node;
2384 struct irq_domain;
2385 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2386 bool pci_host_of_has_msi_map(struct device *dev);
2387
2388 /* Arch may override this (weak) */
2389 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2390
2391 #else /* CONFIG_OF */
2392 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)2393 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
pci_host_of_has_msi_map(struct device * dev)2394 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2395 #endif /* CONFIG_OF */
2396
2397 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)2398 pci_device_to_OF_node(const struct pci_dev *pdev)
2399 {
2400 return pdev ? pdev->dev.of_node : NULL;
2401 }
2402
pci_bus_to_OF_node(struct pci_bus * bus)2403 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2404 {
2405 return bus ? bus->dev.of_node : NULL;
2406 }
2407
2408 #ifdef CONFIG_ACPI
2409 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2410
2411 void
2412 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2413 bool pci_pr3_present(struct pci_dev *pdev);
2414 #else
2415 static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus * bus)2416 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
pci_pr3_present(struct pci_dev * pdev)2417 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2418 #endif
2419
2420 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)2421 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2422 {
2423 return pdev->dev.archdata.edev;
2424 }
2425 #endif
2426
2427 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2428 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2429 int pci_for_each_dma_alias(struct pci_dev *pdev,
2430 int (*fn)(struct pci_dev *pdev,
2431 u16 alias, void *data), void *data);
2432
2433 /* Helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)2434 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2435 {
2436 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2437 }
pci_clear_dev_assigned(struct pci_dev * pdev)2438 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2439 {
2440 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2441 }
pci_is_dev_assigned(struct pci_dev * pdev)2442 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2443 {
2444 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2445 }
2446
2447 /**
2448 * pci_ari_enabled - query ARI forwarding status
2449 * @bus: the PCI bus
2450 *
2451 * Returns true if ARI forwarding is enabled.
2452 */
pci_ari_enabled(struct pci_bus * bus)2453 static inline bool pci_ari_enabled(struct pci_bus *bus)
2454 {
2455 return bus->self && bus->self->ari_enabled;
2456 }
2457
2458 /**
2459 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2460 * @pdev: PCI device to check
2461 *
2462 * Walk upwards from @pdev and check for each encountered bridge if it's part
2463 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2464 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2465 */
pci_is_thunderbolt_attached(struct pci_dev * pdev)2466 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2467 {
2468 struct pci_dev *parent = pdev;
2469
2470 if (pdev->is_thunderbolt)
2471 return true;
2472
2473 while ((parent = pci_upstream_bridge(parent)))
2474 if (parent->is_thunderbolt)
2475 return true;
2476
2477 return false;
2478 }
2479
2480 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2481 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2482 #endif
2483
2484 #include <linux/dma-mapping.h>
2485
2486 #define pci_printk(level, pdev, fmt, arg...) \
2487 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2488
2489 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2490 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2491 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2492 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2493 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2494 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2495 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2496 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2497
2498 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2499 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2500
2501 #define pci_info_ratelimited(pdev, fmt, arg...) \
2502 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2503
2504 #define pci_WARN(pdev, condition, fmt, arg...) \
2505 WARN(condition, "%s %s: " fmt, \
2506 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2507
2508 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2509 WARN_ONCE(condition, "%s %s: " fmt, \
2510 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2511
2512 #endif /* LINUX_PCI_H */
2513