1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #ifndef __MTK_MMSYS_H 7 #define __MTK_MMSYS_H 8 9 enum mtk_ddp_comp_id; 10 struct device; 11 12 enum mtk_ddp_comp_id { 13 DDP_COMPONENT_AAL0, 14 DDP_COMPONENT_AAL1, 15 DDP_COMPONENT_BLS, 16 DDP_COMPONENT_CCORR, 17 DDP_COMPONENT_COLOR0, 18 DDP_COMPONENT_COLOR1, 19 DDP_COMPONENT_DITHER, 20 DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER, 21 DDP_COMPONENT_DITHER1, 22 DDP_COMPONENT_DP_INTF0, 23 DDP_COMPONENT_DP_INTF1, 24 DDP_COMPONENT_DPI0, 25 DDP_COMPONENT_DPI1, 26 DDP_COMPONENT_DSC0, 27 DDP_COMPONENT_DSC1, 28 DDP_COMPONENT_DSI0, 29 DDP_COMPONENT_DSI1, 30 DDP_COMPONENT_DSI2, 31 DDP_COMPONENT_DSI3, 32 DDP_COMPONENT_GAMMA, 33 DDP_COMPONENT_MERGE0, 34 DDP_COMPONENT_MERGE1, 35 DDP_COMPONENT_MERGE2, 36 DDP_COMPONENT_MERGE3, 37 DDP_COMPONENT_MERGE4, 38 DDP_COMPONENT_MERGE5, 39 DDP_COMPONENT_OD0, 40 DDP_COMPONENT_OD1, 41 DDP_COMPONENT_OVL0, 42 DDP_COMPONENT_OVL_2L0, 43 DDP_COMPONENT_OVL_2L1, 44 DDP_COMPONENT_OVL_2L2, 45 DDP_COMPONENT_OVL1, 46 DDP_COMPONENT_POSTMASK0, 47 DDP_COMPONENT_PWM0, 48 DDP_COMPONENT_PWM1, 49 DDP_COMPONENT_PWM2, 50 DDP_COMPONENT_RDMA0, 51 DDP_COMPONENT_RDMA1, 52 DDP_COMPONENT_RDMA2, 53 DDP_COMPONENT_RDMA4, 54 DDP_COMPONENT_UFOE, 55 DDP_COMPONENT_WDMA0, 56 DDP_COMPONENT_WDMA1, 57 DDP_COMPONENT_ID_MAX, 58 }; 59 60 void mtk_mmsys_ddp_connect(struct device *dev, 61 enum mtk_ddp_comp_id cur, 62 enum mtk_ddp_comp_id next); 63 64 void mtk_mmsys_ddp_disconnect(struct device *dev, 65 enum mtk_ddp_comp_id cur, 66 enum mtk_ddp_comp_id next); 67 68 void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val); 69 70 #endif /* __MTK_MMSYS_H */ 71