1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2020-2022 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef ASIC_REG_GAUDI2_REGS_H_ 9 #define ASIC_REG_GAUDI2_REGS_H_ 10 11 #include "gaudi2_blocks_linux_driver.h" 12 #include "psoc_reset_conf_regs.h" 13 #include "psoc_global_conf_regs.h" 14 #include "cpu_if_regs.h" 15 #include "pcie_aux_regs.h" 16 #include "pcie_dbi_regs.h" 17 #include "pcie_wrap_regs.h" 18 #include "pmmu_hbw_stlb_regs.h" 19 #include "psoc_timestamp_regs.h" 20 #include "psoc_etr_regs.h" 21 #include "xbar_edge_0_regs.h" 22 #include "xbar_mid_0_regs.h" 23 #include "arc_farm_kdma_regs.h" 24 #include "arc_farm_kdma_ctx_regs.h" 25 #include "arc_farm_kdma_kdma_cgm_regs.h" 26 #include "arc_farm_arc0_aux_regs.h" 27 #include "arc_farm_arc0_acp_eng_regs.h" 28 #include "arc_farm_kdma_ctx_axuser_regs.h" 29 #include "arc_farm_arc0_dup_eng_axuser_regs.h" 30 #include "arc_farm_arc0_dup_eng_regs.h" 31 #include "dcore0_sync_mngr_objs_regs.h" 32 #include "dcore0_sync_mngr_glbl_regs.h" 33 #include "dcore0_sync_mngr_mstr_if_axuser_regs.h" 34 #include "pdma0_qm_arc_aux_regs.h" 35 #include "pdma0_core_ctx_regs.h" 36 #include "pdma0_core_regs.h" 37 #include "pdma0_qm_axuser_secured_regs.h" 38 #include "pdma0_qm_regs.h" 39 #include "pdma0_qm_cgm_regs.h" 40 #include "pdma0_core_ctx_axuser_regs.h" 41 #include "pdma1_core_ctx_axuser_regs.h" 42 #include "pdma0_qm_axuser_nonsecured_regs.h" 43 #include "pdma1_qm_axuser_nonsecured_regs.h" 44 #include "dcore0_tpc0_qm_regs.h" 45 #include "dcore0_tpc0_qm_cgm_regs.h" 46 #include "dcore0_tpc0_qm_axuser_nonsecured_regs.h" 47 #include "dcore0_tpc0_qm_arc_aux_regs.h" 48 #include "dcore0_tpc0_cfg_regs.h" 49 #include "dcore0_tpc0_cfg_qm_regs.h" 50 #include "dcore0_tpc0_cfg_axuser_regs.h" 51 #include "dcore0_tpc0_cfg_qm_sync_object_regs.h" 52 #include "dcore0_tpc0_cfg_kernel_regs.h" 53 #include "dcore0_tpc0_cfg_kernel_tensor_0_regs.h" 54 #include "dcore0_tpc0_cfg_qm_tensor_0_regs.h" 55 #include "dcore0_tpc0_cfg_special_regs.h" 56 #include "dcore0_tpc0_eml_funnel_regs.h" 57 #include "dcore0_tpc0_eml_etf_regs.h" 58 #include "dcore0_tpc0_eml_stm_regs.h" 59 #include "dcore0_tpc0_eml_busmon_0_regs.h" 60 #include "dcore0_tpc0_eml_spmu_regs.h" 61 #include "pmmu_pif_regs.h" 62 #include "dcore0_edma0_qm_cgm_regs.h" 63 #include "dcore0_edma0_core_regs.h" 64 #include "dcore0_edma0_qm_regs.h" 65 #include "dcore0_edma0_qm_arc_aux_regs.h" 66 #include "dcore0_edma0_core_ctx_regs.h" 67 #include "dcore0_edma0_core_ctx_axuser_regs.h" 68 #include "dcore0_edma0_qm_axuser_nonsecured_regs.h" 69 #include "dcore0_edma1_core_ctx_axuser_regs.h" 70 #include "dcore0_edma1_qm_axuser_nonsecured_regs.h" 71 #include "dcore0_hmmu0_stlb_regs.h" 72 #include "dcore0_hmmu0_mmu_regs.h" 73 #include "rot0_qm_regs.h" 74 #include "rot0_qm_cgm_regs.h" 75 #include "rot0_qm_arc_aux_regs.h" 76 #include "rot0_regs.h" 77 #include "rot0_desc_regs.h" 78 #include "rot0_qm_axuser_nonsecured_regs.h" 79 #include "dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h" 80 #include "dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h" 81 #include "dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h" 82 #include "dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h" 83 #include "dcore0_rtr0_ctrl_regs.h" 84 #include "dcore0_dec0_cmd_regs.h" 85 #include "dcore0_vdec0_brdg_ctrl_regs.h" 86 #include "dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h" 87 #include "dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h" 88 #include "dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h" 89 #include "dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h" 90 #include "dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h" 91 #include "dcore0_vdec0_ctrl_special_regs.h" 92 #include "pcie_vdec0_brdg_ctrl_axuser_dec_regs.h" 93 #include "pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h" 94 #include "pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h" 95 #include "pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h" 96 #include "pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h" 97 #include "pcie_dec0_cmd_regs.h" 98 #include "pcie_vdec0_brdg_ctrl_regs.h" 99 #include "pcie_vdec0_ctrl_special_regs.h" 100 #include "dcore0_mme_qm_regs.h" 101 #include "dcore0_mme_qm_arc_aux_regs.h" 102 #include "dcore0_mme_qm_axuser_secured_regs.h" 103 #include "dcore0_mme_qm_cgm_regs.h" 104 #include "dcore0_mme_qm_arc_acp_eng_regs.h" 105 #include "dcore0_mme_qm_axuser_nonsecured_regs.h" 106 #include "dcore0_mme_qm_arc_dup_eng_regs.h" 107 #include "dcore0_mme_qm_arc_dup_eng_axuser_regs.h" 108 #include "dcore0_mme_sbte0_mstr_if_axuser_regs.h" 109 #include "dcore0_mme_wb0_mstr_if_axuser_regs.h" 110 #include "dcore0_mme_acc_regs.h" 111 #include "dcore0_mme_ctrl_lo_regs.h" 112 #include "dcore1_mme_ctrl_lo_regs.h" 113 #include "dcore3_mme_ctrl_lo_regs.h" 114 #include "dcore0_mme_ctrl_lo_mme_axuser_regs.h" 115 #include "dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h" 116 #include "dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h" 117 #include "dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h" 118 #include "dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h" 119 #include "dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h" 120 #include "dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h" 121 #include "dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h" 122 #include "dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h" 123 #include "dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h" 124 #include "dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h" 125 #include "dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h" 126 #include "dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h" 127 #include "dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h" 128 #include "dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h" 129 #include "dcore0_mme_ctrl_lo_arch_base_addr_regs.h" 130 #include "dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h" 131 #include "dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h" 132 #include "dcore0_mme_ctrl_lo_arch_tensor_a_regs.h" 133 #include "dcore0_mme_ctrl_lo_arch_tensor_b_regs.h" 134 #include "dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h" 135 #include "pcie_wrap_special_regs.h" 136 137 #include "pdma0_qm_masks.h" 138 #include "pdma0_core_masks.h" 139 #include "pdma0_core_special_masks.h" 140 #include "psoc_global_conf_masks.h" 141 #include "psoc_reset_conf_masks.h" 142 #include "arc_farm_kdma_masks.h" 143 #include "arc_farm_kdma_ctx_masks.h" 144 #include "arc_farm_arc0_aux_masks.h" 145 #include "arc_farm_kdma_ctx_axuser_masks.h" 146 #include "dcore0_sync_mngr_objs_masks.h" 147 #include "dcore0_sync_mngr_glbl_masks.h" 148 #include "dcore0_sync_mngr_mstr_if_axuser_masks.h" 149 #include "dcore0_tpc0_cfg_masks.h" 150 #include "dcore0_mme_ctrl_lo_masks.h" 151 #include "dcore0_mme_sbte0_masks.h" 152 #include "dcore0_edma0_qm_masks.h" 153 #include "dcore0_edma0_core_masks.h" 154 #include "dcore0_hmmu0_stlb_masks.h" 155 #include "dcore0_hmmu0_mmu_masks.h" 156 #include "dcore0_dec0_cmd_masks.h" 157 #include "dcore0_vdec0_brdg_ctrl_masks.h" 158 #include "pcie_dec0_cmd_masks.h" 159 #include "pcie_vdec0_brdg_ctrl_masks.h" 160 #include "rot0_masks.h" 161 #include "pmmu_hbw_stlb_masks.h" 162 #include "psoc_etr_masks.h" 163 164 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x4800040 165 166 #define SM_OBJS_PROT_BITS_OFFS 0x14000 167 168 #define DCORE_OFFSET (mmDCORE1_TPC0_QM_BASE - mmDCORE0_TPC0_QM_BASE) 169 #define DCORE_EDMA_OFFSET (mmDCORE0_EDMA1_QM_BASE - mmDCORE0_EDMA0_QM_BASE) 170 #define DCORE_TPC_OFFSET (mmDCORE0_TPC1_QM_BASE - mmDCORE0_TPC0_QM_BASE) 171 #define DCORE_DEC_OFFSET (mmDCORE0_DEC1_VSI_BASE - mmDCORE0_DEC0_VSI_BASE) 172 #define DCORE_HMMU_OFFSET (mmDCORE0_HMMU1_MMU_BASE - mmDCORE0_HMMU0_MMU_BASE) 173 #define NIC_QM_OFFSET (mmNIC0_QM1_BASE - mmNIC0_QM0_BASE) 174 #define PDMA_OFFSET (mmPDMA1_QM_BASE - mmPDMA0_QM_BASE) 175 #define ROT_OFFSET (mmROT1_BASE - mmROT0_BASE) 176 177 #define TPC_CFG_BASE_ADDRESS_HIGH_OFFSET \ 178 (mmDCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE) 179 180 #define TPC_CFG_SM_BASE_ADDRESS_HIGH_OFFSET \ 181 (mmDCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE) 182 183 #define TPC_CFG_STALL_OFFSET (mmDCORE0_TPC0_CFG_TPC_STALL - mmDCORE0_TPC0_CFG_BASE) 184 #define TPC_CFG_STALL_ON_ERR_OFFSET (mmDCORE0_TPC0_CFG_STALL_ON_ERR - mmDCORE0_TPC0_CFG_BASE) 185 #define TPC_CFG_TPC_INTR_MASK_OFFSET (mmDCORE0_TPC0_CFG_TPC_INTR_MASK - mmDCORE0_TPC0_CFG_BASE) 186 #define TPC_CFG_MSS_CONFIG_OFFSET (mmDCORE0_TPC0_CFG_MSS_CONFIG - mmDCORE0_TPC0_CFG_BASE) 187 188 #define MME_ACC_INTR_MASK_OFFSET (mmDCORE0_MME_ACC_INTR_MASK - mmDCORE0_MME_ACC_BASE) 189 #define MME_ACC_WR_AXI_AGG_COUT0_OFFSET (mmDCORE0_MME_ACC_WR_AXI_AGG_COUT0 - mmDCORE0_MME_ACC_BASE) 190 #define MME_ACC_WR_AXI_AGG_COUT1_OFFSET (mmDCORE0_MME_ACC_WR_AXI_AGG_COUT1 - mmDCORE0_MME_ACC_BASE) 191 #define MME_ACC_AP_LFSR_POLY_OFFSET (mmDCORE0_MME_ACC_AP_LFSR_POLY - mmDCORE0_MME_ACC_BASE) 192 #define MME_ACC_AP_LFSR_SEED_SEL_OFFSET (mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL - mmDCORE0_MME_ACC_BASE) 193 #define MME_ACC_AP_LFSR_SEED_WDATA_OFFSET \ 194 (mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA - mmDCORE0_MME_ACC_BASE) 195 196 #define DMA_CORE_CFG_0_OFFSET (mmARC_FARM_KDMA_CFG_0 - mmARC_FARM_KDMA_BASE) 197 #define DMA_CORE_CFG_1_OFFSET (mmARC_FARM_KDMA_CFG_1 - mmARC_FARM_KDMA_BASE) 198 #define DMA_CORE_PROT_OFFSET (mmARC_FARM_KDMA_PROT - mmARC_FARM_KDMA_BASE) 199 #define DMA_CORE_ERRMSG_ADDR_LO_OFFSET (mmARC_FARM_KDMA_ERRMSG_ADDR_LO - mmARC_FARM_KDMA_BASE) 200 #define DMA_CORE_ERRMSG_ADDR_HI_OFFSET (mmARC_FARM_KDMA_ERRMSG_ADDR_HI - mmARC_FARM_KDMA_BASE) 201 #define DMA_CORE_ERRMSG_WDATA_OFFSET (mmARC_FARM_KDMA_ERRMSG_WDATA - mmARC_FARM_KDMA_BASE) 202 203 #define QM_PQ_BASE_LO_0_OFFSET (mmPDMA0_QM_PQ_BASE_LO_0 - mmPDMA0_QM_BASE) 204 #define QM_PQ_BASE_HI_0_OFFSET (mmPDMA0_QM_PQ_BASE_HI_0 - mmPDMA0_QM_BASE) 205 #define QM_PQ_SIZE_0_OFFSET (mmPDMA0_QM_PQ_SIZE_0 - mmPDMA0_QM_BASE) 206 #define QM_PQ_PI_0_OFFSET (mmPDMA0_QM_PQ_PI_0 - mmPDMA0_QM_BASE) 207 #define QM_PQ_CI_0_OFFSET (mmPDMA0_QM_PQ_CI_0 - mmPDMA0_QM_BASE) 208 #define QM_CP_FENCE0_CNT_0_OFFSET (mmPDMA0_QM_CP_FENCE0_CNT_0 - mmPDMA0_QM_BASE) 209 210 #define QM_CP_MSG_BASE0_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 - mmPDMA0_QM_BASE) 211 #define QM_CP_MSG_BASE0_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 - mmPDMA0_QM_BASE) 212 #define QM_CP_MSG_BASE1_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 - mmPDMA0_QM_BASE) 213 #define QM_CP_MSG_BASE1_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 - mmPDMA0_QM_BASE) 214 215 #define QM_CP_CFG_OFFSET (mmPDMA0_QM_CP_CFG - mmPDMA0_QM_BASE) 216 #define QM_PQC_HBW_BASE_LO_0_OFFSET (mmPDMA0_QM_PQC_HBW_BASE_LO_0 - mmPDMA0_QM_BASE) 217 #define QM_PQC_HBW_BASE_HI_0_OFFSET (mmPDMA0_QM_PQC_HBW_BASE_HI_0 - mmPDMA0_QM_BASE) 218 #define QM_PQC_SIZE_0_OFFSET (mmPDMA0_QM_PQC_SIZE_0 - mmPDMA0_QM_BASE) 219 #define QM_PQC_PI_0_OFFSET (mmPDMA0_QM_PQC_PI_0 - mmPDMA0_QM_BASE) 220 #define QM_PQC_LBW_WDATA_0_OFFSET (mmPDMA0_QM_PQC_LBW_WDATA_0 - mmPDMA0_QM_BASE) 221 #define QM_PQC_LBW_BASE_LO_0_OFFSET (mmPDMA0_QM_PQC_LBW_BASE_LO_0 - mmPDMA0_QM_BASE) 222 #define QM_PQC_LBW_BASE_HI_0_OFFSET (mmPDMA0_QM_PQC_LBW_BASE_HI_0 - mmPDMA0_QM_BASE) 223 #define QM_GLBL_ERR_ADDR_LO_OFFSET (mmPDMA0_QM_GLBL_ERR_ADDR_LO - mmPDMA0_QM_BASE) 224 #define QM_PQC_CFG_OFFSET (mmPDMA0_QM_PQC_CFG - mmPDMA0_QM_BASE) 225 #define QM_ARB_CFG_0_OFFSET (mmPDMA0_QM_ARB_CFG_0 - mmPDMA0_QM_BASE) 226 #define QM_GLBL_CFG0_OFFSET (mmPDMA0_QM_GLBL_CFG0 - mmPDMA0_QM_BASE) 227 #define QM_GLBL_CFG1_OFFSET (mmPDMA0_QM_GLBL_CFG1 - mmPDMA0_QM_BASE) 228 #define QM_GLBL_CFG2_OFFSET (mmPDMA0_QM_GLBL_CFG2 - mmPDMA0_QM_BASE) 229 #define QM_GLBL_PROT_OFFSET (mmPDMA0_QM_GLBL_PROT - mmPDMA0_QM_BASE) 230 #define QM_GLBL_ERR_CFG_OFFSET (mmPDMA0_QM_GLBL_ERR_CFG - mmPDMA0_QM_BASE) 231 #define QM_GLBL_ERR_CFG1_OFFSET (mmPDMA0_QM_GLBL_ERR_CFG1 - mmPDMA0_QM_BASE) 232 #define QM_GLBL_ERR_ADDR_HI_OFFSET (mmPDMA0_QM_GLBL_ERR_ADDR_HI - mmPDMA0_QM_BASE) 233 #define QM_GLBL_ERR_WDATA_OFFSET (mmPDMA0_QM_GLBL_ERR_WDATA - mmPDMA0_QM_BASE) 234 #define QM_ARB_ERR_MSG_EN_OFFSET (mmPDMA0_QM_ARB_ERR_MSG_EN - mmPDMA0_QM_BASE) 235 #define QM_ARB_SLV_CHOISE_WDT_OFFSET (mmPDMA0_QM_ARB_SLV_CHOICE_WDT - mmPDMA0_QM_BASE) 236 #define QM_FENCE2_OFFSET (mmPDMA0_QM_CP_FENCE2_RDATA_0 - mmPDMA0_QM_BASE) 237 #define QM_SEI_STATUS_OFFSET (mmPDMA0_QM_SEI_STATUS - mmPDMA0_QM_BASE) 238 239 #define SFT_OFFSET (mmSFT1_HBW_RTR_IF0_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE) 240 #define SFT_IF_RTR_OFFSET (mmSFT0_HBW_RTR_IF1_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE) 241 242 #define ARC_HALT_REQ_OFFSET (mmARC_FARM_ARC0_AUX_RUN_HALT_REQ - mmARC_FARM_ARC0_AUX_BASE) 243 #define ARC_HALT_ACK_OFFSET (mmARC_FARM_ARC0_AUX_RUN_HALT_ACK - mmARC_FARM_ARC0_AUX_BASE) 244 245 #define ARC_REGION_CFG_OFFSET(region) \ 246 (mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_0 + (region * 4) - mmARC_FARM_ARC0_AUX_BASE) 247 248 #define ARC_DCCM_UPPER_EN_OFFSET \ 249 (mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN - mmARC_FARM_ARC0_AUX_BASE) 250 251 #define PCIE_VDEC_OFFSET \ 252 (mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmPCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE) 253 254 #define DCORE_MME_SBTE_OFFSET \ 255 (mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE) 256 257 #define DCORE_MME_WB_OFFSET \ 258 (mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE) 259 260 #define DCORE_RTR_OFFSET \ 261 (mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 262 263 #define DCORE_VDEC_OFFSET \ 264 (mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE) 265 266 #define MMU_OFFSET(REG) (REG - mmDCORE0_HMMU0_MMU_BASE) 267 #define MMU_BYPASS_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_BYPASS) 268 #define MMU_SPI_SEI_MASK_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_MASK) 269 #define MMU_SPI_SEI_CAUSE_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE) 270 #define MMU_ENABLE_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_ENABLE) 271 #define MMU_DDR_RANGE_REG_ENABLE MMU_OFFSET(mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE) 272 #define MMU_RR_SEC_MIN_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0) 273 #define MMU_RR_SEC_MIN_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0) 274 #define MMU_RR_SEC_MAX_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_0) 275 #define MMU_RR_SEC_MAX_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_0) 276 #define MMU_RR_PRIV_MIN_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_0) 277 #define MMU_RR_PRIV_MIN_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_0) 278 #define MMU_RR_PRIV_MAX_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_0) 279 #define MMU_RR_PRIV_MAX_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_0) 280 #define MMU_INTERRUPT_CLR_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_INTERRUPT_CLR) 281 282 #define STLB_OFFSET(REG) (REG - mmDCORE0_HMMU0_STLB_BASE) 283 #define STLB_BUSY_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_BUSY) 284 #define STLB_ASID_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_ASID) 285 #define STLB_HOP0_PA43_12_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA43_12) 286 #define STLB_HOP0_PA63_44_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA63_44) 287 #define STLB_HOP_CONFIGURATION_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP_CONFIGURATION) 288 #define STLB_INV_ALL_START_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_INV_ALL_START) 289 #define STLB_SRAM_INIT_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SRAM_INIT) 290 #define STLB_SET_THRESHOLD_HOP3_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3) 291 #define STLB_SET_THRESHOLD_HOP2_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2) 292 #define STLB_SET_THRESHOLD_HOP1_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1) 293 #define STLB_SET_THRESHOLD_HOP0_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0) 294 #define STLB_RANGE_INV_START_LSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_LSB) 295 #define STLB_RANGE_INV_START_MSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_MSB) 296 #define STLB_RANGE_INV_END_LSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_LSB) 297 #define STLB_RANGE_INV_END_MSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_MSB) 298 299 #define STLB_LL_LOOKUP_MASK_63_32_OFFSET \ 300 STLB_OFFSET(mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32) 301 302 #define STLB_RANGE_CACHE_INVALIDATION_OFFSET \ 303 STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION) 304 305 /* RTR CTR RAZWI related offsets */ 306 #define RTR_MSTR_IF_OFFSET (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE) 307 308 #define RTR_LBW_MSTR_IF_OFFSET \ 309 (mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE) 310 311 /* RAZWI captured hbw aw addr high */ 312 #define DEC_RAZWI_HBW_AW_ADDR_HI \ 313 (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE) 314 315 /* RAZWI captured hbw aw addr low */ 316 #define DEC_RAZWI_HBW_AW_ADDR_LO \ 317 (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE) 318 319 /* RAZWI captured hbw aw set */ 320 #define DEC_RAZWI_HBW_AW_SET \ 321 (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE) 322 323 /* RAZWI captured hbw ar addr high */ 324 #define DEC_RAZWI_HBW_AR_ADDR_HI \ 325 (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE) 326 327 /* RAZWI captured hbw ar addr low */ 328 #define DEC_RAZWI_HBW_AR_ADDR_LO \ 329 (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE) 330 331 /* RAZWI captured hbw ar set */ 332 #define DEC_RAZWI_HBW_AR_SET \ 333 (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE) 334 335 /* RAZWI captured lbw aw addr */ 336 #define DEC_RAZWI_LBW_AW_ADDR \ 337 (mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_ADDR - mmDCORE0_RTR0_CTRL_BASE) 338 339 /* RAZWI captured lbw aw set */ 340 #define DEC_RAZWI_LBW_AW_SET \ 341 (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE) 342 343 /* RAZWI captured lbw ar addr */ 344 #define DEC_RAZWI_LBW_AR_ADDR \ 345 (mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_ADDR - mmDCORE0_RTR0_CTRL_BASE) 346 347 /* RAZWI captured lbw ar set */ 348 #define DEC_RAZWI_LBW_AR_SET \ 349 (mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE) 350 351 /* RAZWI captured shared hbw aw addr high */ 352 #define RR_SHRD_HBW_AW_RAZWI_HI \ 353 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 354 355 /* RAZWI captured shared hbw aw addr low */ 356 #define RR_SHRD_HBW_AW_RAZWI_LO \ 357 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 358 359 /* RAZWI captured shared hbw ar addr high */ 360 #define RR_SHRD_HBW_AR_RAZWI_HI \ 361 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 362 363 /* RAZWI captured shared hbw ar addr low */ 364 #define RR_SHRD_HBW_AR_RAZWI_LO \ 365 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 366 367 /* RAZWI captured shared aw XY coordinates */ 368 #define RR_SHRD_HBW_AW_RAZWI_XY \ 369 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 370 371 /* RAZWI captured shared ar XY coordinates */ 372 #define RR_SHRD_HBW_AR_RAZWI_XY \ 373 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 374 375 /* RAZWI hbw shared occurred due to write access */ 376 #define RR_SHRD_HBW_AW_RAZWI_HAPPENED \ 377 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HAPPENED - \ 378 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 379 380 /* RAZWI hbw shared occurred due to read access */ 381 #define RR_SHRD_HBW_AR_RAZWI_HAPPENED \ 382 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HAPPENED - \ 383 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 384 385 /* RAZWI captured shared lbw aw addr */ 386 #define RR_SHRD_LBW_AW_RAZWI \ 387 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI - \ 388 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 389 390 /* RAZWI captured shared lbw ar addr */ 391 #define RR_SHRD_LBW_AR_RAZWI \ 392 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI - \ 393 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 394 395 /* RAZWI captured shared lbw aw XY coordinates */ 396 #define RR_SHRD_LBW_AW_RAZWI_XY \ 397 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_XY - \ 398 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 399 400 /* RAZWI captured shared lbw ar XY coordinates */ 401 #define RR_SHRD_LBW_AR_RAZWI_XY \ 402 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_XY - \ 403 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 404 405 /* RAZWI lbw shared occurred due to write access */ 406 #define RR_SHRD_LBW_AW_RAZWI_HAPPENED \ 407 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_HAPPENED - \ 408 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 409 410 /* RAZWI lbw shared occurred due to read access */ 411 #define RR_SHRD_LBW_AR_RAZWI_HAPPENED \ 412 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_HAPPENED - \ 413 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 414 415 #define BRDG_CTRL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_BASE - mmDCORE0_DEC0_CMD_BASE) 416 #define SPECIAL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE - mmDCORE0_DEC0_CMD_BASE) 417 #define SFT_DCORE_OFFSET (mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE) 418 #define SFT_IF_OFFSET (mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE) 419 420 #define BRDG_CTRL_NRM_MSIX_LBW_AWADDR \ 421 (mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE) 422 423 #define BRDG_CTRL_NRM_MSIX_LBW_WDATA \ 424 (mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE) 425 426 #define BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR \ 427 (mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE) 428 429 #define BRDG_CTRL_ABNRM_MSIX_LBW_WDATA \ 430 (mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE) 431 432 #define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET \ 433 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0 - \ 434 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 435 436 #define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET \ 437 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0 - \ 438 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 439 440 #define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET \ 441 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0 - \ 442 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 443 444 #define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET \ 445 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0 - \ 446 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 447 448 #define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET \ 449 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0 - \ 450 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 451 452 #define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET \ 453 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0 - \ 454 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 455 456 #define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET \ 457 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0 - \ 458 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 459 460 #define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET \ 461 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0 - \ 462 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 463 464 #define RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET \ 465 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_0 - \ 466 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 467 468 #define RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET \ 469 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_0 - \ 470 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 471 472 #define RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET \ 473 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_0 - \ 474 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 475 476 #define RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET \ 477 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_0 - \ 478 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 479 480 #define RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET \ 481 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0 - \ 482 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 483 484 #define RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET \ 485 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0 - \ 486 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 487 488 #define RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET \ 489 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0 - \ 490 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 491 492 #define RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET \ 493 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0 - \ 494 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE) 495 496 #define RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET \ 497 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_0 - \ 498 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) 499 500 #define RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET \ 501 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_0 - \ 502 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) 503 504 #define RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET \ 505 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_0 - \ 506 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) 507 508 #define RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET \ 509 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_0 - \ 510 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) 511 512 #define RR_LBW_SEC_RANGE_MIN_0_OFFSET \ 513 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_0 - \ 514 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) 515 516 #define RR_LBW_SEC_RANGE_MAX_0_OFFSET \ 517 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_0 - \ 518 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) 519 520 #define RR_LBW_PRIV_RANGE_MIN_0_OFFSET \ 521 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_0 - \ 522 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) 523 524 #define RR_LBW_PRIV_RANGE_MAX_0_OFFSET \ 525 (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_0 - \ 526 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE) 527 528 #define ARC_AUX_DCCM_QUEUE_PUSH_REG_0_OFFSET \ 529 (mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_0 - mmARC_FARM_ARC0_AUX_BASE) 530 531 #define MMU_STATIC_MULTI_PAGE_SIZE_OFFSET \ 532 (mmDCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE - mmDCORE0_HMMU0_MMU_BASE) 533 534 #define HBM_MC_SPI_TEMP_PIN_CHG_MASK BIT(0) 535 #define HBM_MC_SPI_THR_ENG_MASK BIT(1) 536 #define HBM_MC_SPI_THR_DIS_ENG_MASK BIT(2) 537 #define HBM_MC_SPI_IEEE1500_COMP_MASK BIT(3) 538 #define HBM_MC_SPI_IEEE1500_PAUSED_MASK BIT(4) 539 540 #include "nic0_qpc0_regs.h" 541 #include "nic0_qm0_regs.h" 542 #include "nic0_qm_arc_aux0_regs.h" 543 #include "nic0_qm0_cgm_regs.h" 544 #include "nic0_umr0_0_completion_queue_ci_1_regs.h" 545 #include "nic0_umr0_0_unsecure_doorbell0_regs.h" 546 547 #define NIC_OFFSET (mmNIC1_MSTR_IF_RR_SHRD_HBW_BASE - mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE) 548 549 #define NIC_UMR_OFFSET \ 550 (mmNIC0_UMR0_1_UNSECURE_DOORBELL0_BASE - mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE) 551 552 #endif /* ASIC_REG_GAUDI2_REGS_H_ */ 553